Classifications

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  • H10D30/00—Field-effect transistors [FET]
  • H10D30/60—Insulated-gate field-effect transistors [IGFET]
  • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
  • H10D30/66—Vertical DMOS [VDMOS] FETs
  • H10D30/668—Vertical DMOS [VDMOS] FETs having trench gate electrodes, e.g. UMOS transistors
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  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
  • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
  • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
  • H01L21/28008—Making conductor-insulator-semiconductor electrodes
  • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
  • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
  • H01L21/28114—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor characterised by the sectional shape, e.g. T, inverted-T
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  • H10D30/01—Manufacture or treatment
  • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
  • H10D30/028—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs
  • H10D30/0291—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of vertical DMOS [VDMOS] FETs
  • H10D30/0297—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of vertical DMOS [VDMOS] FETs using recessing of the gate electrodes, e.g. to form trench gate electrodes
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  • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
  • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
  • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
  • H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
  • H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] 
  • H10D62/109—Reduced surface field [RESURF] PN junction structures
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  • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
  • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
  • H10D62/113—Isolations within a component, i.e. internal isolations
  • H10D62/115—Dielectric isolations, e.g. air gaps
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  • H10D64/00—Electrodes of devices having potential barriers
  • H10D64/111—Field plates
  • H10D64/112—Field plates comprising multiple field plate segments
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  • H10D64/00—Electrodes of devices having potential barriers
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  • H10D64/117—Recessed field plates, e.g. trench field plates or buried field plates
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  • H10D64/00—Electrodes of devices having potential barriers
  • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
  • H10D64/23—Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes
  • H10D64/251—Source or drain electrodes for field-effect devices
  • H10D64/252—Source or drain electrodes for field-effect devices for vertical or pseudo-vertical devices
  • H10D64/2527—Source or drain electrodes for field-effect devices for vertical or pseudo-vertical devices for vertical devices wherein the source or drain electrodes are recessed in semiconductor bodies
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  • H10D64/00—Electrodes of devices having potential barriers
  • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
  • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
  • H10D64/311—Gate electrodes for field-effect devices
  • H10D64/411—Gate electrodes for field-effect devices for FETs
  • H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
  • H10D64/512—Disposition of the gate electrodes, e.g. buried gates
  • H10D64/513—Disposition of the gate electrodes, e.g. buried gates within recesses in the substrate, e.g. trench gates, groove gates or buried gates
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  • H10D64/00—Electrodes of devices having potential barriers
  • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
  • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
  • H10D64/311—Gate electrodes for field-effect devices
  • H10D64/411—Gate electrodes for field-effect devices for FETs
  • H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
  • H10D64/514—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the insulating layers
  • H10D64/516—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the insulating layers the thicknesses being non-uniform
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  • H10D64/00—Electrodes of devices having potential barriers
  • H10D64/60—Electrodes characterised by their materials
  • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
  • H10D64/68—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator
  • H10D64/681—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator having a compositional variation, e.g. multilayered
  • H10D64/685—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator having a compositional variation, e.g. multilayered being perpendicular to the channel plane
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  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
  • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
  • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
  • H10D62/393—Body regions of DMOS transistors or IGBTs 
• • H—ELECTRICITY
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  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D64/00—Electrodes of devices having potential barriers
  • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
  • H10D64/23—Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes
  • H10D64/251—Source or drain electrodes for field-effect devices
  • H10D64/256—Source or drain electrodes for field-effect devices for lateral devices wherein the source or drain electrodes are recessed in semiconductor bodies

Definitions

• This relates generally to semiconductor devices, and more particularly to vertical MOS transistors in semiconductor devices.
• a vertical metal oxide semiconductor (MOS) transistor with a trench gate in trenches has the gate dielectric layer and gate extending down the trenches past the body, abutting a vertical drift region under the body.
• the trenches have to be deeper than desired to support a desired operating voltage, because the gate dielectric layer cannot support a high electric field in the drift region. If the thickness of the gate dielectric layer is increased, it undesirably increases the resistance of the channel region in the on state.
• a semiconductor device contains a vertical MOS transistor having a trench gate in trenches.
• the trenches extend into a substrate of the semiconductor device past a body of the vertical MOS transistor, abutting a drift region of the vertical MOS transistor under the body.
• the trenches have field plates under the gate.
• the field plates are adjacent to the drift region and have multiple segments.
• a dielectric liner in the trenches separating the field plates from the drift region has a thickness greater than a gate dielectric layer between the gate and the body. The dielectric liner is thicker on a lower segment of the field plate, at a bottom of the trenches, than an upper segment, immediately under the gate.
• FIG. 1 is a cross section of an example semiconductor device containing a vertical n-channel MOS transistor.
• FIG. 2 A through FIG. 2K are cross sections of the semiconductor device of FIG. 1, depicted in successive stages of fabrication.
• FIG. 3 is a cross section of another example semiconductor device containing a vertical n-channel MOS transistor.
• FIG. 4 A through FIG. 4E are cross sections of the semiconductor device of FIG. 3, depicted in successive stages of fabrication.
• FIG. 5 is a cross section of an example semiconductor device containing a vertical p-channel MOS transistor.
• FIG. 6A through FIG. 6H are cross sections of the semiconductor device of FIG. 5, depicted in successive stages of fabrication.
• FIG. 7 is a cross section of another example semiconductor device containing a vertical n-channel MOS transistor.
• a semiconductor device contains a vertical MOS transistor having trenches that extend into a substrate of the semiconductor device.
• a drain region of the vertical MOS transistor is disposed in the substrate at, or below, bottoms of the trenches.
• a drift region is disposed in the substrate above the drain region and between the trenches.
• a body of the vertical MOS transistor is disposed in the substrate, above the drift region and abutting the trenches.
• a source of the vertical MOS transistor is disposed above the body.
• a gate of the vertical MOS transistor is disposed in the trenches adjacent to the body, separated from the body by a gate dielectric layer.
• a field plate with multiple segments is disposed in the trenches below the gate, separated from the drift region by a dielectric liner on sidewalls of the trenches.
• the dielectric liner is thicker on a lower segment of the field plate, at a bottom of the trenches, than an upper segment, immediately under the gate.
• the field plate segments may be connected to each other or may be electrically isolated from each other.
• the upper field plate segment may be connected to the gate or may be electrically isolated from the gate.
• the vertical MOS transistor may be an n-channel MOS transistor or a p-channel MOS transistor.
• RESURF refers to a material that reduces an electric field in an adjacent semiconductor region.
• a RESURF region may be a semiconductor region with an opposite conductivity type from the adjacent semiconductor region.
• RESURF structures are described in Appels, et al., "Thin Layer High Voltage Devices” Philips J, Res. 35 1-13, 1980.
• FIG. 1 is a cross section of an example semiconductor device containing a vertical n-channel MOS transistor.
• the semiconductor device 100 is formed on a substrate 102, which includes a semiconductor material.
• the n-channel vertical MOS transistor 104 referred to herein as the transistor 104, may be the only active component of the semiconductor device 100 or may be one of multiple active devices in the semiconductor device 100.
• the transistor 104 includes an n-type drain region 106 disposed in the substrate 102 below an n-type vertical drift region 108.
• the semiconductor device 100 includes trenches 110, which extend vertically through the vertical drift region 108 proximate to the drain region 106 as depicted in FIG. 1, or possibly into the drain region 106.
• the trenches 110 contain a dielectric liner 112 on sidewalls of the trenches 110 extending to bottoms 114 of the trenches 110 and abutting the substrate 102, and multiple field plate segments 116 on the dielectric liner 112.
• the trenches 110 further contain a gate dielectric layer 118 above the dielectric liner 112 abutting the substrate 102, and a trench gate 120 of the transistor 104 contacting the gate dielectric layer 118.
• the field plate segments 116 include respective lower field plate segments 122 on the respective dielectric liners 112 at the bottoms 114 of the trenches 110, and respective upper field plate segments 124 disposed above the respective lower field plate segments 122.
• the field plate segments 116 and the trench gate 120 may include primarily poly crystalline silicon, referred to as poly silicon.
• the dielectric liner 112 may include primarily silicon dioxide. The dielectric liner 112 separates the lower field plate segment 122 and the upper field plate segment 124 from the substrate 102.
• the dielectric liner 112 disposed on the sidewalls of the trenches 110 between the lower field plate segment 122 and the substrate 102 is thicker than the dielectric liner 112 disposed on the sidewalls of the trenches 110 between the upper field plate segment 124 and the substrate 102.
• the dielectric liner 112 disposed on the sidewalls of the trenches 110 between the upper field plate segment 124 and the substrate 102 is thicker than the gate dielectric layer 118 disposed on the sidewalls of the trenches 110 between the trench gate 120 and the substrate 102.
• the dielectric liner 112 disposed on the sidewalls of the trenches 110 between the lower field plate segment 122 and the substrate 102 may be 900 nanometers to 1000 nanometers thick, and the dielectric liner 112 disposed on the sidewalls of the trenches 110 between the upper field plate segment 124 and the substrate 102 may be 300 nanometers to 400 nanometers thick.
• the lower field plate segment 122 is electrically isolated from the upper field plate segment 124 by a first isolation layer 126, disposed between the lower field plate segment 122 and the upper field plate segment 124.
• the upper field plate segment 124 is electrically isolated from the trench gate 120 by a second isolation layer 128, disposed between the upper field plate segment 124 and the trench gate 120.
• the first isolation layer 126 and the second isolation layer 128 include dielectric material such as silicon dioxide, and may have a similar composition as the dielectric liner 1 12.
• the transistor 104 includes a p-type body 130 in the substrate 102 above the vertical drift region 108, abutting the gate dielectric layer 118.
• the transistor 104 further includes an n-type source 132 above the body 130 and abutting the gate dielectric layer 118.
• the trench gate 120 is partially coextensive with the vertical drift region 108 and the source 132.
• a source electrode 134 is disposed over the substrate 102 making electrical contact to the source 132 and the body 130.
• the source electrode 134 is electrically isolated from the trench gate 120 by a dielectric cap layer 136 over the trench gate 120.
• the trenches 110 may be 13 microns to 17 microns deep and 2.5 microns to 2.8 microns wide.
• the vertical drift region 108 may be 0.5 microns to 3 microns wide, that is, between adjacent trenches 110, and have an average doping density of 1.4 ⁇ 10 16 cm “3 to 1.6 ⁇ 10 16 cm “3 .
• Electrical connection to the trench gate 120 may be made through gate contacts 138 on exposed areas of the gate at a top surface 140 of the substrate 102. Electrical connections to the field plate segments 116 may be made through field plate contacts 142 on field plate risers 144, which extend from the field plate segments 116 up to the top surface 140 of the substrate 102. Other structures for making electrical connections to the field plate segments 116 are within the scope of this example.
• the trench gate 120 being disposed in the trenches 110 advantageously provides a higher on-state current in the area of the top surface 140 occupied by the transistor 104 compared to a similar vertical MOS transistor with a planar gate.
• a combination of the upper field plate segment 124 and the lower field plate segment 122 provide a RESURF configuration to maintain an electric field in the vertical drift region 108 at a desired value with a higher doping density in the vertical drift region 108 compared to a similar vertical MOS transistor with a single field plate.
• the transistor 104 is enabled to have shallower trenches 110 than the similar vertical MOS transistor with a single field plate, advantageously reducing a fabrication cost of the semiconductor device 100.
• Forming the lower field plate segment 122, the upper field plate segment 124 and the trench gate 120 to be electrically isolated from each other may advantageously enable biasing the lower field plate segment 122 and the upper field plate segment 124 independently to increase current density in the transistor 104.
• FIG. 2A through FIG. 2K are cross sections of the semiconductor device of FIG. 1, depicted in successive stages of fabrication.
• the semiconductor device 100 is formed on the substrate 102, such as a bulk silicon wafer or a silicon wafer with an epitaxial layer extending to the top surface 140.
• the substrate 102 such as a bulk silicon wafer or a silicon wafer with an epitaxial layer extending to the top surface 140.
• Other semiconductor materials in the substrate 102 are within the scope of this example.
• the drain region 106 is formed in the substrate 102 to have a doping density greater than l x lO 20 cm "3 .
• the drain region 106 may be formed by implanting n-type dopants such as antimony and possibly arsenic into the substrate 102, followed by an anneal and epitaxial growth of n-type semiconductor material over the implanted n-type dopants, so that the epitaxial layer provides the vertical drift region 108.
• n-type dopants such as antimony and possibly arsenic
• N-type dopants such as phosphorus in the vertical drift region 108 may be incorporated during epitaxial growth or may be implanted later, followed by a thermal drive to diffuse and activate the implanted dopants.
• a hard mask 146 is formed over the substrate 102, which exposes areas for the trenches 110.
• the hard mask 146 may be several hundred nanometers of silicon dioxide, and may be patterned by etching through a photoresist mask.
• the trenches 1 10 are formed by removing material from the substrate 102 in the areas exposed by the hard mask 146. The material may be removed from the substrate 102 by a timed reactive ion etch (RIE) process to attain a desired depth of the trenches 110.
• RIE reactive ion etch
• the dielectric liner 112 abutting the lower field plate segment 122 of FIG. 1 may be formed as a combined layer of a thermal oxide layer 148 and a first deposited silicon dioxide layer 150.
• the thermal oxide layer 148 is formed at sidewalls and bottoms 114 of the trenches 110.
• the thermal oxide layer 148 may be 50 nanometers to 200 nanometers thick.
• the first deposited silicon dioxide layer 150 is formed on the thermal oxide layer 148.
• the first deposited silicon dioxide layer 150 may be 200 nanometers to 400 nanometers thick, and may be formed by a sub-atmospheric chemical vapor deposition (SACVD) process using dichlorosilane and oxygen.
• SACVD sub-atmospheric chemical vapor deposition
• the first deposited silicon dioxide layer 150 may be formed by a plasma enhanced chemical vapor deposition (PECVD) process using tetraethyl orthosilicate, also known as tetraethoxysilane or TEOS.
• PECVD plasma enhanced chemical vapor deposition
• tetraethyl orthosilicate also known as tetraethoxysilane or TEOS.
• the first deposited silicon dioxide layer 150 may be subsequently densified in an anneal step.
• Other layer structures and other processes for the dielectric liner 112 are within the scope of this example.
• a first polysilicon layer 152 is formed on the dielectric liner 112 and extending over the top surface 140 of the substrate 102.
• the first polysilicon layer 152 may be 500 nanometers to 700 nanometers thick over the top surface 140.
• the first polysilicon layer 152 may be doped with phosphorus, during formation to have an average
• the first polysilicon layer 152 may be doped by ion implanting dopants, such as phosphorus, at a dose of l x lO 14 cm “2 to 5 ⁇ 10 15 cm “2 , and subsequent annealed at 900 °C to 1000 °C for 10 to 60 minutes.
• dopants such as phosphorus
• a blanket etchback process removes polysilicon from the first polysilicon layer 152 of FIG. 2B over the top surface 140 and in the trenches 1 10, leaving polysilicon in the lower portions of the trenches 110 to form the lower field plate segment 122.
• the blanket etchback may be performed using a timed plasma etch including fluorine radicals and/or a timed wet etch using choline, ammonium hydroxide or tetramethyl ammonium hydroxide.
• the blanket etchback may be performed in one or more etch steps. In one version of this example, the blanket etchback does not remove a significant amount of the dielectric liner 112.
• a first blanket oxide etchback process removes at least portion, and possibly all, of the first deposited silicon dioxide layer 150 from over the top surface 140 of the substrate 102 and from the trenches 110 above the lower field plate segment 122.
• the lower field plate segment 122 prevents removal of the first deposited silicon dioxide layer 150 from the trenches 110 below a top of the lower field plate segment 122.
• a majority, and possibly all, of the thermal oxide layer 148 remains on sidewalls of the trenches 110 after the first blanket oxide etchback process is completed.
• the first blanket oxide etchback process may include a timed wet etch using a buffered hydrofluoric acid solution.
• An example buffered hydrofluoric acid solution is 10 parts of 40 percent ammonium fluoride in deionized water and 1 part of 49 percent hydrofluoric acid in deionized water; this buffered hydrofluoric acid exhibits an etch rate of densified SACVD silicon dioxide that is more than twice an etch rate of thermal oxide.
• a second deposited silicon dioxide layer 154 is formed over the thermal oxide layer 148 in the trenches 110 and over the lower field plate segment 122.
• the second deposited silicon dioxide layer 154 may be 160 nanometers to 280 nanometers thick, and may be formed by an SACVD process or a PECVD process.
• the second deposited silicon dioxide layer 154 may be subsequently densified in an anneal step.
• the second deposited silicon dioxide layer 154 combined with the thermal oxide layer 148 provide the dielectric liner 112 abutting the upper field plate segment 124 of FIG. 1.
• a portion of the second deposited silicon dioxide layer 154 on the lower field plate segment 122 provides the first isolation layer 126.
• a second poly silicon layer is formed on the dielectric liner 112 in the trenches 110 and over the top surface 140 of the substrate 102, such as described in reference to FIG. 2B.
• a subsequent etchback process removes the polysilicon from over the top surface 140 and from a top portion of the trenches 110, leaving polysilicon on the second deposited silicon dioxide layer 154 to form the upper field plate segment 124.
• the etchback process may be a timed plasma etch and/or a timed wet etch, such as described in reference to FIG. 2C.
• the upper field plate segment 124 is electrically isolated from the lower field plate segment 122 by the second deposited silicon dioxide layer 154.
• a second blanket oxide etchback process removes the second deposited silicon dioxide layer 154 and the thermal oxide layer 148 from over the top surface 140 of the substrate 102 and from the trenches 110 above the upper field plate segment 124.
• the upper field plate segment 124 prevents removal of the second deposited silicon dioxide layer 154 from the trenches 110 below a top of the upper field plate segment 124.
• a portion of the hard mask 146 may be removed by the second blanket oxide etchback process, as depicted in FIG. 2G.
• the second blanket oxide etchback process may be performed so that substantially no semiconductor material is removed from the substrate 102.
• the gate dielectric layer 118 is formed on sidewalls of the trenches 110 above the upper field plate segment 124, and the second isolation layer 128 are concurrently formed on the upper field plate segment 124.
• the gate dielectric layer 118 and the second isolation layer 128 may be formed by thermal oxidation, or a combination of thermal oxidation and deposition of dielectric material. Removing the thermal oxide layer 148 to expose the sidewalls of the trenches 110 advantageously improves process control of a thickness of the gate dielectric layer 118.
• a third layer pf polysilicon 156 is formed contacting the gate dielectric layer 118 and over the top surface 140 of the substrate 102.
• the third layer of polysilicon 156 may be doped with n-type dopants during formation, or may be subsequently implanted with n-type dopants, followed by an anneal.
• a blanket etchback process removes polysilicon from the third layer pf polysilicon 156 of FIG. 21 from over the top surface 140 of the substrate 102 to leave polysilicon contacting the gate dielectric layer 118 to form the trench gate 120 of the transistor 104.
• the trench gate 120 is electrically isolated from the upper field plate segment 124 by the second isolation layer 128.
• the body 130 is formed by implanting p-type dopants such as boron into the substrate 102 above the vertical drift region 108.
• the trench gate 120 may optionally be covered by an implant mask while the p-type dopants are implanted, to prevent counterdoping the trench gate 120.
• the source 132 is formed by implanting n-type dopants such as phosphorus and arsenic into the substrate 102 above the body 130.
• the substrate 102 is subsequently annealed to activate the implanted dopants.
• the body 130 and source 132 extend across the substrate 102 between adjacent trenches 110.
• the cap layer 136 is formed by deposition of silicon dioxide and optionally a sublayer of silicon nitride.
• the cap layer 136 may be formed by a PECVD process using TEOS.
• source contact opening are formed through the cap layer 136 and through the source 132 into the body 130. Additional p-type dopants may be implanted into the body 130 where exposed by the source contact openings, which provides the downward bulge in the body depicted in FIG. 1.
• the source electrode 134 of FIG. 1 is subsequently formed, and further fabrication provides the structure of FIG. 1.
• FIG. 3 is a cross section of another example semiconductor device containing a vertical n-channel MOS transistor.
• the semiconductor device 300 is formed on a substrate 302, which includes a semiconductor material.
• the n-channel vertical MOS transistor 304 referred to herein as the transistor 304, includes an n-type drain region 306 disposed in the substrate 302 below an n-type vertical drift region 308.
• the semiconductor device 300 includes trenches 310, which extend vertically through the vertical drift region 308 proximate to the drain region 306, or possibly into the drain region 306.
• the trenches 310 contain a dielectric liner 312 extending to bottoms 314 of the trenches 310 and abutting the substrate 302, and multiple field plate segments 316 on the dielectric liner 312.
• the trenches 310 further contain a gate dielectric layer 318 above the dielectric liner 312 abutting the substrate 302, and a trench gate 320 of the transistor 304 contacting the gate dielectric layer 318.
• the field plate segments 316 include respective lower field plate segments 322 on the respective dielectric liners 312 at the bottoms 314 of the trenches 310, and respective upper field plate segments 324 disposed above the respective lower field plate segments 322.
• the field plate segments 316 and the trench gate 320 may include primarily n-type polysilicon.
• the dielectric liner 312 may include primarily silicon dioxide.
• the dielectric liner 312 separates the lower field plate segment 322 and the upper field plate segment 324 from the substrate 302.
• the dielectric liner 312 separating the lower field plate segment 322 from the substrate 302 is thicker than the dielectric liner 312 separating the upper field plate segment 324 from the substrate 302.
• the dielectric liner 312 disposed on the sidewalls of the trenches 310 between the upper field plate segment 324 and the substrate 302 is thicker than the gate dielectric layer 318 disposed on the sidewalls of the trenches 310 between the trench gate 320 and the substrate 302.
• the dielectric liner 312 disposed on the sidewalls of the trenches 310 between the lower field plate segment 322 and the substrate 302 may be 100 nanometers to 150 nanometers thick, and the dielectric liner 312 disposed on the sidewalls of the trenches 310 between the upper field plate segment 324 and the substrate 302 may be 50 nanometers to 80 nanometers thick.
• the lower field plate segment 322 is contacting the upper field plate segment 324 in the trenches 310.
• the upper field plate segment 324 is contacting the trench gate 320 in the trenches 310.
• a bias voltage applied to the trench gate 320 in this example also biases the upper field plate segment 324 and the lower field plate segment 322 to the same bias voltage.
• the transistor 304 include a p-type body 330 in the substrate 302 above the vertical drift region 308, abutting the gate dielectric layer 318.
• the transistor 304 further includes an n-type source 332 above the body 330 and abutting the gate dielectric layer 318.
• the trench gate 320 is partially coextensive with the vertical drift region 308 and the source 332.
• a source electrode 334 is disposed over the substrate 302 making electrical contact to the source 332 and the body 330.
• the source electrode 334 is electrically isolated from the trench gate 320 by a dielectric cap layer 336 over the trench gate 320.
• Other configurations for the source electrode 334 with respect to the source 332 and body 330 are within the scope of this example.
• the trenches 310 may be 2.2 microns to 2.8 microns deep and 600 nanometers to 700 nanometers wide.
• the vertical drift region 308 may be 500 nanometers to 1.5 microns wide, that is, between adjacent trenches 310, and have an average doping density of 1.8 ⁇ 10 16 cm “3 to 2.0x l0 16 cm “3 .
• Electrical connection to the trench gate 320 may be made through gate contacts 338 on exposed areas of the gate at a top surface 340 of the substrate 302.
• Other structures for making electrical connections to the trench gate 320 are within the scope of this example. Forming the upper field plate segment 324 to contact the trench gate 320 in the trenches 310, and forming the lower field plate segment 322 to contact the upper field plate segment 324 in the trenches 310, so that electrical connections to the upper field plate segment 324 and the lower field plate segment 322 may be made through the gate contacts 338 may advantageously reduce complexity and fabrication cost of the semiconductor device 300.
• the trench gate 320 advantageously provides higher current density as explained in reference to FIG. 1.
• the field plate segments 316 provide a RESURF configuration to maintain an electric field in the vertical drift region 308 at a desired value, as explained in reference to FIG. 1. Accordingly, by forming the vertical MOS transistor 304 with the combination of the upper field plate segment 324 and the lower field plate segment 322, the transistor 304 is enabled to have shallower trenches 310 than the similar vertical MOS transistor with a single field plate, advantageously reducing a fabrication cost of the semiconductor device 300.
• FIG. 4A through FIG. 4E are cross sections of the semiconductor device of FIG. 3, depicted in successive stages of fabrication.
• the semiconductor device 300 is formed on the substrate 302.
• the drain region 306 is formed in the substrate 302 to have a doping density greater than 1 x 10 20 cm "3 .
• N-type dopants such as phosphorus in the vertical drift region 308 may be incorporated during epitaxial growth or may be implanted later.
• a hard mask 346 is formed over the substrate 302, which exposes areas for the trenches 310.
• the trenches 310 are formed by removing material from the substrate 302 in the areas exposed by the hard mask 346.
• the drain region 306, hard mask 346 and trenches 310 may be formed as described in reference to FIG. 2A.
• a thermal oxide layer 348 is formed at sidewalls and bottoms 314 of the trenches 310.
• the thermal oxide layer 348 is sufficiently thick to provide the complete dielectric liner 312 disposed on the sidewalls of the trenches 310 between the upper field plate segment 324 of FIG. 3 and the substrate 302, such as 70 nanometers to 80 nanometers thick for an operating voltage of 40 volts.
• a deposited silicon dioxide layer 350 is formed on the thermal oxide layer 348.
• the deposited silicon dioxide layer 350 may be 130 nanometers to 170 nanometers thick, formed by an SACVD process or a PECVD process.
• a lower field plate segment 322 is formed in the trenches 310 on the deposited silicon dioxide layer 350, such as described in reference to FIG. 2B and FIG. 2C.
• the thermal oxide layer 348 combined with the deposited silicon dioxide layer 350 provide the dielectric liner 312 separating the lower field plate segment 322 from the substrate 302.
• a first blanket oxide etchback process removes at least portion, and possibly all, of the deposited silicon dioxide layer 350 from the trenches 310 above the lower field plate segment 322.
• the lower field plate segment 322 prevents removal of the deposited silicon dioxide layer 350 from the trenches 310 below a top of the lower field plate segment 322.
• substantially all of the thermal oxide layer 348 remains on sidewalls of the trenches 310 after the first blanket oxide etchback process is completed.
• the first blanket oxide etchback process exposes a top of the lower field plate segment 322.
• an upper field plate segment 324 is formed on the thermal oxide layer 348 and on the lower field plate segment 322 in the trenches 310, such as described in reference to FIG. 2F.
• the thermal oxide layer 348 provides the dielectric liner 312 separating the upper field plate segment 324 from the substrate 302, which may advantageously reduce fabrication complexity and cost of the semiconductor device 300.
• a second blanket oxide etchback process removes the thermal oxide layer 348 from the trenches 310 above the upper field plate segment 324.
• the upper field plate segment 324 prevents removal of the thermal oxide layer 348 from the trenches 310 below a top of the upper field plate segment 324.
• the second blanket oxide etchback process may be performed so that substantially no semiconductor material is removed from the substrate 302.
• the gate dielectric layer 318 is formed on sidewalls of the trenches 310 above the upper field plate segment 324, and dielectric material 358 is concurrently formed on the upper field plate segment 324.
• the gate dielectric layer 318 may be formed by thermal oxidation, or a combination of thermal oxidation and deposition of dielectric material. Removing the thermal oxide layer 348 to expose the sidewalls of the trenches 310 advantageously improves process control of a thickness of the gate dielectric layer 318.
• the dielectric material 358 on the upper field plate segment 324 may be thicker than the gate dielectric layer 318 due to a higher thermal oxide growth rate on polysilicon compared to crystalline silicon.
• an anisotropic etch process such as an RLE process removes the dielectric material 358 of FIG. 4C from the top of the upper field plate segment 324 without significantly degrading the gate dielectric layer 318.
• the gate dielectric layer 318 may be protected by a sacrificial layer of polysilicon or silicon nitride, while the dielectric material 358 is removed, after which the sacrificial layer is removed without significantly degrading the gate dielectric layer 318.
• the trench gate 320 is formed contacting the gate dielectric layer 318 and the upper field plate segment 324.
• the trench gate 320 may be formed as described in reference to FIG. 21 and FIG. 2J.
• removing the dielectric material 358 of FIG. 4C from the top of the upper field plate segment 324 enables the trench gate 320 to make electrical contact with the upper field plate segment 324. Further fabrication provides the structure of FIG. 3.
• FIG. 5 is a cross section of an example semiconductor device containing a vertical p-channel MOS transistor.
• the semiconductor device 500 is formed on a substrate 502, which includes a semiconductor material.
• the p-channel vertical MOS transistor 504, referred to herein as the transistor 504, includes a p-type drain region 506 disposed in the substrate 502 below a p-type vertical drift region 508.
• the semiconductor device 500 includes trenches 510, which extend vertically through the vertical drift region 508 proximate to the drain region 506, or possibly into the drain region 506.
• the trenches 510 contain a dielectric liner 512 extending to bottoms 514 of the trenches 510 and abutting the substrate 502, and multiple field plate segments 516 on the dielectric liner 512.
• the trenches 510 further contain a gate dielectric layer 518 above the dielectric liner 512 abutting the substrate 502, and a trench gate 520 of the transistor 504 contacting the gate dielectric layer 518.
• the field plate segments 516 include respective lower field plate segments 522 on the respective dielectric liners 512 at the bottoms 514 of the trenches 510, and respective upper field plate segments 524 disposed above the respective lower field plate segments 522.
• the field plate segments 516 and the trench gate 520 may include primarily p-type polysilicon.
• the dielectric liner 512 may include primarily silicon dioxide.
• the dielectric liner 512 separates the lower field plate segment 522 and the upper field plate segment 524 from the substrate 502.
• the dielectric liner 512 separating the lower field plate segment 522 from the substrate 502 is thicker than the dielectric liner 512 separating the upper field plate segment 524 from the substrate 502.
• the dielectric liner 512 disposed on the sidewalls of the trenches 510 between the upper field plate segment 524 and the substrate 502 is thicker than the gate dielectric layer 518 disposed on the sidewalls of the trenches 510 between the trench gate 520 and the substrate 502.
• the dielectric liner 512 disposed on the sidewalls of the trenches 510 between the lower field plate segment 522 and the substrate 502 may be 400 nanometers to 500 nanometers thick
• the dielectric liner 512 disposed on the sidewalls of the trenches 510 between the upper field plate segment 524 and the substrate 502 may be 150 nanometers to 200 nanometers thick.
• the lower field plate segment 522 is contacting the upper field plate segment 524 in the trenches 510.
• the upper field plate segment 524 is isolated from the trench gate 520 by an isolation layer 528, disposed between the upper field plate segment 524 and the trench gate 520.
• a bias voltage applied to the upper field plate segment 524 in this example also biases the lower field plate segment 522 to the same bias voltage.
• the transistor 504 includes an n-type body 530 in the substrate 502 above the vertical drift region 508, abutting the gate dielectric layer 518.
• the transistor 504 further includes a p-type source 532 above the body 530 and abutting the gate dielectric layer 518.
• the trench gate 520 is partially coextensive with the vertical drift region 508 and the source 532.
• a source electrode 534 is disposed over the substrate 502 making electrical contact to the source 532 and the body 530.
• the source electrode 534 is electrically isolated from the trench gate 520 by a dielectric cap layer 536 over the trench gate 520.
• Other configurations for the source electrode 534 with respect to the source 532 and body 530 are within the scope of this example.
• the trenches 510 may be 6 microns to 7 microns deep and 1.2 microns to 1.4 microns wide.
• the vertical drift region 508 may be 0.5 microns to 2.0 microns wide, that is, between adjacent trenches 510, and have an average doping density of 1.8 ⁇ 10 cm " to 2. Ox 10 cm " .
• Electrical connection to the trench gate 520 may be made through gate contacts 538 on exposed areas of the gate at a top surface 540 of the substrate 502. Electrical connections to the field plate segments 516 may be made through combined field plate contacts 542 on field plate risers 544, which extend from the field plate segments 516 up to the top surface 540 of the substrate 502. Other structures for making electrical connections to the trench gate 520 and the field plate segments 516 are within the scope of this example.
• Forming the upper field plate segment 524 to be isolated from the trench gate 520 may advantageously enable biasing the field plate segments 516 independently to increase current density in the transistor 504, while forming the lower field plate segment 522 to contact the upper field plate segment 524 in the trenches 510, so that electrical connections to the upper field plate segment 524 and the lower field plate segment 522 may be made through the combined field plate contacts 542 may advantageously reduce complexity and fabrication cost of the semiconductor device 500.
• the trench gate 520 advantageously provides higher current density as explained in reference to FIG. 1.
• the field plate segments 516 provide a RESURF configuration to maintain an electric field in the vertical drift region 508 at a desired value, as explained in reference to FIG. 1. Accordingly, by forming the vertical MOS transistor 504 with the combination of the upper field plate segment 524 and the lower field plate segment 522, the transistor 504 is enabled to have shallower trenches 510 than the similar vertical MOS transistor with a single field plate, advantageously reducing a fabrication cost of the semiconductor device 500.
• FIG. 6A through FIG. 6H are cross sections of the semiconductor device of FIG. 5, depicted in successive stages of fabrication.
• the semiconductor device 500 is formed on the substrate 502.
• the drain region 506 is formed in the substrate 502 to have a doping density greater than 1 x 10 20 cm "3 .
• P-type dopants such as boron in the vertical drift region 508 may be incorporated during epitaxial growth or may be implanted later.
• a hard mask 546 is formed over the substrate 502, which exposes areas for the trenches 510.
• the trenches 510 are formed by removing material from the substrate 502 in the areas exposed by the hard mask 546.
• the drain region 506, hard mask 546 and trenches 510 may be formed as described in reference to FIG. 2A.
• a first thermal oxide layer 548 is formed at sidewalls and bottoms 514 of the trenches 510.
• a deposited silicon dioxide layer 550 is formed on the first thermal oxide layer 548, by an SACVD process or a PECVD process.
• a lower field plate segment 522 is formed in the trenches 510 on the deposited silicon dioxide layer 550, such as described in reference to FIG. 2B and FIG. 2C.
• the lower field plate segment 522 may be p-type polysilicon to provide an effective charge balance in the RESURF structure of the vertical drift region 508.
• the first thermal oxide layer 548 combined with the deposited silicon dioxide layer 550 provide the dielectric liner 512 separating the lower field plate segment 522 from the substrate 502.
• the first thermal oxide layer 548 may be 70 nanometers to 80 nanometers thick
• the deposited silicon dioxide layer 550 may be 330 nanometers to 420 nanometers thick, for an operating voltage of 100 volts.
• a first blanket oxide etchback process removes substantially all of the dielectric liner 512, both the first thermal oxide layer 548 and the deposited silicon dioxide layer 550, from the trenches 510 above the lower field plate segment 522.
• the lower field plate segment 522 prevent removal of the dielectric liner 512 from the trenches 510 below tops of the lower field plate segment 522.
• the first blanket oxide etchback process may include a timed wet etch using a buffered hydrofluoric acid solution.
• a second thermal oxide layer 560 is formed at sidewalls of the trenches 510 above the lower field plate segment 522, and on a top surface of the lower field plate segment 522.
• the second thermal oxide layer 560 provides the dielectric liner 512 between the upper field plate segment 524 of FIG. 5 and the substrate 502.
• the second thermal oxide layer 560 may be 150 nanometers to 200 nanometers thick to provide 100 volt operation for the transistor 504.
• an anisotropic etch process such as an RIE process removes the second thermal oxide layer 560 from the top surface of the lower field plate segment 522, to expose the top surface of the lower field plate segment 522.
• the anisotropic etch process is performed to avoid significantly degrading the second thermal oxide layer 560 on the sidewalls of the trenches 510.
• the anisotropic etch process may form a protective polymer on the second thermal oxide layer 560 on the sidewalls of the trenches 510, which is subsequently removed after the top surface of the lower field plate segment 522 is exposed.
• an upper field plate segment 524 is formed on the second thermal oxide layer 560 and on the lower field plate segment 522 in the trenches 510, such as described in reference to FIG. 2F.
• the upper field plate segment 524 may be p-type polysilicon, as explained in reference to FIG. 6E.
• the second thermal oxide layer 560 provides the dielectric liner 512 separating the upper field plate segment 524 from the substrate 502, which may advantageously reduce fabrication complexity and cost of the semiconductor device 500 be eliminating need to form a second dielectric layer in the dielectric liner 512 separating the upper field plate segment 524 from the substrate 502.
• a second blanket oxide etchback process removes the second thermal oxide layer 560 from the trenches 510 above the upper field plate segment 524.
• the upper field plate segment 524 prevents removal of the second thermal oxide layer 560 from the trenches 510 below a top of the upper field plate segment 524.
• the second blanket oxide etchback process may be performed so that substantially no semiconductor material is removed from the substrate 502.
• the hard mask 546 of FIG. 6E may be removed by the second blanket etchback to expose the top surface 540 of the substrate 502, as depicted in FIG. 6F.
• the gate dielectric layer 518 is formed on sidewalls of the trenches 510 and the isolation layer 528 is formed on a top surface of the upper field plate segment 524, concurrently.
• the gate dielectric layer 518 may also be formed on the top surface 540 as depicted in FIG. 6G.
• the gate dielectric layer 518 and the isolation layer 528 may be formed by thermal oxidation, or a combination of thermal oxidation and deposition of dielectric material. Thermal oxide in the isolation layer 528 may be thicker than thermal oxide in the gate dielectric layer 518, due to a higher thermal oxide growth rate on polysilicon compared to crystalline silicon.
• the trench gate 520 is formed contacting the gate dielectric layer 518 and the isolation layer 528.
• the trench gate 520 may be formed as described in reference to FIG. 21 and FIG. 2J.
• the isolation layer 528 on the top of the upper field plate segment 524 electrically isolates the field plate segments 516 from the trench gate 520, enabling an independent bias of the field plate segments 516 with respect to the trench gate 520. Further fabrication provides the structure of FIG. 5.
• FIG. 7 is a cross section of another example semiconductor device containing a vertical n-channel MOS transistor.
• the semiconductor device 700 is formed on a substrate 702, which includes a semiconductor material.
• the n-channel vertical MOS transistor 704, referred to herein as the transistor 704, includes an n-type drain region 706 disposed in the substrate 702 below an n-type vertical drift region 708.
• the semiconductor device 700 includes trenches 710, which extend vertically through the vertical drift region 708 proximate to the drain region 706, or possibly into the drain region 706.
• the trenches 710 contain a dielectric liner 712 extending to bottoms 714 of the trenches 710 and abutting the substrate 702, and multiple field plate segments 716 on the dielectric liner 712.
• the trenches 710 further contain a gate dielectric layer 718 above the dielectric liner 712 abutting the substrate 702, and a trench gate 720 of the transistor 704 contacting the gate dielectric layer 718.
• the field plate segments 716 include respective lower field plate segments 722 on the respective dielectric liners 712 at the bottoms 714 of the trenches 710, respective middle field plate segments 762 disposed above the respective lower field plate segments 722, and respective upper field plate segments 724 disposed above the respective middle field plate segments 762 and below the respective trench gates 720.
• the field plate segments 716 and the trench gate 720 may include primarily n-type poly silicon.
• the dielectric liner 712 may include primarily silicon dioxide. The dielectric liner 712 separates the lower field plate segment 722, the middle field plate segment 762 and the upper field plate segment 724 from the substrate 702.
• the dielectric liner 712 separating the lower field plate segment 722 from the substrate 702 is thicker than the dielectric liner 712 separating the middle field plate segment 762 from the substrate 702, which is in turn thicker than the dielectric liner 712 separating the upper field plate segment 724 from the substrate 702.
• the dielectric liner 712 disposed on the sidewalls of the trenches 710 between the upper field plate segment 724 and the substrate 702 is thicker than the gate dielectric layer 718 disposed on the sidewalls of the trenches 710 between the trench gate 720 and the substrate 702.
• the lower field plate segment 722 is contacting the middle field plate segment 762 in the trenches 710
• the upper field plate segment 724 is contacting the trench gate 720 in the trenches 710
• the middle field plate segment 762 is separated from the upper field plate segment 724 by an isolation layer 726, disposed between the upper field plate segment 724 and the trench gate 720.
• a bias voltage applied to the trench gate 720 is also thus applied to the upper field plate segment 724 in this example, while an independent bias voltage applied to the middle field plate segment 762 also biases the lower field plate segment 722 to the same independent bias voltage.
• the transistor 704 includes a p-type body 730 in the substrate 702 above the vertical drift region 708, abutting the gate dielectric layer 718.
• the transistor 704 further includes an n-type source 732 above the body 730 and abutting the gate dielectric layer 718.
• the trench gate 720 is partially coextensive with the vertical drift region 708 and the source 732.
• a source electrode 734 is disposed over the substrate 702 making electrical contact to the source 732 and the body 730.
• the source electrode 734 is electrically isolated from the trench gate 720 by a dielectric cap layer 736 over the trench gate 720.
• Other configurations for the source electrode 734 with respect to the source 732 and body 730 are within the scope of this example.
• Electrical connection to the trench gate 720 and the upper field plate segment 724 may be made through gate contacts 738 on exposed areas of the gate at a top surface 740 of the substrate 702. Electrical connections to the middle field plate segment 762 and the lower filed plate segment 722 may be made through combined field plate contacts 742 on field plate risers 744, which extend from the middle field plate segment 762 up to the top surface 740 of the substrate 702. Other structures for making electrical connections to the trench gate 720 and the middle field plate segment 762 are within the scope of this example.
• Forming the trench gate 720 and the upper field plate segment 724 to be isolated from the middle field plate segment 762 and the lower field plate segment 722 may advantageously enable a balance of the advantages of independent biases for the trench gate 720 and the field plate segments 716 as discussed in reference to FIG. 1, and the advantages of the combined field plate contacts 742 as discussed in reference to FIG. 3.
• the trench gate 720 advantageously provides higher current density as explained in reference to FIG. 1.
• the field plate segments 716 provide a RESURF configuration to maintain an electric field in the vertical drift region 708 at a desired value, as explained in reference to FIG. 1. Accordingly, by forming the vertical MOS transistor 704 with the combination of the upper field plate segment 724 and the lower field plate segment 722, the transistor 704 is enabled to have shallower trenches 710 than the similar vertical MOS transistor with a single field plate, advantageously reducing a fabrication cost of the semiconductor device 700.

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