CN108598165B - 屏蔽栅场效应晶体管及其制造方法(柱形) - Google Patents

屏蔽栅场效应晶体管及其制造方法(柱形) Download PDF

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CN108598165B
CN108598165B CN201810351439.7A CN201810351439A CN108598165B CN 108598165 B CN108598165 B CN 108598165B CN 201810351439 A CN201810351439 A CN 201810351439A CN 108598165 B CN108598165 B CN 108598165B
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张帅
黄昕
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Jinan Anhai Semiconductor Co., Ltd
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Abstract

本发明涉及一种屏蔽栅场效应晶体管及其制造方法，属于半导体技术领域。由于该屏蔽栅场效应晶体管的制造方法中，在完成沟槽底部的第一次屏蔽栅掺杂多晶硅淀积后，刻蚀减薄了屏蔽栅侧壁氧化层，再进行第二次屏蔽栅掺杂多晶硅淀积，因此利用该方法形成的屏蔽栅场效应晶体管的屏蔽栅底部的氧化层厚度较其它位置更厚，可以达到减弱屏蔽栅底部电场的目的，从而避免屏蔽栅底部击穿，提升器件耐用性，且本发明的屏蔽栅场效应晶体管的结构简单，其制造方法工艺简便，成本也相当低廉。

Description

屏蔽栅场效应晶体管及其制造方法(柱形)
技术领域
本发明涉及半导体技术领域，特别涉及场效应晶体管技术领域，具体是指一种屏蔽栅场效应晶体管及其制造方法。
背景技术
随着电子信息技术的迅速发展，特别是像时尚消费电子和便携式产品的快速发展，金属氧化物半导体场效应晶体管(MOSFET)等功率器件的需求量越来越大，MOSFET主要分为横向和纵向两种，横向MOSFET的明显优势是其较好的集成性，可以更容易集成到现有技术的工艺平台上，但由于其耐压的漂移区在表面展开，显示出了其最大的不足，占用的面积较大，面积代表成本，耐压越高的器件，劣势越明显，而纵向MOSFET很好的避免了这一问题，因此，超高压的分立器件仍然以纵向为主。
图1为传统的沟槽型纵向场效应晶体管。为了满足高频应用，对电容的要求越来越高，带有屏蔽栅结构的沟槽型场效应晶体管得到了广泛的应用，基本结构如图2所示。随着电压应用的增大，这种结构的弱点就会越来越明显，如图3所示，屏蔽栅底部为器件电场最强的位置，容易被击穿。因此，如何降低屏蔽栅底部电场，防止其被击穿，成为本领域亟待解决的问题。
发明内容
本发明的目的是克服了上述现有技术中的缺点，提供一种通过优化屏蔽栅底部的氧化层的厚度实现减弱屏蔽栅底部电场的目的，从而避免屏蔽栅底部击穿，提升器件耐用性，且结构简单，生产工艺简便，成本低廉的屏蔽栅场效应晶体管及其制造方法。
为了实现上述的目的，本发明的屏蔽栅场效应晶体管的制造方法包括以下步骤：
(1)在作为漏极的N+衬底上利用外延生长工艺产生N-区；
(2)在所述的N-区上设置掩模版进行刻蚀形成位于该N-区内的沟槽；
(3)氧化修复所述沟槽的缺陷，并在器件表面淀积屏蔽栅氧化层；
(4)在所述沟槽底部进行屏蔽栅掺杂多晶硅淀积并回刻；
(5)刻蚀位于所述沟槽底部上方屏蔽栅侧壁的氧化层，减薄屏蔽栅侧壁氧化层；
(6)在所述沟槽内进行屏蔽栅第二次掺杂多晶硅淀积并回刻；
(7)对所述的屏蔽栅顶部进行多晶硅氧化；
(8)在所述的沟槽内淀积氧化层，回刻，并去除所述的掩模版；
(9)在所述的N-区顶部进行P-body区注入和退火，形成P-body区；
(10)进行器件栅刻蚀、栅氧化、多晶硅淀积并刻蚀，形成位于所述沟槽顶部的栅极；
(11)在所述的P-body区顶部沿所述的沟道进行N+注入；
(12)利用后段工艺在器件顶部形成源极。
该屏蔽栅场效应晶体管的制造方法中，所述的掩模版为氮化硅。
该屏蔽栅场效应晶体管的制造方法中，所述的步骤(5)具体为，湿法刻蚀位于所述沟槽底部上方屏蔽栅侧壁的氧化层，减薄屏蔽栅侧壁氧化层。
该屏蔽栅场效应晶体管的制造方法中，所述的步骤(12)具体为，利用后段工艺，设置层间介质层，P+注入及金属连线在器件顶部形成源极。
本发明还提供一种利用上述制造方法制成的屏蔽栅场效应晶体管，其位于所述沟槽底部的屏蔽栅氧化层的厚度为0.7至1.7μm。
采用了该发明屏蔽栅场效应晶体管及其制造方法，由于其在完成沟槽底部的第一次屏蔽栅掺杂多晶硅淀积后，刻蚀减薄了屏蔽栅侧壁氧化层，再进行第二次屏蔽栅掺杂多晶硅淀积，因此其屏蔽栅底部的氧化层的厚度较其它位置更厚，达到减弱屏蔽栅底部电场的目的，从而避免屏蔽栅底部击穿，提升器件耐用性，且本发明的屏蔽栅场效应晶体管的结构简单，其制造方法工艺简便，成本也相当低廉。
附图说明
图1为传统沟槽型纵向场效应晶体管结构示意图。
图2为现有技术中的带有屏蔽栅结构的沟槽型场效应晶体管结构示意图。
图3为现有技术中的带有屏蔽栅结构的沟槽型场效应晶体管屏蔽栅底部击穿点示意图。
图4为本发明的屏蔽栅场效应晶体管及其制造方法的流程示意图。
图5为本发明的屏蔽栅场效应晶体管及其制造方法中EPI生长工艺示意图。
图6为本发明的屏蔽栅场效应晶体管及其制造方法中沟槽刻蚀示意图。
图7为本发明的屏蔽栅场效应晶体管及其制造方法中淀积屏蔽栅氧化层示意图。
图8为本发明的屏蔽栅场效应晶体管及其制造方法中第一次多晶硅淀积示意图。
图9为本发明的屏蔽栅场效应晶体管及其制造方法中减薄屏蔽栅侧壁氧化层示意图。
图10为本发明的屏蔽栅场效应晶体管及其制造方法中第二次多晶硅淀积示意图。
图11为本发明的屏蔽栅场效应晶体管及其制造方法中屏蔽栅多晶硅氧化示意图。
图12为本发明的屏蔽栅场效应晶体管及其制造方法中淀积氧化层、去除掩模版示意图。
图13为本发明的屏蔽栅场效应晶体管及其制造方法中P-body区注入和退火示意图。
图14为本发明的屏蔽栅场效应晶体管及其制造方法中进行器件栅刻蚀、栅氧化、多晶硅淀积并刻蚀示意图。
图15为本发明的屏蔽栅场效应晶体管及其制造方法中进行N+注入示意图。
图16为本发明的屏蔽栅场效应晶体管的结构示意图。
图17为本发明的屏蔽栅场效应晶体管与传统屏蔽栅场效应晶体管的底部电场分布对比示意图。
具体实施方式
为了能够更清楚地理解本发明的技术内容，特举以下实施例详细说明。
请参阅图4所示，为本发明的屏蔽栅场效应晶体管及其制造方法的流程示意图。
在一种实施方式中，该屏蔽栅场效应晶体管的制造方法，包括以下步骤：
(1)如图5所示，在作为漏极的N+衬底上利用外延生长工艺产生N-区；
(2)如图6所示，在所述的N-区上设置氮化硅掩模版进行刻蚀形成位于该N-区内的沟槽；
(3)如图7所示，氧化修复所述沟槽的缺陷，并在器件表面淀积屏蔽栅氧化层；
(4)如图8所示，在所述沟槽底部进行屏蔽栅掺杂多晶硅淀积并回刻；
(5)如图9所示，刻蚀位于所述沟槽底部上方屏蔽栅侧壁的氧化层，减薄屏蔽栅侧壁氧化层；
(6)如图10所示，在所述沟槽内进行屏蔽栅第二次掺杂多晶硅淀积并回刻；
(7)如图11所示，对所述的屏蔽栅顶部进行多晶硅氧化；
(8)如图12所示，在所述的沟槽内淀积氧化层，回刻，并去除所述的掩模版；
(9)如图13所示，在所述的N-区顶部进行P-body区注入和退火，形成P-body区；
(10)如图14所示，进行器件栅刻蚀、栅氧化、多晶硅淀积并刻蚀，形成位于所述沟槽顶部的栅极；
(11)如图15所示，在所述的P-body区顶部沿所述的沟道进行N+注入；
(12)如图16所示，利用后段工艺在器件顶部形成源极。
在优选的实施方式中，
所述的步骤(5)具体为，湿法刻蚀位于所述沟槽底部上方屏蔽栅侧壁的氧化层，减薄屏蔽栅侧壁氧化层。
所述的步骤(12)具体为，利用后段工艺，设置层间介质层，P+注入及金属连线在器件顶部形成源极。
本发明还提供一种利用上述制造方法制成的屏蔽栅场效应晶体管，其结构如图16所示。在优选的实施方式中，位于所述沟槽底部的屏蔽栅氧化层的厚度为0.7至1.7μm。
在本发明的应用中，屏蔽栅底部的氧化层的厚度可根据不同的应用而有所不同。本发明可以涵盖20V～250V的广泛应用范围，以100V应用为例，传统技术屏蔽栅底部的氧化层的厚度大概在0.5～0.7um的范围，而本发明的厚度大致为传统厚度的1.2～2倍；
增大底部氧化层厚度一方面可以承担更大的电场进而得到更高的击穿电压。本发明与传统结构底部电场分布对比如图17所示。本发明中更厚的底部二氧化硅可以有效降低N-外延层(硅)中的电场强度(本发明电场强度E1<传统结构电场强度E2)，进而可以更晚到达临界电场，从而得到更高的击穿电压。
另一方面，同增大底部氧化层厚度还可以进一步减小漏极与源极之间的寄生电容；根据平板电容的理论，C＝εA/d，其中ε为介质层二氧化硅的介电常数，A为面积，d为介质层厚度，因此，Cds会随着介质层厚度d的增大而减小。
采用了该发明屏蔽栅场效应晶体管及其制造方法，由于其在完成沟槽底部的第一次屏蔽栅掺杂多晶硅淀积后，刻蚀减薄了屏蔽栅侧壁氧化层，再进行第二次屏蔽栅掺杂多晶硅淀积，因此其屏蔽栅底部的氧化层的厚度较其它位置更厚，达到减弱屏蔽栅底部电场的目的，从而避免屏蔽栅底部击穿，提升器件耐用性，且本发明的屏蔽栅场效应晶体管的结构简单，其制造方法工艺简便，成本也相当低廉。
在此说明书中，本发明已参照其特定的实施例作了描述。但是，很显然仍可以作出各种修改和变换而不背离本发明的精神和范围。因此，说明书和附图应被认为是说明性的而非限制性的。

Claims (6)

1.一种屏蔽栅场效应晶体管的制造方法，其特征在于，该方法包括以下步骤：
(1)在作为漏极的N+衬底上利用外延生长工艺产生N-区；
(2)在所述的N-区上设置掩模版进行刻蚀形成位于该N-区内的沟槽；
(3)氧化修复所述沟槽的缺陷，并在器件表面淀积屏蔽栅氧化层；
(4)在所述沟槽底部进行屏蔽栅掺杂多晶硅淀积并回刻；
(5)刻蚀位于所述沟槽底部上方屏蔽栅侧壁的氧化层，减薄屏蔽栅侧壁氧化层；
(6)在所述沟槽内进行屏蔽栅第二次掺杂多晶硅淀积并回刻；
(7)对所述的屏蔽栅顶部进行多晶硅氧化；
(8)在所述的沟槽内淀积氧化层，回刻，并去除所述的掩模版；
(9)在所述的N-区顶部进行P-body区注入和退火，形成P-body区；
(10)进行器件栅刻蚀、栅氧化、多晶硅淀积并刻蚀，形成位于所述沟槽顶部的栅极；
(11)在所述的P-body区顶部沿所述的沟槽进行N+注入；
(12)利用后段工艺在器件顶部形成源极。
2.根据权利要求1所述的屏蔽栅场效应晶体管的制造方法，其特征在于，所述的掩模版为氮化硅。
3.根据权利要求1所述的屏蔽栅场效应晶体管的制造方法，其特征在于，所述的步骤(5)具体为，
湿法刻蚀位于所述沟槽底部上方屏蔽栅侧壁的氧化层，减薄屏蔽栅侧壁氧化层。
4.根据权利要求1所述的屏蔽栅场效应晶体管的制造方法，其特征在于，所述的步骤(12)具体为，
利用后段工艺，设置层间介质层，P+注入及金属连线在器件顶部形成源极。
5.一种屏蔽栅场效应晶体管，其特征在于，利用权利要求1至4中任一项所述的制造方法制成。
6.根据权利要求5所述的屏蔽栅场效应晶体管，其特征在于，位于所述沟槽底部的屏蔽栅氧化层的厚度为0.7至1.7μm。
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