WO2016161901A1 - 一种可适应负阈值电压的移位寄存器及其单元 - Google Patents

一种可适应负阈值电压的移位寄存器及其单元 Download PDF

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Publication number
WO2016161901A1
WO2016161901A1 PCT/CN2016/077263 CN2016077263W WO2016161901A1 WO 2016161901 A1 WO2016161901 A1 WO 2016161901A1 CN 2016077263 W CN2016077263 W CN 2016077263W WO 2016161901 A1 WO2016161901 A1 WO 2016161901A1
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Prior art keywords
transistor
terminal
low level
shift register
clock
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PCT/CN2016/077263
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English (en)
French (fr)
Inventor
张盛东
胡治晋
廖聪维
李君梅
李文杰
曹世杰
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Peking University Shenzhen Graduate School
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Peking University Shenzhen Graduate School
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements

Definitions

  • the present application relates to the field of flat panel display, and more particularly to the field of shift registers.
  • the integrated display driving circuit refers to a peripheral circuit such as a gate driving circuit and a data driving circuit being fabricated on a display panel together with a pixel thin film transistor in the form of a thin film transistor (TFT), thereby reducing the number of peripheral driving chips and the voltage sealing thereof.
  • TFT thin film transistor
  • the threshold voltage of the existing oxide thin film transistor tends to be negative, which may cause some transistors in the shift register to fail to be normally turned off to generate leakage. Leakage of the transistor not only increases the power consumption of the circuit, but also causes the circuit to fail in severe cases.
  • the existing circuit design suppresses the circuit leakage by adding a low potential source, multiple sets of clock signals, adopting a feedback structure and a floating gate structure, but the circuit is still complicated. Higher cost and higher power consumption issues. Therefore, how to effectively suppress the leakage of the shift register circuit, so that the shift register circuit can work normally when the transistor is a negative threshold voltage, and also reduce power consumption and cost, becomes a research value.
  • the present application provides a shift register unit, including:
  • a clock signal input terminal for inputting a clock signal (V CK );
  • a first pulse signal input terminal for inputting a first pulse signal (V I1 );
  • a second pulse signal input terminal for inputting a second pulse signal (V I2 );
  • a third pulse signal input terminal for inputting a third pulse signal (V I3 );
  • a scan signal output terminal for outputting a scan signal (V G );
  • V DD High level terminal for inputting high level (V H );
  • V SS1 a first low level terminal for inputting a first low level (V L1 );
  • V SS2 a second low level terminal for inputting a second low level (V L2 );
  • V SS3 a third low level terminal for inputting a third low level (V L3 );
  • a driving module (12) comprising a driving control terminal (Q) and a first driving submodule (121); the first driving submodule (121) is connected to the driving control terminal (Q), a clock signal input end and a scan Between the signal output terminals, the clock signal (V CK ) is transmitted to the scan signal output terminal when the drive control terminal (Q) is at a high level;
  • a charging module (11) connected between the first pulse signal input end, the second pulse signal input end and the drive control end (Q) for the first pulse signal input end (I1) and the second pulse signal
  • the drive control terminal (Q) is charged to a high level
  • a discharge module (13) connected between the second pulse signal input end, the third pulse signal input end and the drive control end (Q), for when the second pulse signal input end is low level and the third pulse When the signal input terminal is high level, the driving control terminal (Q) is discharged to a low level;
  • a low level maintenance module (14) comprising a maintenance control terminal (P), a maintenance control submodule (141) and a maintenance submodule (142); a maintenance control submodule (141) connected to the clock signal input terminal, high power The flat terminal (V DD ), the second low level terminal (V SS2 ) and the maintenance control terminal (P); the maintenance submodule (142) is connected to the driving control terminal (Q), the first low level end ( V SS1 ), between the third low level terminal (V SS3 ) and the sustain control terminal (P); the maintenance control submodule (141) is configured to control the maintenance submodule (142) when the driving control terminal (Q) is low level Maintaining the scan signal (V G ) to a first low level (V L1 );
  • the clock signal (V CK ), the first pulse signal (V I1 ), the second pulse signal (V I2 ), the third pulse signal (V I3 ), the high level (V H ), and the first low level ( V L1 ), the second low level (V L2 ), and the third low level (V L3 ) are configured to:
  • the clock signal includes a clock signal of a low level of the first arrival (V L0) and after the arrival of the high level (V H); low level (V L0) of the clock signal (V CK) of ⁇
  • the first low level (V L1 ) > the second low level (V L2 ) > the third low level (V L3 ), or the low level (V L0 ) of the clock signal (V CK ) > the first low Level (V L1 ) second low level (V L2 )>third low level (V L3 );
  • a high level of the first pulse signal (V I1 ) is located in a low level period of a first clock cycle of the clock signal (V CK ); the sustain sub-module (142) is at a clock signal (V CK )
  • a low level (V L0 ) and a high level (V H ) are respectively received during a low period and a high period of one clock cycle to match the sustain control terminal (P) to prevent the drive control terminal (Q) from leaking
  • the rising edge of the high level of the second pulse signal (V I2 ) leads the falling edge of the high level of the first pulse signal (V I1 ), and the falling edge of the high level of the second pulse signal (V I2 )
  • the rising edge of the third pulse signal (V L3 ) also advances A rising edge of a high level of the second clock cycle of the clock signal (V CK ).
  • the driving module (12) further includes a second driving submodule (122) and a first transmission signal output terminal for outputting the first transmission signal (V C1 ); the second driving submodule (122) Connected between the driving control terminal (Q), the clock signal input terminal and the first transfer signal output terminal for transmitting the clock signal (V CK ) to the first transfer when the drive control terminal (Q) is at a high level Signal output.
  • the driving module (12) further includes a third driving submodule (123), wherein the third driving submodule (123) has two structures:
  • the driving module (12) further includes a fourth pulse signal input end and a second transfer signal output end for outputting the second transfer signal (V C2 ); the fourth pulse signal input end is used for Inputting a fourth pulse signal (V I4 ), wherein a high level of the fourth pulse signal (V I4 ) lags behind a high level of the first pulse signal (V I1 ) by one clock cycle; and the second transfer signal output terminal, For outputting a second transfer signal (V C2 ); the third driving sub-module (123) is connected to the fourth pulse signal input end, the first transfer signal output end, the second transfer signal output end, and the high-level end (V) DD ) for transmitting the voltage of the high level terminal (V DD ) to the second transfer signal output terminal when the fourth pulse signal (V I4 ) or the first transfer signal (V C1 ) is high level;
  • the driving module (12) also includes a second transfer signal output terminal for outputting a second transfer signal (V C2 ); the third drive sub-module is connected to the drive control terminal (Q), Between the second transfer signal output terminal and the high level terminal (V DD ), the voltage of the high level terminal (V DD ) is transmitted to the second transfer signal output terminal when the drive control terminal (Q) is at a high level.
  • the maintenance sub-module (142) is further connected to the first transfer signal output end and the second transfer signal output end; the first transfer signal output end is further configured to provide a sustain sub-module (142) with a clock signal ( V CK ) provides a low level (V L0 ) and a high level (V H ) in the low period and the high level period of the first clock cycle, respectively, to match the sustain control terminal (P) to drive the control terminal (Q) no leakage;
  • the maintenance control sub-module (141) is further configured to control the maintenance sub-module (142) to maintain the first transfer signal (V C1 ) and the second transfer signal (V C2 ) respectively when the drive control terminal (Q) is at a low level. To the third low level (V L3 ), the first low level (V L1 ).
  • the present application provides a shift register including the above shift register unit, further comprising a first clock line (CK 1 ), a second clock line (CK 2 ), and a third clock line ( CK 3 ), fourth clock line (CK 4 ), first common low level line (SS 1 ), second common low level line (SS 2 ), third common low level line (SS 3 ), and common High level line
  • the first common low level line (SS 1 ), the second common low level line (SS 2 ), the third common low level line (SS 3 ), and the common high level line are respectively connected to all shift registers a first low level terminal (V SS1 ), a second low level terminal (V SS2 ), a third low level terminal (V SS3 ), and a high level terminal (V DD );
  • the clock signal input end of the 4i+1th stage shift register unit is connected to the first clock line (CK 1 );
  • the clock signal input end of the 4i+2 stage shift register unit is connected to the second clock line (CK 2 ), wherein the high level of the clock signal output by the second clock line (CK 2 ) lags behind the first clock line (CK 1 ) one quarter clock cycle;
  • the clock signal input end of the 4i+3th stage shift register unit is connected to the third clock line (CK 3 ), wherein the high level of the clock signal outputted by the third clock line (CK 3 ) lags behind the second clock line (CK 2 ) one quarter clock cycle;
  • the clock signal input end of the 4i+4th stage shift register unit is connected to the fourth clock line (CK 4 ), wherein the high level of the clock signal output by the fourth clock line (CK 4 ) lags behind the third clock line (CK 3 ) one quarter clock cycle;
  • the first pulse signal input end of the nth stage shift register unit is connected to the first transfer signal output end of the n-2th stage shift register unit;
  • the second pulse signal input end of the nth stage shift register unit is connected to the second transfer signal output end of the n-2th stage shift register unit;
  • the third pulse signal input end of the nth stage shift register unit is connected to the first transfer signal output end of the n+3th stage shift register unit;
  • the fourth pulse signal input end of the nth stage shift register unit is connected to the first transfer signal output end of the n+2th stage shift register unit;
  • N is an integer greater than 3
  • n is an integer greater than 0 and less than or equal to N
  • i is a non-negative integer
  • the shift register of the present application and the unit can still work when the threshold of the transistor is negative, and the leakage is small and the power consumption is low. At the same time, since the shift register unit only needs one clock signal input terminal, no additional clock signal input terminal is needed, and the circuit structure is simple and the cost is low.
  • FIG. 1 is a circuit structural diagram of a shift register unit in Embodiment 1 of the present application.
  • FIG. 2 is a timing chart showing an operation of a shift register unit in the first embodiment of the present application
  • FIG. 3 is a circuit structural diagram of a shift register unit in Embodiment 2 of the present application.
  • FIG. 5 is a circuit structural diagram of a shift register unit in Embodiment 3 of the present application.
  • FIG. 6 is a timing chart of operation of a shift register unit in Embodiment 3 of the present application.
  • FIG. 7 is a circuit structural diagram of a shift register unit in Embodiment 4 of the present application.
  • FIG. 9 is a circuit structural diagram of a shift register unit in Embodiment 5 of the present application.
  • FIG. 11 is a circuit structural diagram of a shift register unit in Embodiment 6 of the present application.
  • FIG. 13 is a circuit structural diagram of a shift register in Embodiment 7 of the present application.
  • FIG. 16 is a circuit structural diagram of a shift register in Embodiment 8 of the present application.
  • FIG. 19 is a circuit structural diagram of a shift register in Embodiment 9 of the present application.
  • Embodiment 20 is a circuit structural diagram of a shift register in Embodiment 10 of the present application.
  • the transistor in the present application is a three-terminal transistor, the three terminals of which are the control pole, the first pole and the second pole; when the transistor is a bipolar transistor, the control pole refers to the base of the bipolar transistor, the first pole Refers to the collector or emitter of a bipolar transistor. The corresponding second pole refers to the emitter or collector of a bipolar transistor. When the transistor is a field effect transistor, the gate is the gate of the field effect transistor.
  • the first pole refers to the drain or source of the field effect transistor, and the corresponding second pole refers to the source or drain of the field effect transistor.
  • the transistor in the display is usually a field effect transistor.
  • the following is an example of a transistor as an N-channel field effect transistor. Accordingly, the gate of the transistor is referred to as the gate, the first pole is the drain, and the second pole. Refers to the source; of course, in other embodiments the transistor can be other types of field effect transistors or bipolar transistors.
  • this embodiment is a shift register unit, including
  • a clock signal input terminal for inputting a clock signal V CK ;
  • a first pulse signal input terminal for inputting the first pulse signal V I1 ;
  • a second pulse signal input terminal for inputting the second pulse signal V I2 ;
  • a third pulse signal input end for inputting a third pulse signal V I3 ;
  • a scan signal output terminal for outputting a scan signal V G ;
  • High level terminal V DD for inputting high level V H ;
  • a first low level terminal V SS1 for inputting a first low level V L1 ;
  • a second low level terminal V SS2 for inputting a second low level V L2 ;
  • the third low level terminal V SS3 is used to input the third low level V L3 .
  • the driving module 12 includes a driving control terminal Q and a first driving sub-module 121.
  • the first driving sub-module 121 is connected between the driving control terminal Q, the clock signal input terminal and the scan signal output terminal, and is used for driving the control terminal.
  • the clock signal V CK is transmitted to the scan signal output terminal.
  • the first driving sub-module 121 includes a twentieth transistor T20 and a first capacitor C1; the control electrode of the twentieth transistor T20 is connected to the driving control terminal Q, the first pole is connected to the clock signal input end, and the second pole is connected.
  • the first capacitor C1 is connected between the drive control terminal Q and the scan signal output terminal. Therefore, when the voltage of the drive control terminal Q is at a high level, the twentieth transistor T20 is turned on, and the clock signal V CK is transmitted to the scan signal output terminal.
  • the charging module 11 is connected between the first pulse signal input end, the second pulse signal input end and the drive control terminal Q, and is configured to be driven when the first pulse signal input end and the second pulse signal input end are simultaneously at a high level.
  • the control terminal Q is charged to a high level.
  • the charging module 11 includes a first transistor T1; the control electrode of the first transistor T1 is connected to the first pulse signal input end, the first electrode is connected to the second pulse signal input end, and the second electrode is connected to the driving control terminal Q. Therefore, when the first pulse signal V I1 is at a high level, the first transistor T1 is turned on, and if the second pulse signal V I2 is also at a high level at this time, the drive control terminal Q is charged.
  • the discharge module 13 is connected between the second pulse signal input end, the third pulse signal input end and the drive control terminal Q, and is configured to be low when the second pulse signal input end is low and the third pulse signal input end is high Normally, the drive control terminal Q is discharged to a low level.
  • the discharge module 13 includes a third transistor T3; the control electrode of the third transistor T3 is connected to the third pulse signal input end, the first electrode is connected to the second pulse signal input end, and the second electrode is connected to the drive control terminal Q. Therefore, when the third pulse signal V I3 is at a high level, the third transistor T3 is turned on, and if the second pulse signal V I2 is at a low level at this time, the drive control terminal Q is discharged.
  • the low level maintenance module 14 is configured to maintain the scan signal V G at a low level during the non-gating time, and includes a maintenance control terminal P, a maintenance control submodule 141, and a maintenance submodule 142.
  • the sustain control sub-module 141 is connected between the clock signal input terminal, the high-level terminal V DD , the second low-level terminal V SS2 and the sustain control terminal P; specifically, the sustain control sub-module 141 includes the fourth transistor T4 and the fifth transistor T5; the control electrode of the fourth transistor T4 is connected to the clock signal input end, the first pole is connected to the high level terminal V DD , the second pole is connected to the sustain control terminal P; the control pole of the fifth transistor T5 is connected to the driving control Terminal Q, the first pole is connected to the sustain control terminal P, and the second pole is connected to the second low-level terminal V SS2 .
  • the maintenance sub-module 142 is connected between the driving control terminal Q, the first low-level terminal V SS1 , the third low-level terminal V SS3 and the sustain control terminal P; specifically, the maintenance sub-module 142 includes a sixth transistor T6, a seventh transistor T7 and an eighth transistor T8; a control electrode of the sixth transistor T6, the seventh transistor T7 and the eighth transistor T8 are commonly connected to the sustain control terminal P; the first electrode of the sixth transistor T6 is connected to the drive control terminal Q
  • the second pole is connected to the first pole of the seventh transistor T7; the second pole of the seventh transistor T7 is connected to the third low-level terminal V SS3 ; the first pole of the eighth transistor T8 is connected to the scan signal output end, and the second The pole is connected to the first low level terminal V SS1 .
  • the sustain control sub-module 141 is configured to control the maintenance sub-module 142 to maintain the scan signal V G to the first low level V L1 when the drive control terminal Q is at a low level.
  • one configuration of each input signal is:
  • V CK is the clock signal comprises a first clock cycle of the incoming clock signal V CK is low level V L0 and the incoming high level V H;
  • V CK clock signal of a low level V L0 ⁇ first low level V L1 >second low level V L2 >third low level V L3 , or low level V L0 of clock signal V CK >first low level V L1 second low level V L2 > third low power Level V L3 ;
  • the high level of the first pulse signal V I1 is located in the low level period of the first clock cycle of the clock signal V CK ;
  • the sustain sub-module 142 is in the low period of the first clock cycle of the clock signal V CK And a high level period receives a low level V L0 and a high level V H respectively to cooperate with the sustain control terminal P to make the driving control terminal Q not leak;
  • the rising edge of the high level of the second pulse signal V I2 is ahead of The falling edge of the high level of the first pulse signal V I1 , the falling edge of
  • FIG. 2 is a timing diagram of an operation of the shift register unit in the embodiment.
  • the clock signal V CK can be a square wave signal of period T and the duty cycle is 50%.
  • the high level of the first pulse signal V I1 is one half clock period higher than the high level of the clock signal V CK ; the second pole of the sixth transistor T6 is in the high level period of the clock signal V CK , the high voltage A low level V H and a low level V L0 are respectively received in the low level period before the leveling to match the sustain control terminal P so that the driving control terminal Q does not leak; the high level duration of the second pulse signal V I2 is The first pulse signal V I1 is twice the high level, and the rising edge of the high level of the second pulse signal V I2 is synchronized with the rising edge of the high level of the first pulse signal V I1 , and the falling edge is delayed by the first pulse The falling edge of the high level of signal V I1 .
  • the high level of the third pulse signal V L3 lags behind the high level of the first pulse signal V I1 by five quarter clock cycles.
  • the working process of the shift register unit in this embodiment is divided into four phases: a precharge phase P1, a pullup phase P2, a pulldown phase P3, and a low level maintenance phase P4.
  • the present embodiment is described in detail below with reference to FIG. 1 and FIG. A working process of the shift register unit in the example.
  • the precharge phase P1 refers to a process in which the shift register unit of the present stage is in the strobe phase, and the drive control terminal Q is charged to a high level.
  • the clock signal V CK is at a low level V L0 , and the first pulse signal V I1 and the second pulse signal V I2 simultaneously rise to a high level. Therefore, the first transistor T1 is turned on, the driving control terminal Q is charged to a high level, and the level of the high level is a smaller value of V H -V TH1 and V H , that is, Min (V H -V TH1 , V H ), Where V TH1 is the threshold voltage of the first transistor T1.
  • the drive control terminal Q is charged to a high level, so that the twentieth transistor T20 is turned on, discharging the voltage at the output of the scan signal to the low level V L0 of the clock signal V CK .
  • the clock signal V CK is at a low level V L0 , so the fourth transistor T4 is turned off; the drive control terminal Q is at a high level, so the fifth transistor T5 is turned on; the fourth transistor T4 is turned off and The five-transistor T5 is turned on, thereby maintaining the potential of the control terminal P pulled down to the second low level V L2 .
  • V GS V L2 - V L3 > 0 of the seventh transistor T7 at this time, it is in a weakly conducting state, but since the sixth transistor T6 is reliably turned off, the driving control terminal Q does not pass through the transistor T6 and the transistor T7. Leakage.
  • the drive control terminal Q is charged to the high level Min (V H -V TH1 , V H ), and the leakage of the drive control terminal Q can be suppressed.
  • the pull-up phase P2 refers to the process in which the shift register unit of the current stage is in the strobe phase and the output of the scan signal is charged to the high level.
  • the voltage of the first pulse signal V I1 drops to V L0 , the first transistor T1 is turned off, but the drive control terminal Q is still at the high level, so the twentieth transistor T20 is still turned on.
  • the voltage of the clock signal V CK rises from V L0 to V H , and the scan signal output terminal is quickly charged by the turned-on twentieth transistor T20.
  • the voltage of the scan signal V G rises, the voltage of the drive control terminal Q is also raised to a higher voltage, and the voltage of the drive control terminal Q is raised, which in turn increases.
  • the driving ability of the twentieth transistor T20 causes the voltage of the scanning signal V G to rapidly rise to a high level V H .
  • the process in which the voltage of the drive control terminal Q is raised is referred to as bootstrap.
  • the drive control terminal Q should be kept in a floating state, so that it can be bootstrapped to a higher voltage. In other words, if the drive control terminal Q leaks, it will seriously affect the Q.
  • the magnitude of the bootstrap voltage thereby weakening the driving capability of the twentieth transistor T20, which in turn leads to an increase in the rise time delay of the scan signal V G and even circuit failure, especially when the threshold voltage of the transistor in the circuit is negative. this circumstance occurs.
  • the driving control terminal Q does not leak through the first transistor T1 and the third transistor T3: the voltage of the second pulse signal V I2 remains Is high level and the first pulse signal V I1 and the third pulse signal V I3 are at a low level, so the first transistor T1 and the third transistor T3 are reliably turned off; the drive control terminal Q does not pass through the seventh transistor T7 and sixth transistor T6 are leaking: although the voltage of the clock signal V CK is at a high level V H , the fourth transistor T4 is turned on, but the driving control terminal Q is bootstrapped to a higher level, so that the fifth transistor T5 leads The driving force is much larger than the fourth transistor T4, so the potential of the control terminal P is maintained at the second low level V L2 - in order to further ensure that the driving force of the fifth transistor T5 is greater than the driving force of the fourth transistor T4, During the design process, the width of the fifth transistor T5 can be designed to be
  • the driving control terminal Q does not leak electricity, so that the driving control terminal Q can be bootstrapped smoothly, thereby ensuring that the twentieth transistor T20 maintains a large driving capability.
  • the pull-down phase P3 refers to a process in which the voltages of the drive control terminal Q and the scan signal V G are pulled down to a low level.
  • the clock signal V CK drops from the high level V H to V L0 , at which time the voltage of the driving control terminal Q is still at a very high level, and the twentieth transistor T20 remains conductive, so the scan signal output terminal The twentieth transistor T20 is quickly discharged to V L0 .
  • the voltage of the drive control terminal Q also continuously decreases.
  • the voltage of the drive control terminal Q also drops to the time t1.
  • Precharge pressure Min V H -V TH1 , V H ).
  • the third pulse signal V I3 rises to a high level V H , so the third transistor T3 is turned on, and at this time, the second pulse signal V I2 has dropped to a low level V L1 , so the control terminal Q is driven. The voltage is pulled down to the first low level V L1 .
  • the clock signal V CK rises from a low level V L0 to a high level V H .
  • the fourth transistor T4 is turned on, and the high-level terminal V DD charges the sustain control terminal P through the turned-on fourth transistor T4, and charges the voltage of the control terminal P to a high level, and the magnitude of the high-level voltage is V H - The smaller of V TH4 and V H .
  • V TH4 is the threshold voltage of the fourth transistor, and at this time, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 are turned on.
  • the voltage of the drive control terminal Q is pulled down to the third low level V L3 , and the voltage of the scan signal V G is pulled down to the first low level V L1 .
  • the low-level sustain phase P4 refers to the shift register unit of the current stage entering the non-strobe state, and the potential of the scan signal V G outputted by the scan signal output terminal G must be maintained at a low level to avoid being connected to the scan signal output terminal G.
  • the switching transistor in the display pixel is mis-conducted, causing image information to be written incorrectly.
  • the fourth transistor T4 is periodically turned on, and the high level terminal V DD continuously charges the sustain control terminal P through the fourth transistor T4. Therefore, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 are also kept in an on state at all times, thereby maintaining the scan signal V G at a low level.
  • the voltage of the control electrode is V L3 + ⁇ V Q
  • the voltage of the second pole is V L1
  • the twentieth transistor T20 can Being completely turned off, not only can suppress the clock feedthrough effect to reduce the output noise of the scan signal V G , but also suppress the leakage of the twentieth transistor T20 and reduce the power consumption of the circuit
  • the control pole thereof The voltage is V L3 + ⁇ V Q and the voltage of the second pole is V L2 .
  • the leakage of the sustaining terminal P through the fifth transistor T5 is suppressed, not only can the power consumption of the circuit be reduced, but also the voltage of the P terminal can be stably maintained at a high level to ensure that the low level maintains the normal operation of the module.
  • the shift register unit of this embodiment can not only make the threshold voltage of the shift register unit at the transistor of the shift register unit negative by the leakage current of the transistor in the precharge phase, the pull-up phase, the pull-down phase, and the low-level sustain phase of the circuit operation. It works normally and can reduce the power consumption of the circuit.
  • FIG. 3 is a circuit structural diagram of another shift register unit disclosed in the second embodiment. Different from the implementation, the first low-level terminal V SS1 and the second low-level terminal V SS2 in the shift register unit in this embodiment are the same low-level terminal.
  • the first low-level terminal V SS1 and the second low-level terminal V SS2 are the same low-level terminal, and the low-level terminal is the first low-level terminal V SS1 for inputting the first low-level V L1 .
  • FIG. 4 is a working timing diagram of the shift register unit of the embodiment, wherein the low level V L0 of the clock signal V CK ⁇ the first low level V L1 > the third low level V L3 .
  • the operation of the shift register unit in this embodiment is substantially the same as that of the shift register unit in the first embodiment, and details are not described herein again.
  • the shift register unit shown in this embodiment has the advantages of reducing one low-level input and further simplifying the circuit structure.
  • the driving module 12 further includes a second driving submodule 122, a third driving submodule 123, a first transmission signal output end, and a second transmission signal output end. a fourth pulse signal input end, wherein the first transfer signal output end is for outputting the first transfer signal V C1 ; the second transfer signal output end is for outputting the second transfer signal V C2 ; and the fourth pulse signal input end is For inputting the fourth pulse signal V I4 .
  • the second driving sub-module 122 is connected between the driving control terminal Q, the clock signal input end and the first transfer signal output end, and is configured to transmit the clock signal V CK to the first transfer signal output when the drive control terminal Q is at a high level. end.
  • the second driving sub-module 122 includes a twenty-first transistor T21; the control electrode of the twenty-first transistor T21 is connected to the driving control terminal Q, the first pole is connected to the clock signal input end, and the second pole is connected to the first Pass the signal output.
  • the third driving sub-module 123 is connected between the fourth pulse signal input end, the first transfer signal output end, the second transfer signal output end and the high level end V DD for when the fourth pulse signal V I4 or the first pass Transmitting the voltage of the high-level terminal V DD to the second transfer signal output terminal when the signal V C1 is high level; specifically, the third driving sub-module 123 includes the twenty-second transistor T22 and the twenty-third transistor T23; The control electrode of the twelve transistor T22 is connected to the first transfer signal output terminal; the control electrode of the twenty-third transistor T23 is connected to the fourth pulse signal input terminal; the first of the twenty-second transistor T22 and the twenty-third transistor T23 The poles are all connected to the high level terminal V DD , and the second pole is connected to the second signal output terminal.
  • the maintenance sub-module 12 in the low-level maintenance module 14 is further outputted with the first transmission signal, respectively, on the basis of the first embodiment.
  • the second transfer signal output end is connected;
  • the first transfer signal output end is further configured to provide the maintenance sub-module 142 with a low power in the low-level period and the high-level period of the first clock cycle of the clock signal V CK Flat V L0 and high level V H to cooperate with the sustain control terminal P to make the drive control terminal Q not leak;
  • the maintenance control sub-module 141 is further configured to control the maintenance sub-module 142 to be the first when the drive control terminal Q is low.
  • the transfer signal V C1 and the second transfer signal V C2 are respectively maintained to the third low level V L3 and the first low level V L1 ; specifically, the sustain submodule 142 includes the sixth transistor T6 , the seventh transistor T7 , and the eighth The control electrodes of the transistor T8 and the ninth transistor T9, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, and the ninth transistor T9 are commonly connected to the sustain control terminal P; the first electrode of the sixth transistor T6 is connected to Drive control terminal Q, second pole Connected to the first pole of the seventh transistor T7 and connected in common to the first transfer signal output terminal; where the second pole of the sixth transistor T6 and the first pole of the seventh transistor T7 are commonly connected to the first transfer signal output
  • this structure enables the first transfer signal output terminal to be maintained at a low level during the non-stroke period of the register unit.
  • the sub-module 142 provides a low level V L0 and a high level V H respectively in the low-level period and the high-level period of the first clock cycle of the clock signal V CK to cooperate with the sustain control terminal P to drive the control terminal Q
  • the function of the non-leakage; the second pole of the seventh transistor T7 is connected to the second low-level terminal V SS3 ; the first pole of the eighth transistor T8 is connected to the scan signal output terminal G, and the second pole is connected to the first low-level terminal V SS1 ; the first pole of the ninth transistor T9 is connected to the second transfer signal output terminal, and the second pole is connected to the first low-level terminal V SS1 .
  • FIG. 6 is a timing diagram of an operation of the shift register unit in the embodiment.
  • the high level of the first pulse signal V I1 is one half clock period higher than the high level of the clock signal V CK ;
  • the high voltage of the second pulse signal V I2 The flat duration is twice the high level of the first pulse signal V I1 , and the rising edge of the high level of the second pulse signal V I2 is synchronized with the rising edge of the high level of the first pulse signal V I1 , and the falling edge is delayed a falling edge of a high level of the first pulse signal V I1 ;
  • a high level of the third pulse signal V L3 lags behind a high level of five quarter clock cycles of the first pulse signal V I1 ;
  • a fourth pulse signal V The high level of I4 lags the high level of the first pulse signal V I1 by one clock cycle.
  • the precharge phase P1 refers to a process in which the shift register unit of the present stage is in the strobe phase, and the drive control terminal Q is charged to a high level.
  • the clock signal V CK is at a low level V L0 , and the first pulse signal V I1 and the second pulse signal V I2 simultaneously rise to a high level. Therefore, the first transistor T1 is turned on, the driving control terminal Q is charged to a high level, and the level of the high level is a smaller value of V H -V TH1 and V H , that is, Min (V H -V TH1 , V H ), Where V TH1 is the threshold voltage of the first transistor T1.
  • the driving control terminal Q is charged to a high level, so the twentieth transistor T20 and the twenty-first transistor T21 are turned on, discharging the voltage of the scan signal output terminal and the first transfer signal output terminal to the low level V of the clock signal V CK . L0 .
  • the clock signal V CK is at a low level V L0 , so the fourth transistor T4 is turned off; the drive control terminal Q is at a high level, so the fifth transistor T5 is turned on; the fourth transistor T4 is turned off and The five transistors T5 are turned on, thereby maintaining the potential of the control terminal P pulled down to the first low level V L1 .
  • V GS V L1 - V L0 ⁇ 0
  • V GS V L1 - V L0 ⁇ 0
  • V GS V L1 - V L0 ⁇ V TH6
  • the sixth transistor T6 is still reliably turned off.
  • V GS V L1 - V L3 > 0 of the seventh transistor T7 at this time, it is in a weakly conducting state, but since the sixth transistor T6 is reliably turned off, the driving control terminal Q does not pass through the transistor T6 and the transistor T7. Leakage.
  • the drive control terminal Q is charged to the high level Min (V H -V TH1 , V H ), and the leakage of the drive control terminal Q can be suppressed.
  • the pull-up phase P2 refers to a process in which the shift register unit of the stage is in the strobe phase, and the scan signal output terminal and the first transfer signal output terminal are charged to a high level.
  • the voltage of the first pulse signal V I1 drops to V L0 , the first transistor T1 is turned off, but the driving control terminal Q is still at a high level, so the twentieth transistor T20 and the twenty-first transistor T21 are still Turn on.
  • the voltage of the clock signal V CK rises from V L0 to V H , and the scan signal output terminal is rapidly charged by the turned-on twentieth transistor T20, and the second eleventh transistor T21 is turned on.
  • a transfer signal output for fast charging Specifically, in this process, as the voltage of the scan signal V G rises, the voltage of the drive control terminal Q is also raised to a higher voltage, and the voltage of the drive control terminal Q is raised, which in turn increases.
  • the twenty-second transistor T22 is turned on, and the high-level terminal V DD charges the second transfer signal output terminal through the turned-on twenty-second transistor T22, and the second transfer signal V C2 is charged to a voltage value smaller Min V H -V TH22 and the V H (V H -V TH22, V H ), wherein the threshold voltage V TH22 of the twenty-second transistor T22.
  • bootstrap The process in which the voltage of the drive control terminal Q is raised is referred to as bootstrap.
  • the drive control terminal Q should be kept in a floating state, so that it can be bootstrapped to a higher voltage. In other words, if the drive control terminal Q leaks, it will seriously affect the Q. bootstrap voltage magnitude, thus weakening the driving capability of the twenty-first and twenty-transistor T20 the transistor T21, which led to the rise time delay of the scanning signal V G is increased, and even circuit failure, especially when the threshold value of the transistor in the circuit This is more likely to occur when the voltage is negative.
  • the driving control terminal Q does not leak electricity, so that the driving control terminal Q can be bootstrapped smoothly, thereby ensuring that the twentieth transistor T20 maintains a large driving capability.
  • the seventh transistor T7, the eighth transistor T8, and the ninth transistor T9 are in a weakly conducting state, but due to the twentieth transistor T20, the twenty-first transistor T21, and the second The twelve transistors T22 have a large driving capability, so the weak leakage of the seventh transistor T7, the eighth transistor T8, and the ninth transistor T9 does not significantly affect the scan signal V G , the first transfer signal V C1 , and each of the two The rising process of the signal V C2 is transmitted.
  • the pull-down phase P3 refers to a process of driving the control terminal Q, the scan signal V G , and the voltage of the first transfer signal V C1 to be pulled down to a low level.
  • the clock signal V CK drops from the high level V H to V L0 , at which time the voltage of the driving control terminal Q is still at a very high level, and the twentieth transistor T20 and the twenty-first transistor T21 remain guided. Therefore, the scan signal output terminal and the first transfer signal output terminal are quickly discharged to V L0 through the twentieth transistor T20 and the twenty-first transistor T21, respectively. During this process, as the voltage at the output of the scan signal continues to decrease, the voltage of the drive control terminal Q also continuously decreases. When the voltage of the scan signal V G is V L0 , the voltage of the drive control terminal Q also drops to the time t1. Precharge pressure Min (V H -V TH1 , V H ).
  • the voltage of the first transfer signal V C1 is discharged to V L0 , the twenty-second transistor T22 is turned off, but the fourth pulse signal V I4 rises to a high level, so the twenty-third transistor T23 is turned on, the high-level end V DD continues to charge the second transfer signal output through the turned-on transistor T23, so the second transfer signal V C2 remains at a high level.
  • the third pulse signal V I3 rises to a high level V H , so the third transistor T3 is turned on, and at this time, the second pulse signal V I2 has dropped to a low level V L1 , so the control terminal Q is driven. The voltage is pulled down to the first low level V L1 .
  • the clock signal V CK rises from a low level V L0 to a high level V H .
  • the fourth transistor T4 is turned on, and the high-level terminal V DD charges the sustain control terminal P through the turned-on fourth transistor T4, and charges the voltage of the control terminal P to a high level, and the magnitude of the high-level voltage is V H - The smaller of V TH4 and V H .
  • V TH4 is the threshold voltage of the fourth transistor, and at this time, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, and the ninth transistor T9 are turned on.
  • the voltage driving the control terminal Q and the first transfer signal V C1 is pulled down to the third low level V L3 , and the voltages of the scan signal V G and the second transfer signal V C2 are pulled down to the first low level V L1 .
  • the low-level sustain phase P4 refers to that the shift register unit of the current stage enters the non-strobe state, and the potential of the scan signal V G outputted by the scan signal output terminal G is maintained at a low level to avoid connection with the scan signal output terminal G.
  • the switching transistor in the display pixel is erroneously turned on, causing image information to be written incorrectly; the voltages of the first transfer signal V C1 and the second transfer signal V C2 are maintained at corresponding low levels to avoid phase shifting with the shift register unit of the present stage.
  • the associated front-to-back shift register unit produces an erroneous input.
  • the fourth transistor T4 is periodically turned on, and the high level terminal V DD continuously charges the sustain control terminal P through the fourth transistor T4. Therefore, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, and the ninth transistor T9 are also kept in an on state at all times, thereby maintaining the voltages of the scan signal V G , the first transfer signal V C1 , and the second transfer signal V C2 . For the corresponding low level.
  • the voltage of the control electrode is V L3 + ⁇ V Q
  • the voltage of the second pole is V L1
  • V L3 + ⁇ V Q - V L1 ⁇ V TH20 the twentieth transistor T20 can Being completely turned off, not only can suppress the clock feedthrough effect to reduce the output noise of the scan signal V G , but also suppress the leakage of the twentieth transistor T20 and reduce the power consumption of the circuit; similarly, for the twenty-first transistor T21, When V L3 + ⁇ V Q - V L1 ⁇ VT H21 , the output noise of the first transfer signal can be reduced, and the leakage of the transistor T21 can be suppressed.
  • the clock feedthrough effect is relatively small.
  • the gate voltage is V L3
  • the second pole voltage is V L1 , when V L3 -V L1 ⁇ V TH22 or V L3 -V L1 ⁇ V TH23 At this time, the twenty-second transistor T22 and the twenty-third transistor T23 can be reliably turned off, and the leakage thereof is suppressed.
  • the voltage of its gate is V L3 + ⁇ V Q and the voltage of its second pole is V L1 .
  • V L3 + ⁇ V Q - V L1 ⁇ V TH5 the fifth transistor T5 can be reliably turned off. Therefore, the leakage of the sustaining terminal P through the fifth transistor T5 is suppressed, not only can the power consumption of the circuit be reduced, but also the voltage of the P terminal can be stably maintained at a high level to ensure that the low level maintains the normal operation of the module.
  • the shift register unit of this embodiment can not only make the threshold voltage of the shift register unit at the transistor of the shift register unit negative by the leakage current of the transistor in the precharge phase, the pull-up phase, the pull-down phase, and the low-level sustain phase of the circuit operation. It works normally and can reduce the power consumption of the circuit.
  • FIG. 7 is a circuit structure diagram of a shift register unit according to Embodiment 4, which is different from Embodiment 3.
  • the shift register unit further includes a second low-level terminal V SS2 .
  • the second low level V L2 is input, where V L0 ⁇ V L1 >V L2 >V L3 .
  • the fifth transistor T5 is not connected to the first low-level terminal V SS1 but to the second low-level terminal V SS2 as compared with the third embodiment.
  • FIG. 8 is a working timing diagram of the shift register unit in the embodiment.
  • the working process of the shift register unit in this embodiment is basically the same as the shift register in the third embodiment, and details are not described herein again. It should be noted that when the low level V L0 of the clock signal V CK is equal to the first low level V L1 , the scan signal V G of the shift register unit of the embodiment has only a fixed low level.
  • the power consumption of the shift register unit of the present embodiment can be further reduced for the following reason: in the pull-up phase P2, the voltage of the sustain control terminal P is pulled down to the second low level V L2 .
  • the voltage of the gate thereof is V L2
  • the voltage of the second pole is V L1
  • V GS V L2 - V L1 ⁇ V TH9 of the nine transistor T9
  • the eighth transistor T8 and the ninth transistor T9 are reliably turned off. Therefore, in the pull-up phase P2, the power consumption of the circuit is further lowered, and the rising delay of the scan signal V G and the second transfer signal V C2 can be further reduced.
  • the shift register unit shown in this embodiment has a lower-level terminal V SS2 as compared with the shift register unit shown in the third embodiment, but the power consumption of the circuit is further reduced, and the output delay of the circuit is delayed. Got an optimization.
  • FIG. 9 is a circuit structure diagram of a shift register unit disclosed in Embodiment 5, which is different from Embodiment 3 in that:
  • the third driving sub-module 123 is connected between the driving control terminal Q, the high-level terminal V DD and the second transmission signal output terminal for using the high-level terminal V DD when the driving control terminal Q is at a high level.
  • the voltage is transmitted to the second transfer signal output terminal; specifically, the third drive sub-module 123 includes the twenty-second transistor T22; the control electrode of the twenty-second transistor T22 is connected to the drive control terminal Q, and the first pole is connected to the high The level terminal V DD and the second pole are connected to the second transfer signal output terminal.
  • FIG. 10 is a timing diagram of an operation of the shift register unit of the embodiment.
  • the pulse width of pulse signal V I2 according to the present embodiment is three times of the first pulse signal V I1, before the high edge of the first arrival pulse signal V I1, V I2 of the second pulse signal has risen to high The level, while the falling edge of the second pulse signal V I2 still lags behind the falling edge of the first pulse signal V I1 .
  • the second pulse signal V I2 has risen to a high level, at which time the first transistor T1 and the third transistor T3 may be weakly turned on and generate a weak charge to the drive control terminal Q, but Since the sixth transistor T6 and the seventh transistor T7 remain strongly turned on at this time, the leakage of the first transistor T1 and the third transistor T3 does not significantly affect the voltage of the driving control terminal Q, nor does it affect the normal circuit of the circuit.
  • the twenty-second transistor T22 is turned on, and the high-level terminal V DD passes the turned-on twenty-second transistor T22 to the second transfer signal.
  • the output terminal is charged to raise the second transfer signal V C2 to a high level.
  • the shift register unit shown in this embodiment has the advantage of the shift register unit shown in the third embodiment, and has the advantages of reducing one pulse signal and further simplifying the circuit structure.
  • a circuit structure diagram of a shift register unit disclosed in the sixth embodiment is different from the fifth embodiment.
  • the shift register unit further includes a second low-level terminal V SS2 . Used to input the second low level V L2 , where V L0 ⁇ V L1 >V L2 >V L3 .
  • the fifth transistor T5 is not connected to the first low-level terminal V SS1 but to the second low-level terminal V SS2 as compared with the fifth embodiment.
  • FIG. 12 is a working timing diagram of the shift register unit in the embodiment.
  • the working process of the shift register unit in this embodiment is basically the same as that in the fifth embodiment, and details are not described herein again.
  • the shift register unit shown in this embodiment has a lower-level terminal V SS2 as compared with the shift register unit shown in the fifth embodiment, but the power consumption of the circuit is further reduced, and the output delay of the circuit is delayed. Got an optimization.
  • the embodiment discloses a shift register including a shift register unit shown in the third embodiment of the N-stage cascade, a first clock line CK 1 , a second clock line CK 2 , and a third The clock line CK 3 , the fourth clock line CK 4 , the first common low level line SS 1 , the third common low level line SS 3 , and a common high level line.
  • the first common low level line SS 1 , the third common low level line SS 3 , and the common high level line are respectively connected to the first low level end V SS1 , the third low level end V SS3 , and the third low level end V SS3 of each of the shift register units High level V DD .
  • the first clock line CK 1 , the second clock line CK 2 , the third clock line CK 3 , and the fourth clock line CK 4 provide a four-phase overlapping clock signal, and the high level overlap of the clock signals output by the adjacent two clock lines One quarter of the clock cycle, specifically:
  • the clock signal input end of the 4i+1th stage shift register unit is connected to the first clock line CK 1 ;
  • the clock signal input end of the 4i+2 stage shift register unit is connected to the second clock line CK 2 , wherein the high level of the clock signal outputted by the second clock line CK 2 lags behind the quarter of the first clock line CK 1 One clock cycle;
  • the clock signal input end of the 4i+4th stage shift register unit is connected to the fourth clock line CK 4 , wherein the high level of the clock signal outputted by the fourth clock line CK 4 lags behind the fourth clock line CK 3 One clock cycle.
  • the cascaded shift register unit is connected as follows:
  • the first pulse signal input end of the nth stage shift register unit is connected to the first transfer signal output end of the n-2th stage shift register unit;
  • the second pulse signal input end of the nth stage shift register unit is connected to the second transfer signal output end of the n-2th stage shift register unit;
  • the third pulse signal input end of the nth stage shift register unit is connected to the first transfer signal output end of the n+3th stage shift register unit;
  • the fourth pulse signal input end of the nth stage shift register unit is connected to the first transfer signal output end of the n+2th stage shift register unit;
  • N is an integer greater than 3
  • n is an integer greater than 0 and less than or equal to N
  • i is a non-negative integer
  • FIG. 14 is a timing diagram of an operation of the shift register shown in this embodiment.
  • V G(n-2) , V G(n-1) , V G(n), and V G(n+1) are the n-2th, n-1th, nth, and n+1th, respectively.
  • the scan signal V G outputted by the stage shift register unit can be seen that the scan signals V G output by the two-stage shift register unit overlap each other by a half pulse width.
  • a simulation waveform diagram of the shift register shown in the embodiment is shown.
  • the abscissa is time, and the ordinate is the voltage of the scan signal V G outputted by the shift register units of each stage.
  • the threshold voltage V TH of all transistors in the circuit may be -4V, the high level V H , the low level V L0 of the clock signal V CK , the first low level V L1 , and the third low level V L3
  • the values are: 28V, -6V, -9V, -15V.
  • the shift register shown in this embodiment can still operate normally when the transistor threshold voltage is negative.
  • the scan signal output end of each stage of the shift register unit can be connected to the gate scan line of the display panel to provide a gate scan signal for a row of pixel units of the display panel.
  • a shift register disclosed in the eighth embodiment is different from the seventh embodiment.
  • the embodiment includes the N-level cascade of the fourth embodiment instead of the shift register shown in the third embodiment. unit. Accordingly, the shift register of this embodiment further includes a second common low level line SS 2 connected to the second low level terminal V SS2 of all the shift register units.
  • FIG. 18 a simulation waveform diagram of the shift register shown in the embodiment is shown.
  • the abscissa is time, and the ordinate is the voltage of the scan signal V G outputted by the shift register units of each stage.
  • the threshold voltage V TH of all transistors in the circuit be -4V, high level V H , low level V L0 of clock CK, first low level V L1 , second low level V L2 , third
  • the values of the low level V L3 are: 28V, -6V, -6V, -9V, -15V.
  • the shift register shown in this embodiment can still operate normally when the transistor threshold voltage is negative.
  • each of the scan signals outputted by the shift register shown in this embodiment has a unique low level, and its value is -6V.
  • a shift register disclosed in Embodiment 9 is different from Embodiment 7.
  • This embodiment includes the N-level cascade of the above-described Embodiment 5 instead of the shift register shown in Embodiment 3. Units; correspondingly, the connection manners of the shift register units of the various stages in this embodiment are as follows:
  • the first pulse signal input end of the nth stage shift register unit is connected to the first transfer signal output end of the n-2th stage shift register unit;
  • the second pulse signal input end of the nth stage shift register unit is connected to the second transfer signal output end of the n-2th stage shift register unit;
  • the third pulse signal input terminal of the nth stage shift register unit is connected to the first transfer signal output terminal of the n+3th stage shift register unit.
  • the shift register unit of each stage in this embodiment does not need to configure the connection manner of the fourth pulse signal input end, because the shift register unit in this embodiment does not have the fourth pulse signal input end.
  • An operation timing chart and a simulation waveform diagram of the shift register shown in this embodiment are the same as those of the shift register of the seventh embodiment. For details, refer to FIG. 14 and FIG. 15 respectively, and details are not described herein again.
  • a shift register disclosed in Embodiment 10 is different from Embodiment 9.
  • This embodiment includes the N-level cascade of the above-described Embodiment 6 instead of the shift register unit shown in Embodiment 5.
  • the shift register of this embodiment further includes a second common low level line SS 2 connected to the second low level terminal V SS2 of all the shift register units.

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Abstract

一种可适应负阈值电压的移位寄存器及其单元。移位寄存器包括若干级级联的移位寄存器单元，移位寄存器单元包括：充电模块（11），驱动模块（12），放电模块（13），以及低电平维持模块（14）。本移位寄存器及其单元，通过抑制移位寄存器在工作过程的预充阶段、上拉阶段以及低电平维持阶段的晶体管漏电，使电路即使在当晶体管的阈值电压为负值时仍然可以正常工作，具有电路简单、低功耗、低成本的优点。

Description

一种可适应负阈值电压的移位寄存器及其单元 技术领域
本申请涉及平板显示领域，尤其涉及移位寄存器领域。
背景技术
近年来，集成显示驱动电路成为平板显示技术的研究热点。所谓集成显示驱动电路是指将栅极驱动电路和数据驱动电路等外围电路以薄膜晶体管(TFT)的形式与像素薄膜晶体管一起制作于显示面板上，从而可以减少外围驱动芯片的数量及其压封程序、降低成本，此外还能使得显示器外围更加纤薄，使显示器模组更加紧凑，机械和电学可靠性得以增强。
随着显示器向着高帧频、高分辨率、更窄边框的方向发展，对集成显示驱动电路的工作频率、电路面积也提出了更高的要求。传统的氢化非晶硅薄膜晶体管技术一方面受限于低迁移率而很难满足电路高频工作的需要，另一方面电路面积往往较大。低温多晶硅薄膜晶体管则由于器件成本较高，而且存在器件特性不均匀的特点，很难满足大尺寸显示的需求。近年来，以氧化铟镓锌薄膜晶体管(IGZO-TFT)为代表的氧化物薄膜晶体管技术由于具有迁移率高、器件特性均匀、成本较低等优势而备受关注。在基于氧化物薄膜晶体管的集成显示驱动电路中，移位寄存器作为非常重要的模块电路，得到了广泛的研究。
然而，由于氧化物薄膜晶体管制作工艺的原因，现有的氧化物薄膜晶体管的阈值电压往往偏负，这会导致移位寄存器中的一些晶体管无法正常关断而产生漏电。晶体管的漏电不仅增大了电路的功耗，严重时会还会导致电路的失效。为了使得移位寄存器电路能够适应负的阈值电压，现有的电路设计中通过增加低电位源、多套时钟信号、采用反馈结构和浮栅结构等方式来抑制电路漏电，但是仍然存在电路复杂、成本较高和功耗较大等问题。因此，如何在有效地抑制移位寄存器电路的漏电，使移位寄存器电路能够在晶体管为负阈值电压时正常工作的同时，还降低功耗、节约成本，成为一个极具研究价值的问题。
发明内容
根据本申请的第一方面，本申请提供一种移位寄存器单元，包括：
时钟信号输入端，用于输入时钟信号(VCK)；
第一脉冲信号输入端，用于输入第一脉冲信号(VI1)；
第二脉冲信号输入端，用于输入第二脉冲信号(VI2)；
第三脉冲信号输入端，用于输入第三脉冲信号(VI3)；
扫描信号输出端，用于输出扫描信号(VG)；
高电平端(VDD)，用于输入高电平(VH)；
第一低电平端(VSS1)，用于输入第一低电平(VL1)；
第二低电平端(VSS2)，用于输入第二低电平(VL2)；
第三低电平端(VSS3)，用于输入第三低电平(VL3)；
驱动模块(12)，包括驱动控制端(Q)和第一驱动子模块(121)；所述第一驱动子模块(121)连接于所述驱动控制端(Q)、时钟信号输入端和扫描信号输出端之间，用于当驱动控制端(Q)为高电平时将时钟信号(VCK)传输至扫描信号输出端；
充电模块(11)，连接于所述第一脉冲信号输入端、第二脉冲信号输入端和驱动控制端(Q)之间，用于当第一脉冲信号输入端(I1)和第二脉冲信号输入端(I2)为高电平时将驱动控制端(Q)充电至高电平；
放电模块(13)，连接于所述第二脉冲信号输入端、第三脉冲信号输入端和驱动控制端(Q)之间，用于当第二脉冲信号输入端为低电平且第三脉冲信号输入端为高电平时将驱动控制端(Q)放电至低电平；
低电平维持模块(14)，包括维持控制端(P)、维持控制子模块(141)和维持子模块(142)；维持控制子模块(141)连接于所述时钟信号输入端、高电平端(VDD)、第二低电平端(VSS2)和维持控制端(P)之间；所述维持子模块(142)连接于所述驱动控制端(Q)、第一低电平端(VSS1)、第三低电平端(VSS3)和维持控制端(P)之间；维持控制子模块(141)用于当驱动控制端(Q)为低电平时控制维持子模块(142)将扫描信号(VG)维持至第一低电平(VL1)；
所述时钟信号(VCK)、第一脉冲信号(VI1)、第二脉冲信号(VI2)、第三脉冲信号(VI3)、高电平(VH)、第一低电平(VL1)、第二低电平(VL2)和第三低电平(VL3)被配置为：
所述时钟信号一个周期内包括先到来的时钟信号的低电平(VL0)和后到来的高电平(VH)；所述时钟信号(VCK)的低电平(VL0)≥第一低电平(VL1)＞第二低电平(VL2)＞第三低电平(VL3)，或者，时钟信号(VCK)的低电平(VL0)＞第一低电平(VL1)＝第二低电平(VL2)＞第三低电平(VL3)；
所述第一脉冲信号(VI1)的高电平位于时钟信号(VCK)的第一时钟周期的低电平时段内；所述维持子模块(142)在时钟信号(VCK)的第一时钟周期的低电平时段和高电平时段内分别接受一低电平(VL0)和高电平(VH)，以配合维持控制端(P)使驱动控制端(Q)不漏电；第二脉冲信号(VI2)的高电平的上升沿超前于第一脉冲信号(VI1)的高电平的下降沿，第二脉冲信号(VI2)的高电平的下降沿滞后于第一脉冲信号(VI1)的高电平的下降沿且超前于时钟信号(VCK)第二时钟周期的高电平的上升沿，第三脉冲信号(VL3)的上升沿也超前于时钟信号 (VCK)的第二时钟周期的高电平的上升沿。
进一步地，所述驱动模块(12)还包括第二驱动子模块(122)和用于输出第一传递信号(VC1)的第一传递信号输出端；所述第二驱动子模块(122)连接于所述驱动控制端(Q)、时钟信号输入端和第一传递信号输出端之间，用于当驱动控制端(Q)为高电平时将时钟信号(VCK)传输至第一传递信号输出端。
进一步地，所述驱动模块(12)还包括第三驱动子模块(123)，其中第三驱动子模块(123)有两种结构：
第一种结构中，驱动模块(12)还包括第四脉冲信号输入端和用于输出第二传递信号(VC2)的第二传递信号输出端；所述第四脉冲信号输入端，用于输入第四脉冲信号(VI4)，其中第四脉冲信号(VI4)的高电平滞后于第一脉冲信号(VI1)的高电平一个时钟周期；所述第二传递信号输出端，用于输出第二传递信号(VC2)；所述第三驱动子模块(123)连接于第四脉冲信号输入端、第一传递信号输出端、第二传递信号输出端和高电平端(VDD)之间，用于当第四脉冲信号(VI4)或第一传递信号(VC1)为高电平时将高电平端(VDD)的电压传输至第二传递信号输出端；
第二种结构中，驱动模块(12)也包括用于输出第二传递信号(VC2)的第二传递信号输出端；所述第三驱动子模块连接于所述驱动控制端(Q)、第二传递信号输出端和高电平端(VDD)之间，用于当驱动控制端(Q)为高电平时将高电平端(VDD)的电压传输至第二传递信号输出端。
进一步地，所述维持子模块(142)还与第一传递信号输出端、第二传递信号输出端相连；所述第一传递信号输出端还用于给维持子模块(142)在时钟信号(VCK)的第一时钟周期的低电平时段和高电平时段内分别提供一低电平(VL0)和高电平(VH)，以配合维持控制端(P)使驱动控制端(Q)不漏电；
所述维持控制子模块(141)还用于当驱动控制端(Q)为低电平时控制维持子模块(142)将第一传递信号(VC1)、第二传递信号(VC2)分别维持至第三低电平(VL3)、第一低电平(VL1)。
根据本申请的第二方面，本申请提供一种移位寄存器，包括上面的移位寄存器单元，还包括第一时钟线(CK1)、第二时钟线(CK2)、第三时钟线(CK3)、第四时钟线(CK4)、第一公共低电平线(SS1)、第二公共低电平线(SS2)、第三公共低电平线(SS3)和公共高电平线；
所述第一公共低电平线(SS1)、第二公共低电平线(SS2)、第三公共低电平线(SS3)和公共高电平线分别连接于所有移位寄存器单元的第一低电平端(VSS1)、第二低电平端(VSS2)、第三低电平端(VSS3) 和高电平端(VDD)；
第4i+1级移位寄存器单元的时钟信号输入端连接于第一时钟线(CK1)；
第4i+2级移位寄存器单元的时钟信号输入端连接于第二时钟线(CK2)，其中第二时钟线(CK2)输出的时钟信号的高电平滞后于第一时钟线(CK1)的四分之一个时钟周期；
第4i+3级移位寄存器单元的时钟信号输入端连接于第三时钟线(CK3)，其中第三时钟线(CK3)输出的时钟信号的高电平滞后于第二时钟线(CK2)的四分之一个时钟周期；
第4i+4级移位寄存器单元的时钟信号输入端连接于第四时钟线(CK4)，其中第四时钟线(CK4)输出的时钟信号的高电平滞后于第三时钟线(CK3)的四分之一个时钟周期；
第n级移位寄存器单元的第一脉冲信号输入端连接于第n-2级移位寄存器单元的第一传递信号输出端；
第n级移位寄存器单元的第二脉冲信号输入端连接于第n-2级移位寄存器单元的第二传递信号输出端；
第n级移位寄存器单元的第三脉冲信号输入端连接于第n+3级移位寄存器单元的第一传递信号输出端；
第n级移位寄存器单元的第四脉冲信号输入端连接于第n+2级移位寄存器单元的第一传递信号输出端；
其中，N为大于3的整数，n为大于0且小于或等于N的整数，i为非负整数。
通过对充电模块、放电模块和低电平维持模块的设计，使得本申请的移位寄位器其及单元在晶体管的阈值为负时，仍能工作工作，且漏电小、功耗较低。同时，由于移位寄位器单元只需要一个时钟信号输入端，因此不需要额外的时钟信号输入端，电路结构简单，成本较低。
附图说明
图1为本申请实施例一中的一种移位寄存器单元的电路结构图；
图2为本申请实施例一中的移位寄存器单元的一种工作时序图；
图3为本申请实施例二中的一种移位寄存器单元的电路结构图；
图4为本申请实施例二中的移位寄存器单元的一种工作时序图；
图5为本申请实施例三中的一种移位寄存器单元的电路结构图；
图6为本申请实施例三中的移位寄存器单元的一种工作时序图；
图7为本申请实施例四中的一种移位寄存器单元的电路结构图；
图8为本申请实施例四中的移位寄存器单元的一种工作时序图；
图9为本申请实施例五中的一种移位寄存器单元的电路结构图；
图10为本申请实施例五中的移位寄存器单元的一种工作时序图；
图11为本申请实施例六中的一种移位寄存器单元的电路结构图；
图12为本申请实施例六中的移位寄存器单元的一种工作时序图；
图13为本申请实施例七中的一种移位寄存器的电路结构图；
图14为本申请实施例七中的移位寄存器的一种工作时序图；
图15为本申请实施例七中的移位寄存器的一种仿真波形图；
图16为本申请实施例八中的一种移位寄存器的电路结构图；
图17为本申请实施例八中的移位寄存器的一种工作时序图；
图18为本申请实施例八中的移位寄存器的一种仿真波形图；
图19为本申请实施例九中的一种移位寄存器的电路结构图；
图20为本申请实施例十中的一种移位寄存器的电路结构图。
具体实施方式
下面通过具体实施方式结合附图对本申请作进一步详细说明。
首先对本申请中用到的术语进行解释。
本申请中的晶体管为三端子晶体管，其三个端子为控制极、第一极和第二极；当晶体管为双极型晶体管时，控制极是指双极型晶体管的基极，第一极是指双极型晶体管的集电极或发射极，对应的第二极就是指双极型晶体管的发射极或集电极；当晶体管为场效应晶体管时，控制极是指场效应晶体管的栅极，第一极是指场效应晶体管的漏极或源极，对应的第二极就是指场效应晶体管的源极或漏极。
显示器中的晶体管通常为场效应晶体管，下面不妨以晶体管为N沟道场效应晶体管为例对电路进行说明，相应地，此时晶体管的控制极指栅极，第一极指漏极，第二极指源极；当然，在其他实施例中晶体管也可以是其他类型的场效应晶体管或双极型晶体管。
实施例1：
请参考图1，本实施例为一种移位寄存器单元，包括
时钟信号输入端，用于输入时钟信号VCK；
第一脉冲信号输入端，用于输入第一脉冲信号VI1；
第二脉冲信号输入端，用于输入第二脉冲信号VI2；
第三脉冲信号输入端，用于输入第三脉冲信号VI3；
扫描信号输出端，用于输出扫描信号VG；
高电平端VDD，用于输入高电平VH；
第一低电平端VSS1，用于输入第一低电平VL1；
第二低电平端VSS2，用于输入第二低电平VL2；
第三低电平端VSS3，用于输入第三低电平VL3。
驱动模块12，包括驱动控制端Q和第一驱动子模块121；第一驱动子模块121连接于所述驱动控制端Q、时钟信号输入端和扫描信号输出 端之间，用于当驱动控制端Q为高电平时将时钟信号VCK传输至扫描信号输出端。具体地，第一驱动子模块121包括第二十晶体管T20和第一电容C1；第二十晶体管T20的控制极连接于驱动控制端Q，第一极连接于时钟信号输入端，第二极连接于扫描信号输出端；第一电容C1连接于驱动控制端Q与扫描信号输出端之间。因此，当驱动控制端Q的电压为高电平时，第二十晶体管T20导通，将将时钟信号VCK传输至扫描信号输出端。
充电模块11，连接于第一脉冲信号输入端、第二脉冲信号输入端和驱动控制端Q之间，用于当第一脉冲信号输入端和第二脉冲信号输入端同时为高电平时将驱动控制端Q充电至高电平。具体地，充电模块11包括第一晶体管T1；第一晶体管T1的控制极连接于第一脉冲信号输入端，第一极连接于第二脉冲信号输入端，第二极连接于驱动控制端Q。因此，当第一脉冲信号VI1为高电平时，第一晶体管T1导通，若此时第二脉冲信号VI2也为高电平，则驱动控制端Q被充电。
放电模块13，连接于第二脉冲信号输入端、第三脉冲信号输入端和驱动控制端Q之间，用于当第二脉冲信号输入端为低电平且第三脉冲信号输入端为高电平时将驱动控制端Q放电至低电平。具体地，放电模块13包括第三晶体管T3；第三晶体管T3的控制极连接于第三脉冲信号输入端，第一极连接于第二脉冲信号输入端，第二极连接于驱动控制端Q。因此，当第三脉冲信号VI3为高电平时，第三晶体管T3导通，若此时第二脉冲信号VI2为低电平，则驱动控制端Q被放电。
低电平维持模块14，用于在非选通时间维持扫描信号VG为低电平，其包括维持控制端P、维持控制子模块141和维持子模块142。维持控制子模块141连接于时钟信号输入端、高电平端VDD、第二低电平端VSS2和维持控制端P之间；具体地，维持控制子模块141包括第四晶体管T4和第五晶体管T5；第四晶体管T4的控制极连接于所述时钟信号输入端，第一极连接于高电平端VDD，第二极连接于维持控制端P；第五晶体管T5的控制极连接于驱动控制端Q，第一极连接于维持控制端P，第二极连接于第二低电平端VSS2。维持子模块142连接于所述驱动控制端Q、第一低电平端VSS1、第三低电平端VSS3和维持控制端P之间；具体地，维持子模块142包括第六晶体管T6、第七晶体管T7和第八晶体管T8；第六晶体管T6、第七晶体管T7和第八晶体管T8的控制极共同连接于所述维持控制端P；第六晶体管T6的第一极连接于驱动控制端Q，第二极连接于第七晶体管T7的第一极；第七晶体管T7的第二极连接于第三低电平端VSS3；第八晶体管T8的第一极连接于扫描信号输出端，第二极连接于第一低电平端VSS1。维持控制子模块141用于当驱动控制端Q为低电平时控制维持子模块142将扫描信号VG维持至第一低电平VL1。
本实施例的移位寄存器单元，各输入信号的一种配置为：
时钟信号VCK的一个时钟周期包括先到来的时钟信号VCK的低电平VL0和后到来的高电平VH；时钟信号VCK的低电平VL0≥第一低电平VL1＞第二低电平VL2＞第三低电平VL3，或者，时钟信号VCK的低电平VL0＞第一低电平VL1＝第二低电平VL2＞第三低电平VL3；第一脉冲信号VI1的高电平位于时钟信号VCK的第一时钟周期的低电平时段内；维持子模块142在时钟信号VCK的第一时钟周期的低电平时段和高电平时段内分别接受一低电平VL0和高电平VH，以配合维持控制端P使驱动控制端Q不漏电；第二脉冲信号VI2的高电平的上升沿超前于第一脉冲信号VI1的高电平的下降沿，第二脉冲信号VI2的高电平的下降沿滞后于第一脉冲信号VI1的高电平的下降沿且超前于时钟信号VCK第二时钟周期的高电平的上升沿，第三脉冲信号VL3的上升沿也超前于时钟信号VCK的第二时钟周期的高电平的上升沿。这里时钟信号VCK的第一时钟周期，可以是时钟信号VCK的任一时钟周期，相应地，第二时钟周期就是第一时钟周期的下一时钟周期。
请参考图2，为本实施例中移位寄存器单元的一种工作时序图。
在此工作时序图中，时钟信号VCK可为周期是T的方波信号且占空比为50％。时钟信号VCK的低电平VL0＞第一低电平VL1＞第二低电平VL2＞第三低电平VL3。第一脉冲信号VI1的高电平比时钟信号VCK的一个高电平超前半个时钟周期；第六晶体管T6的第二极在时钟信号VCK的此高电平时段内、此高电平之前的低电平时段内分别接受一高电平VH和低电平VL0，以配合维持控制端P使驱动控制端Q不漏电；第二脉冲信号VI2的高电平持续时间是第一脉冲信号VI1高电平的两倍，且第二脉冲信号VI2的高电平的上升沿同步于第一脉冲信号VI1的高电平的上升沿，下降沿滞后于第一脉冲信号VI1的高电平的下降沿。第三脉冲信号VL3的高电平滞后于第一脉冲信号VI1的高电平四分之五个时钟周期。
本实施例中移位寄存器单元的工作过程分为四个阶段：预充阶段P1，上拉阶段P2，下拉阶段P3以及低电平维持阶段P4，下面结合图1和图2，详细介绍本实施例中移位寄存器单元的一种工作过程。
A.预充阶段P1
预充阶段P1是指本级移位寄存器单元处于选通阶段，驱动控制端Q被充电到高电平的过程。
在t1时刻，时钟信号VCK为低电平VL0，第一脉冲信号VI1和第二脉冲信号VI2同时上升为高电平。因此第一晶体管T1导通，驱动控制端Q被充电至高电平，高电平的大小为VH-VTH1和VH中较小的值即Min(VH-VTH1，VH)，其中VTH1为第一晶体管T1的阈值电压。驱动控制端Q被充电至高电平，因此第二十晶体管T20导通，将扫描信号输出端的 电压放电至时钟信号VCK的低电平VL0。
另一方面，时钟信号VCK为低电平VL0，因此第四晶体管T4被关断；驱动控制端Q为高电平，因此第五晶体管T5导通；第四晶体管T4被关断和第五晶体管T5导通，因此维持控制端P的电位下拉至第二低电平VL2。
对于第六晶体管T6，其第二极在时钟信号VCK的低电平时段内接收一低电平VL0，因此VGS＝VL2-VL0<0，当第六晶体管T6的阈值电压VTH6为正时，其被可靠地关断；当第六晶体管T6的阈值电压VTH6为负时，只需VGS＝VL2-VL0<VTH6，第六晶体管T6仍被可靠地关断。尽管此时第七晶体管T7的VGS＝VL2-VL3>0，其处于弱导通状态，但由于第六晶体管T6被可靠地关断，驱动控制端Q不会通过晶体管T6和晶体管T7漏电。
综上所述，在预充阶段P1，驱动控制端Q被充电到高电平Min(VH-VTH1，VH)，且驱动控制端Q的漏电可以得到抑制。
B.上拉阶段P2
上拉阶段P2是指本级移位寄存器单元处于选通阶段，扫描信号输出端被充电至高电平的过程。
在t2时刻，第一脉冲信号VI1的电压下降为VL0，第一晶体管T1被关断，但驱动控制端Q仍然为高电平，因此第二十晶体管T20仍然导通。在t2时刻，时钟信号VCK的电压由VL0上升为VH，并通过导通的第二十晶体管T20对扫描信号输出端进行快速的充电。具体地，在此过程中，随着扫描信号VG的电压上升，驱动控制端Q的电压也被抬高到更高的电压，而驱动控制端Q的电压被抬高又反过来增大了第二十晶体管T20的驱动能力，使得扫描信号VG的电压得以快速的上升至高电平VH。
上述驱动控制端Q的电压被抬升的过程被称为自举。一般来说，在驱动控制端Q自举的过程中，驱动控制端Q应当保持浮空状态，这样才能被自举到较高的电压，换言之，驱动控制端Q若漏电则会严重影响Q的自举电压的大小，从而削弱第二十晶体管T20的驱动能力，进而导致扫描信号VG的上升时间延迟增大，甚至电路失效，尤其是在当电路中晶体管的阈值电压为负值时更容易出现这种情况。而在在本实施例中移位寄存器单元的上拉阶段P2即t2到t3时刻，驱动控制端Q不会通过第一晶体管T1和第三晶体管T3漏电：第二脉冲信号VI2的电压仍保持为高电平且第一脉冲信号VI1和第三脉冲信号VI3为低电平，因此第一晶体管T1和第三晶体管T3被可靠地关断；驱动控制端Q也不会通过第七晶体管T7和第六晶体管T6漏电：虽然时钟信号VCK的电压为高电平VH，因此第四晶体管T4导通，但驱动控制端Q自举到更高的电平，从而第五晶体管T5导通且驱动力要远大于第四晶体管T4，所以维持控制 端P的电位仍然为第二低电平VL2——为了进一步保证第五晶体管T5的驱动力大于第四晶体管T4的驱动力，在设计过程中，第五晶体管T5的宽度可以设计为远大于第四晶体管T4的宽度。在时钟信号VCK的此高电平时段内，第六晶体管T6的第二极接受一高电平VH的输入，故对于第六晶体管T6，VGS＝VL2-VH<VTH6，所以其被可靠地关断，驱动控制端Q不会通过晶体管T6和晶体管T7漏电。
综上所述，驱动控制端Q不会漏电，从而驱动控制端Q可以顺利自举，进而又保证了第二十晶体管T20保持较大的驱动能力。
需要注意的是，对于第八晶体管T8，VGS＝VL2-VL1<0，当其阈值电压VTH8为正时，第八晶体管T8被可靠地关断，扫描信号输出端不会通过第八晶体管T8漏电，当其阈值电压VTH8为负时，第八晶体管T8有可能会处于弱导通状态，但由于第二十晶体管T20拥有较大的驱动能力，因此第八晶体管T8的微弱漏电不会显著的影响到扫描信号VG的上升过程。当然，对于第八晶体管T8，如果VGS＝VL2-VL1<VTH8，则第八晶体管T8可靠地被关断，电路的功耗会进一步降低，扫描信号VG的上升延迟也可以进一步的减小。
C.下拉阶段P3
下拉阶段P3指的是驱动控制端Q和扫描信号VG的电压被下拉至低电平的过程。
在t3时刻，时钟信号VCK由高电平VH下降为VL0，此时驱动控制端Q的电压仍然为很高的电平，第二十晶体管T20仍然保持导通，因此扫描信号输出端通过第二十晶体管T20被快速的放电至VL0。在此过程中，随着扫描信号输出端的电压不断下降，驱动控制端Q的电压也在不断地下降，当扫描信号VG的电压为VL0时，驱动控制端Q的电压也下降为t1时刻的预充电压Min(VH-VTH1，VH)。
在t4时刻，第三脉冲信号VI3上升为高电平VH，因此第三晶体管T3导通，而此时第二脉冲信号VI2已经下降为低电平VL1，所以驱动控制端Q的电压下拉至第一低电平VL1。
在t5时刻，时钟信号VCK由低电平VL0上升为高电平VH。第四晶体管T4导通，高电平端VDD通过导通的第四晶体管T4对维持控制端P进行充电，将维持控制端P的电压充电至高电平，高电平电压的大小为VH-VTH4与VH中较小的值。VTH4为第四晶体管的阈值电压，此时，第六晶体管T6、第七晶体管T7和第八晶体管T8导通。驱动控制端Q的电压被下拉至第三低电平VL3，而扫描信号VG的电压被下拉至第一低电平VL1。
D.低电平维持阶段P4
低电平维持阶段P4指的是本级移位寄存器单元进入非选通状态， 扫描信号输出端G输出的扫描信号VG的电位必须维持在低电平，以避免与扫描信号输出端G相连的显示器像素中的开关晶体管误导通，导致图像信息写入错误。
在t5时刻以后，随着时钟信号VG的高电平周期性地到来，第四晶体管T4被周期性的导通，高电平端VDD通过第四晶体管T4不断地对维持控制端P进行充电，因此第六晶体管T6、第七晶体管T7和第八晶体管T8也时刻保持导通状态，从而维持扫描信号VG为低电平。
值得注意的是，在低电平维持阶段P4，由于第二十晶体管T20的控制极和第一极之间存在寄生电容CGD20，当时钟信号VCK由低电平VL0跳变到高电平VH时，会在驱动控制端Q产生一个耦合电压ΔVQ，该现象称为时钟馈通效应。耦合电压ΔVQ的大小可以表示为：ΔVQ＝CGD20*(VH-VL0)/CQ；其中CQ为驱动控制端Q的总电容。当ΔVQ大于第二十晶体管T20的阈值电压VTH20时，会导致第二十晶体管T20开启，时钟信号VCK就会对扫描信号输出端G充电，从而导致扫描信号输出端G产生较大的噪声电压，并且增大了电路的功耗。对第二十晶体管T20而言，其控制极的电压为VL3+ΔVQ，其第二极电压为VL1，当VL3+ΔVQ-VL1<VTH20时，第二十晶体管T20可以被完全关断，不仅可以抑制时钟馈通效应减小扫描信号VG的输出噪声，还可以抑制第二十晶体管T20的漏电，降低电路的功耗；对第五晶体管T5而言，其控制极的电压为VL3+ΔVQ，其第二极的电压为VL2。当VL3+ΔVQ-VL2<VTH5时，第五晶体管T5可以被可靠地关断。因此，维持控制端P通过第五晶体管T5的漏电得到了抑制，不仅可以减低电路的功耗，而且使得P端的电压可以稳定的维持在高电平，保证低电平维持模块正常的工作。
本实施例的移位寄存器单元通过抑制电路工作的预充阶段、上拉阶段、下拉阶段以及低电平维持阶段中的晶体管的漏电，不仅可以使得移位寄存器单元在晶体管的阈值电压为负值时正常的工作，而且能够降低电路的功耗。
实施例2：
请参考图3，为本实施例二公开的另一种移位寄存器单元的电路结构图。与实施一不同的是，本实施例中的移位寄存器单元中的第一低电平端VSS1与第二低电平端VSS2为同一低电平端。
为便于叙述，第一低电平端VSS1与第二低电平端VSS2为同一低电平端，此低电平端为第一低电平端VSS1，用于输入第一低电平VL1。
请参考图4，为本实施例移位寄存器单元的一种工作时序图，其中时钟信号VCK的低电平VL0≥第一低电平VL1＞第三低电平VL3。本实施例中移位寄存器单元的工作过程与实施例一中的移位寄存器单元基本相 同，在此不再赘述。
本实施例所示的移位寄存器单元同实话例一所示的移位寄存器单元相比，其优势在于：减少了一路低电平输入，电路结构得到进一步简化。
实施例3：
请参考图5，在实施例二的基础上，本实施例中驱动模块12还包括第二驱动子模块122、第三驱动子模块123、第一传递信号输出端、第二传递信号输出端和第四脉冲信号输入端，其中其中第一传递信号输出端，用于输出第一传递信号VC1；第二传递信号输出端，用于输出第二传递信号VC2；第四脉冲信号输入端，用于输入第四脉冲信号VI4。
第二驱动子模块122连接于驱动控制端Q、时钟信号输入端和第一传递信号输出端之间，用于当驱动控制端Q为高电平时将时钟信号VCK传输至第一传递信号输出端。具体地，第二驱动子模块122包括第二十一晶体管T21；第二十一晶体管T21的控制极连接于驱动控制端Q，第一极连接于时钟信号输入端，第二极连接于第一传递信号输出端。
第三驱动子模块123连接于第四脉冲信号输入端、第一传递信号输出端、第二传递信号输出端和高电平端VDD之间，用于当第四脉冲信号VI4或第一传递信号VC1为高电平时将高电平端VDD的电压传输至第二传递信号输出端；具体地，第三驱动子模块123包括第二十二晶体管T22和第二十三晶体管T23；第二十二晶体管T22的控制极连接于第一传递信号输出端；第二十三晶体管T23的控制极连接于第四脉冲信号输入端；第二十二晶体管T22和第二十三晶体管T23的第一极都连接于高电平端VDD，第二极都连接于第二传递信号输出端。
由于驱动模块12增加了第二驱动子模块122和第三驱动子模块123，相应地，在实施例一的基础上，低电平维持模块14中的维持子模块12还与第一传递信号输出端、第二传递信号输出端相连；第一传递信号输出端还用于给维持子模块142在时钟信号VCK的第一时钟周期的低电平时段和高电平时段内分别提供一低电平VL0和高电平VH，以配合维持控制端P使驱动控制端Q不漏电；而维持控制子模块141还用于当驱动控制端Q为低电平时控制维持子模块142将第一传递信号VC1、第二传递信号VC2分别维持至第三低电平VL3、第一低电平VL1；具体地，维持子模块142包括第六晶体管T6、第七晶体管T7、第八晶体管T8和第九晶体管T9；第六晶体管T6、第七晶体管T7、第八晶体管T8和第九晶体管T9的控制极共同连接于所述维持控制端P；第六晶体管T6的第一极连接于驱动控制端Q，第二极连接于第七晶体管T7的第一极并共同连接于所述第一传递信号输出端；在这里第六晶体管T6的第二极和第七晶体管T7的第一极共同连接于第一传递信号输出端，一方面，此 种结构使第一传递信号输出端在寄存器单元非选通时段被维持为低电平，另一方面，在寄存器单元选通阶段，第一传递信号输出端起到了给维持子模块142在时钟信号VCK的第一时钟周期的低电平时段和高电平时段内分别提供一低电平VL0和高电平VH，以配合维持控制端P使驱动控制端Q不漏电的作用；第七晶体管T7的第二极连接于第二低电平端VSS3；第八晶体管T8的第一极连接于扫描信号输出端G，第二极连接于第一低电平端VSS1；第九晶体管T9的第一极连接于第二传递信号输出端，第二极连接于第一低电平端VSS1。
请参考图6，为本实施例中移位寄存器单元的一种工作时序图。
在本实施例中，VL0>VL1>VL3；第一脉冲信号VI1的高电平比时钟信号VCK的一个高电平超前半个时钟周期；第二脉冲信号VI2的高电平持续时间是第一脉冲信号VI1高电平的两倍，且第二脉冲信号VI2的高电平的上升沿同步于第一脉冲信号VI1的高电平的上升沿，下降沿滞后于第一脉冲信号VI1的高电平的下降沿；第三脉冲信号VL3的高电平滞后于第一脉冲信号VI1的高电平四分之五个时钟周期；第四脉冲信号VI4的高电平滞后于第一脉冲信号VI1的高电平一个时钟周期。
下面详细介绍本实施例中移位寄存器单元的工作过程。
A.预充阶段P1
预充阶段P1是指本级移位寄存器单元处于选通阶段，驱动控制端Q被充电到高电平的过程。
在t1时刻，时钟信号VCK为低电平VL0，第一脉冲信号VI1和第二脉冲信号VI2同时上升为高电平。因此第一晶体管T1导通，驱动控制端Q被充电至高电平，高电平的大小为VH-VTH1和VH中较小的值即Min(VH-VTH1，VH)，其中VTH1为第一晶体管T1的阈值电压。驱动控制端Q被充电至高电平，因此第二十晶体管T20和第二十一晶体管T21导通，将扫描信号输出端和第一传递信号输出端的电压放电至时钟信号VCK的低电平VL0。
另一方面，时钟信号VCK为低电平VL0，因此第四晶体管T4被关断；驱动控制端Q为高电平，因此第五晶体管T5导通；第四晶体管T4被关断和第五晶体管T5导通，因此维持控制端P的电位下拉至第一低电平VL1。
对于第六晶体管T6，VGS＝VL1-VL0<0，当第六晶体管T6的阈值电压VTH6为正时，其被可靠地关断；当第六晶体管T6的阈值电压VTH6为负时，只需VGS＝VL1-VL0<VTH6，第六晶体管T6仍被可靠地关断。尽管此时第七晶体管T7的VGS＝VL1-VL3>0，其处于弱导通状态，但由于第六晶体管T6被可靠地关断，驱动控制端Q不会通过晶体管T6和晶体管T7漏电。
综上所述，在预充阶段P1，驱动控制端Q被充电到高电平Min(VH-VTH1，VH)，且驱动控制端Q的漏电可以得到抑制。
B.上拉阶段P2
上拉阶段P2是指本级移位寄存器单元处于选通阶段，扫描信号输出端和第一传递信号输出端被充电至高电平的过程。
在t2时刻，第一脉冲信号VI1的电压下降为VL0，第一晶体管T1被关断，但驱动控制端Q仍然为高电平，因此第二十晶体管T20和第二十一晶体管T21仍然导通。在t2时刻，时钟信号VCK的电压由VL0上升为VH，并通过导通的第二十晶体管T20对扫描信号输出端进行快速的充电，通过导通的第二十一晶体管T21对第一传递信号输出端进行快速的充电。具体地，在此过程中，随着扫描信号VG的电压上升，驱动控制端Q的电压也被抬高到更高的电压，而驱动控制端Q的电压被抬高又反过来增大了第二十晶体管T20和第二十一晶体管T21的驱动能力，使得扫描信号VG的电压得以快速的上升至高电平VH。随着第一传递信号VC1电压的上升，第二十二晶体管T22导通，高电平端VDD通过导通的第二十二晶体管T22对第二传递信号输出端充电，第二传递信号VC2的电压被充电至VH-VTH22和VH的较小数值Min(VH-VTH22，VH)，其中VTH22为第二十二晶体管T22的阈值电压。
上述驱动控制端Q的电压被抬升的过程被称为自举。一般来说，在驱动控制端Q自举的过程中，驱动控制端Q应当保持浮空状态，这样才能被自举到较高的电压，换言之，驱动控制端Q若漏电则会严重影响Q的自举电压的大小，从而削弱第二十晶体管T20和第二十一晶体管T21的驱动能力，进而导致扫描信号VG的上升时间延迟增大，甚至电路失效，尤其是在当电路中晶体管的阈值电压为负值时更容易出现这种情况。而在在本实施例中移位寄存器单元的上拉阶段P2即t2到t3时刻，驱动控制端Q不会通过第一晶体管T1和第三晶体管T3漏电：第二脉冲信号VI2的电压仍保持为高电平且第一脉冲信号VI1和第三脉冲信号VI3为低电平，因此第一晶体管T1和第三晶体管T3被可靠地关断；驱动控制端Q也不会通过第七晶体管T7和第六晶体管T6漏电：虽然时钟信号VCK的电压为高电平VH，因此第四晶体管T4导通，但驱动控制端Q自举到更高的电平，从而第五晶体管T5导通且驱动力要远大于第四晶体管T4，所以维持控制端P的电位仍然为第一低电平VL1，因此对于第六晶体管T6，VGS＝VL1-VH，VGS远小于零，所以其被可靠地关断，驱动控制端Q不会通过晶体管T6和晶体管T7漏电。
综上所述，驱动控制端Q不会漏电，从而驱动控制端Q可以顺利自举，进而又保证了第二十晶体管T20保持较大的驱动能力。
需要注意的是，当阈值电压为负时，第七晶体管T7、第八晶体管 T8和第九晶体管T9会处于弱导通状态，但是由于第二十晶体管T20、第二十一晶体管T21和第二十二晶体管T22有较大的驱动能力，因此第七晶体管T7、第八晶体管T8和第九晶体管T9的微弱漏电不会显著地影响到扫描信号VG、第一传递信号VC1和每台二传递信号VC2的上升过程。
C.下拉阶段P3
下拉阶段P3指的是驱动控制端Q、扫描信号VG、第一传递信号VC1的电压被下拉至低电平的过程。
在t3时刻，时钟信号VCK由高电平VH下降为VL0，此时驱动控制端Q的电压仍然为很高的电平，第二十晶体管T20和第二十一晶体管T21仍然保持导通，因此扫描信号输出端和第一传递信号输出端分别通过第二十晶体管T20、第二十一晶体管T21被快速的放电至VL0。在此过程中，随着扫描信号输出端的电压不断下降，驱动控制端Q的电压也在不断地下降，当扫描信号VG的电压为VL0时，驱动控制端Q的电压也下降为t1时刻的预充电压Min(VH-VTH1，VH)。第一传递信号VC1的电压被放电至VL0，第二十二晶体管T22被关断，但是第四脉冲信号VI4上升为高电平，因此第二十三晶体管T23导通，高电平端VDD继续通过导通的晶体管T23对第二传递信号输出端充电，因此第二传递信号VC2保持为高电平。
在t4时刻，第三脉冲信号VI3上升为高电平VH，因此第三晶体管T3导通，而此时第二脉冲信号VI2已经下降为低电平VL1，所以驱动控制端Q的电压下拉至第一低电平VL1。
在t5时刻，时钟信号VCK由低电平VL0上升为高电平VH。第四晶体管T4导通，高电平端VDD通过导通的第四晶体管T4对维持控制端P进行充电，将维持控制端P的电压充电至高电平，高电平电压的大小为VH-VTH4与VH中较小的值。VTH4为第四晶体管的阈值电压，此时，第六晶体管T6、第七晶体管T7、第八晶体管T8和第九晶体管T9导通。驱动控制端Q和第一传递信号VC1的电压被下拉至第三低电平VL3，而扫描信号VG和第二传递信号VC2的电压被下拉至第一低电平VL1。
D.低电平维持阶段P4
低电平维持阶段P4指的是本级移位寄存器单元进入非选通状态，扫描信号输出端G输出的扫描信号VG的电位维持在低电平，以避免与扫描信号输出端G相连的显示器像素中的开关晶体管误导通，导致图像信息写入错误；第一传递信号VC1和第二传递信号VC2的电压维持在相应的低电平，以避免与本级移位寄存器单元相级联的前后级移位寄存器单元产生错误的输入。
在t5时刻以后，随着时钟信号VG的高电平周期性地到来，第四晶 体管T4被周期性的导通，高电平端VDD通过第四晶体管T4不断地对维持控制端P进行充电，因此第六晶体管T6、第七晶体管T7、第八晶体管T8和第九晶体管T9也时刻保持导通状态，从而维持扫描信号VG、第一传递信号VC1和第二传递信号VC2的电压为相应的低电平。
值得注意的是，在低电平维持阶段P4，由于第二十晶体管T20的控制极和第一极之间存在寄生电容CGD20，当时钟信号VCK由低电平VL0跳变到高电平VH时，会在驱动控制端Q产生一个耦合电压ΔVQ，该现象称为时钟馈通效应。耦合电压ΔVQ的大小可以表示为：ΔVQ＝CGD20*(VH-VL0)/CQ；其中CQ为驱动控制端Q的总电容。当ΔVQ大于第二十晶体管T20的阈值电压VTH20时，会导致第二十晶体管T20开启，时钟信号VCK就会对扫描信号输出端G充电，从而导致扫描信号输出端G产生较大的噪声电压，并且增大了电路的功耗。对第二十晶体管T20而言，其控制极的电压为VL3+ΔVQ，其第二极电压为VL1，当VL3+ΔVQ-VL1<VTH20时，第二十晶体管T20可以被完全关断，不仅可以抑制时钟馈通效应减小扫描信号VG的输出噪声，还可以抑制第二十晶体管T20的漏电，降低电路的功耗；类似地，对于第二十一晶体管T21，当VL3+ΔVQ-VL1<VTH21时，可以减小第一传递信号的输出噪声，并且抑制晶体管T21的漏电。
对于第二传递信号输出端而言，时钟馈通效应相对较小。对于第二十二晶体管T22和第二十三晶体管T23，其控制极电压为VL3，其第二极电压为VL1，当VL3-VL1<VTH22或者VL3-VL1<VTH23时，第二十二晶体管T22和第二十三晶体管T23可以被可靠地关断，其漏电得到抑制。
对第五晶体管T5而言，其控制极的电压为VL3+ΔVQ，其第二极的电压为VL1。当VL3+ΔVQ-VL1<VTH5时，第五晶体管T5可以被可靠地关断。因此，维持控制端P通过第五晶体管T5的漏电得到了抑制，不仅可以减低电路的功耗，而且使得P端的电压可以稳定的维持在高电平，保证低电平维持模块正常的工作。
本实施例的移位寄存器单元通过抑制电路工作的预充阶段、上拉阶段、下拉阶段以及低电平维持阶段中的晶体管的漏电，不仅可以使得移位寄存器单元在晶体管的阈值电压为负值时正常的工作，而且能够降低电路的功耗。
实施例4：
请参考图7，为本实施四公开的一种移位寄存器单元的电路结构图，与实施例三不同的是：本实施例中，移位寄存器单元还包括第二低电平端VSS2，用于输入第二低电平VL2，其中VL0≥VL1＞VL2＞VL3。
具体地，与实施例三相比，第五晶体管T5不是连接到第一低电平 端VSS1而是连接到第二低电平端VSS2。
请参考图8，为本实施例中移位寄存器单元的一种工作时序图，本实施例中移位寄存器单元的工作过程与实施例三中的移位寄存器基本相同，在此不再赘述。需要注意的是，当时钟信号VCK的低电平VL0与第一低电平VL1相等时，本实施例的移位寄存器单元的扫描信号VG只有一个固定的低电平。
与实施例三相经，本实施例的移位寄存器单元的功耗可以进一步降低，原因如下：在上拉阶段P2，维持控制端P的电压被下拉至第二低电平VL2。对与第八晶体管T8和第九晶体管T9，其控制极的电压为VL2，其第二极的电压为VL1，当第八晶体管T8的VGS＝VL2-VL1<VTH8且第九晶体管T9的VGS＝VL2-VL1<VTH9时，第八晶体管T8和第九晶体管T9被可靠地关断。因此在上拉阶段P2，电路的功耗进一步降低，扫描信号VG和第二传递信号VC2的上升延迟可以进一步地减小。
因此，本实施例所示的移位寄存器单元与实施例三所示的移位寄存器单元相比，增加了一个低电平端VSS2，但电路的功耗得到了进一步地降低，电路的输出延迟得到了优化。
实施例5：
请参考图9，为本实施例五公开的一种移位寄存器单元的电路结构图，与实施例三不同的是：
本实施例中，第三驱动子模块123连接于驱动控制端Q、高电平端VDD和第二传递信号输出端之间，用于当驱动控制端Q为高电平时将高电平端VDD的电压传输至第二传递信号输出端；具体地，第三驱动子模块123包括第二十二晶体管T22；第二十二晶体管T22的控制极连接于驱动控制端Q，第一极连接于高电平端VDD，第二极连接于第二传递信号输出端。
请参考图10，为本实施例的移位寄存器单元的一种工作时序图。本实施例中第二脉冲信号VI2的脉冲宽度为第一脉冲信号VI1的3倍，在第一脉冲信号VI1的高电平上升沿到来之前，第二脉冲信号VI2已经上升到高电平，而第二脉冲信号VI2的下降沿仍然滞后于第一脉冲信号VI1的下降沿。因此，在预充阶段P1之前，第二脉冲信号VI2已经上升为高电平，这时第一晶体管T1和第三晶体管T3可能处于弱导通并对驱动控制端Q产生微弱的充电，但是由于此时第六晶体管T6和第七晶体管T7保持强导通，因此第一晶体管T1和第三晶体管T3的漏电不会显著地影响到驱动控制端Q的电压，也不会影响电路正常的四个工作阶段——预充阶段P1、上拉阶段P2、下拉阶段P3和低电平维持阶段P4。
对于第二传递信号VC2，当驱动控制端Q的电压上升到高电平时， 第二十二晶体管T22导通，高电平端VDD通过导通的第二十二晶体管T22对第二传递信号输出端进行充电，从而使第二传递信号VC2上升为高电平。
本实施例所示的移位寄存器单元与实施例三所示的移位寄存器单元相经，其优势在于：减少了一路脉冲信号，且电路结构得到进一步简化。
实施例6：
请参照图11，为本实施例六公开的一种移位寄存器单元的电路结构图，与实施例五不同的是：本实施例中，移位寄存器单元还包括第二低电平端VSS2，用于输入第二低电平VL2，其中VL0≥VL1＞VL2＞VL3。具体地，与实施例五相比，第五晶体管T5不是连接到第一低电平端VSS1而是连接到第二低电平端VSS2。
请参考图12，为本实施例中移位寄存器单元的一种工作时序图，本实施例中移位寄存器单元的工作过程与实施例五中的移位寄存器基本相同，在此不再赘述。
因此，本实施例所示的移位寄存器单元与实施例五所示的移位寄存器单元相比，增加了一个低电平端VSS2，但电路的功耗得到了进一步地降低，电路的输出延迟得到了优化。
实施例7：
请参考图13，本实施例公开了一种移位寄存器，包括N级级联的上述实施例三所示的移位寄存器单元、第一时钟线CK1、第二时钟线CK2、第三时钟线CK3、第四时钟线CK4、第一公共低电平线SS1、第三公共低电平线SS3和公共高电平线。
第一公共低电平线SS1、第三公共低电平线SS3和公共高电平线分别连接于所有移位寄存器单元的第一低电平端VSS1、第三低电平端VSS3和高电平端VDD。
第一时钟线CK1、第二时钟线CK2、第三时钟线CK3和第四时钟线CK4提供四相交叠时钟信号，相邻两根时钟线输出的时钟信号的高电平交叠时钟周期的四分之一，具体地：
第4i+1级移位寄存器单元的时钟信号输入端连接于第一时钟线CK1；
第4i+2级移位寄存器单元的时钟信号输入端连接于第二时钟线CK2，其中第二时钟线CK2输出的时钟信号的高电平滞后于第一时钟线CK1的四分之一个时钟周期；
第4i+3级移位寄存器单元的时钟信号输入端连接于第三时钟线CK3，其中第三时钟线CK3输出的时钟信号的高电平滞后于第二时钟线 CK2的四分之一个时钟周期；
第4i+4级移位寄存器单元的时钟信号输入端连接于第四时钟线CK4，其中第四时钟线CK4输出的时钟信号的高电平滞后于第三时钟线CK3的四分之一个时钟周期。
级联的移位寄存器单元的连接方式如下：
第n级移位寄存器单元的第一脉冲信号输入端连接于第n-2级移位寄存器单元的第一传递信号输出端；
第n级移位寄存器单元的第二脉冲信号输入端连接于第n-2级移位寄存器单元的第二传递信号输出端；
第n级移位寄存器单元的第三脉冲信号输入端连接于第n+3级移位寄存器单元的第一传递信号输出端；
第n级移位寄存器单元的第四脉冲信号输入端连接于第n+2级移位寄存器单元的第一传递信号输出端；
其中，N为大于3的整数，n为大于0且小于或等于N的整数，i为非负整数。
请参照图14，为本实施例所示移位寄存器的一种工作时序图。图中VG(n-2)、VG(n-1)、VG(n)和VG(n+1)分别为第n-2、第n-1、第n和第n+1级移位寄存器单元输出的扫描信号VG，可以看到，相领两级移位寄存器单元输出的扫描信号VG互相交叠半个脉冲宽度。
请参照图15，为本实施例所示移位寄存器的一种仿真波形图，横坐标为时间，纵坐标为各级移位寄存器单元输出的扫描信号VG的电压。其中，不妨令电路中所有晶体管的阈值电压VTH为-4V，高电平VH、时钟信号VCK的低电平VL0、第一低电平VL1、第三低电平VL3的值分别为：28V、-6V、-9V、-15V。由图15可以看出，在晶体管阈值电压为负值时，本实施例所示的移位寄存器仍然能够正常工作。
本移位寄存器，每一级的移位寄存器单元的扫描信号输出端可与显示面板的栅极扫描线相连，为显示面板的一行像素单元提供栅极扫描信号。
实施例8：
请参考图16，为本实施例八公开的一种移位寄存器，与实施例七不同的是，本实施例包括N级级联的上述实施例四而非实施例三所示的移位寄存器单元。相应地，本实施例的移位寄存器，还包括第二公共低电平线SS2，其连接于所有移位寄存器单元的第二低电平端VSS2。
请参照图17，为本实施例所示移位寄存器的一种工作时序图。由于本移位寄存器中的移位寄存器单元包括三个低电平端且VL0≥VL1＞VL2＞VL3，因此当VL0＝VL1时，各级移位寄存器单元的扫描信号VG只有一 个低电平VL0。
请参照图18，为本实施例所示的移位寄存器的一种仿真波形图，横坐标为时间，纵坐标为各级移位寄存器单元输出的扫描信号VG的电压。其中，不妨令电路中所有晶体管的阈值电压VTH为-4V，高电平VH、时钟CK的低电平VL0、第一低电平VL1、第二低电平VL2、第三低电平VL3的值分别为：28V、-6V、-6V、-9V、-15V。由图18可以看出，在晶体管阈值电压为负值时，本实施例所示的移位寄存器仍然能够正常工作。需要注意的是，本实施例所示移位寄存器输出的各个扫描信号均具有唯一的低电平，其值为-6V。
实施例9：
请参考图19，为本实施例九公开的一种移位寄存器，与实施例七不同的是，本实施例包括N级级联的上述实施例五而非实施例三所示的移位寄存器单元；相应地，本实施例中各级联的移位寄存器单元的连接方式如下：
第n级移位寄存器单元的第一脉冲信号输入端连接于第n-2级移位寄存器单元的第一传递信号输出端；
第n级移位寄存器单元的第二脉冲信号输入端连接于第n-2级移位寄存器单元的第二传递信号输出端；
第n级移位寄存器单元的第三脉冲信号输入端连接于第n+3级移位寄存器单元的第一传递信号输出端。
与实施例七不同的是，本实施例中各级联的移位寄存器单元不需要配置第四脉冲信号输入端的连接方式，因为本实施例中的移位寄存器单元没有第四脉冲信号输入端。
本实施所示的移位寄存器的一种工作时序图和一种仿真波形图与实施例七的移位寄存器的相同，具体请分别参见图14和图15，在此不再赘述。
实施例10：
请参考图20，为本实施十公开的一种移位寄存器，与实施例九不同的是，本实施例包括N级级联的上述实施例六而非实施例五所示的移位寄存器单元；相应地，本实施例的移位寄存器，还包括第二公共低电平线SS2，其连接于所有移位寄存器单元的第二低电平端VSS2。
本实施所示的移位寄存器的一种工作时序图和一种仿真波形图与实施例八的移位寄存器的相同，具体请分别参见图17和图18，在此不再赘述。
以上应用了具体个例对本发明进行阐述，只是用于帮助理解本发明， 并不用以限制本发明。对于本领域的一般技术人员，依据本发明的思想，可以对上述具体实施方式进行变化。

Claims (14)

  1. 一种移位寄存器单元，其特征在于，包括：
    时钟信号输入端，用于输入时钟信号(VCK)；
    第一脉冲信号输入端，用于输入第一脉冲信号(VI1)；
    第二脉冲信号输入端，用于输入第二脉冲信号(VI2)；
    第三脉冲信号输入端，用于输入第三脉冲信号(VI3)；
    扫描信号输出端，用于输出扫描信号(VG)；
    高电平端(VDD)，用于输入高电平(VH)；
    第一低电平端(VSS1)，用于输入第一低电平(VL1)；
    第二低电平端(VSS2)，用于输入第二低电平(VL2)；
    第三低电平端(VSS3)，用于输入第三低电平(VL3)；
    驱动模块(12)，包括驱动控制端(Q)和第一驱动子模块(121)；所述第一驱动子模块(121)连接于所述驱动控制端(Q)、时钟信号输入端和扫描信号输出端之间，用于当驱动控制端(Q)为高电平时将时钟信号(VCK)传输至扫描信号输出端；
    充电模块(11)，连接于所述第一脉冲信号输入端、第二脉冲信号输入端和驱动控制端(Q)之间，用于当第一脉冲信号输入端和第二脉冲信号输入端为高电平时将驱动控制端(Q)充电至高电平；
    放电模块(13)，连接于所述第二脉冲信号输入端、第三脉冲信号输入端和驱动控制端(Q)之间，用于当第二脉冲信号输入端为低电平且第三脉冲信号输入端为高电平时将驱动控制端(Q)放电至低电平；
    低电平维持模块(14)，包括维持控制端(P)、维持控制子模块(141)和维持子模块(142)；维持控制子模块(141)连接于所述时钟信号输入端、高电平端(VDD)、第二低电平端(VSS2)和维持控制端(P)之间；所述维持子模块(142)连接于所述驱动控制端(Q)、第一低电平端(VSS1)、第三低电平端(VSS3)和维持控制端(P)之间；维持控制子模块(141)用于当驱动控制端(Q)为低电平时控制维持子模块(142)将扫描信号(VG)维持至第一低电平(VL1)；
    所述时钟信号(VCK)、第一脉冲信号(VI1)、第二脉冲信号(VI2)、第三脉冲信号(VI3)、高电平(VH)、第一低电平(VL1)、第二低电平(VL2)和第三低电平(VL3)被配置为：
    所述时钟信号(VCK)一个周期内包括先到来的时钟信号的低电平(VL0)和后到来的高电平(VH)；所述时钟信号(VCK)的低电平(VL0)≥第一低电平(VL1)＞第二低电平(VL2)＞第三低电平(VL3)，或者，时钟信号(VCK)的低电平(VL0)＞第一低电平(VL1)＝第二低电平(VL2)＞第三低电平(VL3)；
    所述第一脉冲信号(VI1)的高电平位于时钟信号(VCK)的第一时 钟周期的低电平时段内；所述维持子模块(142)在时钟信号(VCK)的第一时钟周期的低电平时段和高电平时段内分别接受一低电平(VL0)和高电平(VH)，以配合维持控制端(P)使驱动控制端(Q)不漏电；第二脉冲信号(VI2)的高电平的上升沿超前于第一脉冲信号(VI1)的高电平的下降沿，第二脉冲信号(VI2)的高电平的下降沿滞后于第一脉冲信号(VI1)的高电平的下降沿且超前于时钟信号(VCK)第二时钟周期的高电平的上升沿，第三脉冲信号(VL3)的上升沿也超前于时钟信号(VCK)的第二时钟周期的高电平的上升沿。
  2. 如权利要求1所述的移位寄存器单元，其特征在于，所述驱动模块(12)还包括：
    第二驱动子模块(122)和用于输出第一传递信号(VC1)的第一传递信号输出端；所述第二驱动子模块(122)连接于所述驱动控制端(Q)、时钟信号输入端和第一传递信号输出端之间，用于当驱动控制端(Q)为高电平时将时钟信号(VCK)传输至第一传递信号输出端。
  3. 如权利要求2所述的移位寄存器单元，其特征在于：所述第二驱动子模块(122)包括第二十一晶体管(T21)，其中所述第二十一晶体管(T21)的控制极连接于所述驱动控制端(Q)，第一极连接于时钟信号输入端，第二极连接于第一传递信号输出端。
  4. 如权利要求2所述的移位寄存器单元，其特征在于，所述驱动模块(12)还包括：
    第三驱动子模块(123)、第四脉冲信号输入端和用于输出第二传递信号(VC2)的第二传递信号输出端；所述第四脉冲信号输入端，用于输入第四脉冲信号(VI4)，其中第四脉冲信号(VI4)的高电平滞后于第一脉冲信号(VI1)的高电平一个时钟周期；所述第二传递信号输出端，用于输出第二传递信号(VC2)；所述第三驱动子模块(123)连接于第四脉冲信号输入端、第一传递信号输出端、第二传递信号输出端和高电平端(VDD)之间，用于当第四脉冲信号(VI4)或第一传递信号(VC1)为高电平时将高电平端(VDD)的电压传输至第二传递信号输出端。
  5. 如权利要求4所述的移位寄存器单元，其特征在于：所述第三驱动子模块(123)包括第二十二晶体管(T22)和第二十三晶体管(T23)；其中所述第二十二晶体管(T22)的控制极连接于所述第一传递信号输出端；所述第二十三晶体管(T23)的控制极连接于第四脉冲信号输入端；所述第二十二晶体管(T22)和第二十三晶体管(T23)的第一极都连接于高电平端(VDD)，第二极都连接于第二传递信号输出端。
  6. 如权利要求2所述的移位寄存器单元，其特征在于，所述驱动模块(12)还包括：
    第三驱动子模块(123)和用于输出第二传递信号(VC2)的第二传 递信号输出端；所述第三驱动子模块连接于所述驱动控制端(Q)、第二传递信号输出端和高电平端(VDD)之间，用于当驱动控制端(Q)为高电平时将高电平端(VDD)的电压传输至第二传递信号输出端。
  7. 如权利要求6所述的移位寄存器单元，其特征在于：所述第三驱动子模块(123)包括第二十二晶体管(T22)，其中所述第二十二晶体管(T22)的控制极连接于所述驱动控制端(Q)，第一极连接于高电平端(VDD)，第二极连接于第二传递信号输出端。
  8. 如权利要求4至7中任一项所述的移位寄存器单元，其特征在于：
    所述维持子模块(142)还与第一传递信号输出端、第二传递信号输出端相连；
    所述第一传递信号输出端还用于给维持子模块(142)在时钟信号(VCK)的第一时钟周期的低电平时段和高电平时段内分别提供一低电平(VL0)和高电平(VH)，以配合维持控制端(P)使驱动控制端(Q)不漏电；
    所述维持控制子模块(141)还用于当驱动控制端(Q)为低电平时控制维持子模块(142)将第一传递信号(VC1)、第二传递信号(VC2)分别维持至第三低电平(VL3)、第一低电平(VL1)。
  9. 如权利要求8所述的移位寄存器单元，其特征在于：
    所述维持控制子模块(141)包括第四晶体管(T4)和第五晶体管(T5)；所述第四晶体管(T4)的控制极连接于所述时钟信号输入端，第一极连接于高电平端(VDD)，第二极连接于维持控制端(P)；所述第五晶体管(T5)的控制极连接于驱动控制端(Q)，第一极连接于维持控制端(P)，第二极连接于第二低电平端(VSS2)；
    所述维持子模块(142)包括第六晶体管(T6)、第七晶体管(T7)、第八晶体管(T8)和第九晶体管(T9)；所述第六晶体管(T6)、第七晶体管(T7)、第八晶体管(T8)和第九晶体管(T9)的控制极共同连接于所述维持控制端(P)；所述第六晶体管(T6)的第一极连接于驱动控制端(Q)，第二极连接于第七晶体管(T7)的第一极并共同连接于所述第一传递信号输出端；第七晶体管(T7)的第二极连接于第二低电平端(VSS3)；所述第八晶体管(T8)的第一极连接于扫描信号输出端(G)，第二极连接于第一低电平端(VSS1)；所述第九晶体管(T9)的第一极连接于第二传递信号输出端，第二极连接于第一低电平端(VSS1)。
  10. 如权利要求1或8所述的移位寄存器单元，其特征在于：
    所述充电模块(11)包括第一晶体管(T1)；所述第一晶体管(T1)的控制极连接于所述第一脉冲信号输入端，第一极连接于第二脉冲信号输入端，第二极连接于驱动控制端(Q)；
    所述放电模块(13)包括第三晶体管(T3)；所述第三晶体管(T3) 的控制极连接于所述第三脉冲信号输入端，第一极连接于第二脉冲信号输入端，第二极连接于驱动控制端(Q)；
    所述第一驱动子模块(121)包括第二十晶体管(T20)和第一电容(C1)；所述第二十晶体管(T20)的控制极连接于所述驱动控制端(Q)，第一极连接于时钟信号输入端，第二极连接于扫描信号输出端(G)；所述第一电容(C1)连接于所述驱动控制端(Q)与扫描信号输出端之间。
  11. 如权利要求1所述的移位寄存器单元，其特征在于：
    所述维持控制子模块(141)包括第四晶体管(T4)和第五晶体管(T5)；所述第四晶体管(T4)的控制极连接于所述时钟信号输入端，第一极连接于高电平端(VDD)，第二极连接于维持控制端(P)；所述第五晶体管(T5)的控制极连接于驱动控制端(Q)，第一极连接于维持控制端(P)，第二极连接于第二低电平端(VSS2)；
    所述维持子模块(142)包括第六晶体管(T6)、第七晶体管(T7)和第八晶体管(T8)；所述第六晶体管(T6)、第七晶体管(T7)和第八晶体管(T8)的控制极共同连接于所述维持控制端(P)；第六晶体管(T6)的第一极连接于驱动控制端(Q)，第二极连接于第七晶体管(T7)的第一极，所述第六晶体管(T6)的第二极还在所述时钟信号(VCK)的第一时钟周期的低电平时段和高电平时段内分别接受一低电平(VL0)和高电平(VH)，以配合维持控制端(P)使驱动控制端(Q)不漏电；第七晶体管(T7)的第二极连接于第三低电平端(VSS3)；第八晶体管(T8)的第一极连接于扫描信号输出端，第二极连接于第一低电平端(VSS1)。
  12. 如权利要求1、9或11所述的移位寄存器单元，其特征在于：所述第一低电平端(VSS1)和第二低电平端(VSS2)为同一低电平端。
  13. 一种移位寄存器，其特征在于，包括N级级联的如权利要求4或5所述的移位寄存器单元、第一时钟线(CK1)、第二时钟线(CK2)、第三时钟线(CK3)、第四时钟线(CK4)、第一公共低电平线(SS1)、第二公共低电平线(SS2)、第三公共低电平线(SS3)和公共高电平线；
    所述第一公共低电平线(SS1)、第二公共低电平线(SS2)、第三公共低电平线(SS3)和公共高电平线分别连接于所有移位寄存器单元的第一低电平端(VSS1)、第二低电平端(VSS2)、第三低电平端(VSS3)和高电平端(VDD)；
    第4i+1级移位寄存器单元的时钟信号输入端连接于第一时钟线(CK1)；
    第4i+2级移位寄存器单元的时钟信号输入端连接于第二时钟线(CK2)，其中第二时钟线(CK2)输出的时钟信号的高电平滞后于第一时钟线(CK1)的四分之一个时钟周期；
    第4i+3级移位寄存器单元的时钟信号输入端连接于第三时钟线 (CK3)，其中第三时钟线(CK3)输出的时钟信号的高电平滞后于第二时钟线(CK2)的四分之一个时钟周期；
    第4i+4级移位寄存器单元的时钟信号输入端连接于第四时钟线(CK4)，其中第四时钟线(CK4)输出的时钟信号的高电平滞后于第三时钟线(CK3)的四分之一个时钟周期；
    第n级移位寄存器单元的第一脉冲信号输入端连接于第n-2级移位寄存器单元的第一传递信号输出端；
    第n级移位寄存器单元的第二脉冲信号输入端连接于第n-2级移位寄存器单元的第二传递信号输出端；
    第n级移位寄存器单元的第三脉冲信号输入端连接于第n+3级移位寄存器单元的第一传递信号输出端；
    第n级移位寄存器单元的第四脉冲信号输入端连接于第n+2级移位寄存器单元的第一传递信号输出端；
    其中，N为大于3的整数，n为大于0且小于或等于N的整数，i为非负整数。
  14. 一种移位寄存器，其特征在于，包括N级级联的如权利要求6或7所述的移位寄存器单元、第一时钟线(CK1)、第二时钟线(CK2)、第三时钟线(CK3)、第四时钟线(CK4)、第一公共低电平线(SS1)、第二公共低电平线(SS2)、第三公共低电平线(SS3)和公共高电平线；
    所述第一公共低电平线(SS1)、第二公共低电平线(SS2)、第三公共低电平线(SS3)和公共高电平线分别连接于所有移位寄存器单元的第一低电平端(VSS1)、第二低电平端(VSS2)、第三低电平端(VSS3)和高电平端(VDD)；
    第4i+1级移位寄存器单元的时钟信号输入端连接于第一时钟线(CK1)；
    第4i+2级移位寄存器单元的时钟信号输入端连接于第二时钟线(CK2)，其中第二时钟线(CK2)输出的时钟信号的高电平滞后于第一时钟线(CK1)的四分之一个时钟周期；
    第4i+3级移位寄存器单元的时钟信号输入端连接于第三时钟线(CK3)，其中第三时钟线(CK3)输出的时钟信号的高电平滞后于第二时钟线(CK2)的四分之一个时钟周期；
    第4i+4级移位寄存器单元的时钟信号输入端连接于第四时钟线(CK4)，其中第四时钟线(CK4)输出的时钟信号的高电平滞后于第三时钟线(CK3)的四分之一个时钟周期；
    第n级移位寄存器单元的第一脉冲信号输入端连接于第n-2级移位寄存器单元的第一传递信号输出端；
    第n级移位寄存器单元的第二脉冲信号输入端连接于第n-2级移位 寄存器单元的第二传递信号输出端；
    第n级移位寄存器单元的第三脉冲信号输入端连接于第n+3级移位寄存器单元的第一传递信号输出端；
    其中，N为大于3的整数，n为大于0且小于或等于N的整数，i为非负整数。
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