WO2016155039A1 - 液晶显示面板及液晶显示装置 - Google Patents

液晶显示面板及液晶显示装置 Download PDF

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Publication number
WO2016155039A1
WO2016155039A1 PCT/CN2015/076701 CN2015076701W WO2016155039A1 WO 2016155039 A1 WO2016155039 A1 WO 2016155039A1 CN 2015076701 W CN2015076701 W CN 2015076701W WO 2016155039 A1 WO2016155039 A1 WO 2016155039A1
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WIPO (PCT)
Prior art keywords
switch tube
signal
liquid crystal
crystal display
switching transistor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2015/076701
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English (en)
French (fr)
Inventor
吴晶晶
郭东胜
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
TCL China Star Optoelectronics Technology Co Ltd
Original Assignee
Shenzhen China Star Optoelectronics Technology Co Ltd
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Filing date
Publication date
Application filed by Shenzhen China Star Optoelectronics Technology Co Ltd filed Critical Shenzhen China Star Optoelectronics Technology Co Ltd
Priority to US14/650,313 priority Critical patent/US9792873B2/en
Publication of WO2016155039A1 publication Critical patent/WO2016155039A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3696—Generation of voltages supplied to electrode drivers
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0289—Details of voltage level shifters arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0291—Details of output amplifiers or buffers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3685—Details of drivers for data electrodes
    • G09G3/3688—Details of drivers for data electrodes suitable for active matrices only

Definitions

  • the present invention relates to the field of liquid crystal display, and in particular to a liquid crystal display panel and a liquid crystal display device.
  • the driving chip of the scan line of the conventional liquid crystal display panel outputs a scan signal through a level shifter and an output buffer, wherein the level shifter converts the input voltage signal into a high-low level signal, and the output buffer includes multiple stages. Inverting amplifiers, each stage of the inverting amplifier inverts the high and low level signals, so that the driver chip finally outputs a scanning signal with sufficient driving capability.
  • the inverting amplifier amplifies the high and low level signals, and inverts the high and low level signals.
  • an even number of inverting amplifiers must be set in the output buffer to match the high and low voltages.
  • the flat signal is subjected to an even number of inverting amplifications. Since an even number of inverting amplifiers must be provided, it is possible to increase the manufacturing cost of the liquid crystal display panel.
  • the invention reduces the manufacturing cost of the liquid crystal display panel, and solves the technical problem of high production cost of the existing liquid crystal display panel and the liquid crystal display device.
  • the invention provides a liquid crystal display panel comprising:
  • a driving circuit for providing a data signal and a scanning signal
  • a pixel unit configured to perform image display using the data signal under control of the scan signal
  • the driving circuit comprises:
  • a level shifter for converting an input voltage signal into a high level signal or a low level signal; the level shifter comprising a non-inverting input, an inverting input, and a level signal output;
  • An output buffer for amplifying the high level signal or the low level signal comprising a plurality of inverting amplifiers
  • the voltage signal of the input of the non-inverting input and the inverting input of the level shifter is determined according to the number of the inverting amplifiers in the output buffer.
  • the output buffer includes an even number of the inverting amplifiers
  • the non-inverting input terminal of the level shifter inputs a positive phase voltage signal
  • the level An inverting voltage signal is input to the inverting input of the converter.
  • the output buffer includes an odd number of the inverting amplifiers
  • the non-inverting voltage input signal of the level shifter inputs the inverted voltage signal
  • the inverting input of the level shifter inputs the positive phase voltage signal.
  • the inverted voltage signal is generated by the positive phase voltage signal through a NOT gate.
  • the level shifter includes a first switch tube, a second switch tube, a third switch tube, a fourth switch tube, a fifth switch tube, a sixth switch tube, and a seventh a switch tube and an eighth switch tube;
  • a control end of the first switch tube is connected to the positive phase input end, an input end of the first switch tube is connected to the low level signal, and an output end of the first switch tube is respectively connected to the first a control end of the eighth switch tube, an output end of the third switch tube, and a control end of the fourth switch tube;
  • a control end of the second switch tube is connected to the inverting input end, an input end of the second switch tube is connected to the low level signal, and an output end of the second switch tube is respectively connected to the first a control end of the third switch tube, an output end of the fourth switch tube, and a control end of the seventh switch tube;
  • the input end of the third switch tube is connected to the high level signal, and the input end of the fourth switch tube is connected to the high level signal;
  • the input end of the fifth switch tube is connected to the low level signal, the control end of the fifth switch tube is connected to the level signal output end, and the output end of the fifth switch tube is respectively associated with the An output end of the seventh switch tube and a control end of the sixth switch tube are connected;
  • An input end of the sixth switch tube is connected to the low level signal, and an output end of the sixth switch tube is connected to the level signal output end;
  • An input end of the seventh switch tube is connected to the high level signal
  • an input end of the eighth switch tube is connected to the high level signal
  • an output end of the eighth switch tube is opposite to the level The signal output is connected.
  • the first switching transistor, the second switching transistor, the fifth switching transistor, and the sixth switching transistor are n-channel MOSFETs.
  • the third switching transistor, the fourth switching transistor, the seventh switching transistor, and the eighth switching transistor are p-channel MOSFETs.
  • the present invention also provides a liquid crystal display device including a backlight and a liquid crystal display panel, the liquid crystal display panel comprising:
  • a driving circuit for providing a data signal and a scanning signal
  • a pixel unit configured to perform image display using the data signal under control of the scan signal
  • the driving circuit comprises:
  • a level shifter for converting an input voltage signal into a high level signal or a low level signal; the level shifter comprising a non-inverting input, an inverting input, and a level signal output;
  • An output buffer for amplifying the high level signal or the low level signal comprising a plurality of inverting amplifiers
  • the voltage signal of the input of the non-inverting input and the inverting input of the level shifter is determined according to the number of the inverting amplifiers in the output buffer.
  • the output buffer includes an even number of the inverting amplifiers
  • the non-inverting input terminal of the level shifter inputs a positive phase voltage signal
  • the level An inverting voltage signal is input to the inverting input of the converter.
  • the output buffer includes an odd number of the inverting amplifiers
  • the non-inverting voltage input signal of the level shifter inputs the inverted voltage signal
  • the inverting input of the level shifter inputs the positive phase voltage signal.
  • the inverted voltage signal is generated by the positive phase voltage signal through a NOT gate.
  • the level shifter includes a first switch tube, a second switch tube, a third switch tube, a fourth switch tube, a fifth switch tube, a sixth switch tube, and a seventh a switch tube and an eighth switch tube;
  • a control end of the first switch tube is connected to the positive phase input end, an input end of the first switch tube is connected to the low level signal, and an output end of the first switch tube is respectively connected to the first a control end of the eighth switch tube, an output end of the third switch tube, and a control end of the fourth switch tube;
  • a control end of the second switch tube is connected to the inverting input end, an input end of the second switch tube is connected to the low level signal, and an output end of the second switch tube is respectively connected to the first a control end of the third switch tube, an output end of the fourth switch tube, and a control end of the seventh switch tube;
  • the input end of the third switch tube is connected to the high level signal, and the input end of the fourth switch tube is connected to the high level signal;
  • the input end of the fifth switch tube is connected to the low level signal, the control end of the fifth switch tube is connected to the level signal output end, and the output end of the fifth switch tube is respectively associated with the An output end of the seventh switch tube and a control end of the sixth switch tube are connected;
  • An input end of the sixth switch tube is connected to the low level signal, and an output end of the sixth switch tube is connected to the level signal output end;
  • An input end of the seventh switch tube is connected to the high level signal
  • an input end of the eighth switch tube is connected to the high level signal
  • an output end of the eighth switch tube is opposite to the level The signal output is connected.
  • the first switching transistor, the second switching transistor, the fifth switching transistor, and the sixth switching transistor are n-channel MOSFETs.
  • the third switching transistor, the fourth switching transistor, the seventh switching transistor, and the eighth switching transistor are p-channel MOSFETs.
  • the liquid crystal display panel and the liquid crystal display device of the present invention determine the positive phase input terminal and the inverting input of the level shifter according to the number of inverting amplifiers in the output buffer.
  • the input voltage signal of the terminal can effectively reduce the manufacturing cost of the liquid crystal display panel; and solves the technical problem of high production cost of the existing liquid crystal display panel and the liquid crystal display device.
  • FIG. 1 is a schematic structural view of a preferred embodiment of a liquid crystal display device of the present invention.
  • FIG. 2A is a schematic structural view of a driving circuit of a first preferred embodiment of a liquid crystal display device of the present invention
  • FIG. 2B is a schematic structural view of a level shifter of a driving circuit of a first preferred embodiment of the liquid crystal display device of the present invention
  • 2C is a schematic diagram of input and output signals of a level shifter of a driving circuit of a first preferred embodiment of the liquid crystal display device of the present invention
  • 3A is a schematic structural view of a driving circuit of a second preferred embodiment of the liquid crystal display device of the present invention.
  • 3B is a schematic structural view of a level shifter of a driving circuit of a second preferred embodiment of the liquid crystal display device of the present invention.
  • 3C is a schematic diagram showing input and output signals of a level shifter of a driving circuit of a second preferred embodiment of the liquid crystal display device of the present invention.
  • FIG. 1 is a schematic structural view of a preferred embodiment of a liquid crystal display panel of the present invention.
  • the liquid crystal display panel 10 of the preferred embodiment includes a driving circuit 11, a data line 12, a scanning line 13, and a pixel unit 14.
  • the driving circuit 11 is for providing a data signal for transmitting a data signal, the scanning line 13 for transmitting a scanning signal, and the pixel unit 14 for performing image display using the data signal under the control of the scanning signal.
  • FIG. 2A is a schematic structural view of a driving circuit of a first preferred embodiment of the liquid crystal display device of the present invention
  • FIG. 2B is a diagram showing the driving circuit of the first preferred embodiment of the liquid crystal display device of the present invention.
  • FIG. 2C is a schematic diagram showing the input and output signals of the level shifter of the driving circuit of the first preferred embodiment of the liquid crystal display device of the present invention.
  • the driving circuit of the liquid crystal display panel includes a level shifter 21 and an output buffer 22 for converting the input voltage signal into a high level signal or a low level signal.
  • the flat converter 21 includes a non-inverting input terminal 211, an inverting input terminal 212, and a level signal output terminal 213.
  • the output buffer 22 is configured to perform amplification processing on a high level signal or a low level signal, and the output buffer 22 includes A plurality of inverting amplifiers 221.
  • the voltage signal of the input of the non-inverting input terminal 211 and the inverting input terminal 212 of the level shifter 21 is determined based on the number of inverting amplifiers 221 in the output buffer 22.
  • the output buffer 22 includes an even number of inverting amplifiers 221, such as two inverting amplifiers 221 or four inverting amplifiers 221, etc.; that is, an even number of inverting amplifiers 221 are used to achieve scanning on the scanning line.
  • the driving power of the signal The non-inverting input terminal 211 of the level shifter 21 inputs a positive phase voltage signal, and the inverting input terminal 212 of the level shifter 21 inputs an inverted voltage signal, wherein the inverted voltage signal is generated by the positive phase voltage signal through the NOT gate 23.
  • the level shifter 21 includes a first switching transistor Q21, a second switching transistor Q22, a third switching transistor Q23, a fourth switching transistor Q24, a fifth switching transistor Q25, a sixth switching transistor Q26, and a seventh.
  • the first switch tube Q21, the second switch tube Q22, the fifth switch tube Q25 and the sixth switch tube Q26 are n-channel MOSFETs
  • the switching transistor Q27 and the eighth switching transistor Q28 are p-channel MOSFETs.
  • the control end of the first switch transistor Q21 is connected to the non-inverting input terminal 211, the input end of the first switch transistor Q21 is connected to the low-level signal Vss_L, and the output end of the first switch transistor Q21 is respectively connected to the control terminal of the eighth switch transistor Q28.
  • the output end of the third switch tube Q23 and the control end of the fourth switch tube Q24 are connected;
  • the control end of the second switch tube Q22 is connected to the inverting input terminal 212, the input end of the second switch tube Q22 is connected to the low level signal Vss_L, and the output end of the second switch tube Q22 is respectively connected to the control end of the third switch tube Q23.
  • the output end of the fourth switch tube Q24 and the control end of the seventh switch tube Q27 are connected;
  • the input end of the third switch tube Q23 is connected to the high level signal VDD_H, and the input end of the fourth switch tube Q24 is connected to the high level signal VDD_H;
  • the input end of the fifth switch tube Q25 is connected to the low level signal Vss_L, the control end of the fifth switch tube Q25 is connected to the level signal output end 213, and the output end of the fifth switch tube Q25 is respectively outputted to the output of the seventh switch tube Q27.
  • the terminal and the control end of the sixth switch tube Q26 are connected;
  • the input end of the sixth switch tube Q26 is connected to the low level signal Vss_L, and the output end of the sixth switch tube Q26 is connected to the level signal output end 213;
  • the input end of the seventh switch tube Q27 is connected to the high level signal VDD_H
  • the input end of the eighth switch tube Q28 is connected to the high level signal VDD_H
  • the output end of the eighth switch tube Q28 is connected to the level signal output end 213.
  • the non-inverting input terminal 211 of the level shifter 21 inputs a positive phase voltage signal
  • the inverting input terminal 212 of the level shifter 21 inputs an inverted voltage signal.
  • the positive phase voltage signal is a high voltage signal
  • the inverted voltage signal is Low voltage signal
  • the inverted voltage signal is a high voltage signal, at which time the second switching transistor Q22 is turned on, the first switching transistor Q21 is turned off, and then the third switching transistor Q23 and the seventh switching transistor Q27 Turning on, the fourth switch tube Q24 and the eighth switch tube Q28 are turned off, then the sixth switch tube Q26 is turned on, the fifth switch tube Q25 is turned off, and the low level signal Vss_L is output from the frequency signal through the sixth switch tube Q26. End 213 is output.
  • the high-low level signal output from the level signal output terminal 213 coincides with the phase of the positive phase voltage signal.
  • the high-low level signal outputted by the level shifter 21 is amplified by an even number of inverting amplifiers 221 in the output buffer 22 and output to the corresponding scan line, and output to the scan line due to an even number of inversion operations.
  • the phase of the scan signal also coincides with the phase of the positive phase voltage signal.
  • FIG. 3A is a schematic structural view of a driving circuit of a second preferred embodiment of the liquid crystal display device of the present invention
  • FIG. 3B is a diagram showing the electric circuit of the driving circuit of the second preferred embodiment of the liquid crystal display device of the present invention
  • FIG. 3C is a schematic diagram of input and output signals of a level shifter of a driving circuit of a second preferred embodiment of the liquid crystal display device of the present invention.
  • the driving circuit of the liquid crystal display panel includes a level shifter 31 and an output buffer 32 for converting the input voltage signal into a high level signal or a low level signal.
  • the flat converter 31 includes a non-inverting input terminal 311, an inverting input terminal 312, and a level signal output terminal 313.
  • the output buffer 32 is configured to perform amplification processing on a high level signal or a low level signal, and the output buffer 32 includes A plurality of inverting amplifiers 321 .
  • the voltage signal of the input of the non-inverting input terminal 311 and the inverting input terminal 312 of the level shifter 31 is determined based on the number of inverting amplifiers 321 in the output buffer 32.
  • the output buffer 32 includes an odd number of inverting amplifiers 321, such as three inverting amplifiers 321 or five inverting amplifiers 321 and the like. That is, an odd number of inverting amplifiers 321 can be used to achieve the driving power of the scanning signal on the scanning line.
  • the non-inverting input signal 311 of the level shifter 31 inputs an inverted voltage signal
  • the inverting input terminal 312 of the level shifter 31 inputs a positive phase voltage signal, wherein the inverted voltage signal is generated by the positive phase voltage signal through the NOT gate 33.
  • the level shifter 31 includes a first switching transistor Q31, a second switching transistor Q32, a third switching transistor Q33, a fourth switching transistor Q34, a fifth switching transistor Q35, a sixth switching transistor Q36, and a seventh.
  • Switch tube Q37 and eighth switch tube Q38 The first switch tube Q31, the second switch tube Q32, the fifth switch tube Q35 and the sixth switch tube Q36 are n-channel metal oxide semiconductor field effect transistors, third switch tube Q33, fourth switch tube Q34, and seventh
  • the switching transistor Q37 and the eighth switching transistor Q38 are p-channel MOSFETs.
  • the control end of the first switch tube Q31 is connected to the non-inverting input terminal 311, the input end of the first switch tube Q31 is connected to the low-level signal Vss_L, and the output end of the first switch tube Q31 and the control end of the eighth switch tube Q38 are respectively The output end of the third switch tube Q33 and the control end of the fourth switch tube Q34 are connected;
  • the control end of the second switch tube Q32 is connected to the inverting input terminal 312, the input end of the second switch tube Q32 is connected to the low level signal Vss_L, and the output end of the second switch tube Q32 is respectively connected to the control end of the third switch tube Q33.
  • the output end of the fourth switch tube Q34 and the control end of the seventh switch tube Q37 are connected;
  • the input end of the third switch tube Q33 is connected to the high level signal VDD_H, and the input end of the fourth switch tube Q34 is connected to the high level signal VDD_H;
  • the input end of the fifth switch tube Q35 is connected to the low level signal Vss_L, the control end of the fifth switch tube Q35 is connected to the level signal output end 313, and the output end of the fifth switch tube Q35 is respectively outputted to the output of the seventh switch tube Q37.
  • the terminal and the control end of the sixth switch tube Q36 are connected;
  • the input end of the sixth switch tube Q36 is connected to the low level signal Vss_L, and the output end of the sixth switch tube Q36 is connected to the level signal output end 313;
  • the input end of the seventh switch Q37 is connected to the high level signal VDD_H
  • the input end of the eighth switch Q38 is connected to the high level signal VDD_H
  • the output end of the eighth switch Q38 is connected to the level signal output end 313.
  • the non-inverting input signal 311 of the level shifter 31 inputs an inverted voltage signal
  • the inverting input terminal 312 of the level shifter 31 inputs a positive phase voltage signal.
  • the positive phase voltage signal is a low voltage signal
  • the inverted voltage signal is High voltage signal
  • the fifth switching transistor Q35 is turned on
  • the sixth switching transistor Q36 is turned off
  • the high level signal VDD_H is output from the level signal output terminal 313 through the eighth switching transistor Q38.
  • the positive phase voltage signal is a high voltage signal
  • the inverted voltage signal is a low voltage signal, at which time the second switching transistor Q32 is turned on, the first switching transistor Q31 is turned off, and then the third switching transistor Q33 and the seventh switching transistor Q37 Turning on, the fourth switch tube Q34 and the eighth switch tube Q38 are turned off, then the sixth switch tube Q36 is turned on, the fifth switch tube Q35 is turned off, and the low level signal Vss_L is output from the frequency signal through the sixth switch tube Q36. End 313 is output.
  • the high-low level signal output from the level signal output terminal 313 is opposite to the phase of the positive phase voltage signal.
  • the high-low level signal outputted by the level shifter 31 is amplified by the odd-numbered inverting amplifiers 321 in the output buffer 32, and then output to the corresponding scan line, and outputted to the scan line due to the odd-numbered inversion operation.
  • the phase of the scan signal coincides with the phase of the positive phase voltage signal.
  • the liquid crystal display panel of the present invention determines the voltage signal of the input of the non-inverting input terminal and the inverting input terminal of the level shifter according to the number of inverting amplifiers in the output buffer, and can perform signal amplification processing using an appropriate number of inverting amplifiers. It is not necessary to fix an even number of inverting amplifiers to ensure the phase accuracy of the scanning signal, so that the manufacturing cost of the liquid crystal display panel can be effectively reduced.
  • the present invention also provides a liquid crystal display device including a backlight and a liquid crystal display panel
  • the driving circuit of the liquid crystal display panel includes a level shifter and an output buffer for converting the input voltage signal A high level signal or a low level signal
  • the level shifter includes a non-inverting input, an inverting input, and a level signal output
  • the output buffer is used to amplify a high level signal or a low level signal
  • the output buffer includes a plurality of inverting amplifiers. Wherein the voltage signal of the input of the non-inverting input and the inverting input of the level shifter is determined according to the number of inverting amplifiers in the output buffer.
  • the output buffer comprises an even number of inverting amplifiers, the non-inverting input of the level shifter inputs a positive phase voltage signal, and the inverting input of the level shifter inputs an inverted voltage signal; eg, the output buffer includes An odd number of inverting amplifiers, the positive phase input of the level shifter inputs an inverted voltage signal, the inverting input of the level shifter inputs a positive phase voltage signal; and the inverted voltage signal is generated by a positive phase voltage signal through a non-gate .
  • the level shifter includes a first switch tube, a second switch tube, a third switch tube, a fourth switch tube, a fifth switch tube, a sixth switch tube, a seventh switch tube, and an eighth switch tube;
  • the control end of the first switch tube is connected to the non-inverting input end, the input end of the first switch tube is connected to the low-level signal, and the output end of the first switch tube is respectively connected with the control end of the eighth switch tube and the third switch tube The output end and the control end of the fourth switch tube are connected;
  • the control end of the second switch tube is connected to the inverting input end, the input end of the second switch tube is connected to the low level signal, the output end of the second switch tube is respectively connected to the control end of the third switch tube, and the fourth switch tube is The output end and the control end of the seventh switch tube are connected;
  • the input end of the third switch tube is connected to the high level signal, and the input end of the fourth switch tube is connected to the high level signal;
  • the input end of the fifth switch tube is connected to the low level signal, the control end of the fifth switch tube is connected to the level signal output end, the output end of the fifth switch tube is respectively connected with the output end of the seventh switch tube and the sixth switch tube Control terminal connection;
  • the input end of the sixth switch tube is connected to the low level signal, and the output end of the sixth switch tube is connected to the level signal output end;
  • the input end of the seventh switch tube is connected to the high level signal
  • the input end of the eighth switch tube is connected to the high level signal
  • the output end of the eighth switch tube is connected to the level signal output end
  • the first switch tube, the second switch tube, the fifth switch tube and the sixth switch tube are n-channel metal oxide semiconductor field effect transistors; third switch tube, fourth switch tube, seventh switch tube and eighth switch
  • the tube is a p-channel metal oxide semiconductor field effect transistor.
  • the specific working principle of the liquid crystal display device of the present invention is the same as or similar to the description of the preferred embodiment of the liquid crystal display panel. For details, refer to the related description in the specific embodiment of the liquid crystal display panel.
  • the liquid crystal display panel and the liquid crystal display device of the present invention determine the voltage signals of the input of the positive phase input terminal and the inverting input terminal of the level converter according to the number of inverting amplifiers in the output buffer, thereby effectively reducing the liquid crystal display panel.
  • the manufacturing cost is solved; the technical problems of high production cost of the conventional liquid crystal display panel and the liquid crystal display device are solved.

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Abstract

一种液晶显示面板（10）及其液晶显示装置，液晶显示面板包括驱动电路（11）、数据线（12）、扫描线（13）以及像素单元（14）；其中驱动电路（11）包括电平转换器（21）以及输出缓冲器（22）；其中根据输出缓冲器（22）中的反相放大器（221）的数量，确定电平转换器（21）的正相输入端（211）和反相输入端（212）输入的电压信号，可有效降低液晶显示面板（10）的制作成本。

Description

液晶显示面板及液晶显示装置 技术领域
本发明涉及液晶显示领域，特别是涉及一种液晶显示面板及液晶显示装置。
 背景技术
随着技术的发展，用户对高清晰大屏幕的显示装置的需求大幅增加，液晶显示装置的市场需求量也越来越大。同时液晶显示面板的技术也越来越成熟，在保证液晶显示面板品质的基础上，降低液晶显示面板的制作成本成为各大显示面板厂商争相研究的方向。
传统液晶显示面板的扫描线的驱动芯片是通过电平转换器以及输出缓冲器来输出扫描信号的，其中电平转换器将输入的电压信号转换为高低电平信号，输出缓冲器中包括多级反相放大器，每一级的反相放大器都将高低电平信号进行反相放大，以使得驱动芯片最终输出具有足够驱动能力的扫描信号。
但是反相放大器在放大高低电平信号的同时，会对高低电平信号进行反相操作，为了保证扫描信号的输出准确性，输出缓冲器中必须设置偶数个的反相放大器，以对高低电平信号进行偶数次的反相放大。由于必须设置偶数个反相放大器，因此可能提高液晶显示面板的制作成本。
故，有必要提供一种液晶显示面板及液晶显示装置，以解决现有技术所存在的问题。
 技术问题
本发明的目的在于提供一种根据输出缓冲器中的反相放大器的数量，确定电平转换器的正相输入端和反相输入端的输入的电压信号的液晶显示面板及液晶显示装置，可有效的降低液晶显示面板的制作成本；以解决现有的液晶显示面板及液晶显示装置的制作成本较高的技术问题。
 技术解决方案
为解决上述问题，本发明提供的技术方案如下：
本发明提供一种液晶显示面板，其包括：
驱动电路，用于提供数据信号以及扫描信号；
数据线，用于传输所述数据信号；
扫描线，用于传输所述扫描信号；以及
像素单元，用于在所述扫描信号的控制下使用所述数据信号进行图像显示；
其中所述驱动电路包括：
电平转换器，用于将输入的电压信号转换为高电平信号或低电平信号；所述电平转换器包括正相输入端、反相输入端以及电平信号输出端；以及
输出缓冲器，用于对所述高电平信号或所述低电平信号进行放大处理；所述输出缓冲器包括多个反相放大器；
其中根据所述输出缓冲器中的所述反相放大器的数量，确定所述电平转换器的所述正相输入端和所述反相输入端的输入的电压信号。
在本发明所述的液晶显示面板中，如所述输出缓冲器包括偶数个所述反相放大器，则所述电平转换器的所述正相输入端输入正相电压信号，所述电平转换器的所述反相输入端输入反相电压信号。
在本发明所述的液晶显示面板中，如所述输出缓冲器包括奇数个所述反相放大器，则所述电平转换器的所述正相输入端输入所述反相电压信号，所述电平转换器的所述反相输入端输入所述正相电压信号。
在本发明所述的液晶显示面板中，所述反相电压信号由所述正相电压信号通过非门生成。
在本发明所述的液晶显示面板中，所述电平转换器包括第一开关管、第二开关管、第三开关管、第四开关管、第五开关管、第六开关管、第七开关管以及第八开关管；
所述第一开关管的控制端与所述正相输入端连接，所述第一开关管的输入端与所述低电平信号连接，所述第一开关管的输出端分别与所述第八开关管的控制端、所述第三开关管的输出端以及所述第四开关管的控制端连接；
所述第二开关管的控制端与所述反相输入端连接，所述第二开关管的输入端与所述低电平信号连接，所述第二开关管的输出端分别与所述第三开关管的控制端，所述第四开关管的输出端以及所述第七开关管的控制端连接；
所述第三开关管的输入端与所述高电平信号连接，所述第四开关管的输入端与所述高电平信号连接；
所述第五开关管的输入端与所述低电平信号连接，所述第五开关管的控制端与所述电平信号输出端连接，所述第五开关管的输出端分别与所述第七开关管的输出端以及所述第六开关管的控制端连接；
所述第六开关管的输入端与所述低电平信号连接，所述第六开关管的输出端与所述电平信号输出端连接；
所述第七开关管的输入端与所述高电平信号连接，所述第八开关管的输入端与所述高电平信号连接，所述第八开关管的输出端与所述电平信号输出端连接。
在本发明所述的液晶显示面板中，所述第一开关管、所述第二开关管、所述第五开关管以及所述第六开关管为n沟道金属氧化物半导体场效应管。
在本发明所述的液晶显示面板中，所述第三开关管、所述第四开关管、所述第七开关管以及所述第八开关管为p沟道金属氧化物半导体场效应管。
本发明还提供一种液晶显示装置，其包括背光源及液晶显示面板，所述液晶显示面板包括：
驱动电路，用于提供数据信号以及扫描信号；
数据线，用于传输所述数据信号；
扫描线，用于传输所述扫描信号；以及
像素单元，用于在所述扫描信号的控制下使用所述数据信号进行图像显示；
其中所述驱动电路包括：
电平转换器，用于将输入的电压信号转换为高电平信号或低电平信号；所述电平转换器包括正相输入端、反相输入端以及电平信号输出端；以及
输出缓冲器，用于对所述高电平信号或所述低电平信号进行放大处理；所述输出缓冲器包括多个反相放大器；
其中根据所述输出缓冲器中的所述反相放大器的数量，确定所述电平转换器的所述正相输入端和所述反相输入端的输入的电压信号。
在本发明所述的液晶显示装置中，如所述输出缓冲器包括偶数个所述反相放大器，则所述电平转换器的所述正相输入端输入正相电压信号，所述电平转换器的所述反相输入端输入反相电压信号。
在本发明所述的液晶显示装置中，如所述输出缓冲器包括奇数个所述反相放大器，则所述电平转换器的所述正相输入端输入所述反相电压信号，所述电平转换器的所述反相输入端输入所述正相电压信号。
在本发明所述的液晶显示装置中，所述反相电压信号由所述正相电压信号通过非门生成。
在本发明所述的液晶显示装置中，所述电平转换器包括第一开关管、第二开关管、第三开关管、第四开关管、第五开关管、第六开关管、第七开关管以及第八开关管；
所述第一开关管的控制端与所述正相输入端连接，所述第一开关管的输入端与所述低电平信号连接，所述第一开关管的输出端分别与所述第八开关管的控制端、所述第三开关管的输出端以及所述第四开关管的控制端连接；
所述第二开关管的控制端与所述反相输入端连接，所述第二开关管的输入端与所述低电平信号连接，所述第二开关管的输出端分别与所述第三开关管的控制端，所述第四开关管的输出端以及所述第七开关管的控制端连接；
所述第三开关管的输入端与所述高电平信号连接，所述第四开关管的输入端与所述高电平信号连接；
所述第五开关管的输入端与所述低电平信号连接，所述第五开关管的控制端与所述电平信号输出端连接，所述第五开关管的输出端分别与所述第七开关管的输出端以及所述第六开关管的控制端连接；
所述第六开关管的输入端与所述低电平信号连接，所述第六开关管的输出端与所述电平信号输出端连接；
所述第七开关管的输入端与所述高电平信号连接，所述第八开关管的输入端与所述高电平信号连接，所述第八开关管的输出端与所述电平信号输出端连接。
在本发明所述的液晶显示装置中，所述第一开关管、所述第二开关管、所述第五开关管以及所述第六开关管为n沟道金属氧化物半导体场效应管。
在本发明所述的液晶显示装置中，所述第三开关管、所述第四开关管、所述第七开关管以及所述第八开关管为p沟道金属氧化物半导体场效应管。
 有益效果
相较于现有的液晶显示面板及液晶显示装置，本发明的液晶显示面板及液晶显示装置根据输出缓冲器中的反相放大器的数量，确定电平转换器的正相输入端和反相输入端的输入的电压信号，可有效的降低液晶显示面板的制作成本；解决了现有的液晶显示面板及液晶显示装置的制作成本较高的技术问题。
 附图说明
图1为本发明的液晶显示装置的优选实施例的结构示意图；
图2A为本发明的液晶显示装置的第一优选实施例的驱动电路的结构示意图；
图2B为本发明的液晶显示装置的第一优选实施例的驱动电路的电平转换器的结构示意图；
图2C为本发明的液晶显示装置的第一优选实施例的驱动电路的电平转换器的输入输出信号示意图；
图3A为本发明的液晶显示装置的第二优选实施例的驱动电路的结构示意图；
图3B为本发明的液晶显示装置的第二优选实施例的驱动电路的电平转换器的结构示意图；
图3C为本发明的液晶显示装置的第二优选实施例的驱动电路的电平转换器的输入输出信号示意图。
 本发明的最佳实施方式
以下各实施例的说明是参考附加的图式，用以例示本发明可用以实施的特定实施例。本发明所提到的方向用语，例如「上」、「下」、「前」、「后」、「左」、「右」、「内」、「外」、「侧面」等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本发明，而非用以限制本发明。
在图中，结构相似的单元是以相同标号表示。
请参照图1，图1为本发明的液晶显示面板的优选实施例的结构示意图。本优选实施例的液晶显示面板10包括驱动电路11、数据线12、扫描线13以及像素单元14。驱动电路11用于提供数据信号以及扫描信号，数据线12用于传输数据信号，扫描线13用于传输扫描信号，像素单元14用于在扫描信号的控制下使用数据信号进行图像显示。
请参照图2A至图2C，图2A为本发明的液晶显示装置的第一优选实施例的驱动电路的结构示意图；图2B为本发明的液晶显示装置的第一优选实施例的驱动电路的电平转换器的结构示意图；图2C为本发明的液晶显示装置的第一优选实施例的驱动电路的电平转换器的输入输出信号示意图。
在本优选实施例中，液晶显示面板的驱动电路包括电平转换器21以及输出缓冲器22，电平转换器21用于将输入的电压信号转换为高电平信号或低电平信号，电平转换器21包括正相输入端211、反相输入端212以及电平信号输出端213；输出缓冲器22用于对高电平信号或低电平信号进行放大处理，该输出缓冲器22包括多个反相放大器221。其中根据输出缓冲器22中的反相放大器221的数量，确定电平转换器21的正相输入端211和反相输入端212的输入的电压信号。
在本优选实施例中，输出缓冲器22包括偶数个反相放大器221，如两个反相放大器221或四个反相放大器221等；即使用偶数个反相放大器221才能达到扫描线上的扫描信号的驱动功率。电平转换器21的正相输入端211输入正相电压信号，电平转换器21的反相输入端212输入反相电压信号，其中反相电压信号由正相电压信号通过非门23生成。
如图2B所示，电平转换器21包括第一开关管Q21、第二开关管Q22、第三开关管Q23、第四开关管Q24、第五开关管Q25、第六开关管Q26、第七开关管Q27以及第八开关管Q28。其中第一开关管Q21、第二开关管Q22、第五开关管Q25以及第六开关管Q26为n沟道金属氧化物半导体场效应管，第三开关管Q23、第四开关管Q24、第七开关管Q27以及第八开关管Q28为p沟道金属氧化物半导体场效应管。
第一开关管Q21的控制端与正相输入端211连接，第一开关管Q21的输入端与低电平信号Vss_L连接，第一开关管Q21的输出端分别与第八开关管Q28的控制端、第三开关管Q23的输出端以及第四开关管Q24的控制端连接；
第二开关管Q22的控制端与反相输入端212连接，第二开关管Q22的输入端与低电平信号Vss_L连接，第二开关管Q22的输出端分别与第三开关管Q23的控制端，第四开关管Q24的输出端以及第七开关管Q27的控制端连接；
第三开关管Q23的输入端与高电平信号VDD_H连接，第四开关管Q24的输入端与高电平信号VDD_H连接；
第五开关管Q25的输入端与低电平信号Vss_L连接，第五开关管Q25的控制端与电平信号输出端213连接，第五开关管Q25的输出端分别与第七开关管Q27的输出端以及第六开关管Q26的控制端连接；
第六开关管Q26的输入端与低电平信号Vss_L连接，第六开关管Q26的输出端与电平信号输出端213连接；
第七开关管Q27的输入端与高电平信号VDD_H连接，第八开关管Q28的输入端与高电平信号VDD_H连接，第八开关管Q28的输出端与电平信号输出端213连接。
电平转换器21的正相输入端211输入正相电压信号，电平转换器21的反相输入端212输入反相电压信号，如正相电压信号为高电压信号，反相电压信号则为低电压信号，这时第一开关管Q21导通，第二开关管Q22断开，随后第四开关管Q24以及第八开关管Q28导通，第三开关管Q23以及第七开关管Q27断开，然后第五开关管Q25导通，第六开关管Q26断开，高电平信号VDD_H通过第八开关管Q28从电平信号输出端213输出。
如正相电压信号为低电压信号，反相电压信号则为高电压信号，这时第二开关管Q22导通，第一开关管Q21断开，随后第三开关管Q23以及第七开关管Q27导通，第四开关管Q24以及第八开关管Q28断开，然后第六开关管Q26导通，第五开关管Q25断开，低电平信号Vss_L通过第六开关管Q26从电频信号输出端213输出。
因此如图2C所示，电平信号输出端213输出的高低电平信号与正相电压信号的相位一致。电平转换器21输出的高低电平信号通过输出缓冲器22中的偶数个反相放大器221的放大处理后输出到相应的扫描线上，由于进行偶数次的反相操作，输出到扫描线上的扫描信号的相位也与正相电压信号的相位一致。
请参照图3A至图3C，图3A为本发明的液晶显示装置的第二优选实施例的驱动电路的结构示意图；图3B为本发明的液晶显示装置的第二优选实施例的驱动电路的电平转换器的结构示意图；图3C为本发明的液晶显示装置的第二优选实施例的驱动电路的电平转换器的输入输出信号示意图。
在本优选实施例中，液晶显示面板的驱动电路包括电平转换器31以及输出缓冲器32，电平转换器31用于将输入的电压信号转换为高电平信号或低电平信号，电平转换器31包括正相输入端311、反相输入端312以及电平信号输出端313；输出缓冲器32用于对高电平信号或低电平信号进行放大处理，该输出缓冲器32包括多个反相放大器321。其中根据输出缓冲器32中的反相放大器321的数量，确定电平转换器31的正相输入端311和反相输入端312的输入的电压信号。
在本优选实施例中，输出缓冲器32包括奇数个反相放大器321，如三个反相放大器321或五个反相放大器321等。即使用奇数个反相放大器321才能达到扫描线上的扫描信号的驱动功率。电平转换器31的正相输入端311输入反相电压信号，电平转换器31的反相输入端312输入正相电压信号，其中反相电压信号由正相电压信号通过非门33生成。
如图3B所示，电平转换器31包括第一开关管Q31、第二开关管Q32、第三开关管Q33、第四开关管Q34、第五开关管Q35、第六开关管Q36、第七开关管Q37以及第八开关管Q38。其中第一开关管Q31、第二开关管Q32、第五开关管Q35以及第六开关管Q36为n沟道金属氧化物半导体场效应管，第三开关管Q33、第四开关管Q34、第七开关管Q37以及第八开关管Q38为p沟道金属氧化物半导体场效应管。
第一开关管Q31的控制端与正相输入端311连接，第一开关管Q31的输入端与低电平信号Vss_L连接，第一开关管Q31的输出端分别与第八开关管Q38的控制端、第三开关管Q33的输出端以及第四开关管Q34的控制端连接；
第二开关管Q32的控制端与反相输入端312连接，第二开关管Q32的输入端与低电平信号Vss_L连接，第二开关管Q32的输出端分别与第三开关管Q33的控制端，第四开关管Q34的输出端以及第七开关管Q37的控制端连接；
第三开关管Q33的输入端与高电平信号VDD_H连接，第四开关管Q34的输入端与高电平信号VDD_H连接；
第五开关管Q35的输入端与低电平信号Vss_L连接，第五开关管Q35的控制端与电平信号输出端313连接，第五开关管Q35的输出端分别与第七开关管Q37的输出端以及第六开关管Q36的控制端连接；
第六开关管Q36的输入端与低电平信号Vss_L连接，第六开关管Q36的输出端与电平信号输出端313连接；
第七开关管Q37的输入端与高电平信号VDD_H连接，第八开关管Q38的输入端与高电平信号VDD_H连接，第八开关管Q38的输出端与电平信号输出端313连接。
电平转换器31的正相输入端311输入反相电压信号，电平转换器31的反相输入端312输入正相电压信号，如正相电压信号为低电压信号，反相电压信号则为高电压信号，这时第一开关管Q31导通，第二开关管Q32断开，随后第四开关管Q34以及第八开关管Q38导通，第三开关管Q33以及第七开关管Q37断开，然后第五开关管Q35导通，第六开关管Q36断开，高电平信号VDD_H通过第八开关管Q38从电平信号输出端313输出。
如正相电压信号为高电压信号，反相电压信号则为低电压信号，这时第二开关管Q32导通，第一开关管Q31断开，随后第三开关管Q33以及第七开关管Q37导通，第四开关管Q34以及第八开关管Q38断开，然后第六开关管Q36导通，第五开关管Q35断开，低电平信号Vss_L通过第六开关管Q36从电频信号输出端313输出。
因此如图3C所示，电平信号输出端313输出的高低电平信号与正相电压信号的相位相反。电平转换器31输出的高低电平信号通过输出缓冲器32中的奇数个反相放大器321的放大处理后输出到相应的扫描线上，由于进行奇数次的反相操作，输出到扫描线上的扫描信号的相位与正相电压信号的相位一致。
本发明的液晶显示面板根据输出缓冲器中的反相放大器的数量，确定电平转换器的正相输入端和反相输入端的输入的电压信号，可以使用合适数量的反相放大器进行信号放大处理，不必固定设置偶数个反相放大器来保证扫描信号的相位准确性，因此可有效的降低液晶显示面板的制作成本。
本发明还提供一种液晶显示装置，该液晶显示装置包括背光源以及液晶显示面板，该液晶显示面板的驱动电路包括电平转换器以及输出缓冲器，电平转换器用于将输入的电压信号转换为高电平信号或低电平信号，电平转换器包括正相输入端、反相输入端以及电平信号输出端；输出缓冲器用于对高电平信号或低电平信号进行放大处理，该输出缓冲器包括多个反相放大器。其中根据输出缓冲器中的反相放大器的数量，确定电平转换器的正相输入端和反相输入端的输入的电压信号。
优选的，如输出缓冲器包括偶数个反相放大器，则电平转换器的正相输入端输入正相电压信号，电平转换器的反相输入端输入反相电压信号；如输出缓冲器包括奇数个反相放大器，则电平转换器的正相输入端输入反相电压信号，电平转换器的反相输入端输入正相电压信号；反相电压信号由正相电压信号通过非门生成。
优选的，电平转换器包括第一开关管、第二开关管、第三开关管、第四开关管、第五开关管、第六开关管、第七开关管以及第八开关管；
第一开关管的控制端与正相输入端连接，第一开关管的输入端与低电平信号连接，第一开关管的输出端分别与第八开关管的控制端、第三开关管的输出端以及第四开关管的控制端连接；
第二开关管的控制端与反相输入端连接，第二开关管的输入端与低电平信号连接，第二开关管的输出端分别与第三开关管的控制端，第四开关管的输出端以及第七开关管的控制端连接；
第三开关管的输入端与高电平信号连接，第四开关管的输入端与高电平信号连接；
第五开关管的输入端与低电平信号连接，第五开关管的控制端与电平信号输出端连接，第五开关管的输出端分别与第七开关管的输出端以及第六开关管的控制端连接；
第六开关管的输入端与低电平信号连接，第六开关管的输出端与电平信号输出端连接；
第七开关管的输入端与高电平信号连接，第八开关管的输入端与高电平信号连接，第八开关管的输出端与电平信号输出端连接；
其中第一开关管、第二开关管、第五开关管以及第六开关管为n沟道金属氧化物半导体场效应管；第三开关管、第四开关管、第七开关管以及第八开关管为p沟道金属氧化物半导体场效应管。
本发明的液晶显示装置的具体工作原理与上述的液晶显示面板的优选实施例的描述相同或相似，具体请参见上述液晶显示面板的具体实施例中的相关描述。
本发明的液晶显示面板及液晶显示装置根据输出缓冲器中的反相放大器的数量，确定电平转换器的正相输入端和反相输入端的输入的电压信号，可有效的降低液晶显示面板的制作成本；解决了现有的液晶显示面板及液晶显示装置的制作成本较高的技术问题。
综上所述，虽然本发明已以优选实施例揭露如上，但上述优选实施例并非用以限制本发明，本领域的普通技术人员，在不脱离本发明的精神和范围内，均可作各种更动与润饰，因此本发明的保护范围以权利要求界定的范围为准。

Claims (16)

  1. 一种液晶显示面板，其包括：
    驱动电路，用于提供数据信号以及扫描信号；
    数据线，用于传输所述数据信号；
    扫描线，用于传输所述扫描信号；以及
    像素单元，用于在所述扫描信号的控制下使用所述数据信号进行图像显示；
    其中所述驱动电路包括：
    电平转换器，用于将输入的电压信号转换为高电平信号或低电平信号；所述电平转换器包括正相输入端、反相输入端以及电平信号输出端；以及
    输出缓冲器，用于对所述高电平信号或所述低电平信号进行放大处理；所述输出缓冲器包括多个反相放大器；
    其中根据所述输出缓冲器中的所述反相放大器的数量，确定所述电平转换器的所述正相输入端和所述反相输入端的输入的电压信号。
  2. 根据权利要求1所述的液晶显示面板，其中如所述输出缓冲器包括偶数个所述反相放大器，则所述电平转换器的所述正相输入端输入正相电压信号，所述电平转换器的所述反相输入端输入反相电压信号。
  3. 根据权利要求2所述的液晶显示面板，其中所述反相电压信号由所述正相电压信号通过非门生成。
  4. 根据权利要求1所述的液晶显示面板，其中如所述输出缓冲器包括奇数个所述反相放大器，则所述电平转换器的所述正相输入端输入所述反相电压信号，所述电平转换器的所述反相输入端输入所述正相电压信号。
  5. 根据权利要求4所述的液晶显示面板，其中所述反相电压信号由所述正相电压信号通过非门生成。
  6. 根据权利要求1所述的液晶显示面板，其中所述电平转换器包括第一开关管、第二开关管、第三开关管、第四开关管、第五开关管、第六开关管、第七开关管以及第八开关管；
    所述第一开关管的控制端与所述正相输入端连接，所述第一开关管的输入端与所述低电平信号连接，所述第一开关管的输出端分别与所述第八开关管的控制端、所述第三开关管的输出端以及所述第四开关管的控制端连接；
    所述第二开关管的控制端与所述反相输入端连接，所述第二开关管的输入端与所述低电平信号连接，所述第二开关管的输出端分别与所述第三开关管的控制端，所述第四开关管的输出端以及所述第七开关管的控制端连接；
    所述第三开关管的输入端与所述高电平信号连接，所述第四开关管的输入端与所述高电平信号连接；
    所述第五开关管的输入端与所述低电平信号连接，所述第五开关管的控制端与所述电平信号输出端连接，所述第五开关管的输出端分别与所述第七开关管的输出端以及所述第六开关管的控制端连接；
    所述第六开关管的输入端与所述低电平信号连接，所述第六开关管的输出端与所述电平信号输出端连接；
    所述第七开关管的输入端与所述高电平信号连接，所述第八开关管的输入端与所述高电平信号连接，所述第八开关管的输出端与所述电平信号输出端连接。
  7. 根据权利要求6所述的液晶显示面板，其中所述第一开关管、所述第二开关管、所述第五开关管以及所述第六开关管为n沟道金属氧化物半导体场效应管。
  8. 根据权利要求6所述的液晶显示面板，其中所述第三开关管、所述第四开关管、所述第七开关管以及所述第八开关管为p沟道金属氧化物半导体场效应管。
  9. 一种液晶显示装置，其包括背光源及液晶显示面板，所述液晶显示面板包括：
    驱动电路，用于提供数据信号以及扫描信号；
    数据线，用于传输所述数据信号；
    扫描线，用于传输所述扫描信号；以及
    像素单元，用于在所述扫描信号的控制下使用所述数据信号进行图像显示；
    其中所述驱动电路包括：
    电平转换器，用于将输入的电压信号转换为高电平信号或低电平信号；所述电平转换器包括正相输入端、反相输入端以及电平信号输出端；以及
    输出缓冲器，用于对所述高电平信号或所述低电平信号进行放大处理；所述输出缓冲器包括多个反相放大器；
    其中根据所述输出缓冲器中的所述反相放大器的数量，确定所述电平转换器的所述正相输入端和所述反相输入端的输入的电压信号。
  10. 根据权利要求9所述的液晶显示装置，其中如所述输出缓冲器包括偶数个所述反相放大器，则所述电平转换器的所述正相输入端输入正相电压信号，所述电平转换器的所述反相输入端输入反相电压信号。
  11. 根据权利要求10所述的液晶显示装置，其中所述反相电压信号由所述正相电压信号通过非门生成。
  12. 根据权利要求9所述的液晶显示装置，其中如所述输出缓冲器包括奇数个所述反相放大器，则所述电平转换器的所述正相输入端输入所述反相电压信号，所述电平转换器的所述反相输入端输入所述正相电压信号。
  13. 根据权利要求12所述的液晶显示装置，其中所述反相电压信号由所述正相电压信号通过非门生成。
  14. 根据权利要求9所述的液晶显示装置，其中所述电平转换器包括第一开关管、第二开关管、第三开关管、第四开关管、第五开关管、第六开关管、第七开关管以及第八开关管；
    所述第一开关管的控制端与所述正相输入端连接，所述第一开关管的输入端与所述低电平信号连接，所述第一开关管的输出端分别与所述第八开关管的控制端、所述第三开关管的输出端以及所述第四开关管的控制端连接；
    所述第二开关管的控制端与所述反相输入端连接，所述第二开关管的输入端与所述低电平信号连接，所述第二开关管的输出端分别与所述第三开关管的控制端，所述第四开关管的输出端以及所述第七开关管的控制端连接；
    所述第三开关管的输入端与所述高电平信号连接，所述第四开关管的输入端与所述高电平信号连接；
    所述第五开关管的输入端与所述低电平信号连接，所述第五开关管的控制端与所述电平信号输出端连接，所述第五开关管的输出端分别与所述第七开关管的输出端以及所述第六开关管的控制端连接；
    所述第六开关管的输入端与所述低电平信号连接，所述第六开关管的输出端与所述电平信号输出端连接；
    所述第七开关管的输入端与所述高电平信号连接，所述第八开关管的输入端与所述高电平信号连接，所述第八开关管的输出端与所述电平信号输出端连接。
  15. 根据权利要求14所述的液晶显示装置，其中所述第一开关管、所述第二开关管、所述第五开关管以及所述第六开关管为n沟道金属氧化物半导体场效应管。
  16. 根据权利要求14所述的液晶显示装置，其中所述第三开关管、所述第四开关管、所述第七开关管以及所述第八开关管为p沟道金属氧化物半导体场效应管。
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CN107481682A (zh) * 2017-07-21 2017-12-15 惠科股份有限公司 显示面板的驱动方法及驱动装置
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