WO2016150073A1 - 薄膜晶体管和阵列基板及其制作方法、显示装置 - Google Patents

薄膜晶体管和阵列基板及其制作方法、显示装置 Download PDF

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WO2016150073A1
WO2016150073A1 PCT/CN2015/086633 CN2015086633W WO2016150073A1 WO 2016150073 A1 WO2016150073 A1 WO 2016150073A1 CN 2015086633 W CN2015086633 W CN 2015086633W WO 2016150073 A1 WO2016150073 A1 WO 2016150073A1
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layer
gate insulating
array substrate
thin film
forming
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PCT/CN2015/086633
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English (en)
French (fr)
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刘晓娣
王刚
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京东方科技集团股份有限公司
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Priority to US14/905,512 priority Critical patent/US9882060B2/en
Priority to EP15832876.5A priority patent/EP3285303A4/en
Publication of WO2016150073A1 publication Critical patent/WO2016150073A1/zh

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    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
    • H—ELECTRICITY
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/34—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies not provided for in groups H01L21/0405, H01L21/0445, H01L21/06, H01L21/16 and H01L21/18 with or without impurities, e.g. doping materials
    • H01L21/38—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions
    • H01L21/385—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
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    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
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    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
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    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1255—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs integrated with passive devices, e.g. auxiliary capacitors
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    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4908—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET for thin film semiconductor, e.g. gate of TFT
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel

Definitions

  • the present invention relates to the field of display technologies, and in particular, to a thin film transistor, an array substrate including the same, a method of fabricating the same, and a display device including the array substrate.
  • the active matrix liquid crystal display comprises an array substrate, a color filter substrate and a liquid crystal molecular layer interposed therebetween, wherein the array substrate is provided with a structure such as a thin film transistor and a pixel electrode, wherein the thin film transistor comprises a gate electrode, an active layer, a gate insulating layer, The source and the drain are electrically connected to the pixel electrode.
  • the material of the active layer may be polysilicon, single crystal silicon, amorphous silicon or metal oxide semiconductor.
  • the thin film transistor is called an oxide thin film transistor, and is oxidized. Thin film transistors are widely used in array substrates because of their high mobility, low leakage current, and low temperature fabrication.
  • the material of the gate insulating layer may be silicon oxide or silicon nitride.
  • the inventors have found that in the display process of the display, the threshold voltage of the oxide thin film transistor on the array substrate is easily drifted, which leads to poor stability and reliability of the array substrate, and the display is likely to be poorly displayed.
  • An object of the present invention is to provide a thin film transistor, an array substrate including the same, a method for fabricating the same, and a display device including the same, which can improve the threshold voltage drift phenomenon of the thin film transistor and improve the stability and reliability of the array substrate. Sex.
  • an embodiment of the present invention provides a thin film transistor including an active layer and a gate insulating layer.
  • the active layer is made of a metal oxide semiconductor.
  • a gate insulating layer that supplies oxygen to the active layer to reduce an interface state density of a contact interface between the active layer and the gate insulating layer Movable impurity concentration.
  • the gate insulating layer comprises at least one film layer, and a film layer of the gate insulating layer contacting the active layer is made of SiOx, Al 2 O 3 , HfO 2 , ZrO 2 One of TiO 2 , Y 2 O 3 , La 2 O 3 , and Ta 2 O 5 , wherein 1.5 ⁇ x ⁇ 2.8; the active layer is made of IGZO, ZnON, ITZO, ZTO, ZIO, IGO And one of AZTO, and, in the process of depositing and forming the active layer, the oxygen content in the deposition atmosphere is less than 20%.
  • the gate insulating layer comprises at least two film layers, wherein a film layer not in contact with the active layer is made of SiOx, Al 2 O 3 , HfO 2 , ZrO 2 , TiO 2 One of Y 2 O 3 , La 2 O 3 , Ta 2 O 5 , SiNx, SiON, wherein x ⁇ 2.8.
  • the thin film transistor further includes an etch barrier layer on the channel region of the active layer for use as a channel.
  • the etch barrier layer comprises at least one film layer, and each film layer is made of one of SiOx, SiNx, SiON, Al 2 O 3 , TEOS, wherein x ⁇ 1.5.
  • Embodiments of the present invention provide a thin film transistor including an active layer and a gate insulating layer.
  • the active layer is made of a metal oxide semiconductor.
  • the gate insulating layer is directed to the active layer. Oxygen is supplied to reduce the interface state density and the movable impurity concentration of the contact interface between the active layer and the gate insulating layer, thereby improving the threshold voltage drift phenomenon of the thin film transistor, thereby improving the stability of the array substrate including the thin film transistor. And reliability to improve the display effect of the display device including the array substrate.
  • an embodiment of the present invention provides an array substrate including the thin film transistor of any of the above.
  • the array substrate further includes a passivation layer on the thin film transistor and a transparent conductive layer on the passivation layer, the passivation layer including at least one film layer.
  • the transparent conductive layer includes a pixel electrode
  • the array substrate further includes a first via hole penetrating the passivation layer
  • the pixel electrode is electrically connected to a drain of the thin film transistor through the first via hole connection.
  • the passivation layer comprises three film layers
  • the first via hole comprises a first portion and a second portion disposed above and below, the first portion penetrating through the two film layers of the passivation layer, a second portion penetrating a film layer of the passivation layer, the first via
  • the aspect ratio of the first portion is greater than the width to depth ratio of the second portion of the first via.
  • a ratio of a width to depth ratio of the first portion of the first via hole to a width to depth ratio of the second portion of the first via hole is between 1.5 and 5.
  • the transparent conductive layer includes a first wiring in a peripheral region of the array substrate, the array substrate further includes a second wiring located in the peripheral region, and a through-passivation layer and the a second via of the gate insulating layer, the second wiring and the gate of the thin film transistor are disposed in the same layer, and the first wiring is electrically connected to the second wiring through the second via.
  • the passivation layer comprises three film layers
  • the second via hole comprises a first portion and a second portion disposed above and below, the first portion penetrating through the two film layers of the passivation layer, a second portion penetrating through a film layer of the passivation layer and the gate insulating layer, wherein a width to depth ratio of the first portion of the second via hole is larger than a width to depth ratio of the second portion of the second via hole .
  • a ratio of a width to depth ratio of the first portion of the second via hole to a width to depth ratio of the second portion of the second via hole is between 1.5 and 5.
  • an embodiment of the present invention further provides a display device including the array substrate of any of the above.
  • embodiments of the present invention provide a method for fabricating a thin film transistor, including the steps of:
  • the gate insulating layer supplies oxygen to the active layer to reduce an interface state density and a movable impurity concentration of a contact interface between the active layer and the gate insulating layer.
  • the gate insulating layer comprises at least one film layer, and a film layer of the gate insulating layer contacting the active layer is made of SiOx, Al 2 O 3 , HfO 2 , ZrO 2 One of TiO 2 , Y 2 O 3 , La 2 O 3 , and Ta 2 O 5 , wherein 1.5 ⁇ x ⁇ 2.8; the active layer is made of IGZO, ZnON, ITZO, ZTO, ZIO, IGO And one of AZTO, and further, a metal oxide semiconductor layer is formed on the base substrate on which the gate insulating layer is formed by a deposition method, wherein in the process of depositing a metal oxide semiconductor layer The oxygen content in the deposition atmosphere is less than 20%.
  • the gate insulating layer is formed on the base substrate on which the pattern including the gate electrode is formed by a chemical vapor deposition method, wherein deposition is performed during deposition of the gate insulating layer
  • the flow ratio of N 2 O to SiH 4 in the atmosphere is greater than 60.
  • a metal oxide semiconductor layer is formed on the base substrate on which the gate insulating layer is formed by a method of sputter deposition, and in the process of forming the metal oxide semiconductor layer, O 2 is deposited in the atmosphere
  • the flow ratio with Ar is between 1/20 and 1/7.
  • the source/drain metal layer further comprising: forming an etch barrier on the substrate substrate on which the pattern including the active layer is formed The film is then patterned to form an etch stop layer on the channel region of the active layer for use as a channel.
  • Embodiments of the present invention provide a method of fabricating a thin film transistor, the method comprising: forming a gate, a gate insulating layer, an active layer, a source and a drain on a base substrate to form a thin film transistor, wherein The source layer is made of a metal oxide semiconductor, and the gate insulating layer supplies oxygen to the active layer to reduce the interface state density and the movable impurity concentration at the contact interface between the active layer and the gate insulating layer, thereby improving the thin film transistor.
  • the threshold voltage drift phenomenon further improves the stability and reliability of the array substrate including the thin film transistor, and improves the display effect of the display device including the array substrate.
  • the embodiment of the invention further provides a method for fabricating an array substrate, which comprises the method for fabricating a thin film transistor according to any of the above.
  • the method for fabricating the array substrate further comprises: forming a passivation layer on the substrate substrate on which the thin film transistor is formed, the passivation layer comprising at least one film layer; On the base substrate of the passivation layer, a transparent conductive film is formed, and then, a patterning process is performed to form a transparent conductive layer.
  • the transparent conductive layer comprises a pixel electrode, and after the forming the passivation layer, before forming the transparent conductive layer, further comprising: forming a first via hole penetrating the passivation layer, the pixel electrode passing through The first via is electrically connected to the drain of the thin film transistor.
  • the passivation layer comprises three film layers
  • the forming the first via hole through the passivation layer comprises: performing wet etching on the passivation layer during the wet etching process And the two layers of the passivation layer are etched to form a first portion of the first via; and a layer of the passivation layer under the first portion of the first via is performed Dry etching to form a second portion of the first via, wherein a first portion of the first via has a width to depth ratio greater than a second portion of the first via.
  • the transparent conductive layer includes a first wiring located in a peripheral region of the array substrate, and a second wiring formed in a peripheral region of the array substrate while forming the gate;
  • the passivation layer before forming the transparent conductive layer, further comprising: forming a second via hole penetrating the passivation layer and the gate insulating layer, the first wiring passing through the second via hole The second wiring is electrically connected.
  • the passivation layer comprises three film layers, and the forming the second via hole through the passivation layer and the gate insulating layer comprises:
  • the two film layers of the passivation layer are etched to form a first portion of the second via hole;
  • first portion of the second via has a width to depth ratio greater than a width ratio of the second portion of the second via.
  • the method further includes:
  • the array substrate is annealed.
  • the annealing temperature is between 120 ° C and 450 ° C
  • the annealing time is between 0.5 hours and 3 hours
  • the annealing environment is vacuum, nitrogen, air or oxygen.
  • FIG. 1 is a schematic structural view of a thin film transistor according to an embodiment of the present invention.
  • FIG. 2 is a diagram showing relationship between threshold voltage drift amount and time of a thin film transistor in an embodiment of the present invention
  • FIG. 3 is a schematic structural diagram of an array substrate according to an embodiment of the present invention.
  • FIG. 4 is a flow chart showing the fabrication of a thin film transistor in an embodiment of the present invention.
  • Embodiments of the present invention provide a thin film transistor capable of improving a threshold voltage drift phenomenon of a thin film transistor and improving stability and reliability of an array substrate including the thin film transistor.
  • the thin film transistor includes an active layer 4 and a gate insulating layer 3.
  • the active layer 4 is made of a metal oxide semiconductor.
  • the gate insulating layer 3 has The source layer 4 is supplied with oxygen to lower the active layer 4 and the gate insulating layer 3
  • the interface state density and the movable impurity concentration between the contact interfaces can improve the threshold voltage drift phenomenon of the thin film transistor and improve the stability and reliability of the array substrate including the thin film transistor.
  • the gate insulating layer 3 may include at least one film layer, wherein a film layer of the gate insulating layer 3 that is in contact with the active layer 4 is made of SiOx, Al 2 O 3 , HfO 2 , and ZrO 2 .
  • a film layer of the gate insulating layer 3 that is in contact with the active layer 4 is made of SiOx, Al 2 O 3 , HfO 2 , and ZrO 2 .
  • a film layer of the gate insulating layer 3 that is in contact with the active layer 4 is made of SiOx, Al 2 O 3 , HfO 2 , and ZrO 2 .
  • a film layer of the gate insulating layer 3 that is in contact with the active layer 4 is made of SiOx, Al 2 O 3 , HfO 2 , and ZrO 2 .
  • TiO 2 , Y 2 O 3 , La 2 O 3 , and Ta 2 O 5 wherein 1.5 ⁇ x ⁇ 2.8.
  • the material of the active layer 4 is
  • the oxygen content of the film layer in contact with the active layer 4 in the gate insulating layer 3 is high, and the oxygen content of the active layer 4 is low.
  • the active layer 4 is in the gate insulating layer 3.
  • the contacted film layer can supply oxygen to the active layer 4, and the contact interface between the gate insulating layer 3 and the active layer 4 is rich in oxygen, and the interface bonding oxygen and free oxygen content are high, thereby effectively reducing the interface state density and
  • the movable impurity concentration is advantageous for improving the stability and reliability of the device, and the film layer in contact with the active layer 4 in the gate insulating layer 3 is supplied with oxygen to the active layer 4, and can also supplement the oxygen vacancies in the active layer 4. Further, the threshold voltage drift phenomenon of the thin film transistor is further improved, and the stability and reliability of the array substrate including the thin film transistor are further improved.
  • the material of the gate insulating layer is usually SiOx, where x ⁇ 1.5, and the material of the active layer is one of IGZO, ZnON, ITZO, ZTO, ZIO, IGO, AZTO. Therefore, in the prior art, The formed gate insulating layer and the active layer have low oxygen contents, which do not cause the gate insulating layer to supply oxygen to the active layer, so that the contact interface between the gate insulating layer and the active layer is rich in oxygen, thereby The interface state density and the movable impurity concentration of the contact interface between the gate insulating layer and the active layer are high, so that the threshold voltage drift phenomenon of the thin film transistor is severe, and in the prior art, the process of depositing the active layer is formed.
  • the oxygen content in the deposition atmosphere is 20% or more. Therefore, in the case where the formed gate insulating layer and the active layer have low oxygen contents, the oxygen content in the formed active layer may be relatively higher than that of the gate.
  • the oxygen content in the polar insulating layer causes oxygen in the active layer to enter the gate insulating layer to achieve an oxygen balance between the active layer and the gate insulating layer, so that oxygen vacancies are formed in the active layer, so that the film
  • the threshold voltage drift phenomenon of the transistor is more Weight, poor stability and reliability of the array substrate comprises a thin film transistor.
  • the gate insulating layer 3 includes at least two film layers, wherein a film layer not in contact with the active layer 4 is made of SiOx, Al 2 O 3 , HfO 2 , ZrO 2 , TiO 2 , Y 2 .
  • a film layer not in contact with the active layer 4 is made of SiOx, Al 2 O 3 , HfO 2 , ZrO 2 , TiO 2 , Y 2 .
  • a film layer not in contact with the active layer 4 is made of SiOx, Al 2 O 3 , HfO 2 , ZrO 2 , TiO 2 , Y 2 .
  • a film layer not in contact with the active layer 4 is made of SiOx, Al 2 O 3 , HfO 2 , ZrO 2 , TiO 2 , Y 2 .
  • the thin film transistor further includes a gate electrode 2 under the gate insulating layer 3, and a source 5 and a drain electrode 6 connected to the active layer 4, wherein the source 5 and the drain 6 are located Above the active layer 4, therefore, in order to prevent the influence of the performance of the active layer 4 as a channel region of the channel in the process of patterning the source 5 and the drain 6, it is preferred in the embodiment of the present invention.
  • the thin film transistor further includes an etch stop layer 7 on the channel region of the active layer 4 for use as a channel.
  • the etch barrier layer 7 may include at least one film layer, and each of the film layers is made of one of SiOx, SiNx, SiON, Al 2 O 3 , and TEOS, wherein x ⁇ 1.5.
  • the material of the gate 2, the source 5 and the drain 6 may be a metal or an alloy such as Mo, Al/Nd, Al/Nd/Mo, Mo/Al/Nd/Mo, Au/Ti, Pt/Ti.
  • the thin film transistor in the embodiment of the present invention further includes a base substrate 1 for supporting the gate electrode 2, the gate insulating layer 3, the active layer 4, the source 5, the drain electrode 6, and the etch barrier layer 7, wherein
  • the base substrate 1 may be a glass substrate, a plastic substrate (for example, a polyimide substrate), a silicon substrate, or the like.
  • FIG. 2 is a threshold voltage shift amount of a thin film transistor in the embodiment (referred to as an improvement) and a thin film transistor in the prior art (before the improvement) in an 80 degree high temperature positive stress test according to an embodiment of the present invention.
  • a diagram of the relationship between time Specifically, as shown in FIG. 2, for the thin film transistor of the prior art, after the test is performed for 2 hours (h), the threshold voltage is gradually drifted by 3.217 volts (V); for the thin film transistor in the embodiment of the present invention, the test is performed for 2 hours. After that, the threshold voltage only drifts by 0.878V, which is only about one quarter of the threshold voltage drift of the thin film transistor in the prior art. After 10 hours of testing, the threshold voltage drifts by 4.448V, as can be seen from FIG. The reliability and stability of the thin film transistor in the embodiment of the present invention are significantly superior to those of the prior art thin film transistor.
  • the embodiment of the present invention provides a thin film transistor including an active layer 4 and a gate insulating layer 3.
  • the active layer 4 is made of a metal oxide semiconductor.
  • the gate insulating layer 3 Oxygen is supplied to the active layer 4 to reduce the interface state density and the movable impurity concentration of the contact interface between the active layer 4 and the gate insulating layer 3, thereby improving the threshold voltage drift phenomenon of the thin film transistor, thereby improving the inclusion of the thin film.
  • Crystal The stability and reliability of the array substrate of the tube improves the display effect of the display device including the array substrate.
  • An embodiment of the present invention provides an array substrate. As shown in FIG. 3, the array substrate includes any one of the thin film transistors described in Embodiment 1.
  • the array substrate further includes a passivation layer 8 on the thin film transistor and a transparent conductive layer on the passivation layer 8, wherein the passivation layer 8 includes at least one film layer.
  • the material of each of the film layers included in the passivation layer 8 may be one of SiOx, SiNx, SiON, Al 2 O 3 , wherein x ⁇ 1.5.
  • the material of the transparent conductive layer is ITO.
  • the transparent conductive layer includes the pixel electrode 10.
  • the array substrate further includes a first via 9 penetrating through the passivation layer 8, and the pixel electrode 10 passes through the first via 9 and the thin film transistor.
  • the drain 6 is electrically connected.
  • the first via hole 9 includes a first portion 91 and a second portion 92 disposed above and below, wherein the first portion 91 penetrates the passivation layer 8
  • the aspect ratio of the first portion 91 (the ratio of the opening width to the depth of the via is defined as the aspect ratio) is wider than the width of the second portion 92.
  • the aspect ratio is large, so that the sidewall of the first via hole 9 is stepped, and the inclination angle of the sidewall is small, which improves the climbing ability of the pixel electrode 10, thereby effectively reducing the occurrence probability of the disconnection and improving the array substrate. Performance and yield.
  • the ratio of the aspect ratio of the first portion 91 of the first via hole 9 to the width-to-depth ratio of the second portion 92 of the first via hole 9 is between 1.5 and 5.
  • the transparent conductive layer includes a first wiring 11 located in a peripheral region of the array substrate, the array substrate further includes a second wiring 12 located in the peripheral region, and a passivation layer 8 and a gate
  • the second via 13 of the insulating layer 3, the second wiring 12 and the gate 2 of the thin film transistor are disposed in the same layer, and the first wiring 11 is electrically connected to the second wiring 12 through the second via 13.
  • the second via hole 13 includes a first portion 131 and a second portion 132 which are disposed above and below, and the first portion 131
  • the second portion 132 penetrates through a film layer of the passivation layer 8 and the gate insulating layer 3, and the width-depth ratio of the first portion 131 is larger than the width-depth ratio of the second portion 132, thereby
  • the sidewall of the second via hole 13 is stepped, and the inclination angle of the sidewall is small, which improves the climbing ability of the first wiring 11 , thereby effectively reducing the probability of occurrence of disconnection and improving the performance and yield of the array substrate.
  • the ratio of the aspect ratio of the first portion 131 of the second via hole to the width to depth ratio of the second portion 132 of the second via hole is between 1.5 and 5.
  • the array substrate in the embodiment of the present invention may further include a first structure disposed in the same layer as the gate 2 and a second structure disposed in the same layer as the source 5 and the drain 6, exemplarily
  • the first structure and the second structure may respectively be traces located in a peripheral region of the array substrate, or the first structure and the second structure may have intersection regions, and the intersection positions may be used as capacitors.
  • an embodiment of the present invention further provides a display device including the above array substrate.
  • the display device may be any product or component having a display function such as a liquid crystal panel, an electronic paper, an organic light emitting display panel, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like.
  • the embodiment of the present invention provides a method for fabricating the thin film transistor described in the first embodiment. Specifically, as shown in FIG. 4, the method for fabricating the thin film transistor includes the following steps S401 to S404.
  • Step S401 forming a gate metal layer on the base substrate, and then, through a patterning process, forming a pattern including the gate.
  • a gate metal layer is formed using a method such as sputtering, and then, a pattern including the gate electrode 2 is formed through a patterning process.
  • Step S402 forming a gate insulating layer on the base substrate on which the pattern including the gate is formed.
  • a gate insulating layer 3 is formed on the base substrate 1 on which the pattern including the gate electrode 2 is formed.
  • Step S403 forming metal oxide on the base substrate on which the gate insulating layer is formed
  • the semiconductor layer is then patterned to form a pattern including the active layer.
  • a metal oxide semiconductor is formed by sputtering, sol-gel, vacuum evaporation, spray coating, inkjet printing, or the like.
  • the layer is then patterned to include the active layer 4 through a patterning process.
  • Step S404 forming a source/drain metal layer on the base substrate on which the pattern including the active layer is formed, and then, through a patterning process, forming a pattern including a source and a drain to form a thin film transistor.
  • a source/drain metal layer is formed using a method such as sputtering, and then, through a patterning process, formation includes a source 5 and The pattern of the drain 6 is to form a thin film transistor.
  • the gate insulating layer 3 supplies oxygen to the active layer 4 to reduce the interface state density and the movable impurity concentration at the contact interface between the active layer 4 and the gate insulating layer 3, thereby improving the thin film transistor.
  • the threshold voltage drift phenomenon further improves the stability and reliability of the array substrate including the thin film transistor, and improves the display effect of the display device including the array substrate.
  • the gate insulating layer 3 includes at least one film layer, and a film layer of the gate insulating layer 3 in contact with the active layer 4 is made of SiOx, Al 2 O 3 , HfO 2 , ZrO 2 , TiO 2 .
  • a film layer of the gate insulating layer 3 in contact with the active layer 4 is made of SiOx, Al 2 O 3 , HfO 2 , ZrO 2 , TiO 2 .
  • One of Y 2 O 3 , La 2 O 3 , and Ta 2 O 5 wherein 1.5 ⁇ x ⁇ 2.8.
  • the material of the active layer 4 is one of IGZO, ZnON, ITZO, ZTO, ZIO, IGO, AZTO, and a metal oxide semiconductor layer is formed on the base substrate 1 on which the gate insulating layer 3 is formed by a deposition method.
  • the oxygen content in the deposition atmosphere is less than 20%. Therefore, the film layer in contact with the active layer 4 in the gate insulating layer 3 in the embodiment of the present invention has a higher oxygen content, and the oxygen content of the active layer 4 is lower.
  • the gate insulating layer 3 The film layer in contact with the active layer 4 is capable of supplying oxygen to the active layer 4, and the contact interface between the gate insulating layer 3 and the active layer 4 is in an oxygen-rich state, and the interface bonding oxygen and the free oxygen content are high, thereby enabling Effectively reducing the density of the interface state and the concentration of the movable impurities is advantageous for improving the stability and reliability of the device, and the film layer in contact with the active layer 4 in the gate insulating layer 3 is supplied with oxygen to the active layer 4, and can also be supplemented with active.
  • the oxygen vacancies in layer 4 further improve the threshold voltage drift phenomenon of the thin film transistor, and further improve the stability and reliability of the array substrate including the thin film transistor.
  • the gate insulating layer 3 is formed on the base substrate 1 on which the pattern including the gate electrode 2 is formed by a chemical vapor deposition method, wherein the gate insulating layer 3 is formed by deposition.
  • the flow ratio of N 2 O and SiH 4 is more than 60, so that the oxygen content of the gate insulating layer 3 formed is high.
  • a metal oxide semiconductor layer is formed on the base substrate 1 on which the gate insulating layer 3 is formed by a sputtering deposition method, and then a pattern including the active layer 4 is formed through a patterning process, wherein Ground, in the process of depositing the metal oxide semiconductor layer, the flow ratio of O 2 and Ar in the deposition atmosphere is between 1/20 and 1/7, so that the formed active layer 4 has a low oxygen content.
  • the pattern including the active layer 4 before forming the source/drain metal layer, further comprising: forming an etch barrier film on the substrate substrate 1 on which the pattern of the active layer 4 is formed, and then patterning In the process, an etch stop layer 7 is formed on the channel region of the active layer 4 serving as a channel.
  • Embodiments of the present invention provide a method of fabricating a thin film transistor, including forming a gate, a gate insulating layer, an active layer, a source and a drain on a base substrate to form a thin film transistor, wherein
  • the source layer is made of a metal oxide semiconductor
  • the gate insulating layer supplies oxygen to the active layer to reduce the interface state density and the movable impurity concentration at the contact interface between the active layer and the gate insulating layer, thereby improving the thin film transistor.
  • the threshold voltage drift phenomenon further improves the stability and reliability of the array substrate including the thin film transistor, and improves the display effect of the display device including the array substrate.
  • the embodiment of the present invention further provides a method for fabricating the array substrate described in the second embodiment.
  • the method for fabricating the array substrate includes the method for fabricating the thin film transistor described in the third embodiment.
  • the method for fabricating the array substrate further includes the following steps S501 to S502.
  • Step S501 forming a passivation layer on the base substrate on which the thin film transistor is formed, the passivation layer including at least one film layer.
  • the passivation layer 8 is continuously grown by pressure chemical vapor deposition, low pressure chemical vapor deposition, plasma assisted chemical vapor deposition, sputtering, etc., as shown in FIG.
  • the array substrate is also annealed.
  • the annealing environment is oxygen, nitrogen or vacuum.
  • the annealing temperature is 200 degrees or more, and the annealing time is 2-3 hours.
  • the inventors have found that when the thin film transistor is fabricated by the fabrication method described in the third embodiment, after the passivation layer 8 is formed, the array substrate can be annealed for a shorter period of time than the prior art, or can be annealed. It is more advantageous to control the oxygen distribution of the contact interface, thereby achieving the purpose of improving the uniformity, stability, and reliability of the array substrate.
  • the array substrate is not annealed.
  • the manufacturing process of the array substrate can be simplified, and the cost is saved.
  • Step S502 forming a transparent conductive film on the base substrate on which the passivation layer is formed, and then forming a transparent conductive layer through a patterning process.
  • a transparent conductive film is formed using a sputtering method, and then, a patterning process is performed to form a transparent conductive layer.
  • the method further includes: forming the first via 9 through the passivation layer 8. So that the pixel electrode 10 is electrically connected to the drain 6 of the thin film transistor through the first via 9.
  • the first via 9 formed through the passivation layer 8 specifically includes the following steps: first, the passivation layer 8 is wet etched, during the wet etching process, The two film layers of the passivation layer 8 are etched to form the first portion 91 of the first via hole 9; then, a film layer of the passivation layer 8 under the first portion 91 of the first via hole 9 is dried. Etching is performed to form the second portion 92 of the first via 9.
  • the width-to-depth ratio of the first portion 91 of the first via 9 is larger than the width-to-depth ratio of the second portion 92 of the first via 9, so that the sidewall of the first via 9 is stepped, and the sidewall The inclination angle is small, and the climbing ability of the pixel electrode 10 is improved, thereby effectively reducing the probability of occurrence of disconnection and improving the performance and yield of the array substrate.
  • the transparent conductive layer comprises the first region located in the peripheral region of the array substrate
  • the wiring 11 and the second wiring 12 located in the peripheral region of the array substrate are also formed in the embodiment of the present invention.
  • the passivation layer 8 is formed, before the transparent conductive layer is formed, The second via hole 13 penetrating through the passivation layer 8 and the gate insulating layer 3 is formed, and the first wiring 11 is electrically connected to the second wiring 12 through the second via hole 13.
  • forming the second via 13 through the passivation layer 8 and the gate insulating layer 3 specifically includes the following steps: First, the passivation layer 8 is wet etched, wet During the etching process, the two film layers of the passivation layer 8 are etched to form the first portion 131 of the second via hole 13; then, the passivation layer 8 under the first portion 131 of the second via hole 13 is formed. A film layer and a gate insulating layer 3 are dry etched to form a second portion 132 of the second via 13.
  • the width-to-depth ratio of the first portion 131 of the second via hole 13 is larger than the width-to-depth ratio of the second portion 132 of the second via hole 13 such that the sidewall of the second via hole 13 is stepped, and the sidewall The inclination angle is small, and the climbing ability of the first wiring 11 is improved, thereby effectively reducing the occurrence probability of disconnection and improving the performance and yield of the array substrate.
  • the method for fabricating the array substrate in the embodiment of the present invention further includes: annealing the array substrate to reduce the number of defects in the active layer 4.
  • the annealing temperature is between 120 ° C and 450 ° C
  • the annealing time is between 0.5 hours and 3 hours
  • the annealing environment is vacuum, nitrogen, air or oxygen.
  • the first via hole 9 and the second via hole 13 are separately formed.
  • the first via 9 and the second via 9 are used.
  • the holes 13 can be formed simultaneously.
  • the depth of the first via hole 9 is smaller than the depth of the second via hole 13, in order to simultaneously form the first via hole 9 and the second via hole 13, first, the first can be simultaneously formed by wet etching.
  • the first portion of the via hole 9 and the first portion of the second via hole 13 may be appropriately adjusted in the process, for example, and the opening size of the first via hole 9 is smaller than the opening size of the second via hole 13 such that the first via hole
  • the depth of the first portion of 9 is less than the depth of the first portion of the second via 13, and then the second portion of the first via 9 and the second portion of the second via 13 are formed by dry etching, wherein The opening size of the first via hole 9 and the opening size of the second via hole 13 are appropriately adjusted during the wet etching, so that the second portion of the first via hole 9 and the second portion
  • the second portion of the two vias 13 is also formed at the same time.

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Abstract

一种薄膜晶体管和阵列基板及其制作方法、显示装置，涉及显示技术领域，能够改善薄膜晶体管的阈值电压漂移现象，提高阵列基板的稳定性和可靠性。该薄膜晶体管包括有源层（4）和栅极绝缘层（3），所述有源层的材质为金属氧化物半导体，在所述薄膜晶体管形成过程中，所述栅极绝缘层（3）向所述有源层（4）输氧，以降低所述有源层（4）和所述栅极绝缘层（3）之间的接触界面的界面态密度和可动杂质浓度。

Description

薄膜晶体管和阵列基板及其制作方法、显示装置 技术领域
本发明涉及显示技术领域，尤其涉及薄膜晶体管和包含该薄膜晶体管的阵列基板及其制作方法、包含该阵列基板的显示装置。
背景技术
有源矩阵液晶显示器包括阵列基板、彩膜基板以及位于其间的液晶分子层，阵列基板上设置有薄膜晶体管和像素电极等结构，其中，薄膜晶体管包括栅极、有源层、栅极绝缘层、源极和漏极，漏极电连接像素电极。
具体地，有源层的材质可以为多晶硅、单晶硅、非晶硅或者金属氧化物半导体等，当有源层的材质为金属氧化物半导体时，薄膜晶体管被称为氧化物薄膜晶体管，氧化物薄膜晶体管具有高迁移率、低漏电流以及可低温制作等优点，因此，被广泛应用于阵列基板中。栅极绝缘层的材质可以为氧化硅或者氮化硅等。
发明人发现，在显示器的显示过程中，阵列基板上的氧化物薄膜晶体管的阈值电压容易漂移，进而导致阵列基板的稳定性和可靠性较差，容易使得显示器出现显示不良。
发明内容
本发明的一个目的在于提供一种薄膜晶体管和包含该薄膜晶体管的阵列基板及其制作方法、包含该阵列基板的显示装置，能够改善薄膜晶体管的阈值电压漂移现象，提高阵列基板的稳定性和可靠性。
为实现上述目的，本发明实施例提供了一种薄膜晶体管，其包括有源层和栅极绝缘层，所述有源层的材质为金属氧化物半导体，在所述薄膜晶体管形成过程中，所述栅极绝缘层向所述有源层输氧，以降低所述有源层和所述栅极绝缘层之间的接触界面的界面态密度和 可动杂质浓度。
优选地，所述栅极绝缘层包括至少一层膜层，所述栅极绝缘层中与所述有源层接触的一层膜层的材质为SiOx、Al2O3、HfO2、ZrO2、TiO2、Y2O3、La2O3、Ta2O5中的一种，其中，1.5≤x≤2.8；所述有源层的材质为IGZO、ZnON、ITZO、ZTO、ZIO、IGO、AZTO中的一种，而且，在沉积形成所述有源层的过程中，沉积气氛中的氧含量低于20％。
进一步优选地，所述栅极绝缘层包括至少两层膜层，其中，不与所述有源层接触的一层膜层的材质为SiOx、Al2O3、HfO2、ZrO2、TiO2、Y2O3、La2O3、Ta2O5、SiNx、SiON中的一种，其中，x≤2.8。
优选地，所述薄膜晶体管还包括位于所述有源层的用于作为沟道的沟道区上的刻蚀阻挡层。
优选地，所述刻蚀阻挡层包括至少一层膜层，每一层膜层的材质为SiOx、SiNx、SiON、Al2O3、TEOS中的一种，其中，x＜1.5。
本发明实施例提供了一种薄膜晶体管，该薄膜晶体管包括有源层和栅极绝缘层，有源层的材质为金属氧化物半导体，在薄膜晶体管形成过程中，栅极绝缘层向有源层输氧，以降低有源层和栅极绝缘层之间的接触界面的界面态密度和可动杂质浓度，从而能够改善薄膜晶体管的阈值电压漂移现象，进而提高包含该薄膜晶体管的阵列基板的稳定性和可靠性，改善包含该阵列基板的显示装置的显示效果。
此外，本发明实施例还提供了一种阵列基板，其包括以上任一所述的薄膜晶体管。
优选地，所述阵列基板还包括位于所述薄膜晶体管上的钝化层以及位于所述钝化层上的透明导电层，所述钝化层包括至少一层膜层。
优选地，所述透明导电层包括像素电极，所述阵列基板还包括贯穿所述钝化层的第一过孔，所述像素电极通过所述第一过孔与所述薄膜晶体管的漏极电连接。
进一步优选地，所述钝化层包括三层膜层，所述第一过孔包括上下设置的第一部分和第二部分，所述第一部分贯穿所述钝化层的两层膜层，所述第二部分贯穿所述钝化层的一层膜层，所述第一过孔的 第一部分的宽深比比所述第一过孔的第二部分的宽深比大。
优选地，所述第一过孔的第一部分的宽深比与所述第一过孔的第二部分的宽深比之比在1.5和5之间。
优选地，所述透明导电层包括位于所述阵列基板的周边区域内的第一布线，所述阵列基板还包括位于所述周边区域内的第二布线、以及贯穿所述钝化层和所述栅极绝缘层的第二过孔，所述第二布线和所述薄膜晶体管的栅极同层设置，所述第一布线通过所述第二过孔与所述第二布线电连接。
进一步优选地，所述钝化层包括三层膜层，所述第二过孔包括上下设置的第一部分和第二部分，所述第一部分贯穿所述钝化层的两层膜层，所述第二部分贯穿所述钝化层的一层膜层和所述栅极绝缘层，所述第二过孔的第一部分的宽深比比所述第二过孔的第二部分的宽深比大。
优选地，所述第二过孔的第一部分的宽深比与所述第二过孔的第二部分的宽深比之比在1.5和5之间。
此外，本发明实施例还提供了一种显示装置，其包括以上任一所述的阵列基板。
为了进一步解决现有技术中存在的技术问题，本发明实施例提供了一种薄膜晶体管的制作方法，包括步骤：
在衬底基板上形成栅极金属层，然后，经过构图工艺，形成包括栅极的图形；
在形成了包括所述栅极的图形的所述衬底基板上，形成栅极绝缘层；
在形成了所述栅极绝缘层的所述衬底基板上，形成金属氧化物半导体层，然后，经过构图工艺，形成包括有源层的图形；
在形成了包括所述有源层的图形的所述衬底基板上，形成源漏极金属层，然后，经过构图工艺，形成包括源极和漏极的图形，以形成薄膜晶体管，其中，
所述栅极绝缘层向所述有源层输氧，以降低所述有源层和所述栅极绝缘层之间的接触界面的界面态密度和可动杂质浓度。
优选地，所述栅极绝缘层包括至少一层膜层，所述栅极绝缘层中与所述有源层接触的一层膜层的材质为SiOx、Al2O3、HfO2、ZrO2、TiO2、Y2O3、La2O3、Ta2O5中的一种，其中，1.5≤x≤2.8；所述有源层的材质为IGZO、ZnON、ITZO、ZTO、ZIO、IGO、AZTO中的一种，而且，通过沉积的方法在形成了所述栅极绝缘层的所述衬底基板上，形成金属氧化物半导体层，其中，在沉积形成金属氧化物半导体层的过程中，沉积气氛中的氧含量低于20％。
优选地，通过化学气相沉积的方法，在形成了包括所述栅极的图形的所述衬底基板上，形成所述栅极绝缘层，其中，在沉积形成栅极绝缘层的过程中，沉积气氛中N2O和SiH4的流量比大于60。
优选地，通过溅射沉积的方法，在形成了所述栅极绝缘层的所述衬底基板上，形成金属氧化物半导体层，在形成金属氧化物半导体层的过程中，沉积气氛中O2和Ar的流量比在1/20和1/7之间。
优选地，在形成包括有源层的图形之后，在形成源漏极金属层之前，还包括：在形成了包括所述有源层的图形的所述衬底基板上，形成一层刻蚀阻挡薄膜，然后，经过构图工艺，在所述有源层的用于作为沟道的沟道区上形成刻蚀阻挡层。
本发明实施例提供了一种薄膜晶体管的制作方法，该制作方法包括在衬底基板上形成栅极、栅极绝缘层、有源层、源极和漏极，以形成薄膜晶体管，其中，有源层的材质为金属氧化物半导体，栅极绝缘层向有源层输氧，以降低有源层和栅极绝缘层之间的接触界面的界面态密度和可动杂质浓度，从而能够改善薄膜晶体管的阈值电压漂移现象，进而提高包含该薄膜晶体管的阵列基板的稳定性和可靠性，改善包含该阵列基板的显示装置的显示效果。
此外，本发明实施例还提供了一种阵列基板的制作方法，其包括以上任一所述的薄膜晶体管的制作方法。
优选地，所述阵列基板的制作方法还包括：在形成了所述薄膜晶体管的所述衬底基板上，形成钝化层，所述钝化层包括至少一层膜层；在形成了所述钝化层的所述衬底基板上，形成透明导电薄膜，然后，经过构图工艺，形成透明导电层。
优选地，所述透明导电层包括像素电极，在所述形成钝化层之后，在形成透明导电层之前，还包括：形成贯穿所述钝化层的第一过孔，所述像素电极通过所述第一过孔与所述薄膜晶体管的漏极电连接。
进一步优选地，所述钝化层包括三层膜层，形成贯穿所述钝化层的第一过孔包括：对所述钝化层进行湿法刻蚀，在所述湿法刻蚀过程中，所述钝化层的两层膜层被刻蚀，以形成所述第一过孔的第一部分；对所述第一过孔的第一部分下方的所述钝化层的一层膜层进行干法刻蚀，以形成所述第一过孔的第二部分，其中，所述第一过孔的第一部分的宽深比比所述第一过孔的第二部分的宽深比大。
优选地，所述透明导电层包括位于所述阵列基板的周边区域内的第一布线，以及，在形成所述栅极的同时，形成位于所述阵列基板的周边区域内的第二布线；
在形成钝化层之后，在形成透明导电层之前，还包括：形成贯穿所述钝化层和所述栅极绝缘层的第二过孔，所述第一布线通过所述第二过孔与所述第二布线电连接。
进一步优选地，所述钝化层包括三层膜层，形成贯穿所述钝化层和所述栅极绝缘层的第二过孔包括：
对所述钝化层进行湿法刻蚀，在所述湿法刻蚀过程中，所述钝化层的两层膜层被刻蚀，以形成所述第二过孔的第一部分；
对所述第二过孔的第一部分下方的所述钝化层的一层膜层和所述栅极绝缘层进行干法刻蚀，以形成所述第二过孔的第二部分，
其中，所述第二过孔的第一部分的宽深比比所述第二过孔的第二部分的宽深比大。
优选地，在形成透明导电层之后，还包括：
对所述阵列基板进行退火。
优选地，退火温度在120℃和450℃之间，退火时间在0.5小时和3小时之间，退火环境为真空、氮气、空气或者氧气。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例描述中所需要使用的附图作简单介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本发明实施例中的薄膜晶体管的结构示意图；
图2为本发明实施例和现有技术中的薄膜晶体管的阈值电压漂移量与时间之间的关系图；
图3为本发明实施例中的阵列基板的结构示意图；
图4为本发明实施例中的薄膜晶体管的制作流程图。
附图标记说明：
1-衬底基板；2-栅极；3-栅极绝缘层；4-有源层；5-源极；6-漏极；7-刻蚀阻挡层；8-钝化层；9-第一过孔；
91-第一过孔的第一部分；92-第一过孔的第二部分；
10-像素电极；11-第一布线；12-第二布线；13-第二过孔；
131-第二过孔的第一部分；132-第二过孔的第二部分。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
实施例一
本发明实施例提供了一种薄膜晶体管，能够改善薄膜晶体管的阈值电压漂移现象，提高包含该薄膜晶体管的阵列基板的稳定性和可靠性。
具体地，如图1所示，该薄膜晶体管包括有源层4和栅极绝缘层3，有源层4的材质为金属氧化物半导体，在薄膜晶体管形成过程中，栅极绝缘层3向有源层4输氧，以降低有源层4和栅极绝缘层3 之间的接触界面的界面态密度和可动杂质浓度，从而能够改善薄膜晶体管的阈值电压漂移现象，提高包含该薄膜晶体管的阵列基板的稳定性和可靠性。
具体地，栅极绝缘层3可以包括至少一层膜层，其中，栅极绝缘层3中与有源层4接触的一层膜层的材质为SiOx、Al2O3、HfO2、ZrO2、TiO2、Y2O3、La2O3、Ta2O5中的一种，其中，1.5≤x≤2.8。有源层4的材质为IGZO、ZnON、ITZO、ZTO、ZIO、IGO、AZTO中的一种，而且，在沉积形成有源层4的过程中，沉积气氛中的氧含量低于20％。因此，栅极绝缘层3中与有源层4接触的膜层的氧含量较高，有源层4的氧含量较低，在后续退火过程中，栅极绝缘层3中与有源层4接触的膜层能够向有源层4输氧，栅极绝缘层3和有源层4之间的接触界面为富氧态，界面键合氧和游离态氧含量高，从而能够有效降低界面态密度和可动杂质浓度，有利于提升器件稳定性和可靠性，并且，栅极绝缘层3中与有源层4接触的膜层向有源层4输氧，还能够补充有源层4中的氧空位，进一步改善薄膜晶体管的阈值电压漂移现象，进一步提高包含该薄膜晶体管的阵列基板的稳定性和可靠性。
而现有技术中，栅极绝缘层的材质通常为SiOx，其中x＜1.5，有源层的材质为IGZO、ZnON、ITZO、ZTO、ZIO、IGO、AZTO中的一种因此，现有技术中形成的栅极绝缘层和有源层的氧含量均较低，不会导致栅极绝缘层向有源层输氧而使得栅极绝缘层与有源层之间的接触界面为富氧态，从而栅极绝缘层和有源层之间的接触界面的界面态密度和可动杂质浓度较高，使得薄膜晶体管的阈值电压漂移现象严重，而且，现有技术中，在沉积形成有源层的过程中，沉积气氛中的氧含量大于等于20％，因此，在形成的栅极绝缘层和有源层的氧含量均较低的情况下，形成的有源层中的氧含量可能相对高于栅极绝缘层中的氧含量，导致有源层中的氧可能会进入栅极绝缘层中以在有源层与栅绝缘层之间达到氧平衡，从而有源层中会形成氧空位，使得薄膜晶体管的阈值电压漂移现象更加严重，包含该薄膜晶体管的阵列基板的稳定性和可靠性不好。
进一步地，栅极绝缘层3包括至少两层膜层，其中，不与有源 层4接触的一层膜层的材质为SiOx、Al2O3、HfO2、ZrO2、TiO2、Y2O3、La2O3、Ta2O5、SiNx、SiON中的一种，其中，x≤2.8。
此外，如图1所示，薄膜晶体管还包括位于栅极绝缘层3下方的栅极2、以及与有源层4连接的源极5和漏极6，其中，源极5和漏极6位于有源层4上方，因此，为了防止在构图形成源极5和漏极6的过程中，对有源层4的用于作为沟道的沟道区的性能产生影响，本发明实施例中优选薄膜晶体管还包括位于有源层4的用于作为沟道的沟道区上的刻蚀阻挡层7。
具体地，刻蚀阻挡层7可以包括至少一层膜层，每一层膜层的材质为SiOx、SiNx、SiON、Al2O3、TEOS中的一种，其中，x＜1.5。栅极2、源极5和漏极6的材质可以为Mo、Al/Nd、Al/Nd/Mo、Mo/Al/Nd/Mo、Au/Ti、Pt/Ti等金属或合金。
此外，本发明实施例中的薄膜晶体管还包括用于支撑栅极2、栅极绝缘层3、有源层4、源极5、漏极6和刻蚀阻挡层7的衬底基板1，其中衬底基板1可以为玻璃基板、塑料基板(例如聚酰亚胺基板)、硅基板等。
图2为本发明实施例中(图中称为改善后)的薄膜晶体管和现有技术中(图中称为改善前)的薄膜晶体管在80度高温正压应力测试下的阈值电压漂移量与时间之间的关系图。具体地，如图2所示，对于现有技术中的薄膜晶体管，测试进行2小时(h)后，阈值电压正漂3.217伏特(V)；对于本发明实施例中的薄膜晶体管，测试进行2h后，阈值电压仅正漂0.878V，仅为现有技术中的薄膜晶体管的阈值电压漂移量的四分之一左右，测试进行10h后，阈值电压正漂4.448V，由图2可以看出，本发明实施例中的薄膜晶体管的可靠性和稳定性明显优于现有技术中的薄膜晶体管。
本发明实施例提供了一种薄膜晶体管，该薄膜晶体管包括有源层4和栅极绝缘层3，有源层4的材质为金属氧化物半导体，在薄膜晶体管形成过程中，栅极绝缘层3向有源层4输氧，以降低有源层4和栅极绝缘层3之间的接触界面的界面态密度和可动杂质浓度，从而能够改善薄膜晶体管的阈值电压漂移现象，进而提高包含该薄膜晶体 管的阵列基板的稳定性和可靠性，改善包含该阵列基板的显示装置的显示效果。
实施例二
本发明实施例提供了一种阵列基板，如图3所示，该阵列基板包括实施例一中所述的任一种薄膜晶体管。
具体地，如图3所示，该阵列基板还包括位于薄膜晶体管上的钝化层8以及位于钝化层8上的透明导电层，其中，钝化层8包括至少一层膜层。
示例性地，钝化层8包括的每一层膜层的材质可以为SiOx、SiNx、SiON、Al2O3中的一种，其中，x＜1.5。透明导电层的材质为ITO。
可选地，如图3所示，透明导电层包括像素电极10，此时，阵列基板还包括贯穿钝化层8的第一过孔9，像素电极10通过第一过孔9与薄膜晶体管的漏极6电连接。
进一步地，如图3所示，当钝化层8包括三层膜层时，第一过孔9包括上下设置的第一部分91和第二部分92，其中，第一部分91贯穿钝化层8的两层膜层，第二部分92贯穿钝化层8的一层膜层，第一部分91的宽深比(过孔的开口宽度和深度的比值定义为宽深比)比第二部分92的宽深比大，从而使得第一过孔9的侧壁呈台阶状，侧壁的倾斜角度较小，提高了像素电极10的爬坡能力，从而能够有效减少断线的发生概率，提高阵列基板的性能和良率。
进一步地，第一过孔9的第一部分91的宽深比与第一过孔9的第二部分92的宽深比之比在1.5和5之间。
可选地，如图3所示，透明导电层包括位于阵列基板的周边区域内的第一布线11，阵列基板还包括位于周边区域内的第二布线12、以及贯穿钝化层8和栅极绝缘层3的第二过孔13，第二布线12和薄膜晶体管的栅极2同层设置，第一布线11通过第二过孔13与第二布线12电连接。
进一步地，如图3所示，当钝化层8包括三层膜层时，第二过孔13包括上下设置的第一部分131和第二部分132，第一部分131 贯穿钝化层8的两层膜层，第二部分132贯穿钝化层8的一层膜层和栅极绝缘层3，第一部分131的宽深比比第二部分132的宽深比大，从而使得第二过孔13的侧壁呈台阶状，侧壁的倾斜角度较小，提高了第一布线11的爬坡能力，从而能够有效减少断线的发生概率，提高阵列基板的性能和良率。
进一步地，第二过孔的第一部分131的宽深比与第二过孔的第二部分132的宽深比之比在1.5和5之间。
此外，如图3所示，本发明实施例中的阵列基板还可以包括和栅极2同层设置的第一结构以及和源极5和漏极6同层设置的第二结构，示例性地，第一结构和第二结构可以分别为位于阵列基板的周边区域内的走线，或者，第一结构和第二结构存在交叉区域，其交叉位置处可以作为电容使用。
此外，本发明实施例还提供了一种显示装置，该显示装置包括以上所述的阵列基板。具体地，该显示装置可以为：液晶面板、电子纸、有机发光显示面板、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等具有显示功能的任何产品或部件。
实施例三
本发明实施例提供了一种用于制作实施例一中所述的薄膜晶体管的制作方法，具体地，如图4所示，该薄膜晶体管的制作方法包括以下步骤S401至S404。
步骤S401、在衬底基板上形成栅极金属层，然后，经过构图工艺，形成包括栅极的图形。
具体地，如图1所示，在衬底基板1上，使用溅射等方法形成栅极金属层，然后，经过构图工艺，形成包括栅极2的图形。
步骤S402、在形成了包括栅极的图形的衬底基板上，形成栅极绝缘层。
具体地，如图1所示，在形成了包括栅极2的图形的衬底基板1上，使用常压化学气相沉积、低压化学气相沉积、等离子辅助体化学气相淀积、溅射等方法，形成栅极绝缘层3。
步骤S403、在形成了栅极绝缘层的衬底基板上，形成金属氧化 物半导体层，然后，经过构图工艺，形成包括有源层的图形。
具体地，如图1所示，在形成了栅极绝缘层3的衬底基板1上，使用溅射、溶胶-凝胶、真空蒸镀、喷涂、喷墨打印等方法，形成金属氧化物半导体层，然后，经过构图工艺，形成包括有源层4的图形。
步骤S404、在形成了包括有源层的图形的衬底基板上，形成源漏极金属层，然后，经过构图工艺，形成包括源极和漏极的图形，以形成薄膜晶体管。
具体地，如图1所示，在形成了包括有源层4的图形的衬底基板1上，使用溅射等方法形成源漏极金属层，然后，经过构图工艺，形成包括源极5和漏极6的图形，以形成薄膜晶体管。
在上述制作过程中，栅极绝缘层3向有源层4输氧，以降低有源层4和栅极绝缘层3之间的接触界面的界面态密度和可动杂质浓度，从而能够改善薄膜晶体管的阈值电压漂移现象，进而提高包含该薄膜晶体管的阵列基板的稳定性和可靠性，改善包含该阵列基板的显示装置的显示效果。
具体地，栅极绝缘层3包括至少一层膜层，栅极绝缘层3中与有源层4接触的一层膜层的材质为SiOx、Al2O3、HfO2、ZrO2、TiO2、Y2O3、La2O3、Ta2O5中的一种，其中，1.5≤x≤2.8。有源层4的材质为IGZO、ZnON、ITZO、ZTO、ZIO、IGO、AZTO中的一种，通过沉积的方法在形成了栅极绝缘层3的衬底基板1上，形成金属氧化物半导体层，其中，在沉积形成金属氧化物半导体层的过程中，沉积气氛中的氧含量低于20％。因此，本发明实施例中的栅极绝缘层3中与有源层4接触的膜层的氧含量较高，有源层4的氧含量较低，在后续退火过程中，栅极绝缘层3中与有源层4接触的膜层能够向有源层4输氧，栅极绝缘层3和有源层4之间的接触界面为富氧态，界面键合氧和游离态氧含量高，从而能够有效降低界面态密度和可动杂质浓度，有利于提升器件稳定性和可靠性，并且，栅极绝缘层3中与有源层4接触的膜层向有源层4输氧，还能够补充有源层4中的氧空位，进一步改善薄膜晶体管的阈值电压漂移现象，进一步提高包含该薄膜晶体管的阵列基板的稳定性和可靠性。
可选地，本发明实施例通过化学气相沉积的方法，在形成了包括栅极2的图形的衬底基板1上，形成栅极绝缘层3，其中，在沉积形成栅极绝缘层3的过程中，沉积气氛中N2O和SiH4的流量比大于60，以使得形成的栅极绝缘层3的氧含量较高。
本发明实施例通过溅射沉积的方法，在形成了栅极绝缘层3的衬底基板1上，形成金属氧化物半导体层，然后经过构图工艺形成包括有源层4的图形，其中，可选地，在沉积形成金属氧化物半导体层的过程中，沉积气氛中O2和Ar的流量比在1/20和1/7之间，以使得形成的有源层4的氧含量较低。
此外，为了防止在构图形成包括源极5和漏极6的图形过程中，对有源层4的用于作为沟道的沟道区的性能产生影响，本发明实施例中，优选地，在形成包括有源层4的图形之后，在形成源漏极金属层之前，还包括：在形成了有源层4的图形的衬底基板1上，形成一层刻蚀阻挡薄膜，然后，经过构图工艺，在有源层4的用于作为沟道的沟道区上形成刻蚀阻挡层7。
本发明实施例提供了一种薄膜晶体管的制作方法，该制作方法包括在衬底基板上形成栅极，栅极绝缘层，有源层，源极和漏极，以形成薄膜晶体管，其中，有源层的材质为金属氧化物半导体，栅极绝缘层向有源层输氧，以降低有源层和栅极绝缘层之间的接触界面的界面态密度和可动杂质浓度，从而能够改善薄膜晶体管的阈值电压漂移现象，进而提高包含该薄膜晶体管的阵列基板的稳定性和可靠性，改善包含该阵列基板的显示装置的显示效果。
实施例四
此外，本发明实施例还提供了一种用于制作实施例二中所述的阵列基板的制作方法，该阵列基板的制作方法包括实施例三中所述的薄膜晶体管的制作方法。
进一步地，阵列基板的制作方法还包括以下步骤S501至S502。
步骤S501、在形成了薄膜晶体管的衬底基板上，形成钝化层，钝化层包括至少一层膜层。
具体地，在形成了薄膜晶体管的衬底基板上，使用热生长、常 压化学气相沉积、低压化学气相沉积、等离子辅助体化学气相淀积、溅射等方法，连续生长钝化层8，如图3所示。
需要说明的是，现有技术中，通常在形成了薄膜晶体管的衬底基板1上，形成钝化层8之后，还对阵列基板进行退火，示例性地，退火环境为氧气、氮气或真空，退火温度为200度以上，退火时间为2-3小时。然而，发明人发现，当薄膜晶体管采用实施例三中所述的制作方法制作时，形成钝化层8之后，对阵列基板进行和现有技术相比较短时间的退火、或者不进行退火，能够更加有利于控制接触界面的氧分布，从而达到提高阵列基板的均匀性、稳定性和可靠性的目的，因此，本发明实施例中优选在形成钝化层8后，不对阵列基板进行退火，一方面提高阵列基板的均匀性、稳定性和可靠性，另一方面，还可以简化阵列基板的制作工艺，节约成本。
步骤S502、在形成了钝化层的衬底基板上，形成透明导电薄膜，然后，经过构图工艺，形成透明导电层。
具体地，在形成了钝化层8的衬底基板1上，使用溅射的方法形成透明导电薄膜，然后，经过构图工艺，形成透明导电层。
可选地，当透明导电层包括像素电极10时，本发明实施例中优选在形成钝化层8之后，在形成透明导电层之前，还包括：形成贯穿钝化层8的第一过孔9，以使得像素电极10通过第一过孔9与薄膜晶体管的漏极6电连接。
当钝化层8包括三层膜层时，形成贯穿钝化层8的第一过孔9具体包括以下步骤：首先，对钝化层8进行湿法刻蚀，在湿法刻蚀过程中，钝化层8的两层膜层被刻蚀，以形成第一过孔9的第一部分91；然后，对第一过孔9的第一部分91下方的钝化层8的一层膜层进行干法刻蚀，以形成第一过孔9的第二部分92。
该实施例中，第一过孔9的第一部分91的宽深比比第一过孔9的第二部分92的宽深比大，从而使得第一过孔9的侧壁呈台阶状，侧壁的倾斜角度较小，提高了像素电极10的爬坡能力，从而能够有效减少断线的发生概率，提高阵列基板的性能和良率。
可选地，当透明导电层包括位于阵列基板的周边区域内的第一 布线11、并且在形成栅极2的同时还形成位于阵列基板的周边区域内的第二布线12时，本发明实施例中优选在形成钝化层8之后，在形成透明导电层之前，还包括：形成贯穿钝化层8和栅极绝缘层3的第二过孔13，第一布线11通过第二过孔13与第二布线12电连接。
当钝化层8包括三层膜层时，形成贯穿钝化层8和栅极绝缘层3的第二过孔13具体包括以下步骤：首先，对钝化层8进行湿法刻蚀，在湿法刻蚀过程中，钝化层8的两层膜层被刻蚀，以形成第二过孔13的第一部分131；然后，对第二过孔13的第一部分131下方的钝化层8的一层膜层和栅极绝缘层3进行干法刻蚀，以形成第二过孔13的第二部分132。
该实施例中，第二过孔13的第一部分131的宽深比比第二过孔13的第二部分132的宽深比大，从而使得第二过孔13的侧壁呈台阶状，侧壁的倾斜角度较小，提高了第一布线11的爬坡能力，从而能够有效减少断线的发生概率，提高阵列基板的性能和良率。
此外，本发明实施例中的阵列基板的制作方法在形成透明导电层之后，还包括：对阵列基板进行退火，以减少有源层4中的缺陷数量。
示例性地，退火温度在120℃和450℃之间，退火时间在0.5小时和3小时之间，退火环境为真空、氮气、空气或者氧气。
上述实施例中仅示出了第一过孔9和第二过孔13各自单独形成的过程，然而，进一步地，为了简化阵列基板的制作工艺、节约成本，第一过孔9和第二过孔13可以同时形成。然而，由于第一过孔9的深度小于第二过孔13的深度，因此，为了使第一过孔9和第二过孔13同时形成，首先，可以通过湿法刻蚀来同时形成第一过孔9的第一部分以及第二过孔13的第一部分，该过程中，例如，可以适当调整并使第一过孔9的开口尺寸小于第二过孔13的开口尺寸，使得第一过孔9的第一部分的深度小于第二过孔13的第一部分的深度，然后，通过干法刻蚀来形成第一过孔9的第二部分以及第二过孔13的第二部分，其中，通过在湿法刻蚀的过程中适当调整第一过孔9的开口尺寸与第二过孔13的开口尺寸，使得第一过孔9的第二部分与第 二过孔13的第二部分也同时形成。
以上所述，仅为本发明的具体实施方式，但本发明的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本发明揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本发明的保护范围之内。因此，本发明的保护范围应以所述权利要求的保护范围为准。

Claims (26)

  1. 一种薄膜晶体管，包括有源层和栅极绝缘层，所述有源层的材质为金属氧化物半导体，其中，
    在所述薄膜晶体管形成过程中，所述栅极绝缘层向所述有源层输氧，以降低所述有源层和所述栅极绝缘层之间的接触界面的界面态密度和可动杂质浓度。
  2. 根据权利要求1所述的薄膜晶体管，其中，
    所述栅极绝缘层包括至少一层膜层，所述栅极绝缘层中与所述有源层接触的一层膜层的材质为SiOx、Al2O3、HfO2、ZrO2、TiO2、Y2O3、La2O3、Ta2O5中的一种，其中，1.5≤x≤2.8；
    所述有源层的材质为IGZO、ZnON、ITZO、ZTO、ZIO、IGO、AZTO中的一种，在沉积形成所述有源层的过程中，沉积气氛中的氧含量低于20％。
  3. 根据权利要求2所述的薄膜晶体管，其中，
    所述栅极绝缘层包括至少两层膜层，其中，不与所述有源层接触的一层膜层的材质为SiOx、Al2O3、HfO2、ZrO2、TiO2、Y2O3、La2O3、Ta2O5、SiNx、SiON中的一种，其中，x≤2.8。
  4. 根据权利要求1-3任一项所述的薄膜晶体管，还包括位于所述有源层的用于作为沟道的沟道区上的刻蚀阻挡层。
  5. 根据权利要求4所述的薄膜晶体管，其中，所述刻蚀阻挡层包括至少一层膜层，每一层膜层的材质为SiOx、SiNx、SiON、Al2O3、TEOS中的一种，其中，x＜1.5。
  6. 一种阵列基板，包括如权利要求1-5任一项所述的薄膜晶体管。
  7. 根据权利要求6所述的阵列基板，还包括位于所述薄膜晶体管上的钝化层以及位于所述钝化层上的透明导电层，所述钝化层包括至少一层膜层。
  8. 根据权利要求7所述的阵列基板，其中，所述透明导电层包括像素电极，所述阵列基板还包括贯穿所述钝化层的第一过孔，所述像素电极通过所述第一过孔与所述薄膜晶体管的漏极电连接。
  9. 根据权利要求8所述的阵列基板，其中，所述钝化层包括三层膜层，所述第一过孔包括上下设置的第一部分和第二部分，所述第一部分贯穿所述钝化层的两层膜层，所述第二部分贯穿所述钝化层的一层膜层，所述第一过孔的第一部分的宽深比比所述第一过孔的第二部分的宽深比大。
  10. 根据权利要求9所述的阵列基板，其中，所述第一过孔的第一部分的宽深比与所述第一过孔的第二部分的宽深比之比在1.5和5之间。
  11. 根据权利要求7-10任一项所述的阵列基板，其中，所述透明导电层包括位于所述阵列基板的周边区域内的第一布线，所述阵列基板还包括位于所述周边区域内的第二布线、以及贯穿所述钝化层和所述栅极绝缘层的第二过孔，所述第二布线和所述薄膜晶体管的栅极同层设置，所述第一布线通过所述第二过孔与所述第二布线电连接。
  12. 根据权利要求11所述的阵列基板，其中，所述钝化层包括三层膜层，所述第二过孔包括上下设置的第一部分和第二部分，所述第一部分贯穿所述钝化层的两层膜层，所述第二部分贯穿所述钝化层的一层膜层和所述栅极绝缘层，所述第二过孔的第一部分的宽深比比所述第二过孔的第二部分的宽深比大。
  13. 根据权利要求12所述的阵列基板，其中，所述第二过孔的第一部分的宽深比与所述第二过孔的第二部分的宽深比之比在1.5和5之间。
  14. 一种显示装置，包括如权利要求6-13任一项所述的阵列基板。
  15. 一种薄膜晶体管的制作方法，包括：
    在衬底基板上形成栅极金属层，然后，经过构图工艺，形成包括栅极的图形；
    在形成了包括所述栅极的图形的所述衬底基板上，形成栅极绝缘层；
    在形成了所述栅极绝缘层的所述衬底基板上，形成金属氧化物半导体层，然后，经过构图工艺，形成包括有源层的图形；
    在形成了包括所述有源层的图形的所述衬底基板上，形成源漏极金属层，然后，经过构图工艺，形成包括源极和漏极的图形，以形成薄膜晶体管，其中，
    所述栅极绝缘层向所述有源层输氧，以降低所述有源层和所述栅极绝缘层之间的接触界面的界面态密度和可动杂质浓度。
  16. 根据权利要求15所述的薄膜晶体管的制作方法，其中，
    所述栅极绝缘层包括至少一层膜层，所述栅极绝缘层中与所述有源层接触的一层膜层的材质为SiOx、Al2O3、HfO2、ZrO2、TiO2、Y2O3、La2O3、Ta2O5中的一种，其中，1.5≤x≤2.8；
    所述有源层的材质为IGZO、ZnON、ITZO、ZTO、ZIO、IGO、AZTO中的一种，通过沉积的方法在形成了所述栅极绝缘层的所述衬底基板上，形成金属氧化物半导体层，在沉积形成金属氧化物半导体层的过程中，沉积气氛中的氧含量低于20％。
  17. 根据权利要求16所述的薄膜晶体管的制作方法，其中，
    通过化学气相沉积的方法，在形成了包括所述栅极的图形的所述衬底基板上，形成所述栅极绝缘层，其中，在沉积形成所述栅极绝缘层的过程中，沉积气氛中N2O和SiH4的流量比大于60；
    通过溅射沉积的方法，在形成了所述栅极绝缘层的所述衬底基板上，形成金属氧化物半导体层，其中，在沉积形成金属氧化物半导体层的过程中，沉积气氛中O2和Ar的流量比在1/20和1/7之间。
  18. 根据权利要求15-17任一项所述的薄膜晶体管的制作方法，其中，在形成包括有源层的图形之后，在形成源漏极金属层之前，所述制作方法还包括：在形成了所述有源层的图形的所述衬底基板上，形成一层刻蚀阻挡薄膜，然后，经过构图工艺，在所述有源层的用于作为沟道的沟道区上形成刻蚀阻挡层。
  19. 一种阵列基板的制作方法，包括如权利要求15-18任一项所述的薄膜晶体管的制作方法。
  20. 根据权利要求19所述的阵列基板的制作方法，还包括：
    在形成了所述薄膜晶体管的所述衬底基板上，形成钝化层，所述钝化层包括至少一层膜层；
    在形成了所述钝化层的所述衬底基板上，形成透明导电薄膜，然后，经过构图工艺，形成透明导电层。
  21. 根据权利要求20所述的阵列基板的制作方法，其中，所述透明导电层包括像素电极，在形成钝化层之后，在形成透明导电层之前，所述制作方法还包括：形成贯穿所述钝化层的第一过孔，所述像素电极通过所述第一过孔与所述薄膜晶体管的漏极电连接。
  22. 根据权利要求21所述的阵列基板的制作方法，其中，所述钝化层包括三层膜层，形成贯穿所述钝化层的第一过孔包括：
    对所述钝化层进行湿法刻蚀，在所述湿法刻蚀过程中，所述钝化层的两层膜层被刻蚀，以形成所述第一过孔的第一部分；
    对所述第一过孔的第一部分下方的所述钝化层的一层膜层进行干法刻蚀，以形成所述第一过孔的第二部分；
    其中，所述第一过孔的第一部分的宽深比比所述第一过孔的第二部分的宽深比大。
  23. 根据权利要求20一22任一项所述的阵列基板的制作方法，其中，所述透明导电层包括位于所述阵列基板的周边区域内的第一布线，并且在形成所述栅极的同时，形成位于所述阵列基板的周边区域内的第二布线；
    在形成钝化层之后，在形成透明导电层之前，所述制作方法还包括：形成贯穿所述钝化层和所述栅极绝缘层的第二过孔，所述第一布线通过所述第二过孔与所述第二布线电连接。
  24. 根据权利要求23所述的阵列基板的制作方法，其中，所述钝化层包括三层膜层，形成贯穿所述钝化层和所述栅极绝缘层的第二过孔包括：
    对所述钝化层进行湿法刻蚀，在所述湿法刻蚀过程中，所述钝化层的两层膜层被刻蚀，以形成所述第二过孔的第一部分；
    对所述第二过孔的第一部分下方的所述钝化层的一层膜层和所述栅极绝缘层进行干法刻蚀，以形成所述第二过孔的第二部分；
    其中，所述第二过孔的第一部分的宽深比比所述第二过孔的第二部分的宽深比大。
  25. 根据权利要求20所述的阵列基板的制作方法，其中，在形成所述透明导电层之后，所述制作方法还包括：
    对所述阵列基板进行退火。
  26. 根据权利要求25所述的阵列基板的制作方法，其中，退火 温度在120℃和450℃之间，退火时间在0.5小时和3小时之间，退火环境为真空、氮气、空气或者氧气。
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