WO2016141805A1 - 薄膜层图案、薄膜晶体管及阵列基板的制备方法 - Google Patents
薄膜层图案、薄膜晶体管及阵列基板的制备方法 Download PDFInfo
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- WO2016141805A1 WO2016141805A1 PCT/CN2016/074360 CN2016074360W WO2016141805A1 WO 2016141805 A1 WO2016141805 A1 WO 2016141805A1 CN 2016074360 W CN2016074360 W CN 2016074360W WO 2016141805 A1 WO2016141805 A1 WO 2016141805A1
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- 239000000758 substrate Substances 0.000 title claims abstract description 137
- 239000010409 thin film Substances 0.000 title claims abstract description 94
- 238000002360 preparation method Methods 0.000 title claims abstract description 13
- 238000000034 method Methods 0.000 claims abstract description 85
- 238000004519 manufacturing process Methods 0.000 claims abstract description 21
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- 239000004065 semiconductor Substances 0.000 claims description 49
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- 239000000463 material Substances 0.000 claims description 15
- 238000004544 sputter deposition Methods 0.000 claims description 10
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 9
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 7
- 229910044991 metal oxide Inorganic materials 0.000 claims description 5
- 150000004706 metal oxides Chemical class 0.000 claims description 5
- 229920005591 polysilicon Polymers 0.000 claims description 5
- 239000010410 layer Substances 0.000 description 112
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- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 5
- 229910001182 Mo alloy Inorganic materials 0.000 description 4
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- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- 238000000137 annealing Methods 0.000 description 3
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- 238000000576 coating method Methods 0.000 description 3
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- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
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- YVTHLONGBIQYBO-UHFFFAOYSA-N zinc indium(3+) oxygen(2-) Chemical compound [O--].[Zn++].[In+3] YVTHLONGBIQYBO-UHFFFAOYSA-N 0.000 description 1
Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
- H01L27/1274—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement using crystallisation of amorphous semiconductor or recrystallisation of crystalline semiconductor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
Definitions
- Embodiments of the present invention relate to a thin film layer pattern, a thin film transistor, and a method of fabricating an array substrate.
- a gate electrode, a semiconductor active layer, a source and a drain are first defined by a yellow light process, and then covered by a photoresist by an etching process.
- the thin film is etched away to obtain a desired pattern; wherein the yellow light process includes photoresist coating, exposure, and development.
- the requirements for the stability of the production equipment are higher and higher when the corresponding pattern is produced by the yellow light process, especially the yellow light and the etching equipment, if the two devices are unstable. Or, it is easy to cause the photoresist to remain or the etching is poor, so that the formed layer patterns are defective.
- the formed pattern is a conductive pattern, for example, a short circuit or an open circuit may occur.
- the manufacturing process takes a long time, and the yield is easily increased. Risk and uncertainty, and the use of conventional photoresist and etching-related liquids is not conducive to the reduction of production costs.
- An embodiment of the present invention provides a method of fabricating a film layer pattern, comprising: providing a mask plate, the mask plate including a mask body and a hollow portion disposed on the mask body; placing the mask Projecting a projection of the hollow portion on the substrate with a projection of a film layer pattern to be formed on the substrate; forming a film on the substrate on which the mask is placed; wherein a first film portion of the hollow portion and a second film portion formed on the mask body are disconnected; the mask is peeled off to retain the first film portion on the substrate to form the film layer pattern .
- the substrate is formed by a sputtering method on a substrate on which the mask is placed film.
- the reticle is a metal reticle.
- the metal reticle has a thickness between 720 um and 880 um.
- the film is an amorphous silicon film, the method further comprising annealing the first film portion remaining on the substrate after peeling the mask to make the first film Partial crystallization.
- Another embodiment of the present invention provides a method of fabricating a thin film transistor, including: forming a gate, a gate insulating layer, a semiconductor active layer, a source and a drain on a substrate; wherein the gate, the semiconductor At least one of the active layer, the source and the drain is formed by the thin film layer pattern preparation method of any of the above.
- the material of the semiconductor active layer includes a metal oxide semiconductor or polysilicon.
- a further embodiment of the present invention provides a method of fabricating an array substrate, comprising: forming a thin film transistor on a substrate; and a pixel electrode electrically connected to a drain of the thin film transistor; the thin film transistor includes a gate and a gate insulating layer a semiconductor active layer, a source and a drain; wherein at least one of the gate, the semiconductor active layer, the source and drain, and the pixel electrode pass through the thin film layer of any of the above
- the pattern preparation method is prepared and formed.
- the method further includes forming a plurality of signal lines on the substrate; wherein the at least one signal line is formed by the thin film layer pattern preparation method of any of the above.
- a further embodiment of the present invention provides a method of fabricating an array substrate, comprising: forming a thin film transistor on a substrate, a pixel electrode electrically connected to a drain of the thin film transistor, and a common electrode; the thin film transistor including a gate a gate insulating layer, a semiconductor active layer, a source and a drain; wherein at least one of the gate, the semiconductor active layer, the source and drain, the pixel electrode, and the common electrode
- a method is prepared by the method for preparing a film layer pattern of any of the above.
- the method further includes forming a plurality of signal lines on the substrate; wherein the at least one signal line is formed by the thin film layer pattern preparation method of any of the above.
- a further embodiment of the present invention provides a method of fabricating an array substrate, comprising: forming a thin film transistor on a substrate, and an electrode layer electrically connected to a drain of the thin film transistor; the thin film transistor includes a gate and a gate insulating layer a semiconductor active layer, a source and a drain; wherein the gate, the semiconductor active layer, the source and drain, and the electrode layer electrically connected to the drain At least one is prepared by the film layer pattern preparation method of any of the above.
- the method further includes forming a plurality of signal lines on the substrate; wherein the at least one signal line is formed by the thin film layer pattern preparation method of any of the above.
- the electrode layer is the anode or cathode of a light emitting diode.
- FIG. 1 is a schematic flow chart of a method for preparing a thin film layer pattern according to an embodiment of the present invention
- FIGS. 2a-2d are schematic diagrams showing relevant stages of a method for forming a thin film layer pattern according to an embodiment of the present invention
- 3a-3i are schematic diagrams showing relevant stages of a method for forming a thin film transistor according to an embodiment of the present invention.
- 4a-4b are schematic diagrams showing relevant stages of a method for forming an array substrate according to an embodiment of the present invention.
- 5a-5b are schematic diagrams showing related stages of a method for forming an array substrate according to an embodiment of the present invention.
- Embodiments of the present invention provide a method for preparing a thin film layer pattern, a thin film transistor, and an array substrate, which can effectively improve product yield, and can shorten a manufacturing cycle and save cost.
- the embodiment of the invention provides a method for preparing a film layer pattern. As shown in FIG. 1 , the preparation method comprises the following steps:
- a mask 10 is provided, the mask 10 including a mask body 101 and a hollow portion 102 disposed on the mask body.
- the material of the mask 10 is not limited.
- the material of the mask 10 may be a material that is not easily deformed.
- the mask 10 is placed on the substrate 30 such that the projection of the hollow portion 102 on the substrate 30 coincides with the projection of the film layer pattern to be formed on the substrate 30. .
- the substrate 30 may be a substrate that does not form an arbitrary pattern, or may be a substrate on which a pattern of each layer is formed.
- the substrate is a substrate on which each layer pattern is formed
- a projection of the hollow portion 102 on the substrate 30 and a projection of the thin film layer pattern to be formed on the substrate 30 are overlapped, that is, The projection of the hollow portion 102 on the base substrate coincides with the projection of the thin film layer pattern to be formed on the base substrate.
- the thin film layer pattern may be a conductive layer pattern such as a gate electrode, a source and a drain, or the like, or may be a semiconductor layer pattern such as a semiconductor active layer, and of course may be other, such as an insulating layer.
- a film 20a is formed on the substrate 30 on which the mask 10 is placed; wherein the first film portion S1 formed on the hollow portion 102 and the mask body 101 are formed The second film portion S2 is broken.
- the material of the film 20a may be a metal material or a semiconductor material, for example This may depend on the pattern of the film layer that is desired to be formed.
- the film portion S1 formed at the hollow portion 102 and the film portion S2 formed on the mask body 101 can be made by controlling the thickness of the mask 10 and/or the process of forming the film 20a. disconnect.
- the first film portion S1 formed in the hollow portion 102 may include, for example, a plurality of first sub-film portions P1, each of the first sub-thin film portions P1 and a second film portion formed on the mask body 101. S2 is disconnected.
- the mask sheet 10 is peeled off, and the first film portion S1 is left on the substrate to form the film layer pattern 20.
- the film 20a is formed on the substrate 30 on which the mask 10 is placed, since the film 20a is formed not only on the mask body 101 but also in the hollow portion 102, When the mask 10 is peeled off, the second film portion S2 on the mask body 101 is carried away along with the mask 10, so that the first film portion S1 located at the hollow portion 102 is left in the The substrate 30 is used as the thin film layer pattern 20.
- the film 20a refers to a film formed by deposition, sputtering or other processes on a substrate by using a certain material
- the film layer pattern is a layer formed as described above. The portion of the film that the film ultimately remains on the substrate 30.
- the film layer pattern 20 may be a gate, or a source and a drain; when the film 20a is a semiconductor film, the film layer pattern 20 may be Semiconductor active layer.
- An embodiment of the present invention provides a method for preparing a thin film layer pattern, the method comprising: providing a mask 10, the mask 10 including a mask body 101 and a hollow portion 102 disposed on the mask body; The mask 10 is placed on the substrate 30 such that the projection of the hollow portion 102 on the substrate coincides with the projection of the thin film layer pattern 20 to be formed on the substrate; the substrate on which the mask 10 is placed Forming a film 20a thereon; wherein a first film portion formed on the hollow portion 102 and a second film portion formed on the mask body 101 are disconnected; the mask sheet 10 is peeled off to form the film layer Pattern 20.
- the yellow light process such as photoresist coating, exposure and development is not required to define the pattern of the photoresist, and the subsequent etching and stripping processes are not required, the fabrication cycle is greatly shortened, and the production cost is reduced. .
- the yellow light and the etching process are not required, the probability of defects of the thin film layer pattern 20 is greatly reduced, thereby effectively improving the product yield.
- the film 20a is formed by a sputtering method.
- the problem of static electricity is generated by depositing the thin film 20a on the substrate 30 on which the mask 10 is placed by plasma enhanced chemical vapor deposition (PECVD), which can be avoided by the sputtering method in the embodiment of the present invention.
- PECVD plasma enhanced chemical vapor deposition
- the mask 10 is a metal mask.
- the mask 10 using the metal material is not easily deformed, it is ensured that the film layer pattern 20 formed in the hollow portion 102 is a desired pattern, and after the film 20a is formed, the mask 10 can be conveniently disposed. Stripped.
- the thickness of the metal mask 10 is between 720 um and 880 um.
- the embodiment of the present invention further provides a method for fabricating a thin film transistor, comprising: forming a gate, a gate insulating layer, a semiconductor active layer, a source and a drain on a base substrate; wherein the gate, the semiconductor At least one of the active layer, the source and the drain is formed by the above-described method of preparing a thin film layer pattern.
- the gate electrode may be formed by the above-described method of forming the thin film layer pattern 20, and/or the semiconductor active layer may be formed, and/or the source and drain electrodes may be formed.
- the thin film 20a is a conductive metal thin film, and the material thereof may be, for example, a metal, a metal alloy such as molybdenum, a molybdenum alloy or the like.
- the thin film 20a described above is a semiconductor thin film, and a material thereof is, for example, amorphous silicon, polycrystalline silicon, metal oxide semiconductor or the like.
- the thin film 20a is a conductive metal thin film, and the material thereof may be, for example, a metal, a metal alloy such as molybdenum, a molybdenum alloy, aluminum, an aluminum alloy, or the like. Titanium, etc.
- the material of the semiconductor active layer in the embodiment of the present invention is, for example, a metal oxide semiconductor or polysilicon, in view of the high mobility requirement of the thin film transistor. That is, when the semiconductor active layer is formed, the material of the thin film 20a is a metal oxide semiconductor or polycrystalline silicon.
- an embodiment of the present invention provides a method for preparing a low temperature polysilicon thin film transistor.
- the method comprises the following steps:
- a buffer layer 40 is formed on the base substrate 301.
- a buffer layer 40 is formed by plasma enhanced chemical vapor deposition or sputtering to block diffusion of impurities contained in the glass into the active layer to prevent diffusion of impurities contained in the glass into the active layer. It affects characteristics such as threshold voltage and leakage current of the thin film transistor element.
- the buffer layer 40 may be a single layer of silicon oxide, silicon nitride or a laminate of the two.
- the mask 10 is placed on the substrate on which the step S101 is completed, so that the hollow portion 102-1 of the mask 10-1 (not shown in FIG. 3a) is projected on the substrate 301.
- the projection of the semiconductor active layer to be formed on the substrate substrate 301 completely coincides.
- step S103 forming an amorphous silicon film 50a by sputtering on the substrate on which step S102 is completed, wherein the first amorphous silicon film portion S1-1 formed in the hollow portion 102-1 and formed The second amorphous silicon film portion S2-1 on the mask body 101 is broken.
- the mask 10-1 is peeled off after the substrate of step S103 is completed, and the substrate from which the mask 10-1 is peeled off is placed in an annealing furnace to perform dehydrogenation treatment.
- the substrate is placed in an annealing furnace for a certain period of time to reduce the hydrogen content in the amorphous silicon to, for example, 2% or less, to avoid the problem of hydrogen explosion occurring in the subsequent laser annealing process.
- the amorphous silicon film 50a is processed by an excimer laser annealing method, and the amorphous silicon film 50a is crystallized to form the semiconductor active layer 50 as shown in FIG. 3c. .
- the first insulating film 60a is formed by a PECVD method.
- the first insulating film 60a may be a single layer of silicon oxide, silicon nitride or a laminate of the two.
- a mask 10-2 is placed on the substrate on which step S106 is completed, so that the hollow portion 102-2 of the mask 10-2 (not labeled in FIG. 3d) is on the base substrate 301.
- the projection completely coincides with the projection of the gate to be formed on the base substrate 301.
- step S108 forming a gate metal film 70a by sputtering on the substrate on which step S107 is completed, wherein the first gate metal film portion S1-2 is formed in the hollow portion 102-2
- the second gate metal film portion S2-2 on the mask body 101 is broken.
- the material of the gate metal film 70a may be a conductive material such as a metal or a metal alloy such as molybdenum or molybdenum alloy.
- the mask sheet 10-2 is peeled off on the substrate on which the step S108 is completed, and the first gate metal film portion S1-2 is left on the substrate to form the gate electrode 70.
- a second insulating film 80a is formed by a PECVD method on the substrate on which step S109 is completed.
- the second insulating film 80a may be a single layer of silicon oxide, silicon nitride or a laminate of the two.
- a first via 801 for connecting the source to the semiconductor active layer 50 and a drain for the semiconductor are formed by a patterning process
- the second via hole 802 to which the active layer 50 is connected forms the first insulating film 60a as the gate insulating layer 60, and the second insulating film 80a is formed as the interlayer insulating layer 80.
- the mask 10-3 is placed such that the hollow portion 102-3 of the mask 10-3 (not labeled in FIG. 3h) is on the base substrate 301.
- a source/drain metal film 90a is formed on the substrate on which the step S112 is completed by a sputtering method, wherein the first source/drain metal film portion S1-3 formed in the hollow portion 102-3 is formed and formed.
- the second source/drain metal film portion S2-3 on the mask body 101 is broken.
- the material of the source/drain metal film 90a may be a conductive material such as a metal or a metal alloy such as molybdenum, molybdenum alloy, aluminum, aluminum alloy, or titanium.
- the mask sheet 10-3 is peeled off on the substrate on which the step S113 is completed, and the first source/drain metal film portion S1-3 is left on the substrate to form the source 901 and the drain 902.
- a low temperature polysilicon thin film transistor can be prepared by the above steps S101 to S114.
- the embodiment of the invention provides a method for preparing an array substrate, comprising: forming a thin film transistor on a base substrate 301 and a pixel electrode electrically connected to the drain 902 of the thin film transistor; the thin film transistor includes a gate 70, a gate insulating layer 60, a semiconductor active layer 50, a source 901, and a drain 902; wherein the gate 70, the semiconductor active layer 50, the source 901 and the drain 902, and the pixel electrode At least one of the preparations is carried out by the above method of preparing the film layer pattern 20.
- the gate electrode 70 can be formed by the above-described method of forming the thin film layer pattern 20, and / Or forming the semiconductor active layer 50, and/or forming the source 901 and the drain 902, and/or forming the pixel electrode.
- the thin film 20a is a transparent conductive film made of, for example, indium tin oxide (ITO), indium zinc oxide (IZO), or the like.
- An embodiment of the present invention provides a method for fabricating an array substrate for a display device.
- the method further includes: on the basis of the foregoing S101-S114,
- a protective layer 100 is formed on the substrate on which the step S114 is completed, and the protective layer 100 includes a third via hole that leaks out the drain 902.
- the mask 10-4 is placed such that the hollow portion 102-4 of the mask 10-4 (not labeled in FIG. 4a) is on the base substrate 301.
- the projection of the pixel electrode to be formed completely coincides with the projection of the pixel substrate 301.
- a pixel transparent conductive film 110a is formed by a sputtering method, wherein the first pixel transparent conductive film portion S1-4 formed in the hollow portion 102-4 and The second pixel transparent conductive film portion S2-4 formed on the mask body 101 is broken.
- the mask sheet 10-4 is peeled off on the substrate on which the step S116 is completed, and the first pixel transparent conductive film portion S1-4 is left on the substrate to form the pixel electrode 110.
- the method further includes forming a plurality of signal lines on the base substrate 301, wherein the at least one signal line is prepared by a method of preparing the thin film layer pattern 20.
- the signal line includes a gate line, a data line, and the like.
- the signal line further includes a common electrode line, and for the array substrate of the organic electroluminescent diode display device, The signal line also includes a power cord.
- the gate line may be formed using the same mask 10-2 as the gate 70, that is, the projection and formation of the hollow portion 102-2 of the mask 10-2 on the substrate substrate 301 may be formed.
- the projection of the gate line and the gate 70 on the base substrate 301 completely coincides.
- the data line may be formed using the same mask 10-3 as the source 901 and the drain 902, that is, the hollow portion 102-3 of the mask 10-3 may be on the substrate.
- the projection of the substrate 301 completely coincides with the projection of the data line and the source 901 and the drain 902 to be formed on the substrate 301.
- the embodiment of the present invention further provides a method for fabricating another array substrate, comprising: forming a thin film transistor on the base substrate 301; and a pixel electrode 110 electrically connected to the drain 902 of the thin film transistor; and a common electrode;
- the thin film transistor includes a gate 70, a gate insulating layer 60, a semiconductor active layer 50, a source 901, and a drain 902; wherein the gate 70, the semiconductor active layer 50, the source 901, and the drain 902, at least one of the pixel electrode 110 and the common electrode is prepared by the above method of preparing the thin film layer pattern 20.
- the gate electrode 70 may be formed by the above-described method of forming the thin film layer pattern 20, and/or the semiconductor active layer 50 may be formed, and/or the source electrode 901 and the drain electrode 902 may be formed, and/or Or forming the pixel electrode 110, and/or the common electrode.
- the thin film 20a is a transparent conductive film such as ITO, IZO or the like.
- An embodiment of the present invention provides a method for fabricating an array substrate for a display device.
- the method further includes: on the basis of the above S101-S118,
- a passivation layer 120 is formed on the substrate on which step S118 is completed.
- the mask 10-5 is placed such that the hollow portion 102-5 of the mask 10-5 (not shown in FIG. 5a) is on the base substrate 301.
- the projection is completely coincident with the projection of the common electrode to be formed on the base substrate 301.
- a common transparent conductive film 130a is formed by a sputtering method, wherein the first common transparent conductive film portion S1-5 formed in the hollow portion 102-5 and The second common transparent conductive film portion S2-5 formed on the mask body 101 is broken.
- the mask sheet 10-5 is peeled off on the substrate on which the step S121 is completed, and the first common transparent conductive film portion S1-5 is left on the substrate to form the common electrode 130.
- the method further includes forming a plurality of signal lines on the base substrate 301, wherein the at least one signal line is prepared by a method of preparing the thin film layer pattern 20.
- the signal lines include gate lines, data lines, common electrode lines, and the like.
- the gate line and the common electrode line may be formed using the same mask 10-2 as the gate 70, that is, the hollow portion 102-2 of the mask 10-2 may be lined.
- the projection of the base substrate 301 completely coincides with the projection of the gate line, the common electrode line, and the gate 70 to be formed on the base substrate 301.
- the data lines can be made with the source 901 and the drain 902
- the same mask 10 - 10 is formed, that is, the projection of the hollow portion 102-3 of the mask 10 on the substrate 301 and the data line and the source 901 and the drain 902 to be formed on the substrate 301 can be formed. The projections are completely coincident.
- the embodiment of the present invention further provides a method for fabricating another array substrate, comprising: forming a thin film transistor on the base substrate 301, and an electrode layer electrically connected to the drain 902 of the thin film transistor; the thin film transistor including the gate a pole 70, a gate insulating layer 60, a semiconductor active layer 50, a source 901, and a drain 902; wherein the gate 70, the semiconductor active layer 50, the source 901 and the drain 902, and At least one of the electrode layers electrically connected to the drain 902 is prepared by the above method of preparing the thin film layer pattern 20.
- the electrode layer is an anode layer or a cathode layer of a photodiode.
- the gate electrode 70 may be formed by the above-described method of forming the thin film layer pattern 20, and/or the semiconductor active layer 50 may be formed, and/or the source electrode 901 and the drain electrode 902 may be formed, and/or Or forming an electrode layer electrically connected to the drain 902.
- the thin film 20a is a transparent or opaque conductive film, for example, electrically connected to the drain 902 according to the method. Whether the electrode layer needs to be transparent depends on it, and will not be described here.
- the method further includes forming a plurality of signal lines on the base substrate 301, wherein the at least one signal line is prepared by a method of preparing the thin film layer pattern 20.
- the signal lines include gate lines, data lines, power lines, and the like.
- the gate line and the power line may be formed using the same mask 10-2 as the gate 70, that is, the hollow portion 102-2 of the mask 10-2 may be on the base substrate 301.
- the data line may be formed using the same mask 10-3 as the source 901 and the drain 902, that is, the hollow portion 102-3 of the mask 10-3 may be on the substrate.
- the projection of the substrate 301 completely coincides with the projection of the data line and the source 901 and the drain 902 to be formed on the substrate 301.
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- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
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Abstract
Description
Claims (14)
- 一种薄膜层图案的制备方法,包括:提供掩模板,所述掩模板包括掩模板本体和设置在所述掩模板本体上的镂空部分;将所述掩模板放置在基板上,使所述镂空部分在所述基板上的投影与待形成的薄膜层图案在所述基板上的投影重合;在放置有所述掩模板的基板上形成薄膜;其中,形成在所述镂空部分的第一薄膜部分和形成在所述掩模板本体上的第二薄膜部分断开;将所述掩模板剥离而在所述基板上保留所述第一薄膜部分以形成所述薄膜层图案。
- 根据权利要求1所述的制备方法,其中,在放置有所述掩模板的基板上,通过溅射方法形成所述薄膜。
- 根据权利要求1或2所述的制备方法,其中,所述掩模板为金属掩模板。
- 根据权利要求1至3中任一项所述的制备方法,其中,所述金属掩模板的厚度在720um~880um之间。
- 根据权利要求1至4中任一项所述的制备方法,其中,所述薄膜为非晶硅薄膜,所述方法还包括在将所述掩模板剥离之后对保留在所述衬底上的第一薄膜部分进行退火处理以使所述第一薄膜部分晶化。
- 一种薄膜晶体管的制备方法,包括:在基板上形成栅极、栅绝缘层、半导体有源层、源极和漏极;其中,所述栅极、所述半导体有源层、所述源极和漏极中的至少一个通过权利要求1至4任一项所述的方法制备形成。
- 根据权利要求6所述的制备方法,其中,所述半导体有源层的材料包括金属氧化物半导体或多晶硅。
- 一种阵列基板的制备方法,包括:在基板上形成薄膜晶体管以及与所述薄膜晶体管的漏极电连接的像素电极;所述薄膜晶体管包括栅极、栅绝缘层、半导体有源层、源极和漏极;其中,所述栅极、所述半导体有源层、所述源极和漏极以及所述像素电 极中的至少一个通过权利要求1至4任一项所述的方法制备形成。
- 根据权利要求8所述的制备方法,所述方法还包括:在基板上形成多条信号线;其中,所述至少一条信号线通过权利要求1至4任一项所述的方法制备形成。
- 一种阵列基板的制备方法,包括:在基板上形成薄膜晶体管、与所述薄膜晶体管的漏极电连接的像素电极、以及公共电极;所述薄膜晶体管包括栅极、栅绝缘层、半导体有源层、源极和漏极;其中,所述栅极、所述半导体有源层、所述源极和漏极、所述像素电极以及所述公共电极中的至少一个通过权利要求1至4任一项所述的方法制备形成。
- 根据权利要求8所述的制备方法,其中,所述方法还包括:在基板上形成多条信号线;其中,所述至少一条信号线通过权利要求1至4任一项所述的方法制备形成。
- 一种阵列基板的制备方法,包括:在基板上形成薄膜晶体管、与所述薄膜晶体管的漏极电连接的电极层;所述薄膜晶体管包括栅极、栅绝缘层、半导体有源层、源极和漏极;其中,所述栅极、所述半导体有源层、所述源极和漏极、以及与所述漏极电连接的所述电极层中的至少一个通过权利要求1至5任一项所述的方法制备形成。
- 根据权利要求12所述的制备方法,其中,所述方法还包括:在基板上形成多条信号线;其中,所述至少一条信号线通过权利要求1至4任一项所述的方法制备形成。
- 根据权利要求12或13所述的制备方法,其中,所述电极层为发光二极管的阳极或阴极。
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CN104658974A (zh) * | 2015-03-12 | 2015-05-27 | 京东方科技集团股份有限公司 | 一种薄膜层图案、薄膜晶体管及阵列基板的制备方法 |
CN105203825B (zh) * | 2015-08-31 | 2018-02-13 | 国家纳米科学中心 | 微测量电极的制作方法和热电势的测量方法及相关装置 |
CN106252418B (zh) * | 2016-09-22 | 2018-05-15 | 南京华东电子信息科技股份有限公司 | 一种薄膜晶体管 |
CN108389938B (zh) * | 2017-02-03 | 2021-01-26 | 山东浪潮华光光电子股份有限公司 | 一种GaAs基LED芯片的无光刻制备方法 |
CN108508521A (zh) * | 2018-03-30 | 2018-09-07 | 武汉华星光电技术有限公司 | 具有遮光层的偏振光栅及其制作方法、阵列基板、显示面板、显示模组及终端 |
CN113808952A (zh) * | 2021-08-13 | 2021-12-17 | 吉林建筑大学 | 一种薄膜晶体管及其制备方法 |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101409304A (zh) * | 2007-10-10 | 2009-04-15 | 株式会社日立显示器 | 有机el显示装置 |
CN103262656A (zh) * | 2010-12-28 | 2013-08-21 | 株式会社半导体能源研究所 | 发光单元、发光装置以及照明装置 |
CN103681942A (zh) * | 2012-08-31 | 2014-03-26 | 上海比亚迪有限公司 | 晶体硅se太阳电池片的制备方法以及晶体硅se太阳电池片 |
CN104658974A (zh) * | 2015-03-12 | 2015-05-27 | 京东方科技集团股份有限公司 | 一种薄膜层图案、薄膜晶体管及阵列基板的制备方法 |
Family Cites Families (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7126161B2 (en) * | 1998-10-13 | 2006-10-24 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device having El layer and sealing material |
US7531470B2 (en) * | 2005-09-27 | 2009-05-12 | Advantech Global, Ltd | Method and apparatus for electronic device manufacture using shadow masks |
US7601566B2 (en) * | 2005-10-18 | 2009-10-13 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and manufacturing method thereof |
US7736936B2 (en) * | 2006-08-29 | 2010-06-15 | Semiconductor Energy Laboratory Co., Ltd. | Method of forming display device that includes removing mask to form opening in insulating film |
US8221964B2 (en) * | 2007-11-20 | 2012-07-17 | Eastman Kodak Company | Integrated color mask |
CN101526683A (zh) * | 2008-03-07 | 2009-09-09 | 北京京东方光电科技有限公司 | Lcd基板的制造方法 |
US8658478B2 (en) * | 2010-09-23 | 2014-02-25 | Advantech Global, Ltd | Transistor structure for improved static control during formation of the transistor |
TWI480398B (zh) * | 2012-01-30 | 2015-04-11 | Innocom Tech Shenzhen Co Ltd | 陰影罩幕及其補償設計方法 |
WO2014121469A1 (zh) * | 2013-02-06 | 2014-08-14 | 深圳市柔宇科技有限公司 | 一种薄膜晶体管及其像素单元的制造方法 |
WO2015009768A1 (en) * | 2013-07-15 | 2015-01-22 | Polyera Corporation | Photopatternable materials and related electronic devices and methods |
CN104037063A (zh) * | 2014-06-13 | 2014-09-10 | 京东方科技集团股份有限公司 | 一种薄膜图形化方法和薄膜图形化装置 |
KR102308621B1 (ko) * | 2014-07-15 | 2021-10-05 | 삼성디스플레이 주식회사 | 박막 트랜지스터 표시판 및 그 제조 방법 |
KR102550322B1 (ko) * | 2016-03-22 | 2023-07-03 | 삼성디스플레이 주식회사 | 표시 장치 및 그 제조 방법 |
-
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- 2015-03-12 CN CN201510108889.XA patent/CN104658974A/zh active Pending
-
2016
- 2016-02-23 US US15/308,229 patent/US20170053954A1/en not_active Abandoned
- 2016-02-23 WO PCT/CN2016/074360 patent/WO2016141805A1/zh active Application Filing
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101409304A (zh) * | 2007-10-10 | 2009-04-15 | 株式会社日立显示器 | 有机el显示装置 |
CN103262656A (zh) * | 2010-12-28 | 2013-08-21 | 株式会社半导体能源研究所 | 发光单元、发光装置以及照明装置 |
CN103681942A (zh) * | 2012-08-31 | 2014-03-26 | 上海比亚迪有限公司 | 晶体硅se太阳电池片的制备方法以及晶体硅se太阳电池片 |
CN104658974A (zh) * | 2015-03-12 | 2015-05-27 | 京东方科技集团股份有限公司 | 一种薄膜层图案、薄膜晶体管及阵列基板的制备方法 |
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