WO2016141786A1 - 场效应晶体管的制作方法 - Google Patents

场效应晶体管的制作方法 Download PDF

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Publication number
WO2016141786A1
WO2016141786A1 PCT/CN2016/072516 CN2016072516W WO2016141786A1 WO 2016141786 A1 WO2016141786 A1 WO 2016141786A1 CN 2016072516 W CN2016072516 W CN 2016072516W WO 2016141786 A1 WO2016141786 A1 WO 2016141786A1
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Prior art keywords
gate oxide
oxide layer
substrate
polysilicon
region
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French (fr)
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金炎
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CSMC Technologies Fab1 Co Ltd
CSMC Technologies Fab2 Co Ltd
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CSMC Technologies Fab1 Co Ltd
CSMC Technologies Fab2 Co Ltd
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/601—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs 
    • H10D30/603—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs  having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended drain IGFETs [EDMOS]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0221—Manufacture or treatment of FETs having insulated gates [IGFET] having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended-drain MOSFETs [EDMOS]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/011—Manufacture or treatment of electrodes ohmically coupled to a semiconductor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H10D64/311—Gate electrodes for field-effect devices
    • H10D64/411—Gate electrodes for field-effect devices for FETs
    • H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
    • H10D64/514—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the insulating layers
    • H10D64/516—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the insulating layers the thicknesses being non-uniform
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P30/00—Ion implantation into wafers, substrates or parts of devices
    • H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
    • H10P30/22—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping using masks

Definitions

  • the present invention relates to the field of semiconductor device technologies, and in particular, to a method of fabricating a field effect transistor.
  • the conventional effect transistor In the application of semiconductor devices, there is an effect transistor that requires the drain terminal of the device to carry a relatively high voltage, such as an acoustic power amplifier device. In this type of application, only the drain terminal needs to carry a higher voltage, and the gate terminal only needs to carry a general low voltage, and the source terminal is usually grounded. Therefore, the conventional effect transistor usually has a silicide blocking layer structure (SAB, Self-aligned) between the gate terminal and the drain terminal. Silicide block The formation of a buffer region to reduce the electric field before the drain gate improves the withstand voltage of the drain terminal, resulting in an excessive area of the device, and an additional silicide blocking layer process also makes the production cost high.
  • SAB silicide blocking layer structure
  • the conventional process is performed after the polysilicon etching is performed, and then the impurity implantation is performed to form the source well region, and the etched polysilicon residue blocks the impurity implantation, so that the impurity is implanted into the source well region.
  • the distribution differs greatly from the distribution that is desired to be achieved, thereby affecting device performance.
  • the channel length of the effect transistor is formed by forming a drain drift region (for example, an N-drift region) and two photolithography forming a gate-end polysilicon structure. Due to the deviation of the size and alignment of the two lithography, it is easy to cause a deviation in the channel length, resulting in a variation in device performance.
  • a drain drift region for example, an N-drift region
  • two photolithography forming a gate-end polysilicon structure. Due to the deviation of the size and alignment of the two lithography, it is easy to cause a deviation in the channel length, resulting in a variation in device performance.
  • a method of fabricating a field effect transistor comprising:
  • the gate oxide layer including a first gate oxide layer and a second gate oxide layer juxtaposed on the substrate, the second gate oxide layer having a thickness smaller than the first The thickness of a gate oxide layer;
  • the second gate oxide layer is adjacent to the source end region, and the first gate oxide layer is adjacent to the drain end region.
  • a gate oxide layer is formed by a double gate oxide process, and the gate oxide layer is divided into a second gate oxide layer slightly thinner toward the source end side and a slightly thicker first gate oxide layer near the drain terminal side.
  • the thicker thickness of the drain and gate oxides can reduce the electric field between the drain gates and improve the withstand voltage of the device. Therefore, with this structure, the silicide blocking layer structure (SAB) between the drain gates can be omitted to reduce the device size.
  • 1 is a schematic structural view of a conventional field effect transistor
  • FIG. 2 is a schematic structural view of forming a source well region according to an embodiment
  • FIG. 3 is a schematic structural view of a device after forming a side of a gate-end polysilicon structure close to a source end according to an embodiment
  • FIG. 4 is a schematic view showing the structure of a gate-side polysilicon structure formed by applying a photoresist on an embodiment
  • FIG. 5 is a schematic structural view of forming a gate-end polysilicon structure after removing a photoresist according to an embodiment
  • Figure 6 is a block diagram showing the structure of a field effect transistor of an embodiment.
  • the vocabulary of the semiconductor field cited herein is a technical vocabulary commonly used by those skilled in the art.
  • the P+ type is simply a P-type representing a heavily doped concentration.
  • the P-type represents a lightly doped concentration of the P type
  • the N+ type represents a heavily doped concentration of the N type
  • the N-type represents a lightly doped concentration of the N type.
  • 1 is a flow chart of a method of fabricating a field effect transistor of an embodiment.
  • Step S110 providing the substrate 100.
  • the material of the substrate 100 is silicon, silicon carbide, gallium arsenide, indium phosphide or germanium silicon.
  • Substrate 100 can be a silicon or silicon-containing P-type substrate, such as a single layer silicon substrate including a silicon wafer, or a substrate including other multilayer structures and a silicon layer.
  • a drain drift region 122 and a shallow trench isolation structure 600 are then formed over the substrate 100.
  • the drain drift region 122 is an N-drift region.
  • Shallow trench isolation structure (STI, shallow Trench Isolation 600 is a field oxide layer which may comprise an oxide of silicon, such as silicon dioxide.
  • the shallow trench isolation structure 600 is mainly used to separate the source structure and the drain structure.
  • the shallow trench isolation structure is the mainstream isolation process below 0.18um.
  • drain drift region 122 and the shallow trench isolation structure 600 are formed, the following steps are performed.
  • Step S120 forming a gate oxide layer on the substrate 100.
  • the material of the gate oxide layer is silicon dioxide.
  • the gate oxide layer includes a first gate oxide layer 210 and a second gate oxide layer 220 juxtaposed on the substrate 100, and the thickness of the second gate oxide layer 220 is smaller than the thickness of the first gate oxide layer 210.
  • the second gate oxide layer 220 is adjacent to the source end region 110
  • the first gate oxide layer 210 is adjacent to the drain end region 120 .
  • the thickness of the second gate oxide layer 220 is between 60 and 600 angstroms
  • the thickness of the first gate oxide layer 210 is between 500 angstroms and 1200 angstroms.
  • the thickness and the boundary position of each of the second gate oxide layer 220 and the first gate oxide layer 210 are determined by the gate drain operating voltage.
  • first gate oxide layer 210 When the gate oxide layer is formed, a slightly thick oxide layer (first gate oxide layer 210) may be first deposited on the substrate 100, and then a portion of the slightly thick oxide layer is etched and then etched. A slightly thin oxide layer (second gate oxide layer 220) is deposited over the substrate 100 of the oxide layer.
  • the gate oxide layer is formed by using a double gate oxide process, and the gate oxide layer is divided into a second gate oxide layer 220 slightly thinner toward the source end side and a first gate oxide layer 210 slightly thicker near the drain end side, thicker thickness
  • the drain gate oxide layer can reduce the electric field between the drain gates and improve the withstand voltage capability of the drain terminal of the device. Therefore, this structure can omit the silicide blocking layer structure (SAB) between the drain gates to reduce the device size, and can reduce the production process and reduce the production cost.
  • SAB silicide blocking layer structure
  • the impurity implantation in the source well region is performed before the polysilicon etching, which can effectively avoid the problem that the distribution of the source well regions in the conventional manufacturing process is largely different.
  • the formation of the gate oxide layer is followed by the following steps.
  • Step S130 forming a polysilicon layer 300 on the gate oxide layer.
  • a polysilicon layer 300 is formed on the gate oxide layer by a deposition process. Since the gate oxide layer includes the second gate oxide layer 220 and the first gate oxide layer 210 having different thicknesses, the upper surface of the polysilicon layer 300 may not be flattened, and thus may be planarized by a planarization process. Of course, it is also possible not to pass the planarization process.
  • Step S140 forming a photoresist 400 on the polysilicon layer 300.
  • a layer of photoresist 400 is applied over the polysilicon layer 300.
  • the photoresist 400 is a photoresist used for impurity implantation of the source well region 112 (P well).
  • Step S150 exposing and developing the photoresist 400 to form an exposed region to expose a portion of the polysilicon layer 300. This step mainly exposes and develops the area where the source structure needs to be formed.
  • step S160 follows.
  • Step S160 performing impurity implantation on the polysilicon layer 300 located in the exposed region at an implantation angle of 45 to 83 with respect to the surface of the substrate 100 to form a source well region 112 on the substrate 100.
  • FIG. 2 is a schematic view showing the structure of forming a source well region in an embodiment.
  • Step S170 etching one side of the polysilicon layer 300 to form a portion of the gate end polysilicon structure 310.
  • the gate-side polysilicon structure is formed on the side close to the source end and the impurity implantation in the source-well region uses the same photolithography (same photoresist).
  • the length of the device channel L is determined by the implantation energy and angle to achieve the adjustment of the longer channel L.
  • a wide range of implant depths can be achieved with different thicknesses of photoresist, and the entire module process is relatively clean. This process is easier to achieve precise control than traditional non-self-aligned implant processes.
  • FIG. 3 is a schematic view showing the structure of a device after forming a side of a gate-end polysilicon structure close to a source end according to an embodiment.
  • Step S180 removing the photoresist 400. After etching the side 311 of the gate polysilicon structure 310 close to the source end, the photoresist 400 can be removed.
  • Step S190 etching the (remaining) polysilicon layer 300 to form a gate-end polysilicon structure 310.
  • the lithography of this step etches the other side of the polysilicon layer 300 using another photoresist 500, a photoresist 500 for etching the polysilicon gate (gate-side polysilicon structure 310).
  • FIG. 4 is a schematic structural view of a gate-side polysilicon structure formed by applying a photoresist
  • FIG. 5 is a schematic structural view of forming a gate-end polysilicon structure after removing the photoresist.
  • Step S200 doping is performed on the substrate 100 to form the source end region 110 and the drain end region 120 (see FIG. 6).
  • the heavily doped drain regions (N+ and P+) and the source regions (N+) are formed, for example, by performing a source-drain implantation process.
  • the source well region 112 is on the lower side of the source end region 110, and the drain drift region 122 is located on the lower side of the drain end region 120.
  • the drain drift region 122 is connected to the source well region 112, and is located below the second gate oxide layer 220, that is, the drain drift region 122 and the source well region 112 are below the second gate oxide layer 220. Pick up.
  • the drain drift region 122 occupies the surface layer of the substrate 100 under the first gate oxide layer 210 and extends to the surface layer of the substrate 100 under the second gate oxide layer 220.
  • the drain drift region 122 and the source well region 112 do not necessarily need to be connected, and some space may be left to increase the breakdown voltage.
  • FIG. 6 is a schematic view showing the structure of a device of a field effect transistor according to an embodiment.
  • the structure formed by the above-described method of fabricating the field effect transistor omits the silicide blocking layer structure (SAB) between the drain gates.
  • SAB silicide blocking layer structure
  • a gate oxide layer is formed by a double gate oxide process, and the gate oxide layer is divided into a second gate oxide layer slightly thinner toward the source end side and a slightly thicker first gate oxide layer near the drain terminal side.
  • the thicker thickness of the drain and gate oxides can reduce the electric field between the drain gates and improve the withstand voltage of the device. Therefore, with this structure, the silicide blocking layer structure (SAB) between the drain gates can be omitted to reduce the device size. And it can reduce production processes and reduce production costs.
  • the impurity implantation in the source well region is performed before the polysilicon etching, which can effectively avoid the problem that the distribution of the source well regions in the conventional manufacturing process is largely different.
  • a large-angle impurity implantation (45°-83° implantation angle) of the source well region is performed by a self-aligned process, and the gate-side polysilicon structure is formed on the side close to the source terminal and the impurity implantation in the source-well region is used the same time.
  • Lithography standard photoresist
  • the channel length of the device is determined by the implantation energy and angle to achieve longer channel adjustment; a wide range of implant depth can be achieved with different thicknesses of photoresist; and the entire module process is relatively clean. It is easier to achieve precise control than traditional non-self-aligned injection processes.
  • the above-mentioned method of fabricating the field effect transistor describes only some main steps, and does not represent all the steps of manufacturing the field effect transistor.
  • the illustrations in Figures 2-6 are also simple examples of some of the main structures of field effect transistors and do not represent the overall structure of the field effect transistors.
  • the field effect transistor described above is an N-type field effect transistor, and may be a P-type field effect transistor in other embodiments.

Landscapes

  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

一种场效应晶体管的制作方法，包括：（S110）提供衬底(100)；（S120）在所述衬底(100)上形成栅氧化层；（S130）在所述栅氧化层上形成多晶硅层(300)；（S140）在所述多晶硅层(300)上形成光刻胶(400)；（S150）对所述光刻胶(400)进行曝光和显影形成暴露区域，以暴露部分多晶硅层(300)；（S160）沿与所述衬底(100)表面呈45°-83°的注入角度对位于所述暴露区域的所述部分多晶硅层(300)进行杂质注入，以在所述衬底(100)上形成源端阱区(112)；（S170）对所述多晶硅层(300)一侧进行刻蚀，以形成部分栅端多晶硅结构(310)；（S180）去除所述光刻胶(400)；（S190）对所述多晶硅层(300)的另一侧进行刻蚀形成栅端多晶硅结构(310)；以及（S200）在所述衬底(100)上进行掺杂形成源端区域(110)和漏端区域(120)。

Description

场效应晶体管的制作方法
【技术领域】
本发明涉及半导体器件技术领域，特别涉及一种场效应晶体管的制作方法。
【背景技术】
在半导体器件的应用中，有一种效应晶体管需要器件的漏端能够承载比较高的电压，例如音响功率放大器件等。在这一类的应用中，只需要漏端承载较高的电压，栅端只要承载一般的低电压，而源端通常是接地。因此，传统效应晶体管通常在栅端和漏端之间设置有硅化物阻挡层结构（SAB，Self-aligned silicide block layer）形成缓冲区域以降低漏栅之前的电场来提高漏端的耐压，导致这种器件面积过大，额外的硅化物阻挡层工艺也使生产成本也较高。而且，在制造效应晶体管时，传统工艺是在进行多晶硅刻蚀后，再进行杂质注入形成源端阱区时，刻蚀后的多晶硅残留会阻挡杂质的注入，使得杂质注入源端阱区的实际分布与所希望实现的分布相差较大，从而影响器件性能。
另外，在传统工艺中，效应晶体管的沟道长度由形成漏端漂移区（例如N-漂移区）和形成栅端多晶硅结构的两次光刻后形成。由于两次光刻在尺寸及对位上的偏差，容易导致沟道长度上的偏差，以致造成器件性能上的偏差。
【发明内容】
有鉴于此，有必要提供一种漏端耐压能力较高的场效应晶体管的制作方法。
一种场效应晶体管的制作方法，包括：
提供衬底；
在所述衬底上形成栅氧化层，所述栅氧化层包括并列在所述衬底上的第一栅氧化层和第二栅氧化层，所述第二栅氧化层的厚度小于所述第一栅氧化层的厚度；
在所述栅氧化层上形成多晶硅层；
在所述多晶硅层上形成光刻胶；
对所述光刻胶进行曝光和显影形成暴露区域，以暴露部分多晶硅层；
沿与所述衬底表面呈45°-83°的注入角度对位于所述暴露区域的所述部分多晶硅层进行杂质注入，以在所述衬底上形成源端阱区；
对所述多晶硅层的一侧进行刻蚀，以形成部分栅端多晶硅结构；
去除所述光刻胶；
对所述多晶硅层的另一侧进行刻蚀，以形成栅端多晶硅结构；以及
在所述衬底上进行掺杂形成源端区域和漏端区域；
其中，所述第二栅氧化层靠近所述源端区域，所述第一栅氧化层靠近所述漏端区域。
上述场效应晶体管的制作方法，通过利用双栅氧工艺制作栅氧化层，栅氧化层分为靠近源端一侧稍薄的第二栅氧化层和靠近漏端一侧稍厚的第一栅氧化层，漏端栅氧较厚的厚度可以降低漏栅之间的电场，提高器件漏端的耐压能力。因此利用此结构，可以省略掉漏栅之间的硅化物阻挡层结构（SAB）以减小器件尺寸。
【附图说明】
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他实施例的附图。
图1是一种传统场效应晶体管的结构示意图；
图2是一实施例的形成源端阱区的结构示意图；
图3是一实施例的形成栅端多晶硅结构靠近源端的一侧后的器件结构示意图；
图4是一实施例的涂抹上光刻胶形成栅端多晶硅结构的结构示意图；
图5是一实施例的去除光刻胶后形成栅端多晶硅结构的结构示意图；以及
图6是一实施例的场效应晶体管的器件结构示意图。
【具体实施方式】
为了便于理解本发明，下面将参照相关附图对本发明进行更全面的描述。附图中给出了本发明的较佳实施例。但是，本发明可以以许多不同的形式来实现，并不限于本文所描述的实施例。相反地，提供这些实施例的目的是使对本发明的公开内容的理解更加透彻全面。
需要说明的是，当元件被称为“固定于”另一个元件，它可以直接在另一个元件上或者也可以存在居中的元件。当一个元件被认为是“连接”另一个元件，它可以是直接连接到另一个元件或者可能同时存在居中元件。
除非另有定义，本文所使用的所有的技术和科学术语与属于本发明的技术领域的技术人员通常理解的含义相同。本文中在本发明的说明书中所使用的术语只是为了描述具体的实施例的目的，不是旨在于限制本发明。本文所使用的术语“及／或”包括一个或多个相关的所列项目的任意的和所有的组合。
本文所引用的半导体领域词汇为本领域技术人员常用的技术词汇，例如对于P型和N型杂质，为区分掺杂浓度，简易的将P+型代表重掺杂浓度的P型， P-型代表轻掺杂浓度的P型，N+型代表重掺杂浓度的N型， N-型代表轻掺杂浓度的N型。
下面结合附图，对本发明的具体实施方式进行详细描述。
图1是一实施例的场效应晶体管的制作方法的流程图。
一种场效应晶体管的制作方法，包括步骤：
步骤S110：提供衬底100。衬底100的材料为硅、碳化硅、砷化镓、磷化铟或锗硅。衬底100可为硅或含硅的P型衬底，例如包括硅晶圆的单层硅衬底，或者包括其他多层结构和硅层的衬底。
然后在衬底100上形成漏端漂移区122和浅沟槽隔离结构600。漏端漂移区122为N-漂移区。浅沟槽隔离结构（STI，shallow trench isolation）600即场氧化层，可以包含硅的氧化物，例如可以是二氧化硅。浅沟槽隔离结构600主要用于分隔源极结构和漏极结构。浅沟槽隔离结构为现今0.18um以下的主流隔离工艺。
漏端漂移区122和浅沟槽隔离结构600形成完成后，接着以下步骤。
步骤S120：在衬底100上形成栅氧化层。栅氧化层的材料为二氧化硅。栅氧化层包括并列在衬底100上的第一栅氧化层210和第二栅氧化层220，第二栅氧化层220的厚度小于第一栅氧化层210的厚度。其中，第二栅氧化层220靠近源端区域110，第一栅氧化层210靠近漏端区域120。第二栅氧化层220的厚度在60-600埃之间，第一栅氧化层210的厚度在500埃-1200埃之间。第二栅氧化层220和第一栅氧化层210各自的厚度及分界位置由栅漏工作电压决定。
在形成栅氧化层时，可以首先在衬底100上淀积一层稍厚的氧化层（第一栅氧化层210），然后再刻蚀去稍厚的氧化层的一部分，再在刻蚀了氧化层的衬底100上淀积一层稍薄的氧化层（第二栅氧化层220）。
通过利用双栅氧工艺制作栅氧化层，栅氧化层分为靠近源端一侧稍薄的第二栅氧化层220和靠近漏端一侧稍厚的第一栅氧化层210，较厚厚度的漏端栅氧化层可以降低漏栅之间的电场，提高器件漏端的耐压能力。因此，此结构可以省略掉漏栅之间的硅化物阻挡层结构（SAB），以减小器件尺寸，而且可以减少生产流程，降低生产成本。在多晶硅刻蚀之前就进行源端阱区的杂质注入，可以有效避免传统制造工艺中源端阱区的分布相差较大的问题。
栅氧化层形成后接着以下步骤。
步骤S130：在栅氧化层上形成多晶硅层300。采用淀积工艺在栅氧化层形成一层多晶硅层300。由于栅氧化层包括厚薄不一的第二栅氧化层220和第一栅氧化层210，因而可能会造成多晶硅层300的上表面也并不平整，因而可以通过平坦化工艺使其平整。当然，也可以不通过平坦化工艺。
步骤S140：在多晶硅层300上形成光刻胶400。在多晶硅层300上涂覆一层光刻胶400。光刻胶400为对源端阱区112（P阱）进行杂质注入所用到的光刻胶。
步骤S150：对光刻胶400进行曝光和显影形成暴露区域，以暴露部分多晶硅层300。此步骤主要对需要形成源极结构区域进行曝光和显影。
显影后，接着步骤S160。
步骤S160：沿与衬底100表面呈45°-83°的注入角度对位于所述暴露区域的多晶硅层300进行杂质注入以在衬底100上形成源端阱区112。
图2是一实施例的形成源端阱区的结构示意图。
步骤S170：对多晶硅层300的一侧进行刻蚀，以形成部分栅端多晶硅结构310。栅端多晶硅结构靠近源端的一侧形成和源端阱区的杂质注入使用同一次光刻（同一光刻胶），器件沟道L长度由注入能量及角度决定，实现更长沟道L的调节；采用不同厚度的光刻胶可以实现宽范围的注入深度，并且整个模块工艺比较干净。和传统非自对准注入工艺相比，本工艺更容易实现精确控制。
图3是一实施例的形成栅端多晶硅结构靠近源端的一侧后的器件结构示意图。
步骤S180：去除光刻胶400。刻蚀完栅端多晶硅结构310靠近源端的一侧311后，就可以将光刻胶400去除。
步骤S190：对（剩余的）多晶硅层300进行刻蚀，以形成栅端多晶硅结构310。此步骤的光刻采用另一光刻胶500，即用于刻蚀多晶硅栅极（栅端多晶硅结构310）的光刻胶500，对多晶硅层300的另一侧进行刻蚀。
图4是涂抹上光刻胶形成栅端多晶硅结构的结构示意图，图5是一实施例的去除光刻胶后形成栅端多晶硅结构的结构示意图。
步骤S200：在衬底100上进行掺杂形成源端区域110和漏端区域120(请参见图6)。例如通过进行源漏注入工艺，形成重掺杂的漏极区（N+和P+）和源极区（N+）。源端阱区112处于源端区域110下侧，漏端漂移区122位于漏端区域120下侧。漏端漂移区122和源端阱区112相接，相接之处位于第二栅氧化层220之下，即漏端漂移区122和源端阱区112在第二栅氧化层220之下相接。也即漏端漂移区122占据位于第一栅氧化层210下的衬底100表层，并延伸至位于第二栅氧化层220之下的衬底100表层。当然，在其他实施例中，漏端漂移区122与源端阱区112不一定需要相接，也可以留一些空间，以提高击穿电压。
图6是一实施例的场效应晶体管的器件结构示意图，由图可以看出，利用上述场效应晶体管的制作方法形成的此结构省略掉漏栅之间的硅化物阻挡层结构（SAB），因此可以减小器件尺寸，而且可以减少生产流程，降低生产成本。
上述场效应晶体管的制作方法，通过利用双栅氧工艺制作栅氧化层，栅氧化层分为靠近源端一侧稍薄的第二栅氧化层和靠近漏端一侧稍厚的第一栅氧化层，漏端栅氧较厚的厚度可以降低漏栅之间的电场，提高器件漏端的耐压能力。因此利用此结构，可以省略掉漏栅之间的硅化物阻挡层结构（SAB）以减小器件尺寸。而且可以减少生产流程，降低生产成本。在多晶硅刻蚀之前就进行源端阱区的杂质注入，可以有效避免传统制造工艺中源端阱区的分布相差较大的问题。
另外，利用自对准工艺进行源端阱区的大角度的杂质注入（45°-83°的注入角度），栅端多晶硅结构靠近源端的一侧形成和源端阱区的杂质注入使用同一次光刻（同一光刻胶），器件沟道长度由注入能量及角度决定，实现更长沟道的调节；采用不同厚度的光刻胶可以实现宽范围的注入深度；并且整个模块工艺比较干净。和传统非自对准注入工艺相比，更容易实现精确控制。
可以理解，上述场效应晶体管的制作方法，仅描述一些主要步骤，并不代表制造场效应晶体管的所有步骤。图2-图6中的图示也是对场效应晶体管的一些主要结构的简单示例，并不代表场效应晶体管的全部结构。上述场效应晶体管为N型场效应晶体管，在其他实施例中还可以是P型场效应晶体管。
以上所述实施例仅表达了本发明的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对本发明专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本发明构思的前提下，还可以做出若干变形和改进，这些都属于本发明的保护范围。因此，本发明专利的保护范围应以所附权利要求为准。

Claims (8)

  1. 一种场效应晶体管的制作方法，其特征在于，包括：
    提供衬底；
    在所述衬底上形成栅氧化层，所述栅氧化层包括并列在所述衬底上的第一栅氧化层和第二栅氧化层，所述第二栅氧化层的厚度小于所述第一栅氧化层的厚度；
    在所述栅氧化层上形成多晶硅层；
    在所述多晶硅层上形成光刻胶；
    对所述光刻胶进行曝光和显影，形成暴露区域，以暴露部分多晶硅层；
    沿与所述衬底表面呈45°-83°的注入角度对位于所述暴露区域的所述部分多晶硅层进行杂质注入，以在所述衬底上形成源端阱区；
    对所述多晶硅层的一侧进行刻蚀，以形成部分栅端多晶硅结构；
    去除所述光刻胶；
    对所述多晶硅层的另一侧进行刻蚀，以形成栅端多晶硅结构；以及
    在所述衬底上进行掺杂形成源端区域和漏端区域；
    其中，所述第二栅氧化层靠近所述源端区域，所述第一栅氧化层靠近所述漏端区域。
  2. 根据权利要求1所述的方法，其特征在于，在所述衬底上形成栅氧化层之前，所述方法还包括：
    在所述衬底上形成漏端漂移区；以及
    在所述衬底上形成浅沟槽隔离结构。
  3. 根据权利要求2所述的方法，其特征在于，所述漏端漂移区为N-漂移区，所述源端阱区为P阱。
  4. 根据权利要求2所述的方法，其特征在于，所述浅沟槽隔离结构由硅的氧化物制成。
  5. 根据权利要求2所述方法，其特征在于，所述漏端漂移区和所述源端阱区在所述第二栅氧化层之下相接。
  6. 根据权利要求1-5所述的场效应晶体管的制作方法，其特征在于，所述衬底的材料为硅、碳化硅、砷化镓、磷化铟或锗硅。
  7. 根据权利要求1所述制作方法，其特征在于，在所述栅氧化层上形成多晶硅层的步骤为：采用淀积工艺在所述栅氧化层形成多晶硅层并通过平坦化工艺使所述多晶硅层平整。
  8. 根据权利要求1所述制作方法，其特征在于，所述衬底为硅或含硅的P型衬底。
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