CN103579344A - 低阈值电压金属氧化物半导体 - Google Patents

低阈值电压金属氧化物半导体 Download PDF

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CN103579344A
CN103579344A CN201310301246.8A CN201310301246A CN103579344A CN 103579344 A CN103579344 A CN 103579344A CN 201310301246 A CN201310301246 A CN 201310301246A CN 103579344 A CN103579344 A CN 103579344A
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伊藤明
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Avago Technologies General IP Singapore Pte Ltd
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Abstract

本公开提供了一种低阈值电压金属氧化物半导体，该半导体器件包括：源区，被布置于半导体衬底；漏区，被布置于半导体衬底；栅区，被布置到半导体衬底上，并位于源区和漏区之间。半导体器件还包括：栅氧区，被布置到半导体衬底上，与栅区接触；以及阱区，被植入到半导体衬底上并位于栅区和栅氧区下面。栅氧区具有与阱区接触的下外沿部分。

Description

低阈值电压金属氧化物半导体
技术领域
本公开大体上涉及金属氧化物半导体场效应晶体管（MOSFET）。更具体地，涉及一种低阈值电压分栅高性能横向扩散的金属氧化物半导体（LDMOS）。
背景技术
硅半导体工艺具有用于制造集成电路的高级复杂的操作。随着制造处理技术的不断进步，集成电路的核心和IO工作电压已被减小。然而，辅助装置的工作电压仍没有变化。辅助装置包括用于与集成电路结合的装置。例如，辅助装置可为任何与集成电路耦接的装置，如打印机、扫描仪、磁盘驱动器、磁带驱动器、麦克风、扬声器，或是照相机。
集成电路可包括：互相连接的有源和无源元件的阵列，举例而言，通过连续的一系列兼容处理集成或沉积在衬底上的晶体管、电阻器、电容器、导体。辅助装置可以在比包含在集成电路中的晶体管的击穿电压高的电压下工作。随着施加在晶体管上的工作电压的增加，该晶体管会最终被击穿而导致无法控制的电流的增加。击穿电压是该无法控制的电流的增加发生时的电压电平。击穿的示例可包括例如穿通、雪崩击穿、以及栅氧击穿。长时间工作在击穿电压以上减少晶体管的寿命。
发明内容
根据本公开的一个实施方式，提供一种半导体器件，包括：源区，被布置于半导体衬底；漏区，被布置于半导体衬底；栅区，被布置到半导体衬底上，并且位于源区和漏区之间；栅氧区，被布置在半导体衬底上并与栅区接触；以及阱区，被植入到半导体衬底上并位于栅区和栅氧区的下面，其中，栅氧区具有与阱区接触的下外沿部分。
根据本公开实施方式的一个方面，阱区包括第一阱和第二阱，第一阱和第二阱被植入不同材料。
根据本公开实施方式的一个方面，栅氧区在第一阱与第二阱之间具有在衬底区之上的低内部部分。
根据本公开实施方式的一个方面，源区、漏区、以及栅区被植入n型材料。
根据本公开实施方式的一个方面，源区、漏区、以及栅区被植入p型材料。
根据本公开实施方式的一个方面，栅氧区包括具有第一厚度的第一部分和具有第二厚度的第二部分，第一厚度基本上大于第二厚度。
根据本公开实施方式的一个方面，阱区包括具有第一长度的第一阱，第一阱与第一部分接触。
根据本公开实施方式的一个方面，阱区还包括第二阱，第二阱具有比第一长度更短的第二长度。
根据本公开的另一种实施方式，提供一种半导体器件，包括：源区，被布置于半导体衬底；漏区，被布置于半导体衬底；栅区，被布置到半导体衬底上，并且位于源区与漏区之间；栅氧区，被布置到半导体衬底上与栅区接触；第一阱，被植入到半导体衬底上并与栅氧区接触，第一阱具有第一高度，以及第二阱，被植入到位于浅槽隔离（STI）区下面的半导体衬底上，第二阱具有第二高度，其中，第一高度比第二高度更大。
根据本公开实施方式的一个方面，第二阱基本上在浅槽隔离区以下。
根据本公开实施方式的一个方面，第一阱和第二阱之间有衬底区，衬底区在栅氧区和包植入层以下延伸，该包植入层与浅槽隔离区接触。
根据本公开实施方式的一个方面，所述半导体器件还包括：第三阱，与第一阱接触。
根据本公开实施方式的一个方面，衬底具有比第二高度更大的深度。
根据本公开实施方式的一个方面，衬底区具有与第一高度基本上相等的深度。
根据本公开实施方式的一个方面，第一阱具有第一长度，第二阱具有第二长度，并且其中，第一长度大于第二长度。
根据本公开实施方式的一个方面，第三阱具有第三长度，并且其中，第三长度大于第二长度。
根据本公开的又一实施方式，提供了一种半导体器件，包括：源区，被布置于半导体衬底；漏区，被布置于半导体衬底；栅区，被布置到半导体衬底上，并且位于源区与漏区之间；栅氧区，被布置在半导体衬底上，与栅区接触；第一阱，被植入到半导体衬底上并与栅氧区接触，第一阱具有第一长度；第二阱，被植入到位于第一浅槽隔离（STI）区下面的半导体衬底上，第二阱具有第二长度；以及第三阱，被植入到位于第二浅槽隔离区下面的半导体衬底上，第三阱具有第三长度，其中，衬底区形成于第一阱和第二阱之间。
根据本公开实施方式的一个方面，半导体器件还包括位于第一阱、第二阱、和第三阱下面的深阱。
根据本公开实施方式的一个方面，第一阱被植入p型材料，第二阱、第三阱以及深阱被植入n型材料。
根据本公开实施方式的一个方面，第一阱被植入n型材料，第二阱、第三阱以及深阱被植入p型材料。
附图说明
本公开的方法与装置可以参考以下附图和说明而被更好地理解。在附图中，相同的附图标记标示在不同的视图之间的对应的部分。
图1示出了根据第一示例性实施方式的低阈值电压LDMOS的第一截面图。
图2示出了根据第二示例性实施方式的低阈值电压LDMOS的第二截面图。
图3示出了根据第三示例性实施方式的低阈值电压LDMOS的第三截面图。
图4示出了根据第四示例性实施方式的低阈值电压LDMOS的第四截面图。
图5示出了根据第五示例性实施方式的低阈值电压LDMOS的第五截面图。
图6示出了根据第六示例性实施方式的低阈值电压LDMOS的第六截面图。
具体实施方式
在传统的LDMOS中，阈值电压高并且没有太多的峰值储备来设计高性能电路。因此，期望有更高性能、高电压和低阈值的LDMOS而无需额外掩模（mask）或加工成本。
以下描述涉及一个半导体器件例如LDMOS。该半导体器件包括以下：源区，被布置于半导体衬底；漏区，被布置于半导体衬底；栅区，被布置到半导体衬底上并位于源区和漏区之间；栅氧区，被布置到半导体衬底上，与栅区相接触；阱区，被植入到半导体衬底上，并位于栅区和栅氧区下。栅氧区具有与阱区相接触的下外沿部分。
图1示出了根据第一示例性实施方式的低阈值电压LDMOS10的第一截面图。LDMOS10形成到一种导电性类型的衬底上。例如，LDMOS10可以是形成在包括p型材料的衬底中的n型LDMOS结构。p型材料可包括接收体类型的杂质原子，该杂质原子能够接收电子，例如但不限于，硼或铝。
具有与衬底基本相反导电性的第一重掺杂区域表征源区105a，该源区被布置于LDMOS10的半导体衬底。例如，源区105a可被布置在包括p型材料的半导体衬底内。
具有与衬底基本相反导电性的第二重掺杂区域表征LDMOS结构10的漏区105b。例如，源区105a和漏区105b可被植入N+材料以分别形成对应于源区105a的第一N+区域和对应于漏区105b的第二N+区域。“+”表示了该区域被植入了比没有被“+”指定的区域更高的载流子浓度。例如，N+区域通常具有比n类型区域更多数量的过剩载流子。P+区域一般地具有比p型衬底更多数量的过剩载流子孔。n型材料可包括供体类型的杂质原子，该杂质原子能够提供电子，举例而言，例如但不限于，磷、砷或锑。
具有与衬底基本相反导电性的第三重掺杂区域表征LDMOS结构10的栅区103。多晶硅可以以与衬底基本相反的导电性被大量地植入以形成栅区103。例如，多晶硅可与N+材料一起被植入以形成一种对应于栅区103的N+多聚区域。栅区103位于源区105a和漏区105b之间。
栅氧化层103a在栅区103与衬底在源区105a与漏区105b之间的沟道区之间作为绝缘体工作。在源区105a和漏区105b之间，栅氧化层103a位于栅区103以下并且/或者与栅区103相接触。栅氧化层103a可利用诸如二氧化硅（SiO2）的介电材料形成，尽管可以使用任何相适合的材料。
在图1中，栅氧化层103a包括第一部分和第二部分。该第一部分被称作第一栅氧化层106a，具有第一厚度；该第二部分被称作第二栅氧化层107，具有第二厚度。第二栅氧化层107也可被称为核心栅氧化层（core gateoxide）。在实施方式中，第一厚度可以与低工作电压处理的薄栅氧化层近似相等；第二厚度可以与高工作电压处理的厚栅氧化层近似相等。第一栅氧化层106的第一厚度比第二栅氧化层107的第二厚度更厚。例如，第一厚度可以近似地为
Figure BDA00003527016900061
。第二厚度可以近似为。栅区103下面的强场飘移区111被第一栅氧化层106所保护。强场飘移区111具有从0.05um到0.25um范围的宽度、从0.1um到0.5um范围的高度以及从0.3um到100um范围的深度。
LDMOS结构10还包括第一浅槽隔离（STI）102、第二STI102a，以及第三STI102b。第一STI102被布置在第二STI102a和第三STI102b之间。第一STI102最接近于第一栅氧化层106并且第二STI102a最接近于第二STI102a。
阱区104被植入到半导体衬底上，并位于栅区103和栅氧区103a下。阱区104包括第一阱101、第二阱109以及第三阱109a。在实施方式中，栅氧区103a具有与第一阱101接触的下外沿部分。例如，第一阱101在第一STI102下并且还接触第一栅氧化层106。第二阱109在第二STI102a下面。第三阱在第三STI102b下面。第一阱101具有第一高度和第一长度。第二阱109具有第二高度和第二长度。第三阱109a具有第三高度和第三长度。在图1中，第一高度要大于或小于第二高度。第二高度和第三高度基本上相同。第一长度小于或大于第二和第三长度。阱和STI的放置可产生高性能高电压的半导体器件。第一阱和第二阱被植入不同材料而第二阱和第三阱则被植入相同材料。在一个实施方式中，第一阱被植入n型材料而第二阱和第三阱被植入p型材料。在另一实施方式中，第一阱被植入p型材料而第二阱和第三阱被植入n型材料。
第一阱101和第二阱109可通过原生层掩模被间隔放置，该原生层掩模在制造处理中方便可行。栅氧化层106和107可被沉积或生长。较薄栅氧区可通过去除初始的氧化或沉积来形成。较厚栅氧区可通过第二沉积或额外生长氧化层来形成。
层100是轻掺杂源层。层100和105形成源区105a。包植入层（pocketimplant layer）108被布置在源区105a下面。层100、源区105a和包植入层108全部接触第二STI102a的侧面。包植入层108可控制LDMOS10的泄漏电平和阈值电压。包植入层108也可被称为晕轮（halo）植入区，包含该区域是为了防止穿通。例如，包植入层108可阻止耗尽区到达源区105a。举例而言，包植入层108可被掺杂磷原子或砷原子。包植入层108一般地比阱略微更重地掺杂。
第一阱101和第二阱109之间有衬底区110。衬底区110基本位于第二栅氧化层107下面。衬底区110具有的深度基本与第一阱101的第一高度相同并且基本比第二阱109和第三阱109a的高度大。衬底区110具有从0.1um到5um范围的宽度、0.1um到800um范围的高度以及0.3um到100um范围的深度。更加优选地，衬底区110具有从0.1um到0.3um范围的宽度、0.3um到600um范围的高度以及0.3um到10um范围的深度。
图2是示出根据第二示例性实施方式的低阈值电压LDMOS20的第二截面图。在实施方式中，图1中的STI102可被移除。通过移除STI102，LDMOS变成基于分栅氧化层器件的有源区域。
图3示出了根据第三示例性实施方式的低阈值电压LDMOS30的第三截面图。在实施方式中，第二阱109在包植入层108和第二栅氧化层107下面延伸。第二阱109与第二STI102a的底面和包植入层108的底面相接触。包植入层108包围源区105a。包植入层108接触第二STI102a。
在图3中，第二阱109的高度大于、小于或等于第一阱101的高度。在第一阱101和第二阱109之间的衬底区110具有比图1-2中的衬底区110的宽度更窄的宽度。
图4示出了根据第四示例性实施方式的低阈值电压LDMOS40的第四截面图。第四实施方式和第三实施方式的不同点之一是图3中的STI102被移除。
图5是示出了根据第五示例性实施方式的低阈值电压LDMOS50的第五截面图。第五实施方式与第一实施方式之间的不同点之一是栅区103和栅氧化层106两者具有统一的厚度。第一阱101接触栅氧化层106的底面。源区105a也接触栅氧化层106的底面。STI区域与阱的位置与图1中的第一实施方式中相似。
图6示出了根据第六示例性实施方式的低阈值电压LDMOS60的第六截面图。在实施方式中，阱区104包括第一阱101、第二阱101a、第三阱101b和深阱101c。第一阱101可为P阱。第二阱101a和第三阱101b可为N阱。深阱101c可为深N阱。第一阱101具有的高度比第二和第三阱的高度高。深阱101c被布置在第一、第二和第三阱下面。第二阱101a具有基本上与第三阱101b的长度相等的长度。第一阱101的长度基本上大于第二阱101a和第三阱101b的长度。深阱101c具有比第一阱101、第二阱101a和第三阱101b的长度之和更长的长度。
源区105a接触STI102。然而，源区105a并不接触第一栅氧化层106和第二栅氧化层107。层100被布置在第二栅氧化层107下面并被包植入层108所包围。第一阱101与第二阱101a之间的衬底区110可被P衬底填充。
本公开可应用于传统LDMOS和p型横向双扩散MOS（PLDMOS）。该方法也可应用于互补金属氧化物半导体（CMOS）工艺，双极型CMOS（BiCMOS）工艺，以及高K栅氧化层工艺。
所有上述半导体器件的实施方式可利用传统掩模制造而不产生额外加工成本。制造过程的更多细节可在美国专利7,161,213中找到。
上述的方法、装置和逻辑可以通过多种不同的硬件、软件或硬件软件组合以多种不同方式来实现。例如，装置的全部或者部分可包括在控制器、微处理器或者专用集成电路（ASIC）中的电路，或者可利用合并在单个集成电路上或者分布在多个集成电路之间的分布式逻辑或部件、或者其它类型的模拟或者数字电路的组合来实施。尽管描述了本公开的各种实施方式，但是对于本领域中的技术人员显而易见的是在本公开的范围内多种其他的实施方式和实现方式是可能的。因此，除了其所附权利要求及其等同物以外，本公开不应该受到限制。

Claims (10)

1.一种半导体器件，包括：
源区，被布置于半导体衬底；
漏区，被布置于所述半导体衬底；
栅区，被布置到所述半导体衬底上，并且位于所述源区和所述漏区之间；
栅氧区，被布置在所述半导体衬底上并与所述栅区接触；以及
阱区，被植入到所述半导体衬底上并位于所述栅区和所述栅氧区的下面，
其中，所述栅氧区具有与所述阱区接触的下外沿部分。
2.根据权利要求1所述的半导体器件，其中，所述栅氧区包括具有第一厚度的第一部分和具有第二厚度的第二部分，所述第一厚度基本上大于所述第二厚度。
3.根据权利要求2所述的半导体器件，其中，所述阱区包括具有第一长度的第一阱，所述第一阱与所述第一部分接触。
4.根据权利要求3所述的半导体器件，其中，所述阱区还包括第二阱，所述第二阱具有比所述第一长度更短的第二长度。
5.一种半导体器件，包括：
源区，被布置于半导体衬底；
漏区，被布置于所述半导体衬底；
栅区，被布置到所述半导体衬底上，并且位于所述源区与所述漏区之间；
栅氧区，被布置到所述半导体衬底上与所述栅区接触；
第一阱，被植入到所述半导体衬底上并与所述栅氧区接触，所述第一阱具有第一高度，以及
第二阱，被植入到位于浅槽隔离（STI）区下面的所述半导体衬底上，所述第二阱具有第二高度，
其中，所述第一高度比所述第二高度更大。
6.根据权利要求5所述的半导体器件，其中，所述第一阱和所述第二阱之间有衬底区，所述衬底区在所述栅氧区和包植入层以下延伸，所述包植入层与所述浅槽隔离区接触。
7.根据权利要求6所述的半导体器件，还包括：第三阱，与所述第一阱接触。
8.根据权利要求7所述的半导体器件，其中，所述第一阱具有第一长度，所述第二阱具有第二长度，并且其中，所述第一长度大于所述第二长度。
9.一种半导体器件，包括：
源区，被布置于半导体衬底；
漏区，被布置于所述半导体衬底；
栅区，被布置到所述半导体衬底上，并且位于所述源区与所述漏区之间；
栅氧区，被布置在所述半导体衬底上，与所述栅区接触；
第一阱，被植入到所述半导体衬底上并与所述栅氧区接触，所述第一阱具有第一长度；
第二阱，被植入到位于第一浅槽隔离（STI）区下面的所述半导体衬底上，所述第二阱具有第二长度；以及
第三阱，被植入到位于第二浅槽隔离区下面的所述半导体衬底上，所述第三阱具有第三长度，
其中，衬底区形成于所述第一阱和所述第二阱之间。
10.根据权利要求9所述的半导体器件，还包括位于所述第一阱、所述第二阱、和所述第三阱下面的深阱。
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2016141786A1 (zh) * 2015-03-10 2016-09-15 无锡华润上华半导体有限公司 场效应晶体管的制作方法
CN110323279A (zh) * 2018-03-29 2019-10-11 拉碧斯半导体株式会社 半导体装置

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9082646B2 (en) * 2012-07-18 2015-07-14 Broadcom Corporation Low threshold voltage metal oxide semiconductor
US9917168B2 (en) 2013-06-27 2018-03-13 Taiwan Semiconductor Manufacturing Company, Ltd. Metal oxide semiconductor field effect transistor having variable thickness gate dielectric
KR102140358B1 (ko) * 2016-12-23 2020-08-03 매그나칩 반도체 유한회사 잡음 감소를 위한 분리 구조를 갖는 통합 반도체 소자
CN110610994B (zh) * 2019-07-17 2023-03-31 成都芯源系统有限公司 一种横向双扩散金属氧化物半导体场效应晶体管
CN111785633B (zh) * 2020-06-11 2022-11-04 上海华虹宏力半导体制造有限公司 Ldmos器件的制备方法和ldmos器件
US11456384B2 (en) * 2020-07-06 2022-09-27 Globalfoundries U.S. Inc. Fin-based laterally diffused structure having a gate with two adjacent metal layers and method for manufacturing the same

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060261408A1 (en) * 2005-05-19 2006-11-23 Khemka Vishnu K Structure and method for RESURF LDMOSFET with a current diverter
US20090114987A1 (en) * 2007-11-07 2009-05-07 Oki Electric Industry Co., Ltd. Semiconductor device and manufacturing method thereof
CN203491263U (zh) * 2012-07-18 2014-03-19 美国博通公司 半导体器件

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7161213B2 (en) 2004-08-05 2007-01-09 Broadcom Corporation Low threshold voltage PMOS apparatus and method of fabricating the same
US20090020813A1 (en) * 2007-07-16 2009-01-22 Steven Howard Voldman Formation of lateral trench fets (field effect transistors) using steps of ldmos (lateral double-diffused metal oxide semiconductor) technology
US8203188B2 (en) 2009-05-22 2012-06-19 Broadcom Corporation Split gate oxides for a laterally diffused metal oxide semiconductor (LDMOS)

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060261408A1 (en) * 2005-05-19 2006-11-23 Khemka Vishnu K Structure and method for RESURF LDMOSFET with a current diverter
US20090114987A1 (en) * 2007-11-07 2009-05-07 Oki Electric Industry Co., Ltd. Semiconductor device and manufacturing method thereof
CN101431103A (zh) * 2007-11-07 2009-05-13 冲电气工业株式会社 半导体元件及其制造方法
CN203491263U (zh) * 2012-07-18 2014-03-19 美国博通公司 半导体器件

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2016141786A1 (zh) * 2015-03-10 2016-09-15 无锡华润上华半导体有限公司 场效应晶体管的制作方法
CN110323279A (zh) * 2018-03-29 2019-10-11 拉碧斯半导体株式会社 半导体装置
CN110323279B (zh) * 2018-03-29 2024-05-31 拉碧斯半导体株式会社 半导体装置

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