WO2016124110A1 - 半导体器件及其制造方法、电子装置 - Google Patents

半导体器件及其制造方法、电子装置 Download PDF

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WO2016124110A1
WO2016124110A1 PCT/CN2016/072743 CN2016072743W WO2016124110A1 WO 2016124110 A1 WO2016124110 A1 WO 2016124110A1 CN 2016072743 W CN2016072743 W CN 2016072743W WO 2016124110 A1 WO2016124110 A1 WO 2016124110A1
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gate
semiconductor substrate
layer
forming
trench
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PCT/CN2016/072743
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French (fr)
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李伟
郝龙
金炎
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无锡华润上华半导体有限公司
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Priority to US15/548,257 priority Critical patent/US20180019159A1/en
Publication of WO2016124110A1 publication Critical patent/WO2016124110A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/0217—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28105—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor next to the insulator having a lateral composition or doping variation, or being formed laterally by more than one deposition step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28123—Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4983—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET with a lateral structure, e.g. a Polysilicon gate with a lateral doping variation or with a lateral composition variation or characterised by the sidewalls being composed of conductive, resistive or dielectric material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate

Definitions

  • the present invention relates to a semiconductor manufacturing process, and in particular to a semiconductor device, a method of fabricating the same, and an electronic device using the same.
  • One type of existing integrated circuit manufacturing process is a high voltage device fabrication process that typically uses a thicker (thickness greater than 200 angstroms) thermal oxide layer as the gate oxide of the high voltage device.
  • STI shallow trench isolation
  • the gate oxide grown on the top corner of the STI is typically much thinner than the gate oxide grown in the flat active region and is generally difficult to adjust through the process.
  • the difference in thickness of the above gate oxide layer is superimposed on the edge effect on the top corner of the STI, so that the gate voltage-drain current (VG-ID) curve of the high voltage device exhibits a double hump phenomenon, as shown in FIG.
  • the curve of the data 1 is shown in the curve.
  • This double hump phenomenon indicates that the static leakage current of the high voltage device is high and the threshold voltage is low, so it is necessary to eliminate this phenomenon as much as possible.
  • the semiconductor industry In order to improve the double hump effect of high voltage devices fabricated using existing processes, the semiconductor industry generally employs a method to increase the thickness of the gate oxide layer formed on the top corner of the STI.
  • the specific process steps include: first, providing a semiconductor substrate And sequentially forming a pad oxide layer and a silicon nitride layer on the semiconductor substrate, the pad oxide layer serving as a buffer layer can release stress between the silicon nitride layer and the semiconductor substrate; and then, the silicon nitride layer After performing annealing, STI etching is performed using a silicon nitride layer as a mask to etch a trench for filling the isolation material constituting the STI in the semiconductor substrate; then, etching back the silicon nitride layer, and in the trench Forming a liner oxide layer on the sidewalls and bottom of the trench; then depositing a spacer material layer to fill the trench; then, etching the spacer material layer 205 to form an STI; and finally, etch
  • the apex of the silicon nitride layer is increased to expose the top corner of the trench, so that the trench is
  • the sidewall and the bottom of the trench form a lining oxide layer (which constitutes the sidewall oxide layer of the STI)
  • the top corner of the trench is relatively rounded, and is subsequently formed in the STI when the gate oxide layer is grown by thermal oxidation.
  • Gate oxide at the top corner The thickness increases, but the magnitude of the increase is very limited and thus does not significantly improve the double hump effect.
  • the oxide layer (the lining oxide layer) formed in the STI trench blocks the oxygen used in the thermal oxidation process from entering the STI.
  • the silicon surface at the top corner causes the thickness of the gate oxide layer grown at this location to be thin, which in turn causes the turn-on voltage of the device to be low, resulting in a double hump effect of the VG-ID curve.
  • a method of fabricating a semiconductor device comprising: providing a semiconductor substrate, forming a shallow trench isolation structure in the semiconductor substrate; forming a gate oxide layer and a gate including a bottom-up stack on the semiconductor substrate a gate structure of the electrode material layer; performing a first ion implantation to form a first dopant ion in the gate material layer; performing a second ion implantation to be located in the shallow trench at the gate material layer A portion above the top corner of the trench isolation structure forms a second dopant ion that is opposite the conductivity type of the first dopant ion.
  • the double hump effect of the device can be completely eliminated.
  • 1A-1F are cross-sectional views of devices respectively obtained by sequentially performing steps of a method according to an embodiment
  • FIG. 2 is a VG-ID curve comparison diagram of a semiconductor device prepared by a method according to an embodiment and a semiconductor device prepared according to an existing process;
  • FIG. 3 is a flow chart of a method of fabricating a semiconductor device in accordance with an embodiment.
  • the constituent material of the gate oxide layer has the characteristics of boron absorbing and phosphorus leaching, the double hump effect usually occurs in the high voltage device HVNMOS using the P well, and thus the present invention is specifically explained by taking the HVNMOS as an example.
  • FIGS. 1A-1F there are shown schematic cross-sectional views of devices respectively obtained in accordance with steps performed sequentially by a method in accordance with an embodiment.
  • FIG. 3 there is shown a flow diagram of steps sequentially performed by a method in accordance with an embodiment for schematically illustrating the flow of the entire manufacturing process.
  • step 301 a semiconductor substrate is provided, and a shallow trench isolation structure is formed in the semiconductor substrate.
  • a semiconductor substrate 100 is provided.
  • the constituent material of the semiconductor substrate 100 may be undoped single crystal silicon, doped monocrystalline silicon, silicon-on-insulator (SOI), or silicon-on-insulator ( SSOI), silicon germanium (S-SiGeOI) on insulator, silicon germanium on insulator (SiGeOI), and germanium on insulator (GeOI).
  • the constituent material of the semiconductor substrate 100 is selected from single crystal silicon.
  • a pad oxide layer 101 and a silicon nitride layer 102 are sequentially deposited on the semiconductor substrate 100, and the pad oxide layer 101 serves as a buffer layer to release stress between the silicon nitride layer 102 and the semiconductor substrate 100.
  • isolation region lithography is performed using the silicon nitride layer 102 as a mask to etch the trench 103 for filling the isolation material.
  • the depth of the trenches 103 can range from 3000 angstroms to 8000 angstroms.
  • the silicon nitride layer 102 is etched back to expose the top corner portion of the trench 103.
  • the thickness of the silicon nitride layer 102 removed by etchback in a direction parallel to the surface of the semiconductor substrate 100 may be 200 angstroms to 400 angstroms.
  • a spacer material is deposited to fill the trench 103 to be on the semiconductor substrate 100.
  • a shallow trench isolation structure 104 is formed in the middle.
  • a step of forming a liner oxide layer on the sidewalls and the bottom of the trench 103 is further included; after the depositing is performed, the step of grinding the spacer material to flatten the top portion thereof is further included. Then, the remaining silicon nitride layer 102 and the pad oxide layer 101 are removed by etching.
  • step S302 a gate structure including a gate oxide layer and a gate material layer stacked from the bottom up is formed on the semiconductor substrate.
  • the gate structure includes a gate oxide layer 105a and a gate material layer 105b stacked from bottom to top.
  • the gate oxide layer 105a includes a silicon oxide (SiO 2 ) layer
  • the gate material layer 105b includes a polysilicon layer.
  • the method of forming the gate oxide layer 105a and the gate material layer 105b may be any prior art known to those skilled in the art, preferably chemical vapor deposition (CVD), such as low temperature chemical vapor deposition (LTCVD), low pressure chemical vapor deposition. (LPCVD), Rapid Thermal Chemical Vapor Deposition (RTCVD), Plasma Enhanced Chemical Vapor Deposition (PECVD).
  • CVD chemical vapor deposition
  • LTCVD low temperature chemical vapor deposition
  • LPCVD low pressure chemical vapor deposition
  • RTCVD Rapid Thermal Chemical Vapor Deposition
  • PECVD Plasma Enhanced Chemical Vapor Deposition
  • sidewall structures 106 abutting the gate structure are formed on both sides of the gate structure.
  • the sidewall structure 106 is comprised of an oxide, a nitride, or a combination of both. Methods of forming the sidewall structure 106 are well known to those skilled in the art and will not be described herein.
  • step S303 a first ion implantation is performed to form a first dopant ion in the gate material layer.
  • a first ion implantation 107 is performed to form a first dopant ion in the gate material layer 105b.
  • the first dopant ion is an N-type ion including ions of phosphorus, nitrogen, arsenic, antimony, bismuth, and the like.
  • step S304 a second ion implantation is performed to form a second dopant ion opposite to the conductivity type of the first dopant ion at a portion of the gate material layer above the top corner of the shallow trench isolation structure.
  • a second ion implantation 109 is performed to be above the top corner of the gate trench layer isolation structure 104 of the gate material layer 105b.
  • the portion forms a second dopant ion that is opposite to the conductivity type of the first dopant ion.
  • the second dopant ion is a P-type ion including ions of boron, aluminum, gallium, indium, antimony, and the like.
  • the fabrication of the entire semiconductor device can be completed by a subsequent process, including: Forming a source/drain region in the semiconductor substrate 100; forming a silicide on top of the source/drain region and on top of the gate material layer 105b; sequentially forming a contact hole etch stop layer and an interlayer insulating layer on the semiconductor substrate 100, And forming a contact hole connecting the silicide at the bottom; forming a contact plug in the contact hole, and forming a first layer of metal wiring connecting the contact plug at the bottom; forming an inter-metal insulating layer covering the first layer of the metal wiring, And forming a second metal wiring in which the first metal wiring is connected; forming another metal insulating layer, forming a third metal wiring in communication with the second metal wiring, and so on, forming a multilayer metal wiring Structure; forming a metal pad for subsequent wire bonding in device packaging
  • the ⁇ ms in the formula represents the work function difference between the gate and the substrate.
  • the work function difference between the P-type substrate and the N-type ion-doped gate material layer is smaller than the P-type lining.
  • the work function between the bottom and the gate material layer doped with P-type ions, and ⁇ ms is usually a negative value. Therefore, the threshold voltage of the HVNMOS can be increased by reducing the doping concentration of the N-type ions or converting them into weak P-type ions by additional ion implantation.
  • the turn-on voltage of the portion of the gate material layer 105b above the top corner of the shallow trench isolation structure 104 can be adjusted to increase the turn-on voltage at the position.
  • the drain current is delayed to rise, thereby improving the leakage of the device and eliminating the double hump effect of the VG-ID curve.
  • the present invention also provides an electronic device including a semiconductor device fabricated according to the method of an exemplary embodiment of the present invention.
  • the electronic device may be any electronic product or device such as a mobile phone, a tablet computer, a notebook computer, a netbook, a game machine, a television, a VCD, a DVD, a navigator, a camera, a video camera, a voice recorder, an MP3, an MP4, a PSP, or the like. It is any intermediate product including the semiconductor device.
  • the electronic device has better performance due to the use of the semiconductor device.

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Abstract

一种半导体器件的制造方法包括：提供半导体衬底(100)，在半导体衬底(100)中形成浅沟槽隔离结构(104)；在半导体衬底(100)上形成包括自下而上层叠的栅极氧化层(105a)和栅极材料层(105b)的栅极结构；执行第一离子注入，以在栅极材料层(105b)中形成第一掺杂离子；执行第二离子注入(109)，以在栅极材料层(105b)的位于浅沟槽隔离结构(104)的顶端拐角之上的部分形成与第一掺杂离子的导电类型相反的第二掺杂离子。

Description

半导体器件及其制造方法、电子装置 技术领域
本发明涉及半导体制造工艺，具体而言涉及一种半导体器件及其制造方法及使用该半导体器件的电子装置。
背景技术
现有的集成电路生产工艺中有一类属于高压器件制造工艺，这类工艺通常使用较厚(厚度大于200埃)的热氧化层作为高压器件的栅极氧化层。由于浅沟槽隔离(STI)本身的结构特性，在STI的顶部拐角上生长的栅极氧化层通常要比在平坦的有源区生长的栅极氧化层薄得多，一般很难通过工艺调整来改善形成于STI的顶部拐角上的栅极氧化层的厚度。上述栅极氧化层的厚度的差异与STI的顶部拐角上的边缘效应相叠加，致使高压器件的栅极电压-漏极电流(VG-ID)曲线表现出双驼峰(hump)现象，如图2中的数据1组成的曲线所示。这种双驼峰现象表征了高压器件的静态漏电流偏高且阈值电压偏低，因而需要尽可能消除该现象。
为了改善采用现有工艺制备的高压器件的双驼峰效应，半导体业界通常采用的方法是提高形成于STI的顶部拐角上的栅极氧化层的厚度，其具体工艺步骤包括：首先，提供半导体衬底，并在半导体衬底上依次形成衬垫氧化物层和氮化硅层，衬垫氧化物层作为缓冲层可以释放氮化硅层和半导体衬底之间的应力；接着，对氮化硅层进行退火之后，利用氮化硅层作为掩膜进行STI蚀刻，以在半导体衬底中蚀刻出用于填充构成STI的隔离材料的沟槽；接着，回蚀刻氮化硅层，并在所述沟槽的侧壁和底部形成衬里氧化层；接着，沉积隔离材料层，以填充所述沟槽；接着，研磨隔离材料层205，以形成STI；最后，蚀刻去除剩余的氮化硅层和衬垫氧化物层，并依次实施栅极氧化层的热氧化生长和栅极材料层的沉积。上述工艺过程中，在半导体衬底中蚀刻出用于填充构成STI的隔离材料的沟槽后，通过增加对氮化硅层的回蚀刻，露出所述沟槽的顶端拐角，这样在所述沟槽的侧壁和底部形成衬里氧化层(其构成STI的侧墙氧化层)的时候，所述沟槽的顶端拐角会比较圆滑，后续通过热氧化生长栅极氧化层的时候，形成于STI的顶端拐角处的栅极氧化层的 厚度增大，但是增大的幅度非常有限，因而不能显著改善所述双驼峰效应。此外，由于器件有源区与STI的顶端拐角的交界处的边缘效应是固有的，形成于STI沟槽里的氧化层(所述衬里氧化层)会阻挡热氧化工艺所使用的氧气进入STI的顶端拐角处的硅表面，导致在此位置生长的栅极氧化层的厚度偏薄，进而造成器件的开启电压偏低，从而出现所述VG-ID曲线的双驼峰效应。
发明内容
有鉴于此，有必要提供一种能够消除器件的双驼峰效应的半导体器件的制造方法。
一种半导体器件的制造方法，包括：提供半导体衬底，在所述半导体衬底中形成浅沟槽隔离结构；在所述半导体衬底上形成包括自下而上层叠的栅极氧化层和栅极材料层的栅极结构；执行第一离子注入，以在所述栅极材料层中形成第一掺杂离子；执行第二离子注入，以在所述栅极材料层的位于所述浅沟槽隔离结构的顶端拐角之上的部分形成与所述第一掺杂离子的导电类型相反的第二掺杂离子。
通过改变器件的栅极材料层中的掺杂杂质分布，可以完全消除器件的双驼峰效应。
附图说明
本发明的下列附图在此作为本发明的一部分用于理解本发明。附图中示出了本发明的实施例及其描述，用来解释本发明的原理。附图中：
图1A-图1F为根据一实施例的方法依次实施的步骤所分别获得的器件的剖面图；
图2为根据一实施例的方法制备的半导体器件与根据现有工艺制备的半导体器件的VG-ID曲线对比图；
图3为根据一实施例的半导体器件的制造方法流程图。
具体实施方式
在下文的描述中，给出了大量具体的细节以便提供对本发明更为彻底的理解。然而，对于本领域技术人员而言显而易见的是，本发明可以无需一个或多个这些细节而得以实施。在其他的例子中，为了避免与本发明发生混淆， 对于本领域公知的一些技术特征未进行描述。
为了彻底理解本发明，将在下列的描述中提出详细的步骤，以便阐释本发明提出的半导体器件及其制造方法、电子装置。显然，本发明的施行并不限定于半导体领域的技术人员所熟习的特殊细节。本发明的较佳实施例详细描述如下，然而除了这些详细描述外，本发明还可以具有其他实施方式。
应当理解的是，当在本说明书中使用术语“包含”和/或“包括”时，其指明存在所述特征、整体、步骤、操作、元件和/或组件，但不排除存在或附加一个或多个其他特征、整体、步骤、操作、元件、组件和/或它们的组合。
由于栅极氧化层的构成材料二氧化硅具有吸硼排磷特性，因此，双驼峰效应通常发生在使用P阱的高压器件HVNMOS，因而在此以HVNMOS为例对本发明做出具体阐释。
参照图1A-图1F，其中示出了根据一实施例的方法依次实施的步骤所分别获得的器件的示意性剖面图。
请一并参照图3，其中示出了根据一实施例的方法依次实施的步骤的流程图，用于简要示出整个制造工艺的流程。
首先，在步骤301中，提供半导体衬底，在半导体衬底中形成浅沟槽隔离结构。
如图1A所示，提供半导体衬底100，半导体衬底100的构成材料可以采用未掺杂的单晶硅、掺杂有杂质的单晶硅、绝缘体上硅(SOI)、绝缘体上层叠硅(SSOI)、绝缘体上层叠锗化硅(S-SiGeOI)、绝缘体上锗化硅(SiGeOI)以及绝缘体上锗(GeOI)等。作为示例，在本实施例中，半导体衬底100的构成材料选用单晶硅。
接下来，在半导体衬底100上依次沉积衬垫氧化物层101和氮化硅层102，衬垫氧化物层101作为缓冲层可以释放氮化硅层102和半导体衬底100之间的应力。
接着，如图1B所示，在对氮化硅层102进行退火之后，利用氮化硅层102作为掩膜进行隔离区光刻，蚀刻出用于填充隔离材料的沟槽103。作为示例，沟槽103的深度可以为3000埃-8000埃。
接着，如图1C所示，回蚀刻氮化硅层102，以露出沟槽103的顶端拐角部分。作为示例，通过回蚀刻去除的氮化硅层102的沿着与半导体衬底100表面相平行的方向上的厚度可以为200埃-400埃。
接着，如图1D所示，沉积隔离材料填充沟槽103，以在半导体衬底100 中形成浅沟槽隔离结构104。在实施所述沉积之前，还包括在沟槽103的侧壁和底部形成衬里氧化层的步骤；在实施所述沉积之后，还包括研磨隔离材料以使其顶部平整的步骤。然后，通过蚀刻去除剩余的氮化硅层102和衬垫氧化物层101。
接下来，在步骤S302中，在半导体衬底上形成包括自下而上层叠的栅极氧化层和栅极材料层的栅极结构。
如图1D所示，栅极结构包括自下而上层叠的栅极氧化层105a和栅极材料层105b。栅极氧化层105a包括二氧化硅(SiO2)层，栅极材料层105b包括多晶硅层。栅极氧化层105a和栅极材料层105b的形成方法可以采用本领域技术人员所熟习的任何现有技术，优选化学气相沉积法(CVD)，如低温化学气相沉积(LTCVD)、低压化学气相沉积(LPCVD)、快热化学气相沉积(RTCVD)、等离子体增强化学气相沉积(PECVD)。形成栅极结构之前，还包括实施阱区注入，以在半导体衬底100中形成阱区的步骤，对于HVNMOS而言，形成的阱区为P阱。
然后，在栅极结构的两侧且形成紧靠栅极结构的侧壁结构106。作为示例，侧壁结构106由氧化物、氮化物或者二者的组合构成。形成侧壁结构106的方法为本领域技术人员所熟习，在此不再赘述。
接着，在步骤S303中，执行第一离子注入，以在栅极材料层中形成第一掺杂离子。
如图1E所示，执行第一离子注入107，以在栅极材料层105b中形成第一掺杂离子。对于HVNMOS而言，所述第一掺杂离子为N型离子，其包括磷、氮、砷、锑、铋等离子。
接着，在步骤S304中，执行第二离子注入，以在栅极材料层的位于浅沟槽隔离结构的顶端拐角之上的部分形成与第一掺杂离子的导电类型相反的第二掺杂离子。
如图1F所示，在栅极材料层105b上形成图案化的掩膜层108后，执行第二离子注入109，以在栅极材料层105b的位于浅沟槽隔离结构104的顶端拐角之上的部分形成与所述第一掺杂离子的导电类型相反的第二掺杂离子。对于HVNMOS而言，所述第二掺杂离子为P型离子，其包括硼、铝、镓、铟、铊等离子。
至此，完成了根据本发明示例性实施例的方法实施的工艺步骤，接下来，去除掩膜层108后，可以通过后续工艺完成整个半导体器件的制作，包括： 在半导体衬底100中形成源/漏区；在源/漏区的顶部以及栅极材料层105b的顶部形成硅化物；在半导体衬底100上依次形成接触孔蚀刻停止层和层间绝缘层，并在其中形成底部连通所述硅化物的接触孔；在接触孔中形成接触塞，并形成底部连通所述接触塞的第一层金属布线；形成覆盖第一层金属布线的金属间绝缘层，并在其中形成连通第一层金属布线的第二层金属布线；形成另一金属间绝缘层，并在其中形成连通第二层金属布线的第三层金属布线，依次类推，形成多层金属布线结构；形成金属焊盘，用于后续实施器件封装时的引线键合。
由NMOS的阈值电压公式(1)可知，
阈值电压
Figure PCTCN2016072743-appb-000001
公式中的φms表示的是栅极与衬底之间的功函数差，对于HVNMOS而言，P型衬底与掺杂N型离子的栅极材料层之间的功函数差要小于P型衬底与掺杂P型离子的栅极材料层之间的功函数，且φms通常为负值。因此，通过额外的离子注入来降低所述N型离子的掺杂浓度或者使其转变为弱P型离子，可以提高HVNMOS的阈值电压。
如图2中的数据2组成的曲线所示，通过改变栅极材料层105b的位于浅沟槽隔离结构104的顶端拐角之上的部分的掺杂杂质浓度，可以调高该位置的开启电压，在器件的栅极电压上升的过程中，漏极电流得以延迟上升，从而改善器件的漏电，消除VG-ID曲线的双驼峰效应。
本发明还提供一种电子装置，其包括根据本发明示例性实施例的方法制造的半导体器件。所述电子装置可以是手机、平板电脑、笔记本电脑、上网本、游戏机、电视机、VCD、DVD、导航仪、照相机、摄像机、录音笔、MP3、MP4、PSP等任何电子产品或设备，也可以是任何包括所述半导体器件的中间产品。所述电子装置，由于使用了所述半导体器件，因而具有更好的性能。
本发明已经通过上述实施例进行了说明，但应当理解的是，上述实施例只是用于举例和说明的目的，而非意在将本发明限制于所描述的实施例范围内。此外本领域技术人员可以理解的是，本发明并不局限于上述实施例，根据本发明的教导还可以做出更多种的变型和修改，这些变型和修改均落在本发明所要求保护的范围以内。本发明的保护范围由附属的权利要求书及其等效范围所界定。

Claims (7)

  1. 一种半导体器件的制造方法，包括：
    在半导体衬底中形成浅沟槽隔离结构；
    在所述半导体衬底上形成栅极结构，所述栅极结构包括自下而上层叠的栅极氧化层和栅极材料层；
    执行第一离子注入，以在所述栅极材料层中形成第一掺杂离子；及
    执行第二离子注入，以在所述栅极材料层的位于所述浅沟槽隔离结构的顶端拐角之上的部分形成与所述第一掺杂离子的导电类型相反的第二掺杂离子。
  2. 根据权利要求1所述的方法，其特征在于，形成所述浅沟槽隔离结构的步骤包括：
    在所述半导体衬底上依次沉积衬垫氧化物层和氮化硅层；
    利用所述氮化硅层作为掩膜进行隔离区光刻，蚀刻出用于填充隔离材料的沟槽；
    回蚀刻所述氮化硅层，以露出所述沟槽的顶端拐角部分；
    沉积隔离材料填充所述沟槽，以在所述半导体衬底中形成所述浅沟槽隔离结构；及
    通过蚀刻去除剩余的所述氮化硅层和衬垫氧化物层。
  3. 根据权利要求2所述的方法，其特征在于，所述沟槽的深度为3000埃-8000埃，通过所述回蚀刻去除的所述氮化硅层的沿着与所述半导体衬底表面相平行的方向上的厚度为200埃-400埃。
  4. 根据权利要求2所述的方法，其特征在于，在实施所述沉积之前，还包括在所述沟槽的侧壁和底部形成衬里氧化层的步骤；在实施所述沉积之后，还包括研磨所述隔离材料以使其顶部平整的步骤。
  5. 根据权利要求1所述的方法，其特征在于，所述第一掺杂离子为N型离子，所述第二掺杂离子为P型离子。
  6. 一种采用权利要求1-5任意一项所述的方法制造的半导体器件。
  7. 一种电子装置，所述电子装置包括权利要求6所述的半导体器件。
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