WO2016123839A1 - 一种阵列基板的检测线路及阵列基板 - Google Patents

一种阵列基板的检测线路及阵列基板 Download PDF

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WO2016123839A1
WO2016123839A1 PCT/CN2015/074446 CN2015074446W WO2016123839A1 WO 2016123839 A1 WO2016123839 A1 WO 2016123839A1 CN 2015074446 W CN2015074446 W CN 2015074446W WO 2016123839 A1 WO2016123839 A1 WO 2016123839A1
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test
pins
signal
array substrate
pin
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PCT/CN2015/074446
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English (en)
French (fr)
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田勇
赵莽
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深圳市华星光电技术有限公司
武汉华星光电技术有限公司
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Publication of WO2016123839A1 publication Critical patent/WO2016123839A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136254—Checking; Testing

Definitions

  • the present invention relates to the field of liquid crystal display technology, and in particular to a detection circuit of an array substrate and an array substrate.
  • the existing array substrate detection circuit has a defect of excessive height, which makes the area occupied by the detection line too large. Since the array substrate detection lines are disposed on the periphery of the array substrate, the detection circuit area is too large, and the frame of the liquid crystal display is too large.
  • an embodiment of the present invention first provides a detection circuit for an array substrate, including:
  • a signal pin area including a plurality of signal pins, wherein the signal pins are correspondingly connected to signal lines in the array substrate;
  • test pin area including a plurality of test pins
  • the fanout trace area is connected between the signal pin area and the test pin area, and includes a plurality of fan-out traces.
  • the signal pins are connected to some test pins through fan-out traces, and are connected to the signal pins.
  • the pins are not adjacent to each other, so that the height of the fanout route area is reduced.
  • the signal pin in the signal pin area has a distribution density smaller than the test pin The distribution density of the test pins in the zone.
  • the test pin area includes a first test pin and a second test pin, and each of the first test pins is connected to the fan-out trace, and the second test pin is not connected to the fan-out line. Connected, there is at least one second test pin between the adjacent first test pins.
  • the number of second test pins present between adjacent first test pins is the same.
  • the signal line comprises a data line.
  • the signal line comprises a gate line.
  • the test pins are uniformly arranged in a "one" shape in the test pin area.
  • the signal pins are uniformly arranged in a "one" shape in a signal pin area in a direction parallel to the test pin area.
  • the test pin is constructed of a conductive material.
  • the present invention also provides an array substrate comprising the detection line of any of the above.
  • the signal pins are connected to the partial test pins through the fan-out traces, and the test pins connected to the signal pins are not adjacent to each other.
  • the detection circuit provided by the present invention has a larger space for the fan-out route in the same fan-out route area. This also makes it unnecessary to increase the height of the traces by fan-out traces, that is, to increase the separation distance between the test pin area and the pin area to meet the requirements of the design process such as the length, width and spacing of the traces. Therefore, compared with the existing detection circuit, the array substrate detection circuit provided by the invention has a lower height and a smaller occupied area, and is beneficial to the design and production of the narrow-frame liquid crystal display.
  • first test pins there may be a plurality of second test pins (ie, test pins not connected to the signal pins) between adjacent first test pins (ie, test pins connected to the signal pins).
  • second test pins ie, test pins not connected to the signal pins
  • adjacent first test pins ie, test pins connected to the signal pins.
  • the distribution area of the fan-out trace increases as the distribution range of the first test pin increases, the number of fan-out traces is constant for an array substrate of a specific size and resolution, so this time The distribution density of the fan-out traces will be reduced, and the separation distance between the adjacent two fan-out traces will become larger, which will reduce the mutual interference between the fan-out traces, thereby improving the accuracy of the detection results.
  • the reduced distribution density of the first test pin also reduces the distributed density of the test ports of the external test equipment connected to the test line, which helps to improve the electromagnetic interference phenomenon at the test port of the external test equipment, thereby Further improve the accuracy of the test results.
  • FIG. 1 is a schematic structural view of a detection line of a conventional high-resolution array substrate
  • FIG. 2 is a schematic structural view of a detection line of a conventional low-resolution array substrate
  • FIG. 3 is a structural diagram of a detection line of an array substrate according to an embodiment of the present invention.
  • FIG. 4 is a structural diagram of a detection line of an array substrate according to another embodiment of the present invention.
  • FIG. 5 is a structural diagram of a detection line of an array substrate according to still another embodiment of the present invention.
  • the number of pixels included in the array substrate in the liquid crystal panels of different sizes and resolutions is different.
  • the pixels arranged in the array are respectively connected with a gate line and a data line, and in the process of detecting the array substrate, each gate line and the data line need to be detected. Therefore, the number of pixels included in the array substrate is different, so that the number of test pins required is different, that is, the low-resolution array substrate requires fewer test pins, and the high-resolution array substrate requires There are more test pins.
  • FIG. 1 is a schematic view showing the structure of a conventional high-resolution array substrate detecting circuit.
  • the existing array substrate detection line includes a plurality of signal pins 101 and a plurality of test pins 102.
  • the test pins 102 are connected in one-to-one correspondence with the signal pins 101, and the signal pins 101 are also respectively connected to the data lines in the array substrate.
  • the external test device can send a test signal to the data line in the array substrate through the test pin 102, thereby achieving the purpose of detecting the array substrate.
  • the detection lines disposed on the array substrates of different sizes and resolutions often share a set of production molds, that is, the detection of the array substrates of different sizes and resolutions.
  • the number and arrangement of test pins in the line are the same. Since the low resolution array substrate has fewer data lines, when the low resolution array substrate is detected, some of the test pins in the detection line are not connected to the signal pins.
  • FIG. 2 is a schematic view showing the structure of a detection line of a conventional low-resolution array substrate.
  • test pins 102 included in the detection lines configured for the high resolution and low resolution array substrates are the same.
  • the test lines of the low-resolution array substrate contain fewer signal pins than the number of test pins, so only the test pins in the middle area are connected to the signal pins, and the test is located on both sides of the test pin area. The pin is not connected to the signal pin. Thus, the test pins connected to the signal pins are concentrated in a continuous test pin area.
  • the test pin 102 and the signal pin 101 are connected by a fan-out trace.
  • the fan-out trace needs to meet certain length and width requirements, and at the same time, A certain interval requirement needs to be met between the adjacent fan-out lines.
  • the height H of the fanout traces (ie, between the test pin area and the signal pin area) The distance) needs to be larger. This results in a higher height of the existing array substrate detection line and a larger footprint.
  • the present embodiment provides a new array substrate detection line, and FIG. 3 shows a schematic structural view of the detection line.
  • the array substrate detection circuit provided in this embodiment is mainly directed to a low resolution array substrate, which includes a test pin area 301, a fanout trace area 302, and a signal pin area 303.
  • the signal pin area 303 includes a plurality of signal pins 304
  • the test pin area 301 also includes a plurality of test pins.
  • Each of the signal pins 304 in the signal pin area 303 is respectively connected to a signal line in the array substrate.
  • the signal line to which the signal pin 304 is connected is a data line.
  • the signal line to which the signal pin 304 is connected may also be a gate line, and the present invention is not limited thereto.
  • the fanout trace area 302 is connected between the test pin area 301 and the signal pin area 303, and includes a plurality of fanout traces 307.
  • the detection lines provided in this embodiment are produced using the existing test pin production mold, that is, for the high resolution and low resolution array substrate, the test pin area 301
  • the number of test pins included and the arrangement are the same.
  • the present embodiment provides In the detection circuit, the signal pin 304 is connected to a portion of the test pin through the fan-out trace 307, and the test pins connected to the signal pin 304 are not adjacent to each other. Since the external device transmits the test signal to the pin through the test pin and the fan-out trace, and then to the thin film transistor in the array substrate, both the test pin and the fan-out trace need to be made of a conductive material.
  • the distribution density of the test pins in the test pin area 301 is greater than the distribution density of the signal pins in the signal pin area 303. Since the test pins connected to the signal pins 304 are not adjacent to each other, the detection lines provided in this embodiment are in the same fan-out manner as compared with the existing distribution manner of the test pins connected to the signal pins. In the line area, the fan-out route has more space for routing. This also makes it unnecessary for the fan-out trace to increase the trace height, that is, to increase the separation distance between the test pin region 301 and the signal pin region 303 to meet the requirements of the design process such as the length, width and spacing of the trace. . Therefore, compared with the existing detection circuit, the array substrate detection circuit provided by the embodiment has a lower height and a smaller occupied area, which is beneficial to the design and generation of the narrow-frame liquid crystal display.
  • the test pin area 301 includes a first test pin 305 and a second test pin 306.
  • the first test pin 305 is a test pin connected to the fanout trace 307, that is, the first test pin 305 is a pin connected to the signal pin 304.
  • the second test pin 306 is not connected to the fanout trace 307, that is, the second test pin 306 is a pin that is not connected to the signal pin 304.
  • each test pin in the test pin area 301 is arranged in a "one" shape, and each signal pin in the signal pin area 303 is also arranged in a "one" shape, and the signal pin area 303 and the test tube are arranged.
  • the foot regions 301 are parallel.
  • the pins in the signal pin area and the test pin area may also adopt other reasonable arrangements, such as a curved arrangement, etc., and the present invention is not limited thereto.
  • a second test pin 306 is present between adjacent first test pins 305. It should be noted that, in other embodiments of the present invention, the number of second test pins existing between adjacent second test pins may also be other reasonable values, such as two, three, or more. 3, etc., the invention is not limited thereto.
  • two second test pins 306 are present between adjacent first test pins 305 in the array substrate test line.
  • the spacing distance between adjacent first test pins 305 is further increased, which not only helps to reduce the height of the fanout trace area 302, but also helps to reduce mutual interference between the fanout traces 307. .
  • the distribution area of the fanout trace 307 also increases.
  • the number of fanout traces 307 is constant, so the distribution density of the fanout traces 307 will be reduced at this time, and the separation distance between the adjacent two fanout traces 307. Become bigger. This will also reduce The mutual interference between the fanout traces 307 improves the accuracy of the detection results.
  • the reduced density of distribution of the first test pin 305 also reduces the distribution density of the corresponding traces in the test port of the external test device connected to the test line, which helps to improve the presence of the test port of the external test device. Electromagnetic interference phenomenon, thereby further improving the accuracy of the test results.
  • the number of second test pins 306 existing between adjacent first test pins 305 may also be different, and the present invention is not limited thereto.
  • the present invention also provides an array substrate comprising the detection lines as described above.
  • the external test device detects the array substrate through the detection line.
  • the signal pins are connected to the partial test pins through the fan-out traces, and the test pins connected to the signal pins are not adjacent to each other. Therefore, the routing space of the fan-out trace is larger than that of the existing test pin connected to the signal pin. This also makes it unnecessary to increase the height of the traces by fan-out traces, that is, to increase the separation distance between the test pin area and the pin area to meet the requirements of the design process such as the length, width and spacing of the traces. Therefore, compared with the existing detection circuit, the array substrate detection circuit provided by the invention has a lower height and a smaller occupied area, which is beneficial to the design and generation of the narrow-frame liquid crystal display.

Abstract

一种阵列基板的检测线路及阵列基板，其中，检测线路包括：信号管脚区(303)，其包括多个信号管脚(304)，信号管脚(304)与阵列基板中的信号线对应连接；测试管脚区(301)，其包括多个测试管脚(305,306)；扇出走线区(302)，其连接在信号管脚区(303)与测试管脚区(301)之间，包括多条扇出走线(307)，信号管脚(304)通过扇出走线(307)连接至部分测试管脚，与信号管脚连接的测试管脚均互不相邻，从而使得扇出走线区(302)的高度减小。

Description

一种阵列基板的检测线路及阵列基板
相关技术的交叉引用
本申请要求享有2015年02月04日提交的名称为：“一种阵列基板的检测线路及阵列基板”的中国专利申请CN201510059935.1的优先权，其全部内容通过引用并入本文中。
技术领域
本发明涉及液晶显示技术领域，具体地说，涉及一种阵列基板的检测线路及阵列基板。
背景技术
一般在制作液晶显示器的阵列基板的过程中，会使用外延的方式在阵列基板上形成数百万个薄膜晶体管来作为控制单元。然而，在阵列基板生产的过程中，如果部分薄膜晶体管的质量没有达到预设要求，那么将可能导致这些薄膜晶体管无法具备开关控制的功能，从而使得液晶显示器出现亮点或暗点的缺陷，大幅降低液晶显示器的质量。因此，在阵列基板生产过程中，必须有效地对阵列基板进行检测，以确保阵列基板的质量。
而现有的阵列基板检测线路存在高度过高的缺陷，这使得检测线路占用的面积过大。由于阵列基板检测线路多设置在阵列基板的外围，所以检测线路面积过大也造成液晶显示器的边框过大。
基于上述情况，亟需一种高度较小的阵列基板检测线路。
发明内容
本发明所要解决的问题是为了减小阵列基板检测线路的高度。为解决上述问题，本发明的实施例首先提供了一种阵列基板的检测线路，包括：
信号管脚区，其包括多个信号管脚，所述信号管脚与阵列基板中的信号线对应连接；
测试管脚区，其包括多个测试管脚；
扇出走线区，其连接在信号管脚区与测试管脚区之间，包括多条扇出走线，所述信号管脚通过扇出走线连接至部分测试管脚，与信号管脚连接的测试管脚均互不相邻，以使得扇出走线区的高度减小。
根据本发明的一个实施例，所述信号管脚区中信号管脚的分布密度小于所述测试管脚 区中测试管脚的分布密度。
根据本发明的一个实施例，所述测试管脚区包括第一测试管脚和第二测试管脚，各个第一测试管脚与扇出走线对应连接，第二测试管脚不与扇出走线连接，相邻的第一测试管脚之间存在有至少一个第二测试管脚。
根据本发明的一个实施例，相邻的第一测试管脚之间存在的第二测试管脚的数量相同。
根据本发明的一个实施例，所述信号线包括数据线。
根据本发明的一个实施例，所述信号线包括栅极线。
根据本发明的一个实施例，所述测试管脚在测试管脚区呈“一”字型均匀排列。
根据本发明的一个实施例，所述信号管脚在信号管脚区沿平行于测试管脚区的方向呈“一”字型均匀排列。
根据本发明的一个实施例，所述测试管脚由导电材质构成。
本发明还提供了一种阵列基板，所述阵列基板包括如上任一项所述的检测线路。
本发明所提供的阵列基板检测线路中，信号管脚通过扇出走线连接至部分测试管脚，并且，与信号管脚连接的测试管脚均互不相邻。相较于现有的与信号管脚连接的测试管脚的分布方式，本发明所提供的检测线路在相同的扇出走线区域内，扇出走线的走线空间更大。这也就使得扇出走线不需要依靠增加走线高度，即依靠增大测试管脚区与管脚区之间的间隔距离，来满足走线长度、宽度和间隔等设计工艺的要求。因此，相较于现有的检测线路，本发明所提供的阵列基板检测线路的高度更低，占用面积更小，有利于窄边框液晶显示器的设计与生产。
同时，相邻的第一测试管脚(即与信号管脚连接的测试管脚)之间还可以存在多个第二测试管脚(即不与信号管脚连接的测试管脚)。这样，相邻的第一测试管脚之间的间隔距离进一步增大，这不仅有助于减小扇出走线区域的高度，还有助于减小扇出走线之间的相互干扰。
因为随着第一测试管脚的分布范围的增大，扇出走线的分布区域也随之增大，而对于特定尺寸和分辨率的阵列基板，扇出走线的数量是一定的，所以此时扇出走线的分布密度将会减小，相邻的两个扇出走线之间的间隔距离变大，这样也就降低了扇出走线之间的相互干扰，从而提高了检测结果的准确性。
此外，第一测试管脚的分布密度降低也会使得与该检测线路连接的外部测试设备的测试端口的分布密度降低，这有助于改善外部测试设备的测试端口处存在的电磁干扰现象，从而进一步提高检测结果的准确性。
本发明的其它特征和优点将在随后的说明书中阐述，并且，部分地从说明书中变得显而易见，或者通过实施本发明而了解。本发明的目的和其他优点可通过在说明书、权利要求书以及附图中所特别指出的结构来实现和获得。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要的附图做简单的介绍：
图1是现有的高分辨率阵列基板的检测线路的结构示意图；
图2是现有的低分辨率阵列基板的检测线路的结构示意图；
图3是根据本发明一个实施例的阵列基板的检测线路的结构图；
图4是根据本发明另一个实施例的阵列基板的检测线路的结构图；
图5是根据本发明又一个实施例的阵列基板的检测线路的结构图。
具体实施方式
以下将结合附图及实施例来详细说明本发明的实施方式，借此对本发明如何应用技术手段来解决技术问题，并达成技术效果的实现过程能充分理解并据以实施。需要说明的是，只要不构成冲突，本发明中的各个实施例以及各实施例中的各个特征可以相互结合，所形成的技术方案均在本发明的保护范围之内。
同时，在以下说明中，出于解释的目的而阐述了许多具体细节，以提供对本发明实施例的彻底理解。然而，对本领域的技术人员来说显而易见的是，本发明可以不用这里的具体细节或者所描述的特定方式来实施。
由于存在多种尺寸和分辨率的液晶面板，因此也就使得不同尺寸和分辨率的液晶面板中阵列基板所包含的像素个数不同。阵列排布的像素分别对应连接有栅极线和数据线，而在对阵列基板进行检测的过程中，需要对各个栅极线和数据线均进行检测。所以阵列基板中所包含的像素个数不同也就使得所需要的测试管脚的数量不同，即低分辨率的阵列基板所需要的测试管脚较少，而高分别率的阵列基板所需要的测试管脚较多。
图1示出了现有的高分辨率阵列基板检测线路的结构示意图。
如图1所示，现有的阵列基板检测线路包含有多个信号管脚101和多个测试管脚102。其中，测试管脚102与信号管脚101一一对应连接，信号管脚101还分别与阵列基板中的数据线连接。这样，外部测试装置通过测试管脚102，便可以向阵列基板中的数据线发送测试信号，从而达到对阵列基板进行检测的目的。
在阵列基板的设计过程中，为了节约检测线路的生产成本，设置在不同尺寸和分辨率的阵列基板上的检测线路往往共用一套生产模具，即不同尺寸和分辨率的阵列基板所配置的检测线路中测试管脚的数量和排布方式均相同。由于低分辨率的阵列基板的数据线较少，因此在对低分辨率的阵列基板进行检测时，检测线路中部分测试管脚并不与信号管脚连接。
图2示出了现有的低分辨率阵列基板的检测线路的结构示意图。
结合图1和图2可以看出，高分辨率和低分辨率的阵列基板所配置的检测线路中所包含的测试管脚102的数量和排布方式均相同。低分辨率阵列基板的测试线路所包含的信号管脚较少，其数量小于测试管脚的数量，所以只有中间区域的测试管脚与信号管脚相连，而位于测试管脚区域两侧的测试管脚则不与信号管脚连接。由此可见，与信号管脚连接的测试管脚集中在一连续的测试管脚区域中。
测试管脚102与信号管脚101之间是通过扇出走线连接的，在检测线路的设计过程中，为了保证导电线路的电学性能，扇出走线需要满足一定的长度和宽度要求，同时，相邻的扇出走线之间还需要满足一定的间隔要求。
如图2所示，由于与信号管脚连接的测试管脚是相邻的，因此为了满足扇出走线的设计要求，扇出走线的高度H(即测试管脚区域与信号管脚区域之间的距离)就需要较大。这也就导致了现有阵列基板检测线路的高度较高，占用面积较大。
为了解决现有阵列基板检测线路高度过高、占用面积过大的问题，本实施例提供了一种新的阵列基板检测线路，图3示出了该检测线路的结构示意图。
如图3所示，本实施例所提供的阵列基板检测线路主要针对低分辨率阵列基板，其包括测试管脚区301、扇出走线区302和信号管脚区303。其中，信号管脚区303包括多个信号管脚304，测试管脚区301同样包括多个测试管脚。
信号管脚区303中的各个信号管脚304分别与阵列基板中的信号线对应连接。本实施例中，信号管脚304所连接的信号线为数据线。当然，在本发明的其他实施例中，信号管脚304所连接的信号线也可以为栅极线，本发明不限于此。扇出走线区302连接在测试管脚区301与信号管脚区303之间，其包括多条扇出走线307。
为了降低阵列基板检测线路的生产成本，本实施例中所提供的检测线路使用了现有的测试管脚生产模具来生产，即对于高分辨率和低分辨率的阵列基板，测试管脚区301所包含的测试管脚的数量和排布方式均相同。
由于低分辨率阵列基板的数据线较少，因此检测线路中信号管脚304的数量要少于测试管脚的数量(通常信号管脚的数量为测试管脚的数量的一半)。所以，本实施例所提供 的检测线路中，信号管脚304通过扇出走线307连接至部分测试管脚，并且，与信号管脚304连接的测试管脚均互不相邻。由于外部设备通过测试管脚和扇出走线来将测试信号传输到管脚，进而传输至阵列基板中的薄膜晶体管，因此，测试管脚和扇出走线均需要由导电材料构成。
本实施例中，测试管脚区301中测试管脚的分布密度大于信号管脚区303中信号管脚的分布密度。由于与信号管脚304连接的测试管脚均互不相邻，因此相较于现有的与信号管脚连接的测试管脚的分布方式，本实施例所提供的检测线路在相同的扇出走线区域内，扇出走线的走线空间更大。这也就使得扇出走线不需要依靠增加走线高度，即依靠增大测试管脚区301与信号管脚区303之间的间隔距离，来满足走线长度、宽度和间隔等设计工艺的要求。因此，相较于现有的检测线路，本实施例所提供的阵列基板检测线路的高度更低，占用面积更小，有利于窄边框液晶显示器的设计与产生。
本实施例中，测试管脚区301包括第一测试管脚305和第二测试管脚306。其中，第一测试管脚305为与扇出走线307连接的测试管脚，即第一测试管脚305为与信号管脚304对应连接的管脚。第二测试管脚306不与扇出走线307连接，即第二测试管脚306为不与信号管脚304连接的管脚。为了减小扇出走线区域302的高度，即减小测试管脚区301与信号管脚区303之间的间隔距离，本实施例中，相邻的第一测试管脚305之间存在有第二测试管脚306。
如图3所示，测试管脚区301中各个测试管脚呈“一”字形排列，信号管脚区303中各个信号管脚也成“一”字形排列，并且信号管脚区303与测试管脚区301平行。当然，在本发明的其他实施例中，信号管脚区和测试管脚区中管脚还可以采用其他合理的排列方式，例如弧形排列等，本发明不限于此。
本实施例中，相邻的第一测试管脚305之间均存在一个第二测试管脚306。需要说明的是，在本发明的其他实施例中，相邻的第二测试管脚之间存在的第二测试管脚的数量还可以为其他合理值，例如2个、3个或是多于3个等，本发明不限于此。
如图4所示，在本发明的一个实施例中，阵列基板测试线路中相邻的第一测试管脚305之间均存在两个第二测试管脚306。这样，相邻的第一测试管脚305之间的间隔距离进一步增大，这不仅有助于减小扇出走线区302的高度，还有助于减小扇出走线307之间的相互干扰。
随着第一测试管脚305的分布范围的增大，扇出走线307的分布区域也随之增大。而对于特定尺寸和分辨率的阵列基板，扇出走线307的数量是一定的，所以此时扇出走线307的分布密度将会减小，相邻的两个扇出走线307之间的间隔距离变大。这样也就降低 了扇出走线307之间的相互干扰，从而提高了检测结果的准确性。
同时，第一测试管脚305的分布密度降低也会使得与该检测线路连接的外部测试设备的测试端口中相应走线的分布密度降低，这有助于改善外部测试设备的测试端口处存在的电磁干扰现象，从而进一步提高检测结果的准确性。
此外还需要说明的是，在本发明的其他实施例中，相邻的第一测试管脚305之间存在的第二测试管脚306的数量还可以不相同，本发明同样不限于此。例如，如图5所示，在本发明的一个实施例中，相邻的第一测试管脚305之间既可以存在一个第二测试管脚306，也可以存在两个第二测试管脚306。
本发明还提供了一种阵列基板，该阵列基板包括如上所述的检测线路。外部测试设备通过该检测线路来对阵列基板进行检测。
从上述描述中可以看出，本发明所提供的阵列基板检测线路中，信号管脚通过扇出走线连接至部分测试管脚，并且，与信号管脚连接的测试管脚均互不相邻。因此相较于现有的与信号管脚连接的测试管脚的分布方式，扇出走线的走线空间更大。这也就使得扇出走线不需要依靠增加走线高度，即依靠增大测试管脚区与管脚区之间的间隔距离，来满足走线长度、宽度和间隔等设计工艺的要求。因此，相较于现有的检测线路，本发明所提供的阵列基板检测线路的高度更低，占用面积更小，有利于窄边框液晶显示器的设计与产生。
应该理解的是，本发明所公开的实施例不限于这里所公开的特定结构，而应当延伸到相关领域的普通技术人员所理解的这些特征的等同替代。还应当理解的是，在此使用的术语仅用于描述特定实施例的目的，而并不意味着限制。
说明书中提到的“一个实施例”或“实施例”意指结合实施例描述的特定特征、结构或特性包括在本发明的至少一个实施例中。因此，说明书通篇各个地方出现的短语“一个实施例”或“实施例”并不一定均指同一个实施例。
为了方便，在此使用的多个项目、结构单元、组成单元和/或材料可出现在共同列表中。然而，这些列表应解释为该列表中的每个元素分别识别为单独唯一的成员。因此，在没有反面说明的情况下，该列表中没有一个成员可仅基于它们出现在共同列表中便被解释为相同列表的任何其它成员的实际等同物。另外，在此还可以连同针对各元件的替代一起来参照本发明的各种实施例和示例。应当理解的是，这些实施例、示例和替代并不解释为彼此的等同物，而被认为是本发明的单独自主的代表。
此外，所描述的特征、结构或特性可以任何其他合适的方式结合到一个或多个实施例中。在上面的描述中，提供一些具体的细节，例如长度、宽度、形状等，以提供对本发明的实施例的全面理解。然而，相关领域的技术人员将明白，本发明无需上述一个或多个具 体的细节便可实现，或者也可采用其它方法、组件、材料等实现。在其它示例中，周知的结构、材料或操作并未详细示出或描述以免模糊本发明的各个方面。
虽然上述示例用于说明本发明在一个或多个应用中的原理，但对于本领域的技术人员来说，在不背离本发明的原理和思想的情况下，明显可以在形式上、用法及实施的细节上作各种修改而不用付出创造性劳动。因此，本发明由所附的权利要求书来限定。

Claims (20)

  1. 一种阵列基板的检测线路，其中，所述检测线路包括：
    信号管脚区，其包括多个信号管脚，所述信号管脚与阵列基板中的信号线对应连接；
    测试管脚区，其包括多个测试管脚；
    扇出走线区，其连接在信号管脚区与测试管脚区之间，包括多条扇出走线，所述信号管脚通过扇出走线连接至部分测试管脚，与信号管脚连接的测试管脚均互不相邻，以使得扇出走线区的高度减小。
  2. 如权利要求1所述的检测线路，其中，所述信号管脚区中信号管脚的分布密度小于所述测试管脚区中测试管脚的分布密度。
  3. 如权利要求1所述的检测线路，其中，所述测试管脚区包括第一测试管脚和第二测试管脚，各个第一测试管脚与扇出走线对应连接，第二测试管脚不与扇出走线连接，相邻的第一测试管脚之间存在有至少一个第二测试管脚。
  4. 如权利要求2所述的检测线路，其中，所述测试管脚区包括第一测试管脚和第二测试管脚，各个第一测试管脚与扇出走线对应连接，第二测试管脚不与扇出走线连接，相邻的第一测试管脚之间存在有至少一个第二测试管脚。
  5. 如权利要求3所述的检测线路，其中，相邻的第一测试管脚之间存在的第二测试管脚的数量相同。
  6. 如权利要求1所述的检测线路，其中，所述信号线包括数据线。
  7. 如权利要求1所述的检测线路，其中，所述信号线包括栅极线。
  8. 如权利要求1所述的检测线路，其中，所述测试管脚在测试管脚区呈“一”字型均匀排列。
  9. 如权利要求8所述的检测线路，其中，所述信号管脚在信号管脚区沿平行于测试管脚区的方向呈“一”字型均匀排列。
  10. 如权利要求1所述的检测线路，其中，所述测试管脚由导电材质构成。
  11. 一种阵列基板，其中，所述阵列基板包括检测线路，所述检测线路包括：
    信号管脚区，其包括多个信号管脚，所述信号管脚与阵列基板中的信号线对应连接；
    测试管脚区，其包括多个测试管脚；
    扇出走线区，其连接在信号管脚区与测试管脚区之间，包括多条扇出走线，所述信号管脚通过扇出走线连接至部分测试管脚，与信号管脚连接的测试管脚均互不相邻，以使得扇出走线区的高度减小。
  12. 如权利要求11所述的阵列基板，其中，所述信号管脚区中信号管脚的分布密度 小于所述测试管脚区中测试管脚的分布密度。
  13. 如权利要求11所述的阵列基板，其中，所述测试管脚区包括第一测试管脚和第二测试管脚，各个第一测试管脚与扇出走线对应连接，第二测试管脚不与扇出走线连接，相邻的第一测试管脚之间存在有至少一个第二测试管脚。
  14. 如权利要求12所述的阵列基板，其中，所述测试管脚区包括第一测试管脚和第二测试管脚，各个第一测试管脚与扇出走线对应连接，第二测试管脚不与扇出走线连接，相邻的第一测试管脚之间存在有至少一个第二测试管脚。
  15. 如权利要求13所述的阵列基板，其中，相邻的第一测试管脚之间存在的第二测试管脚的数量相同。
  16. 如权利要求11所述的阵列基板，其中，所述信号线包括数据线。
  17. 如权利要求11所述的阵列基板，其中，所述信号线包括栅极线。
  18. 如权利要求11所述的阵列基板，其中，所述测试管脚在测试管脚区呈“一”字型均匀排列。
  19. 如权利要求18所述的阵列基板，其中，所述信号管脚在信号管脚区沿平行于测试管脚区的方向呈“一”字型均匀排列。
  20. 如权利要求11所述的阵列基板，其中，所述测试管脚由导电材质构成。
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