WO2016106870A1 - 一种液晶显示器驱动电路 - Google Patents

一种液晶显示器驱动电路 Download PDF

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Publication number
WO2016106870A1
WO2016106870A1 PCT/CN2015/070925 CN2015070925W WO2016106870A1 WO 2016106870 A1 WO2016106870 A1 WO 2016106870A1 CN 2015070925 W CN2015070925 W CN 2015070925W WO 2016106870 A1 WO2016106870 A1 WO 2016106870A1
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Prior art keywords
level
module
output
input end
gate
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English (en)
French (fr)
Inventor
曹尚操
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TCL China Star Optoelectronics Technology Co Ltd
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Shenzhen China Star Optoelectronics Technology Co Ltd
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Priority to US14/436,591 priority Critical patent/US9799292B2/en
Publication of WO2016106870A1 publication Critical patent/WO2016106870A1/zh
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0283—Arrangement of drivers for different directions of scanning
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery

Definitions

  • the present invention relates to the field of liquid crystal display technology, and in particular, to a liquid crystal display driving circuit.
  • the array substrate row driving technology is to use the front-end array (Array) process of the existing thin film transistor liquid crystal display to fabricate the gate row scanning driving signal circuit on the array substrate of the liquid crystal display panel to realize the driving technology for gate progressive scanning.
  • Array front-end array
  • the gate driving integrated circuit portion can be omitted, thereby reducing the product cost from the material cost and the manufacturing process.
  • the gate row scan driving signal circuit integrated on the array substrate by the array substrate row driving technology is also referred to as an array substrate row driving circuit.
  • the gate driving signal of the current stage is used as a trigger signal generated by the next-stage gate driving signal, resulting in instability of the GOA circuit level transmission.
  • the embodiment of the invention provides a liquid crystal display driving circuit, which realizes the separation of the level transmission signal and the gate driving signal, and improves the stability of the driving circuit level transmission.
  • the invention provides a liquid crystal display driving circuit, and the liquid crystal display driving circuit comprises: a scanning control module, a level transfer module and a gate driving signal output module, wherein:
  • the control level input end of the scan control module inputs a voltage for controlling the forward and reverse scan, and the level signal input end of the scan control module is connected to the upper level pass signal output by the level transfer module, and the scan control The output end of the module outputs a scan control signal to the output control signal input end of the gate drive signal output module and the level transfer control signal input end of the level transfer module;
  • the gate driving signal output module includes a first gate driving signal output sub-module, a second gate driving signal output sub-module, and a first inverter, and the scan control signal output by the scan control module passes through the first inversion Sub-module output control signal input end of the first gate drive signal output sub-module and sub-module output control signal input end of the second gate drive signal output sub-module, the first gate drive signal output
  • the clock input terminal of the sub-module inputs CK1 and the clock input terminal of the second gate drive signal output sub-module inputs CK2;
  • the clock input end of the level transfer module inputs CKV;
  • the clock cycle of CK1 and CK2 is 1/2 of the clock cycle of CKV, and the high-level occurrence time of CK1 and the high-level occurrence time of CK2 do not coincide with each other.
  • the scan control module transmits the level transfer signal to the level transfer module and the gate drive signal module respectively by receiving the upper level pass signal output by the level transfer module, and the level transfer module is low in the CKV.
  • the gate driving signal module outputs two levels of gate driving signals when the high level of each of CK1 and CK2 arrives, thereby realizing the level transmitting signal and the gate driving signal. Separation improves the stability of the drive circuit level transmission.
  • FIG. 1 is a schematic diagram of a mechanism of a liquid crystal display driving circuit according to an embodiment of the present invention
  • FIG. 2 is a schematic structural diagram of a liquid crystal display driving circuit according to another embodiment of the present invention.
  • FIG. 3 is a schematic structural diagram of a liquid crystal display driving circuit according to another embodiment of the present invention.
  • FIG. 4 is a schematic structural diagram of a liquid crystal display driving circuit according to another embodiment of the present invention.
  • FIG. 5 is a timing chart of operation of a liquid crystal display driving circuit according to an embodiment of the present invention.
  • FIG. 1 is a schematic structural diagram of a liquid crystal display driving circuit according to an embodiment of the present invention.
  • the liquid crystal display driving circuit includes a scan control module 100, a gate driving signal output module 200, and The pass-through module 300, wherein:
  • the control level input terminal 11 of the scan control module 100 inputs a voltage for controlling the forward and reverse scan, and the level signal input terminal 12 of the scan control module 100 accesses the upper level pass signal output by the level transfer module, and the scan
  • the output terminal 13 of the control module 100 outputs a scan control signal to the output control signal input terminal 14 of the gate drive signal output module 200 and the level transfer control signal input terminal 15 of the level transfer module 300, respectively.
  • the gate driving signal output module 200 includes a first gate driving signal output sub-module 210, a second gate driving signal output sub-module 220, and a first inverter 230.
  • the scan control signal output by the scan control module 100 After the first inverter 230 is input, the submodule output control signal input terminal 16 of the first gate drive signal output submodule 210 and the submodule output control signal input terminal 17 of the second gate drive signal output submodule are input.
  • the clock input terminal 18 of the first gate driving signal output sub-module 210 inputs CK1
  • the clock input terminal 19 of the second gate driving signal output sub-module 220 inputs CK2.
  • the clock input terminal 20 of the level transfer module inputs CKV, wherein the clock cycles of CK1 and CK2 are 1/2 of the clock period of CKV, and the high-level occurrence time of CK1 and the high-level occurrence time of CK2 do not coincide with each other. .
  • the scan control module transmits the level transmission signal to the level transmission module and the gate driving signal module respectively by receiving the upper level transmission signal output by the level transmission module, and the level transmission module is in the CKV.
  • the gate driving signal module outputs two levels of gate driving signals when the respective high levels of CK1 and CK2 arrive, thereby realizing the level transmission signal and the gate driving signal.
  • the separation improves the stability of the drive circuit level transmission.
  • FIG. 2 is a schematic structural diagram of a liquid crystal display driving circuit according to another embodiment of the present invention, as the picture shows:
  • the level signal module includes a first NAND gate 3001, a second NAND gate 3002, a third NAND gate 3003, and a fourth NAND gate 3004.
  • the first input end of the first NAND gate 3001 is connected.
  • a scan control signal output by the scan control module 100 a first input end of the second NAND gate 3002 is connected to an output end of the first NAND gate 3001, and a first input of the third NAND gate 3003
  • the first input end of the fourth NAND gate 3004 is connected to the output end of the third NAND gate 3002, and the first NAND gate 3001 is connected to the output end of the second NAND gate 3002.
  • the second input end is connected to the output end of the second NAND gate 3002, and the second input end of the second NAND gate 3002 and the second input end of the third NAND gate 3003 are respectively connected to the fourth
  • the output end of the NOT gate 3004 the second input end of the fourth NAND gate 3004 is connected to the CKV, and the output end of the fourth NAND gate 3004 outputs a level transmission signal.
  • the level signal module 300 includes a latch submodule 310 and a level signal generating submodule 320.
  • the latch submodule 310 includes the first NAND gate 3001 and the second NAND gate 3002. After the gate driving signal of the current stage and the gate driving signal of the next stage are generated, the corresponding signal of the current stage is high level, so that the gate driving signal output module of the current stage does not work when the driving circuit of the next stage is working. Affected by CK1 and CK2.
  • the level signal generation sub-module 320 includes a third NAND gate 3003 and a fourth NAND gate 3004 for generating a sub-module for generating a level-transmitted signal.
  • the first gate drive signal output sub-module includes a ninth NAND gate 2101 and an odd number of inverters, and the first input end of the ninth NAND gate 2101 inputs the first reverse output of the scan control module.
  • the phase inversion reverses the scan control signal, the second output of the ninth NAND gate 2101 inputs CK1, and the odd number of inverters pass through the input of the previous inverter and the output of the latter inverter
  • the connected mode is connected, the input of the first inverter is connected to the output of the ninth NAND gate 2101, and the output of the last inverter outputs a gate drive signal.
  • the second gate driving signal output sub-module includes a tenth NAND gate 2201 and an odd number of inverters, and the first input end of the tenth NAND gate 2201 is input to the first output of the scan control module 100.
  • the inverter reverses the scan control signal, the second output of the tenth NAND gate 2201 inputs CK2, and the odd inverter passes the output of the previous inverter and the output of the latter inverter
  • the terminal connection mode is connected to the phase connection.
  • the input terminal of the first inverter is connected to the output terminal of the tenth NAND gate 2201, and the output terminal of the last inverter outputs a gate drive signal.
  • the scan control module 100 includes a first transmitter 1001 and a second transmitter 1002.
  • the sweep The control level input terminal of the control module 100 includes a first control level input end and a second control level input end, and the first control level input end and the second control level input end are respectively connected to the forward and reverse directions.
  • Scanning control voltages U2D and D2U when the scan control voltage U2D is at a high level and D2U is at a low level, the second transmitter 1002 is turned on, the drive circuit is in a forward scan state, and when the scan control voltage U2D is low
  • the first transmitter 1001 is turned on, and the driving circuit is in a reverse scanning state.
  • the level signal input end of the scan control module 100 includes a first level signal input end and a second level signal input end, and the first stage signal input end is used to access the output of the first stage level transfer module.
  • the level-transmitting signal is used to access the level-transmitted signal output by the next-stage level transmitting module.
  • the scan control module transmits the level transmission signal to the level transmission module and the gate driving signal module respectively by receiving the upper level transmission signal output by the level transmission module, and the level transmission module is in the CKV.
  • the gate driving signal module outputs two levels of gate driving signals when the respective high levels of CK1 and CK2 arrive, thereby realizing the level transmission signal and the gate driving signal.
  • the separation improves the stability of the drive circuit level transmission.
  • FIG. 3 is a schematic structural diagram of a liquid crystal display driving circuit according to another embodiment of the present invention, as shown in the following figure:
  • the level signal module includes a fifth NAND gate 3005, a sixth NAND gate 3006, a seventh NAND gate 3007, and an eighth NAND gate 3008.
  • the first input end of the fifth NAND gate 3005 is connected.
  • the scan control signal output by the scan control module 100, the output end of the fifth NAND gate 3005 is respectively connected to the second input end of the fifth NAND gate 3005 and the first of the sixth NAND gate 3006 Input end, a first input end of the seventh NAND gate 3007 is connected to an output end of the sixth NAND gate 3006, and a first input end of the eighth NAND gate 3008 is connected to the seventh NAND gate
  • the output end of the third NAND gate 3006 and the second input end of the seventh NAND gate 3007 are respectively connected to the output end of the eighth NAND gate 3008, the eighth The second input of the NAND gate 3008 inputs CKV, and the output of the eighth NAND gate 3008 outputs a level-transmitted signal.
  • the level signal module 300 includes a latch submodule 320 and a level signal generating submodule 330.
  • the latch submodule 300 includes the fifth NAND gate 3005 and the sixth NAND gate 3006. It is used to ensure the generation of the gate drive signal and the next-stage gate drive signal after the generation The number is high, so that the gate drive signal output module of this stage is not affected by CK1 and CK2 when the next stage drive circuit operates.
  • the level signal generating sub-module 330 includes a seventh NAND gate 3007 and an eighth NAND gate 3008 for generating a sub-module for generating a level-transmitted signal.
  • the first gate driving signal output sub-module includes a first transmitter 2102 and an even number of inverters, the first transmitter 2102 includes a P-channel enhancement type field effect transistor and an N-channel enhancement type field effect a transistor, the even number of inverters are connected by a connection of an input end of the previous inverter and an output end of the latter inverter, and an input end of the first inverter is connected to the first transmitter 2102 a source of the P-channel enhancement type field effect transistor and a source of the N-channel enhancement type field effect transistor, and an output terminal of the last inverter outputs a gate driving signal, and a P groove in the first transmitter 2102
  • the drain of the track enhancement type field effect transistor and the drain of the N-channel enhancement type field effect transistor are connected to CK1.
  • the first gate driving signal output sub-module includes a second transmitter 2202 and an even number of inverters
  • the second transmitter 2202 includes a P-channel enhancement type field effect transistor and an N-channel enhancement type field effect a transistor
  • the even number of inverters are connected by a connection of an input end of the previous inverter and an output end of the latter inverter
  • an input end of the first inverter is connected to the second transmitter 2202 a source of the P-channel enhancement type field effect transistor and a source of the N-channel enhancement type field effect transistor
  • an output terminal of the last inverter outputs a gate driving signal, and a P groove in the second transmitter 2202
  • the drain of the track enhancement type field effect transistor and the drain of the N-channel enhancement type field effect transistor are connected to CK2.
  • the control level input end of the scan control module 100 includes a first control level input end and a second control level input end, and the first control level input end and the second control level input end are respectively connected to the positive Reverse scan control voltage U2D and D2U, when the scan control voltage U2D is high level and D2U is low level, the drive circuit is in a forward scan state, when the scan control voltage U2D is low level and D2U is high level The drive circuit is in a reverse scan state.
  • the level signal input end of the scan control module 100 includes a first level signal input end and a second level signal input end, and the first stage signal input end is used to access the output of the first stage level transfer module.
  • the level-transmitting signal is used to access the level-transmitted signal output by the next-stage level transmitting module.
  • the scan control module transmits the level transmission signal to the level transmission module and the gate driving signal module respectively by receiving the upper level transmission signal output by the level transmission module, where the level transmission module is When the low level of CKV arrives, the signal of the current stage is outputted, and the gate driving signal module outputs two levels of gate driving signals when the high level of each of CK1 and CK2 arrives, thereby realizing the level transmitting signal and the gate.
  • the separation of the drive signals improves the stability of the drive circuit level transmission.
  • FIG. 4 is a schematic structural diagram of another liquid crystal display starting circuit according to an embodiment of the present invention
  • FIG. 5 is a working timing diagram of the liquid crystal display driving circuit, as shown in the figure:
  • the working circuit is connected by a two-stage liquid crystal display driving circuit, and the level signal output end of the level transmitting module of the driving circuit of the current stage is connected to the first stage signal input end of the scanning control module of the next stage driving circuit. 25 and the second stage signal input terminal 26, the level signal output terminal 24 of the level transfer module of the next stage drive circuit is connected to the first stage signal input terminal 22 and the second stage pass of the scan control module of the drive circuit of the first stage Signal input terminal 23.
  • the level transfer module of the next stage driving circuit further includes a second NAND gate 3009. When the clock CKV is at a high level, the clock input end of the level transfer module is connected to the low level after being reversed by the second inverter. CKV.
  • the first stage signal input terminal 21 is connected to the upper level transmitting signal output by the level transmitting module, and if the signal of the upper level is low level,
  • the scan control module of the driving circuit of the current stage outputs a low-level scan control signal Qn-2 to the output control signal input end of the gate drive signal output module of the present stage and the level transfer control signal input end of the level transfer module.
  • the level transmitting module After receiving the low level Qn-2, the level transmitting module generates a low level local level signal Qn when the CKV low level arrives.
  • the low-level scan signal is respectively connected to the sub-module output control signal input end and the second gate drive signal output end of the first gate drive signal output sub-module after being reversed by the first inverter
  • the submodule of the module outputs a control signal input end, and when the clock input end of the first gate drive signal output submodule receives the high level CK1, the second gate drive signal output submodule receives the clock input end a low level CK2, the first gate driving signal output submodule outputs a driving signal Gn for driving the gate of the current stage, and when the clock input end of the first gate driving signal output submodule receives a low level CK1, the clock input end of the second gate driving signal output sub-module receives CK2 of a high level, and the second gate driving signal output sub-module outputs a driving signal Gn+1 for driving the
  • the level transmitting module After receiving the low level Qn, the level transmitting module generates a low level next level transmission signal Qn+2 when the CKV high level arrives.
  • the first stage signal input of the scan control module of the next stage drive circuit The terminal 25 and the second-stage signal input terminal 26 are respectively connected to the low-level Qn generated by the level-level transmitting module of the current level, and the scanning signal of the low level is reversed by the first inverter in the next-stage driving circuit.
  • the first gate driving signal output submodule in the next stage driving circuit outputs a driving signal Gn+2 driving the gate of the current stage, when the first gate in the next stage driving circuit
  • the clock input end of the pole drive signal output sub-module receives CK1 of a low level
  • the clock input end of the second gate drive signal output sub-module of the next-stage drive circuit receives a high level CK2, the lower The first in the primary drive circuit
  • the two gate drive signal output sub-module outputs a drive signal Gn+3 that drives the next-stage gate
  • the level transmission control signal input end of the level transmission module receives the low level transmission control signal, and the clock input end of the level transmission module is connected to the low level In the case of CKV, the level transfer module outputs a high level of the current level signal.
  • the first stage signal input end is connected to the next stage level transmission signal output by the level transmission module, and if the next stage level transmission signal is low level, the scan control module respectively drives the gate drive signal
  • the output control signal input end of the output module and the level control signal input end of the level transfer module output a low level scan control signal.
  • the level transmitting module After receiving the low level Qn+2, the level transmitting module generates a low level local level signal Qn when the CKV low level arrives.
  • the low-level scan signal is respectively connected to the sub-module output control signal input end and the second gate drive signal output end of the first gate drive signal output sub-module after being reversed by the first inverter
  • the submodule of the module outputs a control signal input end, and when the clock input end of the first gate drive signal output submodule receives the high level CK1, the second gate drive signal output submodule receives the clock input end a low level CK2, the first gate driving signal output sub-module outputs a driving signal Gn+3 for driving the gate of the current stage, and receives a low voltage when the clock input end of the first gate driving signal output sub-module receives Flat CK1, the clock input end of the second gate drive signal output sub-module receives CK2 of a high level, and the second gate drive signal output sub-module outputs a drive
  • the level transmitting module After receiving the low level Qn, the level transmitting module generates a low level next level transmission signal Qn-2 when the CKV high level arrives.
  • the first stage signal input terminal 25 and the second stage signal input terminal 26 of the scan control module of the next stage driving circuit respectively respectively access the low level Qn generated by the level transmitting module of the level, and the low level scanning signal
  • the sub-module output control signal input terminal and the second gate driving signal of the first gate driving signal output sub-module in the next-stage driving circuit are respectively respectively connected.
  • the submodule output control signal input end of the output submodule when the clock input end of the first gate drive signal output submodule in the next stage drive circuit receives the high level CK1, the next stage drive circuit
  • the clock input terminal of the second gate driving signal output sub-module receives CK2 of a low level
  • the first gate driving signal output sub-module of the next-stage driving circuit outputs a driving signal Gn for driving the gate of the current stage +1
  • the clock input terminal receives a high level CK2
  • the second gate driving signal output submodule in the next stage driving circuit outputs a driving signal Gn for driving the next stage gate.
  • the level transmission control signal input end of the level transmission module receives a low level transmission control signal, and when the clock input end of the level transmission module is connected to a low level CKV, the level transmission module outputs a high level The level of the signal.
  • the level-transmitting signal for starting the first-level and second-level high-level output signals of the liquid crystal display is started to be a low level; when the driving circuit is in the reverse scanning, the generating is started.
  • the level signal of the last stage of the liquid crystal display and the high level output signal of the penultimate stage is low.
  • the scan control module transmits the level transmission signal to the level transmission module and the gate driving signal module respectively by receiving the upper level transmission signal output by the level transmission module, and the level transmission module is in the CKV.
  • the gate driving signal module outputs two levels of gate driving signals when the respective high levels of CK1 and CK2 arrive, thereby realizing the level transmission signal and the gate driving signal.
  • the separation improves the stability of the drive circuit level transmission.

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Abstract

一种液晶显示器驱动电路，所述驱动电路包括：扫描控制模块（100）、栅极驱动信号输出模块（200）和级传模块（300），其中：所述扫描控制模块（100）的控制电平输入端（11）输入控制正反向扫描的电压，所述扫描控制模块（100）的输出端（13）分别向栅极驱动信号输出模块（200）和级传模块（300）输出扫描控制信号；所述栅极驱动信号输出模块（200）包括第一栅极驱动信号输出子模块（210）、第二栅极驱动信号输出子模块（220）以及第一反相器（230），所述第一栅极驱动信号输出子模块（210）的时钟输入端（18）输入CK1，所述第二栅极驱动信号输出子模块（220）的时钟输入端（19）输入CK2；所述级传模块（300）的时钟输入端（20）输入CKV。上述设计可以提高驱动电路级传的稳定性。

Description

一种液晶显示器驱动电路
本发明要求2014年12月31日递交的发明名称为“一种液晶显示器驱动电路”的申请号201410856540.X的在先申请优先权，上述在先申请的内容以引入的方式并入本文本中。
技术领域
本发明涉及液晶显示技术领域，尤其涉及一种液晶显示器驱动电路。
背景技术
近些年来，液晶显示装置的发展呈现出高集成度、低成本的发展趋势。其中一项非常重要的技术就是阵列基板行驱动(Gate Driver on Array，GOA)技术量产化的实现。阵列基板行驱动技术就是利用现有的薄膜晶体管液晶显示器的前段阵列(Array)制程将栅极行扫描驱动信号电路制作在液晶显示面板的阵列基板上，实现对栅极逐行扫描的驱动技术。利用阵列基板行驱动技术将栅极行扫描驱动信号电路集成在液晶显示面板的阵列基板上，可以省掉栅极驱动集成电路部分，从而从材料成本和制作工艺两方面降低产品成本。这种利用阵列基板行驱动技术集成在阵列基板上的栅极行扫描驱动信号电路也称阵列基板行驱动电路。但是目前很多GOA电路存在以下问题：GOA电路输出的本级栅极驱动信号后，将本级栅极驱动信号作为下一级栅极驱动信号产生的触发信号，导致GOA电路级传的不稳定。
发明内容
本发明实施例提供一种液晶显示器驱动电路，实现了级传信号和栅极驱动信号的分离，提高了驱动电路级传的稳定性。
本发明提供了一种液晶显示器驱动电路，所述液晶显示器驱动电路包括：扫描控制模块、级传模块和栅极驱动信号输出模块，其中：
所述扫描控制模块的控制电平输入端输入控制正反向扫描的电压，扫描控制模块的级传信号输入端接入级传模块输出的上一级级传信号，所述扫描控制 模块的输出端分别向栅极驱动信号输出模块的输出控制信号输入端和级传模块的级传控制信号输入端输出扫描控制信号；
所述栅极驱动信号输出模块包括第一栅极驱动信号输出子模块、第二栅极驱动信号输出子模块以及第一反相器，所述扫描控制模块输出的扫描控制信号经过第一反相器后输入所述第一栅极驱动信号输出子模块的子模块输出控制信号输入端和第二栅极驱动信号输出子模块的子模块输出控制信号输入端，所述第一栅极驱动信号输出子模块的时钟输入端输入CK1，所述第二栅极驱动信号输出子模块的时钟输入端输入CK2；
所述级传模块的时钟输入端输入CKV；
其中，CK1和CK2的时钟周期为CKV的时钟周期的1/2，并且CK1的高电平出现时间与CK2的高电平出现时间相互不重合。
本发明中扫描控制模块通过接收级传模块输出的上一级级传信号，分别将所述级传信号传输给所述级传模块和栅极驱动信号模块，所述级传模块在CKV的低电平到达时输出本级级传信号，所述栅极驱动信号模块在CK1和CK2各自的高电平到达时，分别输出两级栅极驱动信号，实现了级传信号和栅极驱动信号的分离，提高了驱动电路级传的稳定性。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本发明实施例提供的一种液晶显示器驱动电路的机构示意图；
图2是本发明另一实施例提供的一种液晶显示器驱动电路的结构示意图；
图3是本发明又一实施例提供的一种液晶显示器驱动电路的结构示意图；
图4是本发明又已实施例提供的一种液晶显示器驱动电路的结构示意图；
图5是本发明实施例提供的液晶显示器驱动电路的工作时序图。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
如图1所示是本发明实施例提供的一种液晶显示器驱动电路的结构示意图，是本发明如图所示，所述液晶显示器驱动电路包括扫描控制模块100、栅极驱动信号输出模块200和级传模块300，其中：
所述扫描控制模块100的控制电平输入端11输入控制正反向扫描的电压，扫描控制模块100的级传信号输入端12接入级传模块输出的上一级级传信号，所述扫描控制模块100的输出端13分别向栅极驱动信号输出模块200的输出控制信号输入端14和级传模块300的级传控制信号输入端15输出扫描控制信号。
所述栅极驱动信号输出模块200包括第一栅极驱动信号输出子模块210、第二栅极驱动信号输出子模块220以及第一反相器230，所述扫描控制模块100输出的扫描控制信号经过第一反相器230后输入所述第一栅极驱动信号输出子模块210的子模块输出控制信号输入端16和第二栅极驱动信号输出子模块的子模块输出控制信号输入端17，所述第一栅极驱动信号输出子模块210的时钟输入端18输入CK1，所述第二栅极驱动信号输出子模块220的时钟输入端19输入CK2。
所述级传模块的时钟输入端20输入CKV，其中，CK1和CK2的时钟周期为CKV的时钟周期的1/2，并且CK1的高电平出现时间与CK2的高电平出现时间相互不重合。
本实施例中扫描控制模块通过接收级传模块输出的上一级级传信号，分别将所述级传信号传输给所述级传模块和栅极驱动信号模块，所述级传模块在CKV的低电平到达时输出本级级传信号，所述栅极驱动信号模块在CK1和CK2各自的高电平到达时，分别输出两级栅极驱动信号，实现了级传信号和栅极驱动信号的分离，提高了驱动电路级传的稳定性。
图2是本发明又一实施例提供的一种液晶显示器驱动电路的结构示意图， 如图所示：
所述级传信号模块包括第一与非门3001、第二与非门3002、第三与非门3003和第四与非门3004，所述第一与非门3001的第一输入端接入所述扫描控制模块100输出的扫描控制信号，所述第二与非门3002的第一输入端连接所述第一与非门3001的输出端，所述第三与非门3003的第一输入端连接所述第二与非门3002的输出端，所述第四与非门3004的第一输入端连接所述第三与非门3002的输出端，所述第一与非门3001的第二输入端连接所述第二与非门3002的输出端，所述第二与非门3002的第二输入端、所述第三与非门3003的第二输入端分别连接所述第四与非门3004的输出端，所述第四与非门3004的第二输入端连接CKV，所述第四与非门3004的输出端输出级传信号。
可选的，所述级传信号模块300包括锁存子模块310和级传信号产生子模块320，所述锁存子模块310包括所述第一与非门3001和第二与非门3002，用于保证本级栅极驱动信号和下一级栅极驱动信号产生后，对应的本级级传信号为高电平，以使本级栅极驱动信号输出模块在下一级驱动电路工作时不受CK1和CK2的影响。所述级传信号产生子模块320包括第三与非门3003和第四与非门3004，用于产生子模块用于产生级传信号。
所述第一栅极驱动信号输出子模块包括第九与非门2101和奇数个反相器，所述第九与非门2101的第一输入端输入所述扫描控制模块输出的经过第一反相器反向的扫描控制信号，所述第九与非门2101的第二输出端输入CK1，所述奇数个反相器通过前一个反相器的输入端和后一个反相器的输出端相连接的方式连接相连接，最前一个反相器的输入端连接所述第九与非门2101的输出端，最后一个反相器的输出端输出栅极驱动信号。
所述第二栅极驱动信号输出子模块包括第十与非门2201和奇数个反相器，所述第十与非门2201的第一输入端输入所述扫描控制模块100输出的经过第一反相器反向的扫描控制信号，所述第十与非门2201的第二输出端输入CK2，所述奇数个反相器通过前一个反相器的输入端和后一个反相器的输出端相连接的方式连接相连接，最前一个反相器的输入端连接所述第十与非门2201的输出端，最后一个反相器的输出端输出栅极驱动信号。
所述扫描控制模块100包括第一传输器1001和第二传输器1002。所述扫 描控制模块100的控制电平输入端包括第一控制电平输入端和第二控制电平输入端，所述第一控制电平输入端和第二控制电平输入端分别接入正反向扫描控制电压U2D和D2U，当扫描控制电压U2D为高电平且D2U为低电平时，所述第二传输器1002导通，所述驱动电路处于正向扫描状态，当扫描控制电压U2D为低电平且D2U为高电平时，所述第一传输器1001导通，所述驱动电路处于反向扫描状态。
所述扫描控制模块100的级传信号输入端包括第一级传信号输入端和第二级传信号输入端，所述第一级传信号输入端用于接入上一级级传模块输出的级传信号，第二级传信号输入端用于接入下一级级传模块输出的级传信号。
本实施例中扫描控制模块通过接收级传模块输出的上一级级传信号，分别将所述级传信号传输给所述级传模块和栅极驱动信号模块，所述级传模块在CKV的低电平到达时输出本级级传信号，所述栅极驱动信号模块在CK1和CK2各自的高电平到达时，分别输出两级栅极驱动信号，实现了级传信号和栅极驱动信号的分离，提高了驱动电路级传的稳定性。
图3是本发明又一实施例提供的一种液晶显示器驱动电路的结构示意图，如图所示：
所述级传信号模块包括第五与非门3005、第六与非门3006、第七与非门3007和第八与非门3008，所述第五与非门3005的第一输入端接入所述扫描控制模块100输出的扫描控制信号，所述第五与非门3005的输出端分别连接所述第五与非门3005的第二输入端和所述第六与非门3006的第一输入端，所述第七与非门3007的第一输入端连接所述第六与非门3006的输出端，所述第八与非门3008的第一输入端连接所述第七与非门3007的输出端，所述第六与非门3006的第二输入端、所述第七与非门3007的第二输入端分别连接所述第八与非门3008的输出端，所述第八与非门3008的第二输入端输入CKV，所述第八与非门3008的输出端输出级传信号。
可选的，所述级传信号模块300包括锁存子模块320和级传信号产生子模块330，所述锁存子模块300包括所述第五与非门3005和第六与非门3006，用于保证本级栅极驱动信号和下一级栅极驱动信号产生后，对应的本级级传信 号为高电平，以使本级栅极驱动信号输出模块在下一级驱动电路工作时不受CK1和CK2的影响。所述级传信号产生子模块330包括第七与非门3007和第八与非门3008，用于产生子模块用于产生级传信号。
所述第一栅极驱动信号输出子模块包括第一传输器2102和偶数个反相器，所述第一传输器2102包括一个P沟道增强型场效应晶体管和一个N沟道增强型场效应晶体管，偶数个反相器通过前一个反相器的输入端和后一个反相器的输出端相连接的方式连接相连接，最前一个反相器的输入端连接所述第一传输器2102中的P沟道增强型场效应晶体管的源极和N沟道增强型场效应晶体管的源极，最后一个反相器的输出端输出栅极驱动信号，所述第一传输器2102中的P沟道增强型场效应晶体管的漏极和N沟道增强型场效应晶体管的漏极连接CK1。
所述第一栅极驱动信号输出子模块包括第二传输器2202和偶数个反相器，所述第二传输器2202包括一个P沟道增强型场效应晶体管和一个N沟道增强型场效应晶体管，偶数个反相器通过前一个反相器的输入端和后一个反相器的输出端相连接的方式连接相连接，最前一个反相器的输入端连接所述第二传输器2202中的P沟道增强型场效应晶体管的源极和N沟道增强型场效应晶体管的源极，最后一个反相器的输出端输出栅极驱动信号，所述第二传输器2202中的P沟道增强型场效应晶体管的漏极和N沟道增强型场效应晶体管的漏极连接CK2。
所述扫描控制模块100的控制电平输入端包括第一控制电平输入端和第二控制电平输入端，所述第一控制电平输入端和第二控制电平输入端分别接入正反向扫描控制电压U2D和D2U，当扫描控制电压U2D为高电平且D2U为低电平时，所述驱动电路处于正向扫描状态，当扫描控制电压U2D为低电平且D2U为高电平时，所述驱动电路处于反向扫描状态。
所述扫描控制模块100的级传信号输入端包括第一级传信号输入端和第二级传信号输入端，所述第一级传信号输入端用于接入上一级级传模块输出的级传信号，第二级传信号输入端用于接入下一级级传模块输出的级传信号。
本实施例中扫描控制模块通过接收级传模块输出的上一级级传信号，分别将所述级传信号传输给所述级传模块和栅极驱动信号模块，所述级传模块在 CKV的低电平到达时输出本级级传信号，所述栅极驱动信号模块在CK1和CK2各自的高电平到达时，分别输出两级栅极驱动信号，实现了级传信号和栅极驱动信号的分离，提高了驱动电路级传的稳定性。
图4是本发明实施例提供的又一液晶显示器启动电路的结构示意图，图5是所述液晶显示器驱动电路的工作时序图，如图所示：
如图4所示工作电路由两级液晶显示器驱动电路相连而成，本级驱动电路的级传模块的级传信号输出端连接下一级驱动电路的扫描控制模块的第一级传信号输入端25和第二级传信号输入端26，下一级驱动电路的级传模块的级传信号输出端24连接本级驱动电路的扫描控制模块的第一级传信号输入端22和第二级传信号输入端23。下一级驱动电路的级传模块还包括第二与非门3009，当时钟CKV处于高电平时，所述级传模块的时钟输入端接入经过第二反相器反向后的低电平的CKV。
当所述驱动电路处于正向扫描状态时，所述第一级传信号输入端21接入级传模块输出的上一级级传信号，若所述上一级级传信号为低电平，本级驱动电路的扫描控制模块分别向本级栅极驱动信号输出模块的输出控制信号输入端和级传模块的级传控制信号输入端输出低电平的扫描控制信号Qn-2。
所述级传模块接收到低电平的Qn-2后，在CKV低电平到达时产生低电平的本级级传信号Qn。所述低电平的扫描信号经过所述第一反相器反向后分别接入所述第一栅极驱动信号输出子模块的子模块输出控制信号输入端和第二栅极驱动信号输出子模块的子模块输出控制信号输入端，当所述第一栅极驱动信号输出子模块的时钟输入端接收到高电平的CK1，所述第二栅极驱动信号输出子模块的时钟输入端接收低电平的CK2，所述第一栅极驱动信号输出子模块输出驱动本级栅极的驱动信号Gn，当所述第一栅极驱动信号输出子模块的时钟输入端接收到低电平的CK1，所述第二栅极驱动信号输出子模块的时钟输入端接收高电平的CK2，所述第二栅极驱动信号输出子模块输出驱动下一级栅极的驱动信号Gn+1。
所述级传模块接收到低电平的Qn后在CKV高电平到达时产生低电平的下一级级传信号Qn+2。下一级驱动电路的扫描控制模块的第一级传信号输入 端25和第二级传信号输入端26分别接入本级级传模块产生的低电平Qn，所述低电平的扫描信号经过下一级驱动电路中的第一反相器反向后分别接入下一级驱动电路中的第一栅极驱动信号输出子模块的子模块输出控制信号输入端和第二栅极驱动信号输出子模块的子模块输出控制信号输入端，当所述下一级驱动电路中的第一栅极驱动信号输出子模块的时钟输入端接收到高电平的CK1，所述下一级驱动电路中的第二栅极驱动信号输出子模块的时钟输入端接收低电平的CK2，所述下一级驱动电路中的第一栅极驱动信号输出子模块输出驱动本级栅极的驱动信号Gn+2，当所述下一级驱动电路中的第一栅极驱动信号输出子模块的时钟输入端接收到低电平的CK1，所述下一级驱动电路中的第二栅极驱动信号输出子模块的时钟输入端接收高电平的CK2，所述下一级驱动电路中的第二栅极驱动信号输出子模块输出驱动下一级栅极的驱动信号Gn+3。
当所述驱动电路处于反向扫描状态时，所述级传模块的级传控制信号输入端接收低电平的级传控制信号，且所述级传模块的时钟输入端接入低电平的CKV时，所述级传模块输出高电平的本级级传信号。
所述第一级传信号输入端接入级传模块输出的下一级级传信号，若所述下一级级传信号为低电平，所述扫描控制模块分别向所述栅极驱动信号输出模块的输出控制信号输入端和级传模块的级传控制信号输入端输出低电平的扫描控制信号。
所述级传模块接收到低电平的Qn+2后，在CKV低电平到达时产生低电平的本级级传信号Qn。所述低电平的扫描信号经过所述第一反相器反向后分别接入所述第一栅极驱动信号输出子模块的子模块输出控制信号输入端和第二栅极驱动信号输出子模块的子模块输出控制信号输入端，当所述第一栅极驱动信号输出子模块的时钟输入端接收到高电平的CK1，所述第二栅极驱动信号输出子模块的时钟输入端接收低电平的CK2，所述第一栅极驱动信号输出子模块输出驱动本级栅极的驱动信号Gn+3，当所述第一栅极驱动信号输出子模块的时钟输入端接收到低电平的CK1，所述第二栅极驱动信号输出子模块的时钟输入端接收高电平的CK2，所述第二栅极驱动信号输出子模块输出驱动上一级栅极的驱动信号Gn+2。
所述级传模块接收到低电平的Qn后在CKV高电平到达时产生低电平的下一级级传信号Qn-2。下一级驱动电路的扫描控制模块的第一级传信号输入端25和第二级传信号输入端26分别接入本级级传模块产生的低电平Qn，所述低电平的扫描信号经过下一级驱动电路中的第一反相器反向后分别接入下一级驱动电路中的第一栅极驱动信号输出子模块的子模块输出控制信号输入端和第二栅极驱动信号输出子模块的子模块输出控制信号输入端，当所述下一级驱动电路中的第一栅极驱动信号输出子模块的时钟输入端接收到高电平的CK1，所述下一级驱动电路中的第二栅极驱动信号输出子模块的时钟输入端接收低电平的CK2，所述下一级驱动电路中的第一栅极驱动信号输出子模块输出驱动本级栅极的驱动信号Gn+1，当所述下一级驱动电路中的第一栅极驱动信号输出子模块的时钟输入端接收到低电平的CK1，所述下一级驱动电路中的第二栅极驱动信号输出子模块的时钟输入端接收高电平的CK2，所述下一级驱动电路中的第二栅极驱动信号输出子模块输出驱动下一级栅极的驱动信号Gn。
所述级传模块的级传控制信号输入端接收低电平的级传控制信号，且所述级传模块的时钟输入端接入低电平的CKV时，所述级传模块输出高电平的本级级传信号。
当所述驱动电路处于正向扫描时，启动产生液晶显示器的第一级和第二级高电平输出信号的级传信号为低电平；当所述驱动电路处于反向扫描时，启动产生液晶显示器的最后一级和倒数第二级高电平输出信号的级传信号为低电平。
本实施例中扫描控制模块通过接收级传模块输出的上一级级传信号，分别将所述级传信号传输给所述级传模块和栅极驱动信号模块，所述级传模块在CKV的低电平到达时输出本级级传信号，所述栅极驱动信号模块在CK1和CK2各自的高电平到达时，分别输出两级栅极驱动信号，实现了级传信号和栅极驱动信号的分离，提高了驱动电路级传的稳定性。
以上所揭露的仅为本发明一种较佳实施例而已，当然不能以此来限定本发明之权利范围，本领域普通技术人员可以理解实现上述实施例的全部或部分流程，并依本发明权利要求所作的等同变化，仍属于发明所涵盖的范围。

Claims (12)

  1. 一种液晶显示器驱动电路，其中，包括：扫描控制模块、栅极驱动信号输出模块和级传模块，其中：
    所述扫描控制模块的控制电平输入端输入控制正反向扫描的电压，扫描控制模块的级传信号输入端接入级传模块输出的上一级级传信号，所述扫描控制模块的输出端分别向栅极驱动信号输出模块的输出控制信号输入端和级传模块的级传控制信号输入端输出扫描控制信号；
    所述栅极驱动信号输出模块包括第一栅极驱动信号输出子模块、第二栅极驱动信号输出子模块以及第一反相器，所述扫描控制模块输出的扫描控制信号经过第一反相器后输入所述第一栅极驱动信号输出子模块的子模块输出控制信号输入端和第二栅极驱动信号输出子模块的子模块输出控制信号输入端，所述第一栅极驱动信号输出子模块的时钟输入端输入CK1，所述第二栅极驱动信号输出子模块的时钟输入端输入CK2；
    所述级传模块的时钟输入端输入CKV；
    其中，CK1和CK2的时钟周期为CKV的时钟周期的1/2，并且CK1的高电平出现时间与CK2的高电平出现时间相互不重合。
  2. 如权利要求1所述的液晶显示器驱动电路，其中，所述级传信号模块包括第一与非门、第二与非门、第三与非门和第四与非门，所述第一与非门的第一输入端接入所述扫描控制模块输出的扫描控制信号，所述第二与非门的第一输入端连接所述第一与非门的输出端，所述第三与非门的第一输入端连接所述第二与非门的输出端，所述第四与非门的第一输入端连接所述第三与非门的输出端，所述第一与非门的第二输入端连接所述第二与非门的输出端，所述第二与非门的第二输入端、所述第三与非门的第二输入端分别连接所述第四与非门的输出端，所述第四与非门的第二输入端连接CKV，所述第四与非门的输出端输出级传信号。
  3. 如权利要求1所述的液晶显示器驱动电路，其中，所述级传信号模块 包括第五与非门、第六与非门、第七与非门和第八与非门，所述第五与非门的第一输入端接入所述扫描控制模块输出的扫描控制信号，所述第五与非门的输出端分别连接所述第五与非门的第二输入端和所述第六与非门的第一输入端，所述第七与非门的第一输入端连接所述第六与非门的输出端，所述第八与非门的第一输入端连接所述第七与非门的输出端，所述第六与非门的第二输入端、所述第七与非门的第二输入端分别连接所述第八与非门的输出端，所述第八与非门的第二输入端输入CKV，所述第八与非门的输出端输出级传信号。
  4. 如权利要求1所述的液晶显示器驱动电路，其中，
    所述第一栅极驱动信号输出子模块包括第九与非门和奇数个反相器，所述第九与非门的第一输入端输入所述扫描控制模块输出的经过第一反相器反向的扫描控制信号，所述第九与非门的第二输出端输入CK1，所述奇数个反相器通过前一个反相器的输入端和后一个反相器的输出端相连接的方式连接相连接，最前一个反相器的输入端连接所述第九与非门的输出端，最后一个反相器的输出端输出栅极驱动信号；
    所述第二栅极驱动信号输出子模块包括第十与非门和奇数个反相器，所述第十与非门的第一输入端输入所述扫描控制模块输出的经过第一反相器反向的扫描控制信号，所述第十与非门的第二输出端输入CK2，所述奇数个反相器通过前一个反相器的输入端和后一个反相器的输出端相连接的方式连接相连接，最前一个反相器的输入端连接所述第十与非门的输出端，最后一个反相器的输出端输出栅极驱动信号。
  5. 如权利要求1所述的液晶显示器驱动电路，其中，
    所述第一栅极驱动信号输出子模块包括第一传输器和偶数个反相器，所述传输器包括一个P沟道增强型场效应晶体管和一个N沟道增强型场效应晶体管，偶数个反相器通过前一个反相器的输入端和后一个反相器的输出端相连接的方式连接相连接，最前一个反相器的输入端连接所述第一传输器中的P沟道增强型场效应晶体管的源极和N沟道增强型场效应晶体管的源极，最后一个反相器的输出端输出栅极驱动信号，所述第一传输器中的P沟道增强型场效应 晶体管的漏极和N沟道增强型场效应晶体管的漏极连接CK1；
    所述第一栅极驱动信号输出子模块包括第二传输器和偶数个反相器，所述传输器包括一个P沟道增强型场效应晶体管和一个N沟道增强型场效应晶体管，偶数个反相器通过前一个反相器的输入端和后一个反相器的输出端相连接的方式连接相连接，最前一个反相器的输入端连接所述第二传输器中的P沟道增强型场效应晶体管的源极和N沟道增强型场效应晶体管的源极，最后一个反相器的输出端输出栅极驱动信号，所述第二传输器中的P沟道增强型场效应晶体管的漏极和N沟道增强型场效应晶体管的漏极连接CK2。
  6. 如权利要求1所述的液晶显示器驱动电路，其中，
    所述扫描控制模块的控制电平输入端包括第一控制电平输入端和第二控制电平输入端，所述第一控制电平输入端和第二控制电平输入端分别接入正反向扫描控制电压U2D和D2U，当扫描控制电压U2D为高电平且D2U为低电平时，所述驱动电路处于正向扫描状态，当扫描控制电压U2D为低电平且D2U为高电平时，所述驱动电路处于反向扫描状态；
    所述扫描控制模块的级传信号输入端包括第一级传信号输入端和第二级传信号输入端，所述第一级传信号输入端用于接入上一级级传模块输出的级传信号，第二级传信号输入端用于接入下一级级传模块输出的级传信号。
  7. 如权利要求6所述的液晶显示器驱动电路，其中，当所述驱动电路处于正向扫描状态时：
    所述第一级传信号输入端接入级传模块输出的上一级级传信号，若所述上一级级传信号为低电平，所述扫描控制模块分别向所述栅极驱动信号输出模块的输出控制信号输入端和级传模块的级传控制信号输入端输出低电平的扫描控制信号；
    所述低电平的扫描信号经过所述第一反相器反向后分别接入所述第一栅极驱动信号输出子模块的子模块输出控制信号输入端和第二栅极驱动信号输出子模块的子模块输出控制信号输入端，当所述第一栅极驱动信号输出子模块的时钟输入端接收到高电平的CK1，所述第二栅极驱动信号输出子模块的时 钟输入端接收低电平的CK2，所述第一栅极驱动信号输出子模块输出驱动本级栅极的驱动信号，当所述第一栅极驱动信号输出子模块的时钟输入端接收到低电平的CK1，所述第二栅极驱动信号输出子模块的时钟输入端接收高电平的CK2，所述第二栅极驱动信号输出子模块输出驱动下一级栅极的驱动信号；
    所述级传模块的级传控制信号输入端接收低电平的级传控制信号，且所述级传模块的时钟输入端接入低电平的CKV时，所述级传模块输出高电平的本级级传信号。
  8. 如权利要求6所述的液晶显示器驱动电路，其中，当所述驱动电路处于正向扫描状态时：
    所述第一级传信号输入端接入级传模块输出的下一级级传信号，若所述下一级级传信号为低电平，所述扫描控制模块分别向所述栅极驱动信号输出模块的输出控制信号输入端和级传模块的级传控制信号输入端输出低电平的扫描控制信号；
    所述低电平的扫描信号经过所述第一反相器反向后分别接入所述第一栅极驱动信号输出子模块的子模块输出控制信号输入端和第二栅极驱动信号输出子模块的子模块输出控制信号输入端，当所述第一栅极驱动信号输出子模块的时钟输入端接收到高电平的CK1，所述第二栅极驱动信号输出子模块的时钟输入端接收低电平的CK2，所述第一栅极驱动信号输出子模块输出驱动本级栅极的驱动信号，当所述第一栅极驱动信号输出子模块的时钟输入端接收到低电平的CK1，所述第二栅极驱动信号输出子模块的时钟输入端接收高电平的CK2，所述第二栅极驱动信号输出子模块输出驱动上一级栅极的驱动信号；
    所述级传模块的级传控制信号输入端接收低电平的级传控制信号，且所述级传模块的时钟输入端接入低电平的CKV时，所述级传模块输出高电平的本级级传信号。
  9. 如权利要求7所述的液晶显示器驱动电路，其中，所述级传模块还包括第二与非门，当时钟CKV处于高电平时，所述级传模块的时钟输入端接入经过第二反相器反向后的低电平的CKV。
  10. 如权利要求8所述的液晶显示器驱动电路，其中，所述级传模块还包括第二与非门，当时钟CKV处于高电平时，所述级传模块的时钟输入端接入经过第二反相器反向后的低电平的CKV。
  11. 如权利要求9所述的液晶显示器驱动电路，其中，当所述驱动电路处于正向扫描时，启动产生液晶显示器的第一级和第二级高电平输出信号的级传信号为低电平；当所述驱动电路处于反向扫描时，启动产生液晶显示器的最后一级和倒数第二级高电平输出信号的级传信号为低电平。
  12. 如权利要求10所述的液晶显示器驱动电路，其中，当所述驱动电路处于正向扫描时，启动产生液晶显示器的第一级和第二级高电平输出信号的级传信号为低电平；当所述驱动电路处于反向扫描时，启动产生液晶显示器的最后一级和倒数第二级高电平输出信号的级传信号为低电平。
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