WO2016101762A1 - 一种模数转换器及模数转换方法 - Google Patents
一种模数转换器及模数转换方法 Download PDFInfo
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- 230000005540 biological transmission Effects 0.000 claims abstract description 109
- 230000000737 periodic effect Effects 0.000 claims abstract description 9
- 229910044991 metal oxide Inorganic materials 0.000 claims description 14
- 150000004706 metal oxides Chemical class 0.000 claims description 14
- 239000004065 semiconductor Substances 0.000 claims description 14
- 238000005070 sampling Methods 0.000 claims description 13
- 230000009471 action Effects 0.000 claims description 9
- 230000000295 complement effect Effects 0.000 claims description 4
- 238000012546 transfer Methods 0.000 claims description 4
- 230000000694 effects Effects 0.000 claims description 3
- 230000002708 enhancing effect Effects 0.000 claims description 3
- 101100328957 Caenorhabditis elegans clk-1 gene Proteins 0.000 description 18
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- 238000010586 diagram Methods 0.000 description 12
- 101150085102 Clk3 gene Proteins 0.000 description 7
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- 238000005516 engineering process Methods 0.000 description 5
- 230000008859 change Effects 0.000 description 4
- 238000012545 processing Methods 0.000 description 2
- 230000008054 signal transmission Effects 0.000 description 2
- 230000002776 aggregation Effects 0.000 description 1
- 238000004220 aggregation Methods 0.000 description 1
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- 238000011161 development Methods 0.000 description 1
- 238000002059 diagnostic imaging Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/66—Digital/analogue converters
- H03M1/74—Simultaneous conversion
- H03M1/742—Simultaneous conversion using current sources as quantisation value generators
- H03M1/747—Simultaneous conversion using current sources as quantisation value generators with equal currents which are switched by unary decoded digital signals
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
- G06F1/10—Distribution of clock signals, e.g. skew
-
- G—PHYSICS
- G10—MUSICAL INSTRUMENTS; ACOUSTICS
- G10L—SPEECH ANALYSIS TECHNIQUES OR SPEECH SYNTHESIS; SPEECH RECOGNITION; SPEECH OR VOICE PROCESSING TECHNIQUES; SPEECH OR AUDIO CODING OR DECODING
- G10L15/00—Speech recognition
- G10L15/08—Speech classification or search
- G10L15/12—Speech classification or search using dynamic programming techniques, e.g. dynamic time warping [DTW]
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/06—Continuously compensating for, or preventing, undesired influence of physical parameters
- H03M1/08—Continuously compensating for, or preventing, undesired influence of physical parameters of noise
- H03M1/0836—Continuously compensating for, or preventing, undesired influence of physical parameters of noise of phase error, e.g. jitter
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/1205—Multiplexed conversion systems
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/34—Analogue value compared with reference values
- H03M1/38—Analogue value compared with reference values sequentially only, e.g. successive approximation type
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/34—Analogue value compared with reference values
- H03M1/38—Analogue value compared with reference values sequentially only, e.g. successive approximation type
- H03M1/42—Sequential comparisons in series-connected stages with no change in value of analogue signal
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/66—Digital/analogue converters
- H03M1/74—Simultaneous conversion
- H03M1/76—Simultaneous conversion using switching tree
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/1205—Multiplexed conversion systems
- H03M1/121—Interleaved, i.e. using multiple converters or converter parts for one channel
- H03M1/1215—Interleaved, i.e. using multiple converters or converter parts for one channel using time-division multiplexing
Definitions
- the present invention relates to the field of electronic technologies, and in particular, to an analog-to-digital converter and an analog-to-digital conversion method.
- ADCs analog-to-digital converters
- the current high-precision ADC often uses a timing interleaving method to operate multiple high-precision ADCs in parallel to form a multi-channel ADC, and for multiple clock signals corresponding to multi-channel ADCs, in the conventional technical solution.
- the conventional scheme since each clock signal passes through different D flip-flops and output drivers, When there is a process deviation between multiple D flip-flops, the clock skew of each clock generally reaches the picosecond (ps) level. Due to the clock offset, different ADC channels can be converted by analog to digital. In the obtained spectrum, harmonics related to the clock frequency appear, which affects the conversion accuracy of the multi-channel ADC.
- FIG. 1 includes two parallel arrangements. And the gates are respectively used for receiving an input clock signal, and re-determining the two input clock signals respectively received by the two AND gates by using a homologous clock signal
- the clock between the two output clock signals The offset can be on the order of a few hundred femtoseconds (fs), but in high-speed, high-precision interleaved ADC sampling, as the frequency of the input signal increases, the clock offset on the order of hundreds of femtoseconds is difficult to satisfy linearity. Degree requirements, so it is not necessary to design a clock generator with a lower clock skew.
- Embodiments of the present invention provide an analog-to-digital converter and an analog-to-digital conversion method to implement a lower-level clock offset and meet the requirements of a high-speed and high-precision interleaved analog-to-digital converter for clock skew.
- the present invention provides an analog-to-digital converter comprising: a clock generator including M transmission gates, the M transmission gates for receiving a periodic first clock signal, and respectively for the a clock signal is gated to generate M second clock signals, wherein M is an integer greater than or equal to 2, each period of the first clock signal includes M clock pulses, and the M second clocks The period of the signal is equal to the period of the first clock signal, and each of the second clock signals includes one of the M clock pulses in each period; M ADC channels are used to receive an analog a signal, and respectively sampling, and analog-to-digital conversion of the analog signal under the control of the M second clock signals to obtain M digital signals, wherein each ADC channel respectively corresponds to the M second clock signals One of the clock signals; an adder for adding the M digital signals in the digital domain to obtain a digital output signal.
- a clock generator including M transmission gates, the M transmission gates for receiving a periodic first clock signal, and respectively for the a clock signal is gated to generate M second clock signals, wherein M is
- a phase of each of the M second clock signals constitutes an arithmetic progression with a tolerance of 2 ⁇ /M, and 2 ⁇ represents a period of the M second clock signals.
- any one of the M ADC channels includes a sample-and-hold circuit and an analog-to-digital conversion circuit connected in series
- the sampling and holding circuit is configured to receive the analog signal, and under the control of one of the M second clock signals, sample the analog signal to obtain a first sampling signal.
- the first analog-to-digital conversion circuit is configured to perform analog-to-digital conversion on the first sampling signal under the control of the one clock signal to obtain a digital signal.
- the M transmission gates include at least one complementary Metal oxide semiconductor CMOS transmission gate, P-type metal oxide semiconductor PMOS transmission gate or N-type metal oxide semiconductor NMOS transmission gate.
- the at least one CMOS transmission gate includes: a PMOS transistor and an NMOS transistor, wherein: a source of the PMOS transistor and the a drain of the NMOS and a signal input end of the at least one CMOS transmission gate are coupled to a point, and a drain of the PMOS transistor is coupled to a source of the NMOS transistor and a signal output end of the at least one CMOS transmission gate Or the source of the PMOS transistor is coupled to the source of the NMOS and the signal input end of the at least one CMOS transmission gate, the drain of the PMOS transistor and the drain of the NMOS transistor Signal transmission of at least one CMOS transmission gate
- the output terminal is connected to a point; the signal input end is configured to receive the first clock signal, and a gate of the PMOS transistor and a gate of the NMOS transistor are respectively used as the control terminal of the at least one CMOS transmission gate, Performing gating control on the first clock
- the gate of the PMOS transistor is specifically configured to receive the control signal
- the gate of the NMOS transistor is specifically configured to receive an inverted signal of the control signal to control conduction of the at least one CMOS transmission gate, thereby implementing gating control of the first clock signal.
- the analog-to-digital converter further includes: an oscillator, configured to generate the A clock signal.
- the first clock signal is a system clock signal independent of the ADC.
- the clock generation The device further includes a buffer for receiving the first clock signal and enhancing a driving capability of the first clock signal, and transmitting the first clock signal with enhanced driving capability to the M transmission gates, respectively.
- the present invention provides an analog to digital conversion method for an analog to digital converter ADC, the ADC comprising: a clock generator, M ADC channels, and an adder, wherein the clock generator includes M Transmitting a gate, the method comprising: the clock generator receiving a periodic first clock signal, and performing gate control on the first clock signal by the M transmission gates to generate M second clocks a signal, wherein M is an integer greater than or equal to 2, each of the first clock signals includes M clock pulses, and a period of the M second clock signals is equal to a period of the first clock signal, And each of the two clock signals includes one of the M clock pulses in each cycle; the M ADC channels receive an analog signal, and are respectively controlled by the M second clock signals And sampling the analog signal and performing analog-to-digital conversion to obtain M digital signals, wherein each ADC channel respectively corresponds to one of the M second clock signals; the adder is in the number The word field adds the M digital signals to obtain a digital output signal.
- the clock generator includes M Transmitting a gate
- each of the M second clock signals has a phase difference of 2 ⁇ /M, and 2 ⁇ represents a period of the M second clock signals.
- the method further includes: the clock generator receiving a system clock of a system where the ADC is located, and The first clock signal or the first clock signal is generated by oscillation.
- the present invention provides a wireless transceiver comprising: a mixer and any of the first to eighth possible embodiments of the first aspect, the first aspect, the first aspect, the first aspect,
- the ADC is configured to receive a radio frequency signal, and mix the radio frequency signal by using a preset local oscillator signal to obtain an analog baseband signal; the ADC is configured to receive the analog baseband signal And performing digital-to-analog conversion on the analog baseband signal to obtain a digital baseband signal and outputting.
- the clock generator in the ADC since the clock generator in the ADC generates the M second clock signals without using the logic gate, the M gates directly use the first clock signal of the same source.
- the gate control is respectively performed, and therefore, the clock offset between the respective second clock signals is only related to the switch on-resistance of the MOS transistors in the respective transfer gates, and when the respective transfer gates are turned on, in each of the transfer gates
- the MOS transistors are all in the deep linear region, and the threshold voltage variation of each transmission gate has little influence on the mismatch of the on-resistance of the switch, so that the clock offset between the respective second clock signals is very small, therefore,
- the ADC provided by the present invention a lower level of clock offset can be realized, which satisfies the requirement of high speed and high precision interleaved analog-to-digital converter for clock skew.
- 1 is an architectural diagram of a clock generator in the prior art
- FIG. 2a is an architectural diagram of an analog-to-digital converter according to an embodiment of the present invention.
- 2b is a structural diagram of another analog-to-digital converter according to an embodiment of the present invention.
- 2c is a structural diagram of still another analog-to-digital converter according to an embodiment of the present invention.
- FIG. 3 is a schematic structural diagram of a clock generator according to an embodiment of the present invention.
- FIG. 4 is a timing diagram of gate control performed by the clock generator shown in FIG. 3;
- FIG. 5 is a schematic structural diagram of another analog-to-digital converter according to an embodiment of the present disclosure.
- FIG. 6 is a schematic structural diagram of another clock generator according to an embodiment of the present disclosure.
- FIG. 7 is a timing diagram of gate control performed by the clock generator shown in FIG. 6;
- FIG. 8 is a schematic diagram of a signal conversion method according to an embodiment of the present invention.
- FIG. 9 is a structural diagram of a wireless transceiver according to an embodiment of the present invention.
- an embodiment of the present invention provides an analog-to-digital converter ADC100, including:
- the clock generator 101 includes M transmission gates for receiving periodic first clock signals, and respectively performing gate control on the first clock signals to generate M second clock signals.
- M is an integer greater than or equal to 2
- each period of the first clock signal includes M clock pulses
- a period of the M second clock signals is equal to a period of the first clock signal
- Each of the M second clock signals includes one of the M clock pulses in each cycle;
- M ADC channels here schematically illustrated by two ADC channels (ie 102 and 103) for receiving an analog signal and respectively under the control of the M second clock signals Sampling and analog-to-digital conversion of the analog signal to obtain M digital signals, wherein each ADC channel respectively corresponds to one of the M second clock signals;
- An adder for adding the M digital signals in a digital domain to obtain a digital output signal An adder for adding the M digital signals in a digital domain to obtain a digital output signal.
- the M transmission gates include at least one complementary metal oxide semiconductor CMOS transmission gate, a P-type metal oxide semiconductor PMOS transmission gate or an N-type metal oxide semiconductor NMOS transmission gate, that is, M Any one of the transmission gates can be either a CMOS transmission gate, a PMOS transmission gate, or an NMOS transmission gate, or a combination of multiple transmission gates.
- CMOS transmission gate a complementary metal oxide semiconductor
- PMOS transmission gate a P-type metal oxide semiconductor PMOS transmission gate
- NMOS transmission gate N-type metal oxide semiconductor NMOS transmission gate
- M Any one of the transmission gates can be either a CMOS transmission gate, a PMOS transmission gate, or an NMOS transmission gate, or a combination of multiple transmission gates.
- two CMOS transmission gates are connected in series to form a new transmission.
- the specific implementation form of the gate and the transmission gate can be determined according to the performance. If the performance requirement is high, the CMOS transmission is adopted. For gates with low performance requirements, PMOS pass gates or NMOS pass gates
- the gate control signals of the respective transmission gates When the voltage domain is between 0 and 2.5 V, that is, the voltage domain of the first clock signal is lower than the voltage domain of the gate control signal of each transmission gate, a single NMOS transmission gate can be used.
- each of the M second clock signals has a phase difference of 2 ⁇ /M, wherein 2 ⁇ represents a period of the M second clock signals.
- the clock generator 101 provided in this embodiment transmits the gate pairs by using multiple CMOS transmissions.
- a clock signal performs gate control to generate a plurality of second clock signals. Because during the gate control process, one clock pulse in each cycle of the first clock signal passes through each MOS transistor in the CMOS transmission gate (ie, PMOS) The channel between the source and the drain of the transistor and the NMOS transistor is transmitted, and the signal transmission process does not pass through any logic gate, so that the clock offset between the plurality of second clock signals is only with a plurality of CMOS transmission gates.
- V gs is a gate-source voltage
- ⁇ V th is a threshold voltage change amount
- ⁇ is a conductive factor
- ⁇ V th is usually small relative to the threshold voltage V th , it is known from the above equation that when the CMOS transmission gate is turned on, ⁇ V th has little effect on the on-resistance R of the switch, that is, due to multiple The threshold voltages of the respective MOS transistors of the CMOS transmission gate are not matched, and the influence of the clock offset between the plurality of second clock signals is small; the transmission gates such as the PMOS transmission gate and the NMOS transmission gate are in the gate control process. The principle is similar, and will not be repeated here.
- the first clock signal is generally gate-controlled by various logic gate devices to generate a plurality of second clock signals.
- a MOS inverter is taken as an example for description.
- the source thereof is used.
- the on current I D between the drains is as shown in equation (2):
- I D ⁇ (V gs -V th ) 2 (2)
- ⁇ V gs represents the amount of change in the gate-source voltage
- ⁇ V in represents the amount of change in the input voltage of the MOS inverter
- the timing mismatch between the second clock signals generated by the various logic gates is mainly caused by a change in the threshold voltage, in other words, the process of generating the second clock signal required for the plurality of ADC channels.
- the second clock signal generated by these logic gate devices is difficult to meet the requirements of high-speed and high-precision ADCs due to the different threshold values between the various logic devices.
- Logic gates include, but are not limited to, logic devices such as AND gates, NOT gates, NAND gates, AND OR gates;
- a femtosecond-level clock mismatch can be implemented between multiple second clock signals, thereby satisfying the low mismatch requirement of the high-speed and high-precision ADC for the clock signal.
- the analog-to-digital converter provided by the present invention will be further described below by taking the multi-channel ADC shown in FIG. 2b, FIG. 2c and FIG. 5 as an example.
- an embodiment of the present invention provides a two-channel analog-to-digital converter 100, including:
- the clock generator 101 is configured to receive the first clock signal SysClk, and respectively perform gate control on the first clock signal to generate second clock signals Clk1 and Clk2, wherein phases of Clk1 and Clk2 are different;
- the ADC channel 102 and the ADC channel 103 are configured in a time-interleaved manner, and each ADC channel is respectively configured to receive an analog signal, and under the control of the second clock signal, sample the analog signal and perform analog-to-digital conversion to obtain a a digital signal, wherein the ADC channel 102 corresponds to the second clock signal Clk1, and the ADC channel 103 corresponds to the second clock signal Clk2;
- the adder 104 is configured to add two digital signals generated by the ADC channel 102 and the ADC channel 103 in the digital domain to obtain a digital output signal.
- the ADC channel 102 may include a sample-and-hold circuit 1021 and an analog-to-digital conversion circuit 1022 connected in series, wherein the sample and hold circuit 1021 is configured to receive an analog signal, and sample the analog signal under the control of Clk1 to obtain The first sampling signal, the first analog-to-digital conversion circuit 1022 is configured to perform analog-to-digital conversion on the first sampling signal based on Clk1 to obtain a digital signal.
- the circuit structure of the ADC channel 103 can be the same as that of the ADC channel 102, and includes a series-connected sample-and-hold circuit and an analog-to-digital conversion circuit. The difference is that the ADC channel 103 is sampled and analog-to-digital converted under the control of Clk2, and should be known.
- the function of the sample-and-hold circuit 1021 is to acquire the instantaneous value of the analog signal at a certain moment, and keep the output voltage unchanged during the conversion of the analog-to-digital conversion circuit 1022.
- the specific hardware implementation of the sample-and-hold circuit 1021 and the analog-to-digital conversion circuit 1022 can be Refer to the prior art and do not elaborate here.
- the clock generator 101 may include a first complementary metal oxide semiconductor (CMOS) transmission gate 1012 and a second CMOS transmission gate 1013, the first CMOS transmission
- the gate 1012 and the second CMOS transmission gate 1013 are configured to respectively receive the first clock signal SysClk and perform gate control on the first clock signal to generate two second clock signals Clk1 and Clk2.
- CMOS complementary metal oxide semiconductor
- the clock generator 101 may further include a buffer 1011 for enhancing the driving capability of the first clock signal SysClk, wherein the preset value may be an empirical value or according to the first clock signal during transmission The degree of signal attenuation is determined.
- the first CMOS transmission gate 1012 may include: a P-type metal oxide semiconductor PMOS transistor and an N-type metal oxide semiconductor NMOS transistor, wherein a source of the PMOS transistor The source of the NMOS and the signal input end of the first CMOS transmission gate 1012 are coupled to one point, the drain of the PMOS transistor and the drain of the NMOS transistor and the signal output of the first CMOS transmission gate 1012 The signal input end is configured to receive the first clock signal, and the gate of the PMOS transistor and the gate of the NMOS transistor serve as control ends of the first CMOS transmission gate 1012, respectively.
- the gate signal is gate-controlled by the first control signal Ctrl 1 to obtain a second clock signal Clk1 at the signal output end and output.
- the first CMOS transmission gate 1012 may include: a P-type metal oxide semiconductor PMOS transistor and an N-type metal oxide semiconductor NMOS transistor, wherein a source of the PMOS transistor Connected to a drain of the NMOS and a signal input end of the first CMOS transmission gate 1012 to a point, a drain of the PMOS transistor and a source of the NMOS transistor and a signal of the first CMOS transmission gate 1012 The output end is coupled to the point; the signal input end is configured to receive the first clock signal, and the gate of the PMOS transistor and the gate of the NMOS transistor are respectively used as the first CMOS transmission gate control end, Under the action of the first control signal Ctrl 1, the first clock signal is gate-controlled to obtain a second clock signal Clk1 at the signal output and output.
- connection relationship between the PMOS transistor and the NMOS transistor is different, but since the source and the drain of the PMOS transistor and the NMOS transistor are equivalent in the switching circuit, there is practically no difference, the PMOS transistor and The NMOS transistors respectively use a channel between the source and the drain as a transmission channel, and by applying mutually opposite bias control signals to the respective gates of the PMOS transistor and the NMOS transistor, the PMOS transistor and the NMOS transistor can be simultaneously controlled.
- the gate can apply the inverted signal of the control signal to control the conduction of the first CMOS transmission gate 1012, thereby implementing gating control of the first clock signal; those skilled in the art should know that when the PMOS transistor When the gate voltage is low, or the gate voltage of the NMOS transistor is high, the first CMOS transmission gate 1012 can be turned on, and vice versa.
- the specific principle can refer to the prior art, and is not described in detail herein.
- control signal here may be generated by an external logic circuit, and the control signals corresponding to different CMOS transmission gates are required to meet the requirements of respectively selecting each pulse signal in each cycle of the first clock signal. Or, or based on the consideration of the same frequency of the control signal and the first clock signal, the control signal may also be obtained by the logic operation of the first clock signal;
- the first clock signal is a rail-to-rail signal
- the PMOS transistor and the NMOS transistor in the first CMOS transmission gate 1012 are required to be turned on or off at the same time, so that the first CMOS transmission gate 1012 is led.
- the equivalent resistance of the through-time is small; the structure of the second CMOS transmission gate 1013 may be the same as that of any of the above-described embodiments of the two first CMOS transmission gates 1012.
- the first CMOS transmission gate 1012 and the second CMOS transmission gate 1013 may respectively perform gate control on the first clock signal according to the timing control logic shown in FIG. 4 to generate two second clock signals.
- Clk1 and Clk2 in particular, the first CMOS transmission gate 1012 can select the 2ath pulse of a periodic first clock signal SysClk under the action of the first control signal Ctrl1 to form a new second clock.
- the signal Clk1; the second CMOS transmission gate 1013 can select the 2a-1th pulse of a periodic first clock signal SysClk under the action of the second control signal Ctrl2 to form a new second clock signal Clk2.
- a is an integer greater than 0
- Clk1 can also be regarded as a clock signal obtained by delaying the phase of Clk2 by ⁇ .
- the first clock signal may be a system clock signal in a system in which the analog-to-digital converter 100 is located, and it should be known that in various existing CMOS-based systems, For example: System on a Chip (SOC), processor, etc., in order to ensure signal integrity and consistency, the system usually integrates a phase-locked loop (PLL) device internally. Other devices provide a unified clock signal, which is faster and more accurate than the system clock received from the outside; or as shown in FIG. 2c, the analog-to-digital converter 100 includes An oscillator 105 for generating the first clock signal.
- SOC System on a Chip
- PLL phase-locked loop
- an embodiment of the present invention further provides a 4-channel analog-to-digital converter 400, including:
- the clock generator 401 is configured to receive the first clock signal SysClk, and perform gate control on the first clock signal to generate second clock signals Clk1, Clk2, Clk3, and Clk4, where Clk1, Clk2, and Clk3 The phase is different from Clk4;
- ADC channels 402, 403, 406, and 407 configured in a time-interleaved manner, each of which is configured to receive an analog signal and sample and simulate the analog signal under the control of a second clock signal The number conversion is performed to obtain a digital signal, wherein the ADC channel 402 corresponds to the second clock signal Clk1, the ADC channel 403 corresponds to the second clock signal Clk2, the ADC channel 406 corresponds to the second clock signal Clk3, and the ADC channel 407 corresponds to the second clock signal Clk4, wherein the ADC channel 407 corresponds to the second clock signal Clk4, wherein
- the circuit structure of any ADC channel is the same as the ADC channel shown in Figure 2b or Figure 2c, and will not be described in detail here;
- An adder 404 is configured to add four digital signals generated by the four ADC channels 402, 403, 406, and 407 in the digital domain to obtain a digital output signal.
- the specific circuit structure of the clock generator 401 is shown in FIG. 6.
- the clock generator 401 includes four CMOS transmission gates (4012, 4013, 4014, and 4015), which are four CMOS devices.
- the transmission gate is configured to receive the first clock signal SysClk and perform gate control on the first clock signal SysClk to generate four second clock signals Clk1, Clk2, Clk3, and Clk4.
- the four CMOS transmission gates 4012, 4013, 4014, and 4015 can perform gate control on the first clock signal SysClk according to the timing control logic shown in FIG. 7, respectively, to generate four second clock signals Clk1. Clk2, Clk3, and Clk4, by way of example, the CMOS transmission gate 4012 can select the 4b-3th pulse of a periodic first clock signal SysClk under the action of the first control signal Ctrl1 to form a new one.
- the first clock signal Clk1; the CMOS transmission gate 4013 can select the 4b-2th pulse in the first clock signal SysClk under the action of the second control signal Ctrl2 to form a new second clock signal Clk2; CMOS transmission The gate 4014 may select the 4b-1th pulse in the first clock signal SysClk to form a new first clock signal Clk3 under the action of the third control signal Ctrl3; the CMOS transmission gate 4015 may be in the fourth control signal.
- the 4bth pulse in the first clock signal SysClk is selected to form a new second clock signal Clk5, where b is an integer greater than 0, and the phase difference of each of Clk1, Clk2, Clk3, and Clk4 is ⁇ /2.
- FIG. 2b, FIG. 2c, and FIG. 5 are schematic diagrams illustrating the technical solution of the present invention by using an analog-to-digital converter including two ADC channels and four ADC channels, respectively, and those skilled in the art based on the technology of the present invention. It is contemplated that any multi-channel ADC that is extended based on Figures 2b, 2c, and 5 is within the scope of the present invention.
- the second embodiment of the present invention further provides an analog-to-digital conversion method for an analog-to-digital converter, where the analog-to-digital converter includes: a clock generator, and M ADC channels configured in a time-interleaved manner.
- the clock generator includes M transmission gates, wherein any one of the M transmission gates may include: a CMOS transmission gate, a PMOS transmission gate or an NMOS transmission gate, that is, in M transmission gates Any one of the transmission gates may be a CMOS transmission gate, or a PMOS transmission gate, or an NMOS transmission gate, or may be a combination of a plurality of transmission gates, for example, two CMOS transmission gates are connected in series to form a new transmission gate.
- Methods include:
- the clock generator receives a first clock signal, and performs gate control on the first clock signal by using the M transmission gates to generate M second clock signals, where M is greater than or equal to 2.
- M is greater than or equal to 2.
- each period of the first clock signal includes M clock pulses, a period of the M second clock signals being equal to a period of the first clock signal, and each of the second clock signals
- One of the M clock pulses is included in each cycle; exemplarily, the clock generator may respectively select one of M clock pulses included in each cycle of the first clock signal Clock pulses to generate the M second clock signals;
- the M ADC channels receive an analog signal, and respectively sample and analog-digitally convert the analog signal under the control of the M second clock signals to obtain M digital signals, where each ADC Channels respectively corresponding to one of the M second clock signals;
- the adder adds the M digital signals in a digital domain to obtain a digital output signal.
- the first clock signal of the same source is gate-controlled by using multiple transmission gates to generate a plurality of second clock signals.
- Each cycle of the first clock signal is generated during the gate control process.
- One of the clock pulses is transmitted through the channel between the source and the drain of each MOS transistor (ie, PMOS transistor and/or NMOS transistor) in the gate, without passing through any logic gate, so that multiple second clocks
- the clock offset between the signals is only related to whether the switch on-resistance between the multiple transmission gates is matched.
- each MOS transistor When the transmission gate is turned on, each MOS transistor is in a deep linear region because the respective MOS transistors of the respective transmission gates The mismatch of the threshold voltages has little effect on the clock offset between the plurality of second clock signals, so that a low mismatch can be achieved between the plurality of second clock signals.
- each of the M second clock signals has a phase difference of 2 ⁇ /M, wherein 2 ⁇ represents a period of the M second clock signals.
- the method may further include:
- S104a Receive a system clock of a system where the ADC is located and use the first clock signal.
- the method further includes:
- analog-to-digital conversion method of this embodiment is based on the analog-to-digital converter provided in the foregoing first embodiment. (As shown in FIG. 2b, FIG. 2c and FIG. 5), the related technical features can be referred to each other in reference to the first embodiment.
- the third embodiment of the present invention further provides a wireless transceiver 10 applied to a communication device, where the communication device includes but is not limited to a base station and a mobile terminal.
- the wireless transceiver 10 includes: a mixer 200 and an analog-to-digital converter 100 as described in the foregoing first embodiment;
- the mixer 200 is configured to receive a radio frequency signal, and mix the radio frequency signal by using a preset local oscillator (LO) signal to obtain an analog baseband (also referred to as a baseband) signal, which needs to be explained.
- LO local oscillator
- the mixing here includes various frequency conversion modes such as zero intermediate frequency and intermediate frequency, which are not limited here;
- the ADC 100 is configured to receive the analog baseband signal, perform digital-to-analog conversion on the analog baseband signal, and obtain a digital baseband signal and output. It should be noted that the simulation received by the ADC 100 in the first embodiment The signal is the analog baseband signal in this embodiment, and the digital output signal output by the ADC 100 is the digital baseband signal in this embodiment.
- a person skilled in the art should also include an antenna 300 for receiving wireless signals transmitted by other devices from an air interface.
- the antenna duplexer 400 may also be used.
- the radio frequency signal is obtained by separating each carrier in the wireless signal.
- the communication device may further include a baseband chip 500 (or a baseband processor) for processing the digital baseband signal generated by the ADC 100.
- a baseband chip 500 or a baseband processor for processing the digital baseband signal generated by the ADC 100.
- the wireless transceiver 10 is used as a transmitter from the perspective of a receiver, the signal processing process of each module is just the opposite, and will not be described here.
- the wireless transceiver 10 in the embodiment of the present invention may be integrated into one radio frequency chip or may be separately disposed in multiple chips.
- the mixer 200 is located in the radio frequency chip
- the ADC 100 is located in the baseband chip.
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Abstract
Description
Claims (13)
- 一种模数转换器ADC,其特征在于,包括:时钟生成器,包括M个传输门,所述M个传输门用于接收周期性的第一时钟信号,并分别对所述第一时钟信号进行选通控制,生成M个第二时钟信号,其中,M为大于等于2的整数,所述第一时钟信号的每个周期中包括M个时钟脉冲,所述M个第二时钟信号的周期与所述第一时钟信号的周期相等,且每个第二时钟信号的每个周期中分别包括所述M个时钟脉冲中的一个时钟脉冲;M个ADC通道,用于接收一个模拟信号,并分别在所述M个第二时钟信号的控制下,对所述模拟信号进行采样以及模数转换,得到M个数字信号,其中每个ADC通道分别对应所述M个第二时钟信号中的一个时钟信号;加法器,用于在数字域对所述M个数字信号相加,得到一个数字输出信号。
- 如权利要求1所述的模数转换器,其特征在于,所述M个第二时钟信号各自的相位构成公差为2π/M的等差数列,2π表示所述M个第二时钟信号的周期。
- 如权利要求1或2所述的模数转换器,其特征在于,所述M个ADC通道中的任一ADC通道包括串联的采样保持电路和模数转换电路,其中,所述采样保持电路用于接收所述模拟信号,并在所述M个第二时钟信号中的一个时钟信号的控制下,对所述模拟信号进行采样,得到第一采样信号,所述第一模数转换电路用于在所述一个时钟信号的控制下对所述第一采样信号进行模数转换,得到一个数字信号。
- 如权利要求1至3任一所述的模数转换器,其特征在于,所述M个传输门中包括至少一个互补金属氧化物半导体CMOS传输门,P型金属氧化物半导体PMOS传输门或者N型金属氧化物半导体NMOS传输门。
- 如权利要求4所述的模数转换器,其特征在于,所述至少一个CMOS传输门包括:PMOS管以及NMOS管,其中:所述PMOS管的源极与所述NMOS的漏极以及所述至少一个CMOS传输门的信号输入端连结于一点,所述PMOS管的漏极与所述NMOS管的源极以及所述至少一个CMOS传输门的信号输出端连结于一点,或者,所述PMOS管的源极与所述NMOS的源极以及所述至少一个CMOS传输门的信号输入端连结于一点,所述PMOS管的漏极与所述NMOS管的漏极以及所述至少一个CMOS传输门的信号输出端连结于一点;所述信号输入端用于接收所述第一时钟信号,所述PMOS管的栅极和所述NMOS管的栅极分别作为所述至少一个CMOS传输门控制端,用于在控制信号的作用下,对所述第 一时钟信号进行选通控制,以在所述信号输出端得到一个第二时钟信号并输出;其中,所述控制信号为外部逻辑电路生成,或者由所述第一时钟信号通过逻辑运算得到。
- 如权利要求4或5所述的模数转换器,其特征在于,所述PMOS管的栅极具体用于接收所述控制信号,所述NMOS管的栅极具体用于接收所述控制信号的反相信号,以控制所述至少一个CMOS传输门的导通,从而实现对所述第一时钟信号的选通控制。
- 如权利要求1至6任一所述的模数转换器,其特征在于,所述模数转换器还包括:振荡器,用于生成所述第一时钟信号。
- 如权利要求1至6任一所述的模数转换器,其特征在于,所述第一时钟信号为独立于所述ADC的系统时钟信号。
- 如权利要求1至8任一所述的模数转换器,其特征在于,所述时钟生成器还包括缓冲器,用于接收所述第一时钟信号并增强所述第一时钟信号的驱动能力,以及将驱动能力增强后的所述第一时钟信号分别传输给所述M个传输门。
- 一种模数转换方法,用于模数转换器ADC,其特征在于,所述ADC包括:时钟生成器、M个ADC通道以及加法器,其中,所述时钟生成器包括M个传输门,所述方法包括:所述时钟生成器接收周期性的第一时钟信号,并通过所述M个传输门对所述所述第一时钟信号进行选通控制,生成M个第二时钟信号,其中,M为大于等于2的整数,所述第一时钟信号的每个周期中包括M个时钟脉冲,所述M个第二时钟信号的周期与所述第一时钟信号的周期相等,且每个第二时钟信号的每个周期中分别包括所述M个时钟脉冲中的一个时钟脉冲;所述M个ADC通道接收一个模拟信号,并分别在所述M个第二时钟信号的控制下,对所述模拟信号进行采样以及模数转换,得到M个数字信号,其中每个ADC通道分别对应所述M个第二时钟信号中的一个时钟信号;所述加法器在数字域对所述M个数字信号进行相加,得到一个数字输出信号。
- 如权利要求10所述的方法,其特征在于,所述M个第二时钟信号各自的相位构成公差为2π/M的等差数列,2π表示所述M个第二时钟信号的周期。
- 如权利要求10或11所述的方法,其特征在于,还包括:所述时钟生成器接收所述ADC所在系统的系统时钟并作为所述第一时钟信号,或者通过振荡生成所述第一时钟信号。
- 一种无线收发信机,其特征在于,包括:混频器和如权利要求1至9任一所述的模数转换器ADC;所述混频器用于接收射频信号,并利用预设的本振信号对所述射频信号进行混频,得到模拟基频信号;所述ADC用于接收所述模拟基频信号,并对所述模拟基频信号进行数模转换,得到一个数字基频信号并输出。
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WO2018041332A1 (en) * | 2016-08-30 | 2018-03-08 | Huawei Technologies Co., Ltd. | Analogue to digital converter |
CN107896110B (zh) * | 2017-12-15 | 2020-11-10 | 上海贝岭股份有限公司 | 自举采样开关电路、采样保持电路及时间交织型adc |
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CN112152626B (zh) * | 2020-09-29 | 2024-06-14 | 珠海格力电器股份有限公司 | 一种模数转换采集电路和芯片 |
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US20180254781A1 (en) | 2018-09-06 |
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