CN1973533A - 基于fft的多通道视频接收机 - Google Patents

基于fft的多通道视频接收机 Download PDF

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Publication number
CN1973533A
CN1973533A CNA2005800208884A CN200580020888A CN1973533A CN 1973533 A CN1973533 A CN 1973533A CN A2005800208884 A CNA2005800208884 A CN A2005800208884A CN 200580020888 A CN200580020888 A CN 200580020888A CN 1973533 A CN1973533 A CN 1973533A
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CN
China
Prior art keywords
frequency
circuit
signals
video receiver
generate
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Granted
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CNA2005800208884A
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CN100466694C (zh
Inventor
伟杰·君
塞谬尔·盛
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Spreadtrum Communications Shanghai Co Ltd
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Telegent Systems Inc
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Publication of CN1973533A publication Critical patent/CN1973533A/zh
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    • H04N7/00—Television systems
    • H04N7/015—High-definition television systems
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    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00—Details of television systems
    • H04N5/44—Receiver circuitry for the reception of television signals according to analogue transmission standards
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    • G01S1/00—Beacons or beacon systems transmitting signals having a characteristic or characteristics capable of being detected by non-directional receivers and defining directions, positions, or position lines fixed relatively to the beacon transmitters; Receivers co-operating therewith
    • G01S1/02—Beacons or beacon systems transmitting signals having a characteristic or characteristics capable of being detected by non-directional receivers and defining directions, positions, or position lines fixed relatively to the beacon transmitters; Receivers co-operating therewith using radio waves
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Abstract

本发明公开了一种多通道视频接收机，其具有模/数转换器、快速傅立叶变换电路、以及傅立叶逆变换电路。模/数转换器电路生成用于传送多个视频信号的频带的数字化表示，以及快速傅立叶变换电路生成频带的数字化表示的频域表示。傅立叶逆变换电路从频域表示中恢复对应于多个视频信号的多个数字化的时域视频信号。

Description

基于FFT的多通道视频接收机
相关申请的交叉参考
本申请要求于2004年4月30日提交的题目为“FFT-BASEDMULTICHANNEL TUNER/DECODER ARCHITECTURE”的美国临时申请第60/567,333号的优先权，其内容结合于此作为参考。
技术领域
本发明涉及视频接收领域。
背景技术
历史上，使用多达几百个分立组件并消耗差不多2至3瓦的功率，完全在模拟域实现用于视频频带应用的调谐解调器(“盒状调谐器(tuner can)”)。然而，尽管它们成本低且性能好，但盒状调谐器通常只限于单通道选择，因此其通常在要求同时接收多于一个视频通道的应用中重复，因此增加了所需组件的数量，从而由于将被同时接收多个通道而浪费电能和空间。
附图说明
参照附图，通过但不限于实例示出了本发明，其中，相同的参考标号表示相同的元件，并且其中：
图1示出了根据一个实施例的基于FFT的多通道视频接收机的结构；
图2示出可在图1的多通道视频接收机中使用的基带处理电路的实施例；以及
图3A和图3B示出可包括在图1或图2的基带处理电路中的示例性解码器。
具体实施方式
在下列描述和附图中，使用特定的术语和附图标号，以提供对本发明的透彻理解。在一些实例中，术语和标号可表示无需在本发明中实践的特定细节。例如，可将在电路元件或电路块之间的中间连接表示或描述为多导体或单导体信号线。可选地，多导体信号线中的每一条可为单导体信号线，以及可选地，单导体信号线中的每一条可为多导体信号线。示出和描述为单终端的信号和信号路径也可以是有区别的，反之亦然。当信号驱动电路确定(或不确定，如果由上下文明确表示或指出)在连接在信号驱动电路和信号接收电路之间的信号线上的信号时，信号驱动电路被描述为将信号“输出”到信号接收电路。文中使用的术语“连接”表示直接连接以及通过一个或多个中间电路或结构连接。文中使用的术语“示例性”表示实例，不是优选的或必需的。
文中以各个实施例公开了可在单个集成电路(即，单芯片)中实现并采用数字信号处理技术以同时解调多个视频通道的视频接收结构。例如，在一个多通道接收机的实施例中，集成的调谐器和解调器采用数字信号处理，其具体目标在于在保持整体调谐性能的同时降低对模拟域的性能要求，从而提供了N并行盒状调谐器的等效性能，其中，死区和功耗仅随着N成比例地减弱。
图1示出多通道视频接收机100的实施例，其包括信号输出端101、高动态范围低噪声放大器103、模/数转换器(ADC)组105、快速傅立叶变换(FFT)引擎107、内插频率校正电路109(IFC)、傅立叶逆变换组111、基带处理组113、合成器115、压控振荡器(117)、相位控制电路119、以及导频(pilot)提取电路121，它们中的任意一个或全部均可集成到在文中称为主(host)IC的单个集成电路(IC)装置上。主IC可为单IC管芯或包括两个或多个管芯的IC封装件(例如，多芯片模块)。此外，主IC自身也可以是任意数量主系统的组件，该主系统包括但不限于电视机、视频记录器、移动电话、个人计算机、个人数字助理(PDA)、视频播放器、置顶盒、或期望多通道视频接收的任何其他装置。主系统可包括各种类型的用户接口，用于接收用户提供的通道选择和配置信息等；显示器，用于显示由视频接收机100恢复的一个或多个视频信号；记录介质，用于记录一个或多个视频信号；以及可选地，音频变换器，用于生成由视频接收机100恢复的一个或多个音频信号的声频输出。
通过低噪放大器103放大经由信号输入端101(例如，用于容纳电缆或其他导电或导光介质的天线或插座)接收的信号，以提供可在后续电路块中被数字化和处理的输入视频信号。在一个实施例中，尽管在可选实施例中任意频带实际上均可以包括在放大器的范围(例如，50MHz至1GHz的电缆频谱或者任何其他频谱)内，但还将低噪放大器103设计成放大落在视频频带(例如，50MHz至850MHz)内的信号。在放大器103的输出处，在放大的信号中添加导频音(其可以相对于放大的频带在频带外或者是可能在频带内)。放大的接收信号(即，放大器103的输出)连同带有导频一起通过ADC组105转换成数字域。在示出的实施例中，ADC组105包括一组K个M位分辨率的ADC(ADC1至ADCk)，其通过一组错时(time-staggered)的采样时钟信号120(即，多相位时钟信号)触发，以提供K乘以采样时钟频率的有效采样率。例如，在特定实施例中，ADC组105包括8个10位ADC，其中每一个均由各个错时的250MHz的采样时钟信号触发，以提供2GHz的有效采样率。可使用后台校准(例如，正弦导频音或伪噪声序列)，以确保ADC组105内子ADC之间的匹配以及校正它们之间的相对错时(时间调整)。
将ADC组105的输出提供给FFT引擎107，其执行例如重叠(overlap)/添加(add)型FFT运算，以生成接收到的信号和导频音的等效频域表示。例如，假设接收到的信号包括在期望的频带的上限和下限之间的全部视频通道(例如，在50MHz与850MHz之间的所有6MHz视频通道)，则在FFT的每个“格元(bin)”中的信息(即，在每个频谱偏移中出现的信息关系信号)可看成每个视频通道自身的数据表示。此外，因为以频率(即，通过FFT的正交特性)划分FFT和视频通道自身，所以相对于每个独立视频通道的ADC组105的有效动态范围通常远远大于ADC输出的M位分辨率。例如，继续使用250MHz的采样时钟，在上述8个ADC的实例中，以2GHz有效采样在感兴趣视频频带内的每个视频通道，在标准的6MHz视频通道的情况下产生极大的过采样比。通过实现过采样增益来对FFT取平均值，从而增加了每个独立通道的信噪比(SNR)。
在一个实施例中，相对于ADC组105的导频音校准，将具有期望视频频带外频率的单一正弦导频118添加到放大的接收信号(即，ADC组的输入)中。因为导频音118具有恒定的频率和振幅，所以FFT引擎107将生成导频音频率的恒定输出。即，在导频音“格元”中的数据将基本保持不随时间改变。因此，在导频提取电路121中检测到的导频音“格元”的任意调制或误差均表示，由于在组成ADC组105的各个ADC之间的相对定时中的相位噪声或误差所造成的采样操作自身的不完整性。因此，通过测量由FFT引擎107生成的FFT中的导频，导频提取电路121可调节VCO的频率和/或ADC组105中ADC的定相，以实现改善的性能，从而减少采样时钟信号120中的相位噪声以及补偿在子ADC自身中的运行变化(例如，由于工艺、温度、电压等)。
还将在频域中执行最终的频率调节。例如，通过在内插频率校正电路109中执行频域内插，可调节有效的解调载波频率，使其符合解调视频传输所需的公差(例如，在NTSC标准视频传输中的50KHz)。此外，在图1的实施例中，可在频域中执行整个载波-基带操作，使得传统上在时域系统中模拟混频器级中执行的解调操作可替代地在(数字)频域中使用直接数字转换操作来执行。
在电路109的频率校正和通道选择之后，可通过例如在IDFT组111的子IDFT电路中执行逆FFT(IDFT)操作，来将期望通道信号组的视频信号转回到时域中。在基带处理组113的各个基带处理电路内，可进一步在时域中处理现在处于基带的期望视频信号，以提取视频信息。参照图2中所示基带处理电路的实施例(其可被用于实现图1的组113中的任意基带处理电路)，例如可在直接数字合成器/混频器151(DDS)中校正任何残留频率误差，在低通滤波器153中过滤校正的信号，以去除由混频操作所引入的高频成分。如果存在分离的音频副载波，则可随后将生成的基带信号提供给副载波分离电路155，以恢复视频输出和音频输出。更具体地，可在副载波电路155中应用适当的视频解码器，来对视频信息进行解码。例如，可应用NTSC(国家电视标准委员会)解码器来解码标准的北美电视信号，应用如图3A中所示的ATSC(高级电视标准委员会)8-VSB解码器来解码北美高清晰度电视(HDTV)信号，或者应用如图3B中所示的DVB-T/H(数字视频宽广播，地面/手持)COFDM解码器来解码欧洲数字电视广播。还可应用其他视频解码器来解码符合其他传统视频标准(例如，PAL(逐行倒相制式)或SECAM(顺序彩色存储制)以及各种其他高清晰度视频标准)传输的视频信息。
最终的视频输出是可流入视频显示器和/或MPEG(运动图像专家组)解码器的数字流。数字流可符合许多行业标准(例如，CCIR/ITU 601/656或SPI)。
应当注意，编程的处理器可用于实现上述数字处理功能的功能或其任意子集，其中，数字处理功能包括但不限于FFT引擎、内插频率校正电路、IDFT电路、DDS频率校正电路、通道选择滤波器、副载波分离电路、以及其中解码的任意MPEG的功能。可在具有视频接收机的集成电路上形成处理器，或者可在相同或不同的集成电路封装件中的单独集成电路管芯上形成处理器。实际上，处理器可以是任意类型的处理器，包括但不限于通用处理器或特殊用途的处理器(例如，微控制器(其可包括集成ADC组)、数字信号处理器(DSP)等)，并且该处理器可包括内部程序存储器，用于存储由处理器执行以实现上述功能的程序代码。可选地，可提供单独的芯片上或芯片外的程序存储器(例如，易失性或非易失性存储器，未示出的或任意其他处理器或包括但不限于半导体存储器以及磁和/或光介质的计算机可读介质)，并且其通过例如专用或公用总线连接至处理器。存储在程序存储器中的程序代码可包括当由处理器执行时使处理器实现上述功能的指令和/或数据。
还应该注意，根据电路的行为、寄存器传输、逻辑元件、晶体管、布局集合结构、和/或其他特性方面，可使用计算机辅助设计工具描述这里所公开的多种电路，并将该电路表示(或表现)为包含在各种计算机可读介质中的数据和/或指令。文件和可在其中实现这种电路表示的其他对象的格式包括但不限于支持行为语言(例如，C、Verilog、和HLDL)的格式、支持寄存器等级描述语言(例如，RTL)的格式、支持几何描述语言(例如，GDSII、GDSIII、GDSIV、CIF、MEBES)的格式、以及任何其他适合的格式和语言。可包含这种格式化的数据和/或指令的计算机可读介质包括但不限于各种形式的非易失性存储介质(例如，光、磁、或半导体存储介质)以及可用于通过无线、光学、或有线信号传输介质或任何其组合来传输这种格式化的数据和/或指令的载波。通过载波传输这种格式化的数据和/或指令的实例包括但不限于通过一个或多个数据传输协议(例如，HTTP、FTP、SMTP等)在互联网和/或其他计算机网络上传输(上传、下载、电邮等)。
当在计算机系统中通过一个或多个计算机可读介质接收时，可以通过计算机系统中的处理实体(例如，一个或多个处理器)连同执行一个或多个计算机程序(包括但不限于网络列表生成程序、位置和路由程序等)一起处理上述电路的基于这种数据和/或指令的表示，以生成这种电路物理表现的表达或图像。例如，通过启动生成用于在装置制造工艺中形成电路各个部件的一个或多个掩模，可将这种表达或图像其后用于装置制造。
尽管参照其特定实施例描述了本发明，但应当理解，在不背离本发明的更宽泛的精神和范围内，可作出各种修改和变化。因此，说明书和附图被认为是示例性的而不是限定性的。在确定与文中参考相结合的任意文件的条款冲突，或者与文中相似或相关的条款不符合的情况下，文中条款将至少用于控制解释所附权利要求。

Claims (20)

1.一种多通道视频接收机，包括：
模/数转换器电路，生成用于传送多个视频信号的频带的数字化表示；
快速傅立叶变换电路，生成所述频带的所述数字化表示的频域表示；以及
傅立叶逆变换电路，从所述频域表示中恢复对应于所述多个视频信号的多个数字化时域视频信号。
2.根据权利要求1所述的多通道视频接收机，其中，所述模/数转换器(ADC)电路包括多个子ADC电路，以生成输入视频频带信号的各个数字采样。
3.根据权利要求2所述的多通道视频接收机，还包括时钟生成电路，用于生成多个采样时钟信号，以触发所述多个子ADC电路中的各个采样操作。
4.根据权利要求3所述的多通道视频接收机，其中，所述时钟生成电路包括相位控制电路，用于使所述采样时钟信号中的每一个相对于彼此错相。
5.根据权利要求1所述的多通道视频接收机，还包括导频音发生器，用于生成基本上频率固定的导频信号，所述导频音发生器用于将所述导频信号提供给所述模/数转换器。
6.根据权利要求5所述的多通道视频接收机，其中，所述模/数转换器用于生成导频音的数字化表示，其中，所述快速傅立叶变换电路用于生成所述导频音的所述数字化表示的频域表示，以及其中，所述多通道接收机还包括导频提取电路，用于在所述导频音的所述数字化表示的所述频域表示中检测相位误差和频率误差中的至少一个。
7.根据权利要求6所述的多通道视频接收机，还包括相位控制电路，用于基于通过所述导频提取电路发送的相位误差来调节提供给所述模/数转换电路的采样时钟信号的相位。
8.根据权利要求6所述的多通道视频接收机，还包括压控振荡器，用于基于通过所述导频提取电路发送的频率误差来调节提供给所述模/数转换电路的采样时钟信号的频率。
9.根据权利要求1所述的多通道视频接收机，还包括基带处理电路，用于生成对应于所述多个数字化时域视频信号中的一个的视频输出信号。
10.根据权利要求9所述的多通道视频接收机，其中，所述基带处理电路包括混频电路，用于调节所述多个数字化时域视频信号中的一个的频率。
11.根据权利要求9所述的多通道视频接收机，其中，所述基带处理电路包括副载波分离电路，用于分离在所述多个数字化时域视频信号中的一个中传送的音频和视频信息。
12.根据权利要求9所述的多通道视频接收机，其中，所述基带处理电路包括MPEG解码器。
13.一种在多通道视频接收机中操作的方法，所述方法包括：
生成用于传送多个视频信号的频带的数字化表示；
在快速傅立叶变换运算中转换所述频带的所述数字化表示，以生成所述频带的所述数字化表示的频域表示；以及
在傅立叶逆变换运算中转换所述频域表示，以生成对应于所述多个视频信号的多个数字化时域信号。
14.根据权利要求13所述的方法，其中，生成用于传送多个视频信号的频带的数字化表示包括响应于多相位采样时钟信号对接收的信号进行采样。
15.根据权利要求13所述的方法，还包括：
生成基本上频率固定的导频信号；
响应于所述多相位采样时钟信号对所述导频信号进行采样，以生成所述导频信号的数字化表示；以及
在快速傅立叶变换运算中转换所述导频信号的所述数字化表示，以生成所述导频信号的频域表示。
16.根据权利要求15所述的方法，还包括根据由所述导频信号的所述频域表示指示的相位误差，调节所述多相位采样时钟信号的相位。
17.根据权利要求15所述的方法，还包括根据由所述导频信号的所述频域表示指示的频率误差，调节所述多相位采样时钟信号的频率。
18.根据权利要求13所述的方法，还包括基带处理，生成对应于所述多个数字化时域信号中的一个的视频输出信号。
19.根据权利要求18所述的方法，其中，生成视频输出信号包括
生成对应于所述多个数字化时域信号中的一个的数字位流。
20.一种多通道视频接收机，其包括：
用于生成传送多个视频信号所使用的频带的数字化表达表示的装置；
用于在快速傅立叶变换运算中转换所述频带的所述数字化表示以生成所述频带的所述数字化表示的频域表示的装置；以及
用于在傅立叶逆变换运算中转换所述频域表示以生成对应于所述多个视频信号的多个数字化时域信号的装置。
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