WO2016086431A1 - 液晶显示装置及其移位寄存器 - Google Patents

液晶显示装置及其移位寄存器 Download PDF

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Publication number
WO2016086431A1
WO2016086431A1 PCT/CN2014/093351 CN2014093351W WO2016086431A1 WO 2016086431 A1 WO2016086431 A1 WO 2016086431A1 CN 2014093351 W CN2014093351 W CN 2014093351W WO 2016086431 A1 WO2016086431 A1 WO 2016086431A1
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WIPO (PCT)
Prior art keywords
switch tube
node
switch
type mos
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2014/093351
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English (en)
French (fr)
Inventor
虞晓江
张鑫
夏军
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TCL China Star Optoelectronics Technology Co Ltd
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Shenzhen China Star Optoelectronics Technology Co Ltd
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Application filed by Shenzhen China Star Optoelectronics Technology Co Ltd filed Critical Shenzhen China Star Optoelectronics Technology Co Ltd
Priority to US14/433,609 priority Critical patent/US9484112B2/en
Publication of WO2016086431A1 publication Critical patent/WO2016086431A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3685—Details of drivers for data electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3696—Generation of voltages supplied to electrode drivers
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0202—Addressing of scan or signal lines
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit

Definitions

  • the present invention relates to the field of liquid crystal display driving technologies, and in particular to a liquid crystal display device and a shift register thereof.
  • the liquid crystal display device needs to have an appropriate driving circuit, and the driving circuit generally includes a data driving circuit and a scan driving circuit.
  • the scan driver circuit often uses a shift register as a core circuit component.
  • the shift register is formed by a series of shift register units, and the output signal of the shift register unit of the previous stage is used as an input signal of the shift register unit of the subsequent stage.
  • the structure of most single shift register units is relatively complicated, and the area occupied by the plurality of shift register units after connection is large, which is disadvantageous to the narrow bezel or borderless design of the liquid crystal display panel, and the complicated structure is easy to reduce the liquid crystal display. The process yield of the panel.
  • the technical problem to be solved by the embodiments of the present invention is to provide a liquid crystal display device and a shift register thereof, which are beneficial to a narrow bezel or a borderless design of the liquid crystal display panel, and improve the process yield of the liquid crystal display panel.
  • a technical solution adopted by the present invention is to provide a shift register having a plurality of shift register units, each shift register unit including a storage circuit for receiving and temporarily storing a pre-stage signal, and a potential control a circuit and an inverter circuit for charging and discharging the scan line of the liquid crystal display panel, a first node between the potential control circuit and the inverter circuit, a second node between the storage circuit and the potential control circuit, and the storage circuit is used in the first Selectively inverting the received level signal and outputting it to the second node under control of a timing signal, the potential control circuit is configured to provide a low level signal for the first node, and the inverting circuit is used for controlling the second timing signal Selectively inverting the low level signal provided by the potential control circuit and outputting;
  • the storage circuit includes an input end, a first switch tube, a second switch tube, a first inverter, and a second inverter.
  • the first switch tube is connected to the input end, and between the first switch tube and the first inverter With a third node, the second switch is connected to the second inverter, the potential control circuit comprises a seventh switch tube, an eighth switch tube and a ninth switch tube, and the seventh switch tube and the ninth switch tube are connected to the second node,
  • the eighth switch tube is connected to the first node
  • the inverter circuit comprises a tenth switch tube, an eleventh switch tube and an output end, the tenth switch tube and the eleventh switch tube are connected to the first node, and the eleventh switch tube is The two ends are connected to the output.
  • the control end of the first switch tube is connected to the external circuit to receive the first timing signal, and the first end of the first switch tube is connected to the input end to receive the output signal of the shift register unit of the previous stage, and the second switch of the first switch tube
  • the terminal is connected to the third node, and the control end of the second switch tube is connected to the external circuit to receive the first timing signal, the first end of the second switch tube is connected to the second inverter, and the second end of the second switch tube is connected to the third node .
  • the first switch tube is an N-type MOS tube, and the control end, the first end and the second end of the first switch tube are respectively a gate, a source and a drain of the N-type MOS tube, and the second switch tube is a P-type
  • the MOS transistor, the control terminal, the first terminal and the second terminal of the second switching transistor are respectively a gate, a source and a drain of the P-type MOS transistor.
  • the first inverter includes a third switch tube and a fourth switch tube
  • the second inverter includes a fifth switch tube and a sixth switch tube
  • the control end of the third switch tube is connected to the third node
  • the third switch tube The first end is connected to the external circuit to receive the high level signal
  • the second end of the third switch tube is connected to the second node
  • the control end of the fourth switch tube is connected to the third node
  • the first end of the fourth switch tube is connected to the external circuit
  • the second end of the fourth switch tube is connected to the second node
  • the control end of the fifth switch tube is connected to the second node
  • the first end of the fifth switch tube is connected to the external circuit to receive the high level signal.
  • the second end of the fifth switch tube is connected to the second end of the second switch tube
  • the control end of the sixth switch tube is connected to the second node
  • the first end of the sixth switch tube is connected to the external circuit to receive the low level signal
  • sixth The second end of the switch tube is connected to the second end of the second switch tube.
  • the third switch tube is a P-type MOS tube
  • the control end, the first end and the second end of the third switch tube are respectively a gate, a source and a drain of the P-type MOS tube
  • the fourth switch tube is an N-type
  • the MOS tube, the control end, the first end and the second end of the fourth switch tube are respectively a gate, a source and a drain of the N-type MOS tube
  • the fifth switch tube is a P-type MOS tube
  • the fifth switch tube is controlled
  • the first end, the first end and the second end are respectively a gate, a source and a drain of the P-type MOS tube
  • the sixth switch tube is an N-type MOS tube
  • the control end, the first end and the second end of the sixth switch tube They are the gate, source and drain of the N-type MOS transistor, respectively.
  • control end of the seventh switch tube is connected to the second node
  • first end of the seventh switch tube is connected to the second node
  • second end of the seventh switch tube is connected to the first node
  • control end of the eighth switch tube is connected to the external circuit Receiving the second timing signal
  • first end of the eighth switch tube is connected to the second node
  • the second end of the eighth switch tube is connected to the first node
  • the control end of the ninth switch tube is connected to the external circuit to receive the second timing signal
  • the first end of the ninth switch tube is connected to the second node
  • the second end of the ninth switch tube is connected to an external circuit to receive a high level signal.
  • the seventh switch tube is an N-type MOS tube or a P-type MOS tube
  • the control end, the first end and the second end of the seventh switch tube are respectively a gate and a source of the N-type MOS tube or the P-type MOS tube
  • the drain, the eighth switch tube is an N-type MOS tube, and the control end, the first end and the second end of the eighth switch tube are respectively a gate, a source and a drain of the N-type MOS tube
  • the ninth switch tube is a P
  • the MOS transistor, the control terminal, the first terminal and the second terminal of the ninth switch transistor are respectively a gate, a source and a drain of the P-type MOS transistor.
  • the control end of the tenth switch tube is connected to the first node, the first end of the tenth switch tube is connected to the input end to receive the output signal of the shift register unit of the upper stage, and the second end of the tenth switch tube is connected to the external circuit.
  • Receiving a high level signal the control end of the eleventh switch tube is connected to the first node, the first end of the eleventh switch tube is connected to an external circuit to receive a low level signal, and the second end of the eleventh switch tube is connected to the output end .
  • the tenth switch tube is a P-type MOS tube, and the control end, the first end and the second end of the tenth switch tube are respectively a gate, a source and a drain of the P-type MOS tube, and the eleventh switch tube is a N
  • the MOS transistor, the control terminal, the first terminal and the second terminal of the eleventh switch transistor are respectively a gate, a source and a drain of the N-type MOS transistor.
  • a shift register having a plurality of shift register units, each shift register unit including a storage circuit and a potential for receiving and temporarily storing the pre-stage signals.
  • a control circuit and an inverter circuit for charging and discharging the scan line of the liquid crystal display panel, a first node between the potential control circuit and the inverter circuit, and a second node between the storage circuit and the potential control circuit, the storage circuit being used for Selectively inverting the received level signal and outputting to the second node under control of the first timing signal
  • the potential control circuit is configured to provide a low level signal for the first node
  • the inverting circuit is used for the second timing signal Under control, the low-level signal provided by the potential control circuit is selectively inverted and output.
  • the storage circuit includes an input end, a first switch tube, a second switch tube, a first inverter, and a second inverter.
  • the first switch tube and the first inverter have a third node, and the first switch Tube
  • the control terminal is connected to the external circuit to receive the first timing signal, the first end of the first switch tube is connected to the input end to receive the output signal of the shift register unit of the previous stage, and the second end of the first switch tube is connected to the third node
  • the control end of the second switch tube is connected to the external circuit to receive the first timing signal, the first end of the second switch tube is connected to the second inverter, and the second end of the second switch tube is connected to the third node.
  • the first switch tube is an N-type MOS tube, and the control end, the first end and the second end of the first switch tube are respectively a gate, a source and a drain of the N-type MOS tube, and the second switch tube is a P-type
  • the MOS transistor, the control terminal, the first terminal and the second terminal of the second switching transistor are respectively a gate, a source and a drain of the P-type MOS transistor.
  • the first inverter includes a third switch tube and a fourth switch tube
  • the second inverter includes a fifth switch tube and a sixth switch tube
  • the control end of the third switch tube is connected to the third node
  • the third switch tube The first end is connected to the external circuit to receive the high level signal
  • the second end of the third switch tube is connected to the second node
  • the control end of the fourth switch tube is connected to the third node
  • the first end of the fourth switch tube is connected to the external circuit
  • the second end of the fourth switch tube is connected to the second node
  • the control end of the fifth switch tube is connected to the second node
  • the first end of the fifth switch tube is connected to the external circuit to receive the high level signal.
  • the second end of the fifth switch tube is connected to the second end of the second switch tube
  • the control end of the sixth switch tube is connected to the second node
  • the first end of the sixth switch tube is connected to the external circuit to receive the low level signal
  • sixth The second end of the switch tube is connected to the second end of the second switch tube.
  • the third switch tube is a P-type MOS tube
  • the control end, the first end and the second end of the third switch tube are respectively a gate, a source and a drain of the P-type MOS tube
  • the fourth switch tube is an N-type
  • the MOS tube, the control end, the first end and the second end of the fourth switch tube are respectively a gate, a source and a drain of the N-type MOS tube
  • the fifth switch tube is a P-type MOS tube
  • the fifth switch tube is controlled
  • the first end, the first end and the second end are respectively a gate, a source and a drain of the P-type MOS tube
  • the sixth switch tube is an N-type MOS tube
  • the control end, the first end and the second end of the sixth switch tube They are the gate, source and drain of the N-type MOS transistor, respectively.
  • the potential control circuit includes a seventh switch tube, an eighth switch tube and a ninth switch tube, wherein the control end of the seventh switch tube is connected to the second node, and the first end of the seventh switch tube is connected to the second node, and the seventh switch tube
  • the second end is connected to the first node
  • the control end of the eighth switch tube is connected to the external circuit to receive the second timing signal
  • the first end of the eighth switch tube is connected to the second node
  • the second end of the eighth switch tube is connected to the first end
  • the control end of the ninth switch tube is connected to the external circuit to receive the second timing signal
  • the first end of the ninth switch tube is connected to the second node
  • the second end of the ninth switch tube is connected to the external circuit. Receive a high level signal.
  • the seventh switch tube is an N-type MOS tube or a P-type MOS tube
  • the control end, the first end and the second end of the seventh switch tube are respectively a gate and a source of the N-type MOS tube or the P-type MOS tube
  • the drain, the eighth switch tube is an N-type MOS tube, and the control end, the first end and the second end of the eighth switch tube are respectively a gate, a source and a drain of the N-type MOS tube
  • the ninth switch tube is a P
  • the MOS transistor, the control terminal, the first terminal and the second terminal of the ninth switch transistor are respectively a gate, a source and a drain of the P-type MOS transistor.
  • the inverting circuit comprises a tenth switch tube, an eleventh switch tube and an output end, wherein the control end of the tenth switch tube is connected to the first node, and the first end of the tenth switch tube is connected to the input end to receive the shift of the upper stage
  • the output signal of the register unit, the second end of the tenth switch tube is connected to the external circuit to receive the high level signal, the control end of the eleventh switch tube is connected to the first node, and the first end of the eleventh switch tube is connected to the external circuit to Receiving a low level signal, the second end of the eleventh switch is connected to the output end.
  • the tenth switch tube is a P-type MOS tube, and the control end, the first end and the second end of the tenth switch tube are respectively a gate, a source and a drain of the P-type MOS tube, and the eleventh switch tube is a N
  • the MOS transistor, the control terminal, the first terminal and the second terminal of the eleventh switch transistor are respectively a gate, a source and a drain of the N-type MOS transistor.
  • a liquid crystal display device including a liquid crystal display panel, a data driving circuit for providing a data signal to the liquid crystal display panel, and a scan driving for providing a scanning signal to the liquid crystal display panel.
  • the circuit, the data driving circuit and the scan driving circuit respectively comprise a shift register for controlling the output timing of the data signal and the scan signal
  • the shift register has a plurality of shift register units, each shift register unit includes receiving and temporarily storing the pre-stage a storage circuit of the signal, a potential control circuit, and an inverter circuit for charging and discharging the scan line of the liquid crystal display panel, a first node between the potential control circuit and the inverter circuit, and a second node between the storage circuit and the potential control circuit
  • the storage circuit is configured to selectively invert the received level signal to output to the second node under the control of the first timing signal
  • the potential control circuit is configured to provide a low level signal for the first node
  • the inverting circuit is used for Selectively lowering the power provided by the potential control circuit under the control of the second timing signal After the output signal is inverted.
  • the embodiment of the present invention includes only a storage circuit, a potential control circuit, and an inverting circuit by designing each shift register unit, wherein the potential control circuit and the inverting circuit are Having a second node therebetween, the storage circuit and the potential control circuit have a second node, and the storage circuit is configured to selectively connect under the control of the first timing signal The received level signal is inverted and output to the second node, the potential control circuit is configured to provide a low level signal for the first node, and the inverting circuit is configured to selectively provide the potential control circuit under the control of the second timing signal The low-level signal is inverted and outputted.
  • the shift register formed by connecting the plurality of shift register units in series has a large area, thereby facilitating the narrow border of the liquid crystal display panel or The frameless design, and the structure of the short answer is easier to ensure the process yield of the liquid crystal display panel.
  • FIG. 1 is a schematic structural view of a liquid crystal display device according to a preferred embodiment of the present invention.
  • FIG. 2 is a circuit diagram of a shift register unit according to a first embodiment of the present invention.
  • FIG. 3 is a circuit diagram of a shift register unit according to a second embodiment of the present invention.
  • Figure 4 is a schematic view showing the connection of a preferred embodiment of the shift register unit shown in Figure 2;
  • Figure 5 is a timing diagram of signals applied to an embodiment of the shift register unit shown in Figure 4.
  • the liquid crystal display device 10 includes a liquid crystal display panel 11, a data driving circuit 12 for providing a data signal to the liquid crystal display panel 11, and a liquid crystal display panel.
  • a scan driving circuit 13 for providing a scan signal, the liquid crystal display device 10 is manufactured by a GOA (Gate Driver on Array) technology, and the data driving circuit 12 and the scan driving circuit 13 respectively pass through a plurality of data lines and a plurality of scanning lines and the liquid crystal display panel 11 connection.
  • GOA Gate Driver on Array
  • the scan driving circuit 13 includes a shift register, and controls the output timing of the data signal and the scan signal through the shift register.
  • the scan driving circuit 13 sequentially outputs a high level signal to a plurality of scan lines under the control of the shift register to control the on and off of the thin film transistors arranged in a matrix column by column, thereby realizing the display screen.
  • each shift register unit 20 includes a storage circuit 31 that receives and temporarily stores the previous stage signals, a potential control circuit 32, and The inverter circuit 33 for charging and discharging the scanning line of the liquid crystal display panel 11.
  • the storage node 31 and the potential control circuit 32 have a second node P 2 between them, and the potential control circuit 32 and the inverter circuit 33 have a first node P 1 between them, and the storage circuit 31 is used under the control of the first timing signal CK 1 Selectively inverting the received level signal and outputting it to the second node P 2 , the potential control circuit 32 is for supplying the first node P 1 with the low level signal V GL , and the inverting circuit 33 is for the second timing signal Under the control of CK 2 , the low level signal V GL supplied from the potential control circuit 32 is selectively inverted and output.
  • CK 1 Selectively inverting the received level signal and outputting it to the second node P 2
  • the potential control circuit 32 is for supplying the first node P 1 with the low level signal V GL
  • the inverting circuit 33 is for the second timing signal Under the control of CK 2
  • the low level signal V GL supplied from the potential control circuit 32 is selectively inverted and output.
  • the memory circuit 31 includes an input terminal V1N1, a first switching transistor T 1, a second switching transistor T 2, a first inverter 311 and second inverter 312.
  • the first switch tube T 1 and the first inverter 311 have a third node P 3 , and the control end G 1 of the first switch tube T 1 is connected to an external circuit to receive the first timing signal CK 1 , and the first switch tube T S 1 of the first terminal 1 is connected to the input terminal V1N1 receiving an output signal of the shift register unit 20, a first switch transistor T 1 D 1 of a second end connected to the third node P 3, the second switching transistor T 2
  • the control terminal G 2 is connected to the external circuit to receive the first timing signal CK 1
  • the first terminal S 2 of the second switching transistor T 2 is connected to the second inverter 312, and the second terminal D 2 of the second switching transistor T 2 is connected.
  • the third node P 3 wherein the control terminal of the first switching transistor T 1 as G 1 in the second switching transistor and the control terminal T 2
  • the first switching transistor T 1 is N-MOS transistor
  • the control terminal of the first switch transistor T 1 G 1, S 1 a first end and a second gate terminals D 1 are N-type MOS transistor
  • the second switching transistor T 2 is a P-type MOS transistor
  • the second switching transistor control terminal T 2 of G 2 a first end and a second end S 2 D 2 respectively, the gate of the P-type MOS transistor, the source And the drain.
  • the first inverter 311 is preferably constituted by a third switching transistor T 3 and a fourth switching transistor T 4
  • the second inverter 312 is composed of a fifth switching transistor T 5 and a sixth switching transistor T 6 . among them:
  • the control terminal G 3 of the third switch tube T 3 is connected to the third node P 3 , and the first end S 3 of the third switch tube T 3 is connected to the external circuit to receive the high level signal V GH , and the third switch tube T 3
  • the two ends D 3 are connected to the second node P 2 .
  • the control terminal G 4 of the fourth switch tube T 4 is connected to the third node P 3 , and the first end S 4 of the fourth switch tube T 4 is connected to an external circuit to receive the low level signal V GL , and the fourth switch tube T 4
  • the two ends D 4 are connected to the second node P 2 .
  • the control terminal G 5 of the fifth switch tube T 5 is connected to the second node P 2 , and the first end S 5 of the fifth switch tube T 5 is connected to the external circuit to receive the high level signal V GH , and the fifth switch tube T 5 D 5 second end connected to the second end of the second switch transistor T 2 D 2.
  • the control terminal G 6 of the sixth switch tube T 6 is connected to the second node P 2 , and the first end S 6 of the sixth switch tube T 6 is connected to the external circuit to receive the low level signal V GL , and the sixth switch tube T 6 second end connected to the second switch transistor D 6 T D 2 of the second end 2.
  • the third switch transistor T 3 is a P-type MOS transistor, the control terminal of the third switching transistor T 3 of G 3, a first end and a second end S 3 D 3 are P-type MOS transistor gate , source and drain, the fourth switch T 4 are N-type MOS transistor, the control terminal of the fourth switching transistor T 4 G 4, a first end and a second end D 4 S 4 are N-MOS transistor gate electrode, source and drain electrodes, a fifth switch transistor T 5 is a P-type MOS transistor, the control terminal of the fifth switch transistor T 5 is G 5, a first end and a second end S 5 D 5 P-type MOS transistors respectively of the the gate, source and drain, the sixth switch transistor T 6 are N-type MOS transistor, the control terminal of the sixth switch transistor T 6, G 6, a first end and a second end S 6 D 6 are N-type MOS transistor The gate, source and drain.
  • the third switching transistor a first end of a first T 3 S 3, a first end of the fourth switching transistor T 4 S 4, a first end of the fifth switching transistor T S 5 and the sixth switch. 6 of the tube 5 T
  • the terminal S 6 can be connected to different external circuits, or can be combined to connect different external circuits.
  • the potential control circuit 32 includes a seventh switching transistor T 7 , an eighth switching transistor T 8 , and a ninth switching transistor T 9 .
  • the control terminal G 7 of the seventh switch tube T 7 is connected to the second node P 2
  • the first end S 7 of the seventh switch tube T 7 is connected to the second node P 2
  • the second end D 7 of the seventh switch tube T 7 is connected.
  • the first node P 1 , the control terminal G 8 of the eighth switch tube T 8 is connected to the external circuit to receive the second timing signal CK 2 , and the first end S 8 of the eighth switch tube T 8 is connected to the second node P 2 , the eighth The second end D 8 of the switch tube T 8 is connected to the first node P 1 , and the control end G 9 of the ninth switch tube T 9 is connected to the external circuit to receive the second timing signal CK 2 , the first end of the ninth switch tube T 9 S 9 connected to the second node P 2, the second end of the ninth switching transistor T D 9 9 connected to an external circuit to receive a high level signal V GH.
  • the seventh switch transistor T 7 is an N-type MOS transistor
  • the control terminal of the seventh switch transistor T 7 of the G 7 a first end and a second end S 7 D 7 are gate of the N-type MOS transistor , source and drain
  • the eighth switching transistor T 8 are N-type MOS transistor
  • the control terminal of the eighth switch transistor T 8 of G 8 a first end and a second end S 8 D 8 are N-type MOS transistor gate electrode, source and drain
  • a ninth switch transistor T 9 P-type MOS transistor the control terminal of the ninth switching transistor T 9 of G 9, a first end and a second end S 9 D 9 respectively of the P-MOS transistor Gate, source and drain.
  • the inverter circuit 33 includes a tenth switch tube T 10 , an eleventh switch tube T 11 and an output terminal VOUT , and the control terminal G 10 of the tenth switch tube T 10 is connected to the first node P 1 and the tenth switch tube T 10
  • One end S 10 is connected to the input terminal V1N1 to receive the output signal of the shift register unit of the upper stage, and the second end D 10 of the tenth switch tube T 10 is connected to the external circuit to receive the high level signal.
  • the eleventh switch tube T 11 The control terminal G 11 is connected to the first node P 1 , the first end S 11 of the eleventh switch tube T 11 is connected to the external circuit to receive the low level signal, and the second end D 11 of the eleventh switch tube T 11 is connected to the output. End VOUT.
  • the tenth switch transistor T 10 is a P-type MOS transistor
  • the control terminal of the tenth switch transistor T 10 of the G 10 a first end and a second end S 10 D 10 are P-type MOS transistor gate , source and drain
  • the eleventh switching transistor T 11 are N-type MOS transistor
  • an eleventh switching transistor of the control terminal T 11 G 11 S 11 a first end and a second end D 11 are N-type MOS transistor The gate, source and drain.
  • the tenth switch and the eleventh switch transistor T 10 T 11 configured with inverter for the liquid crystal display panel 11 of the scanning line charging and discharging, a memory circuit 31 for temporarily receiving and storing from The amount of power that is input to the input terminal V1N1.
  • the first timing signal CK 1 is at a high potential
  • the first switching transistor T 1 is turned on and the second switching transistor T 2 is turned off, and the high potential connected from the input terminal V1N1 can be transmitted to the third node P 3 .
  • the first inverter 311 composed of the third switching transistor T 3 and the fourth switching transistor T 4 can pull the second node P 2 to a low potential.
  • the second switching transistor T 2 is turned on and the first switching transistor T 1 is turned off, by the third switching transistor T 3 , the fourth switching transistor T 4 , and the fifth
  • the closed loop formed by the switch tube T 5 , the sixth switch tube T 6 , and the second switch tube T 2 can stably maintain the high potential of the third node P 3 and the low potential of the second node P 2 .
  • the eighth switching transistor T 8 is turned on and the ninth switching transistor T 9 is turned off, and the first node P 1 can be pulled down to the low potential by the second node P 2 .
  • the first points P 1 through the tenth and the eleventh switch transistor T 10 the inverted switching action of the inverter constituting the tube T 11 outputs a high voltage to the shift register unit 20 connected to the scanning line.
  • the eighth switching transistor T 8 is turned off and the ninth switching transistor T 9 is turned on, and the first node P 1 is pulled high by the high-level signal V GH to output a low potential to The scan line to which the shift register unit 20 is connected.
  • the second node P 2 is at a high potential
  • the seventh switch T 7 is turned on
  • the first node P 1 is connected to the second node P 2 and is stably at a high potential
  • the output low potential can be stably outputted to the shift register.
  • the scan line to which unit 20 is connected.
  • the second node P 2 is at a low potential
  • the seventh switching transistor T 7 is turned off, without affecting the potential of the first node P 1 and the charging of the scanning line connected to the shift register unit 20.
  • the seventh switch transistor T 7 may also be a P-type MOS transistor shown in FIG. 3, when the control terminal of the seventh switch transistor T 7 of the G 7, a first end S 7 and second terminal D 7 are the gate, source and drain of the N-type MOS transistor, respectively.
  • the difference from the embodiment shown in FIG. 2 is that during non-charging, the third node P 3 is at a low potential and the second node P 2 is at a high potential, and the seventh switching transistor T 7 is turned on to ensure that it is not charged. during the first points P 1 and P 2 connected to the second node at a high potential, thereby stabilizing the output scan lines and the low potential to the shift register unit 20 is connected. During charging, the third node P 3 is at a high potential, and the seventh switching transistor T 7 is turned off, without affecting charging.
  • FIG. 4 is a connection diagram of a preferred embodiment of the shift register unit 20 of FIG. 2.
  • the shift register unit 20 connected to the scanning lines of the odd-numbered items such as the first, third, fifth, and n-1 is distributed on the left side of the liquid crystal display panel 11, and the second and fourth,
  • the shift register unit 20 to which the scanning lines of the even-numbered items of the n-th order are connected is distributed on the right side of the liquid crystal display panel 11.
  • Each shift register unit 20 controls the potential of one horizontal scanning line, for example, the shift register unit is connected to the n-th scanning line G n to G n 20 controls the potential of the scanning line.
  • the shift register unit 20 on both sides of the liquid crystal display panel 11 is connected to the driving IC located at the lower portion of the liquid crystal display panel 11 to obtain a driving signal, and the adjacent two shift register units 20 are also connected by a signal line, thereby ensuring each shift.
  • the bit register unit 20 can control the charging and discharging of the scanning lines column by column.
  • Figure 5 is a timing diagram of signals applied to an embodiment of the shift register unit shown in Figure 4.
  • the DC high voltage source is turned on to obtain a high level signal V GH
  • the DC low voltage source is turned on to obtain a low level signal V GL
  • CK 1 _L and CK 2 —L are driving the liquid crystal display panel 11 to the left side.
  • the clock signals of the bit register unit 20, CK 1 —R and CK 2 —R are clock signals of the shift register unit 20 on the right side of the liquid crystal display panel 11.
  • t1 to t3 are the preparation time of the n-2th scanning line Gn -2 before charging
  • t3 to t4 are the charging time of the scanning line Gn -2
  • t3 ⁇ t5 is the n-th scanning line G n at the time of preparation before charging
  • t5 ⁇ t6 scanning line G n is the charging time.
  • the potentials of CK 2 _L and scan line G n-4 start to rise, the third node P 3 of the shift register unit 20 connected to the scan line G n-2 is charged to a high potential, and the second node P 2 is pulled. To low potential.
  • the potentials of CK 2 —L and the scanning line G n-4 are lowered, but the amount of electric power stored in the storage circuit 31 in the shift register unit 20 can cause the third node P of the shift register unit 20 to which the scanning line G n-2 is connected
  • the potential of 3 and the second node P 2 can be temporarily saved until the next potential rise of CK 2 _L.
  • the potential of CK 1 _L rises, the eighth switching transistor T 8 of the shift register unit 20 connected to the scanning line G n-2 is turned on, and the ninth switching transistor T 9 is turned off, at which time the shift register unit 20 is turned off.
  • the first node P 1 is brought to a low potential by the second node P 2 , and is outputted from the output terminal VOUT to the scanning line G n-2 via the inversion of the tenth switching transistor T 10 and the eleventh switching transistor T 11 .
  • the potential of CK 1 _L is lowered, the eighth switching transistor T 8 of the shift register unit 20 connected to the scanning line G n-2 is turned off, and the ninth switching transistor T 9 is turned on.
  • the shift register unit is turned on.
  • the first node P 1 of 20 is pulled to a high potential, and the scanning line G n-4 is pulled to a low potential.
  • CK2_L raising the potential shift register unit connected to the scanning line G n of the eighth switch 20 is turned on tube T 8 T 9 and the ninth switching transistor off, the first node of the shift register unit P 1 of 20
  • the second node P 2 is pulled to a low potential, and after the inversion of the tenth switching transistor T 10 and the eleventh switching transistor T 11 , a high potential is output from the output terminal VOUT to the scanning line G n-2 .
  • the potential of CK 2 _L is lowered, the eighth switching transistor T 8 of the shift register unit 20 connected to the scanning line G n is turned off, and the ninth switching transistor T 9 is turned on, and the first node of the shift register unit 20 is turned on.
  • P 1 is pulled to a high potential, and the scanning line G n is pulled to a low potential.
  • each shift register unit 20 connected to the scan lines G 1 , G 2 , ... G n-1 , G n can be column-by-rowd as scan lines G 1 , G 2 under appropriate driving of the clock signal.
  • ... G n-1 , G n are charged and discharged, so that the liquid crystal display panel 11 normally displays a picture.
  • the embodiment of the present invention includes, by designing each shift register unit, only a storage circuit for receiving and temporarily storing a pre-stage signal, a potential control circuit, and an inverter circuit for charging and discharging a scan line of the liquid crystal display panel, wherein There is a first node between the potential control circuit and the inverter circuit, and the storage circuit and the potential control circuit have a second node, and the storage circuit is configured to selectively invert the received level signal after the control of the first timing signal Outputting to the second node, the potential control circuit is configured to provide a low level signal for the first node, and the inverting circuit is configured to selectively invert the low level signal provided by the potential control circuit and output the output under the control of the second timing signal Since the structure of the single shift register unit is relatively simple, the shift register formed by connecting the plurality of shift register units in series has a large area, thereby facilitating the narrow border or the borderless design of the liquid crystal display panel, and the short answer The structure is relatively easy to ensure the process yield of

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Abstract

一种液晶显示装置及其移位寄存器。该移位寄存器的每一移位寄存单元包括接收并暂时存储前级讯号的存储电路（31）、电位控制电路（32）以及为扫描线充电和放电的反相电路（33），电位控制电路（32）和反相电路（33）之间具有第一节点（P2），存储电路（31）和电位控制电路（32）之间具有第二节点（P1），存储电路（31）用于选择性将接收的电平信号（V1N1）反相后输出至第二节点（P1），电位控制电路（32）用于为第一节点（P2）提供低电平信号，反相电路（33）用于选择性将电位控制电路（32）提供的低电平信号反相后输出。该移位寄存器有利于液晶显示面板的窄边框或无边框设计，并提升制程良率。

Description

液晶显示装置及其移位寄存器 【技术领域】
本发明涉及液晶显示驱动技术领域，具体而言涉及一种液晶显示装置及其移位寄存器。
【背景技术】
液晶显示装置需要具有适当的驱动电路，驱动电路一般包括数据驱动电路和扫描驱动电路。其中，扫描驱动电路常应用移位寄存器作为核心电路元件。
通常，移位寄存器由多个移位寄存单元串联而成，并且上一级移位寄存单元的输出信号作为后一级移位寄存单元的输入信号。然而，当前多数单个移位寄存单元的结构较为复杂，多个移位寄存单元串联后所占区域较大，不利于液晶显示面板的窄边框或无边框设计，并且复杂的结构极易降低液晶显示面板的制程良率。
【发明内容】
有鉴于此，本发明实施例所要解决的技术问题是提供一种液晶显示装置及其移位寄存器，有利于液晶显示面板的窄边框或无边框设计，并提升液晶显示面板的制程良率。
为解决上述技术问题，本发明采用的一个技术方案是：提供一种移位寄存器，具有多个移位寄存单元，每一移位寄存单元包括接收并暂时存储前级讯号的存储电路、电位控制电路和为液晶显示面板的扫描线充电和放电的反相电路，电位控制电路和反相电路之间具有第一节点，存储电路和电位控制电路之间具有第二节点，存储电路用于在第一时序信号的控制下选择性将接收的电平信号反相后输出至第二节点，电位控制电路用于为第一节点提供低电平信号，反相电路用于在第二时序信号的控制下选择性将电位控制电路提供的低电平信号反相后输出；
其中，存储电路包括输入端、第一开关管、第二开关管、第一反相器和第二反相器，第一开关管连接输入端，第一开关管和第一反相器之间具 有第三节点，第二开关管连接第二反相器，电位控制电路包括第七开关管、第八开关管和第九开关管，第七开关管和第九开关管连接第二节点，第八开关管连接第一节点，反相电路包括第十开关管、第十一开关管和输出端，第十开关管和所述第十一开关管连接第一节点，第十一开关管的第二端连接输出端。
其中，第一开关管的控制端连接外部电路以接收第一时序信号，第一开关管的第一端连接输入端以接收上一级移位寄存单元的输出信号，第一开关管的第二端连接第三节点，第二开关管的控制端连接外部电路以接收第一时序信号，第二开关管的第一端连接第二反相器，第二开关管的第二端连接第三节点。
其中，第一开关管为N型MOS管，第一开关管的控制端、第一端和第二端分别为N型MOS管的栅极、源极和漏极，第二开关管为P型MOS管，第二开关管的控制端、第一端和第二端分别为P型MOS管的栅极、源极和漏极。
其中，第一反相器包括第三开关管和第四开关管，第二反相器包括第五开关管和第六开关管，第三开关管的控制端连接第三节点，第三开关管的第一端连接外部电路以接收高电平信号，第三开关管的第二端连接第二节点，第四开关管的控制端连接第三节点，第四开关管的第一端连接外部电路以接收低电平信号，第四开关管的第二端连接第二节点，第五开关管的控制端连接第二节点，第五开关管的第一端连接外部电路以接收高电平信号，第五开关管的第二端连接第二开关管的第二端，第六开关管的控制端连接第二节点，第六开关管的第一端连接外部电路以接收低电平信号，第六开关管的第二端连接第二开关管的第二端。
其中，第三开关管为P型MOS管，第三开关管的控制端、第一端和第二端分别为P型MOS管的栅极、源极和漏极，第四开关管为N型MOS管，第四开关管的控制端、第一端和第二端分别为N型MOS管的栅极、源极和漏极，第五开关管为P型MOS管，第五开关管的控制端、第一端和第二端分别为P型MOS管的栅极、源极和漏极，第六开关管为N型MOS管，第六开关管的控制端、第一端和第二端分别为N型MOS管的栅极、源极和漏极。
其中，第七开关管的控制端连接第二节点，第七开关管的第一端连接第二节点，第七开关管的第二端连接第一节点，第八开关管的控制端连接外部电路以接收第二时序信号，第八开关管的第一端连接第二节点，第八开关管的第二端连接第一节点，第九开关管的控制端连接外部电路以接收第二时序信号，第九开关管的第一端连接第二节点，第九开关管的第二端连接外部电路以接收高电平信号。
其中，第七开关管为N型MOS管或P型MOS管，第七开关管的控制端、第一端和第二端分别为N型MOS管或P型MOS管的栅极、源极和漏极，第八开关管为N型MOS管，第八开关管的控制端、第一端和第二端分别为N型MOS管的栅极、源极和漏极，第九开关管为P型MOS管，第九开关管的控制端、第一端和第二端分别为P型MOS管的栅极、源极和漏极。
其中，第十开关管的控制端连接第一节点，第十开关管的第一端连接输入端以接收上一级移位寄存单元的输出信号，第十开关管的第二端连接外部电路以接收高电平信号，第十一开关管的控制端连接第一节点，第十一开关管的第一端连接外部电路以接收低电平信号，第十一开关管的第二端连接输出端。
其中，第十开关管为P型MOS管，第十开关管的控制端、第一端和第二端分别为P型MOS管的栅极、源极和漏极，第十一开关管为N型MOS管，第十一开关管的控制端、第一端和第二端分别为N型MOS管的栅极、源极和漏极。
为解决上述技术问题，本发明采用的另一个技术方案是：提供一种移位寄存器，具有多个移位寄存单元，每一移位寄存单元包括接收并暂时存储前级讯号的存储电路、电位控制电路和为液晶显示面板的扫描线充电和放电的反相电路，电位控制电路和反相电路之间具有第一节点，存储电路和电位控制电路之间具有第二节点，存储电路用于在第一时序信号的控制下选择性将接收的电平信号反相后输出至第二节点，电位控制电路用于为第一节点提供低电平信号，反相电路用于在第二时序信号的控制下选择性将电位控制电路提供的低电平信号反相后输出。
其中，存储电路包括输入端、第一开关管、第二开关管、第一反相器和第二反相器，第一开关管和第一反相器之间具有第三节点，第一开关管 的控制端连接外部电路以接收第一时序信号，第一开关管的第一端连接输入端以接收上一级移位寄存单元的输出信号，第一开关管的第二端连接第三节点，第二开关管的控制端连接外部电路以接收第一时序信号，第二开关管的第一端连接第二反相器，第二开关管的第二端连接第三节点。
其中，第一开关管为N型MOS管，第一开关管的控制端、第一端和第二端分别为N型MOS管的栅极、源极和漏极，第二开关管为P型MOS管，第二开关管的控制端、第一端和第二端分别为P型MOS管的栅极、源极和漏极。
其中，第一反相器包括第三开关管和第四开关管，第二反相器包括第五开关管和第六开关管，第三开关管的控制端连接第三节点，第三开关管的第一端连接外部电路以接收高电平信号，第三开关管的第二端连接第二节点，第四开关管的控制端连接第三节点，第四开关管的第一端连接外部电路以接收低电平信号，第四开关管的第二端连接第二节点，第五开关管的控制端连接第二节点，第五开关管的第一端连接外部电路以接收高电平信号，第五开关管的第二端连接第二开关管的第二端，第六开关管的控制端连接第二节点，第六开关管的第一端连接外部电路以接收低电平信号，第六开关管的第二端连接第二开关管的第二端。
其中，第三开关管为P型MOS管，第三开关管的控制端、第一端和第二端分别为P型MOS管的栅极、源极和漏极，第四开关管为N型MOS管，第四开关管的控制端、第一端和第二端分别为N型MOS管的栅极、源极和漏极，第五开关管为P型MOS管，第五开关管的控制端、第一端和第二端分别为P型MOS管的栅极、源极和漏极，第六开关管为N型MOS管，第六开关管的控制端、第一端和第二端分别为N型MOS管的栅极、源极和漏极。
其中，电位控制电路包括第七开关管、第八开关管和第九开关管，第七开关管的控制端连接第二节点，第七开关管的第一端连接第二节点，第七开关管的第二端连接第一节点，第八开关管的控制端连接外部电路以接收第二时序信号，第八开关管的第一端连接第二节点，第八开关管的第二端连接第一节点，第九开关管的控制端连接外部电路以接收第二时序信号，第九开关管的第一端连接第二节点，第九开关管的第二端连接外部电路以 接收高电平信号。
其中，第七开关管为N型MOS管或P型MOS管，第七开关管的控制端、第一端和第二端分别为N型MOS管或P型MOS管的栅极、源极和漏极，第八开关管为N型MOS管，第八开关管的控制端、第一端和第二端分别为N型MOS管的栅极、源极和漏极，第九开关管为P型MOS管，第九开关管的控制端、第一端和第二端分别为P型MOS管的栅极、源极和漏极。
其中，反相电路包括第十开关管、第十一开关管和输出端，第十开关管的控制端连接第一节点，第十开关管的第一端连接输入端以接收上一级移位寄存单元的输出信号，第十开关管的第二端连接外部电路以接收高电平信号，第十一开关管的控制端连接第一节点，第十一开关管的第一端连接外部电路以接收低电平信号，第十一开关管的第二端连接输出端。
其中，第十开关管为P型MOS管，第十开关管的控制端、第一端和第二端分别为P型MOS管的栅极、源极和漏极，第十一开关管为N型MOS管，第十一开关管的控制端、第一端和第二端分别为N型MOS管的栅极、源极和漏极。
为解决上述技术问题，本发明采用的又一个技术方案是：提供一种液晶显示装置，包括液晶显示面板、为液晶显示面板提供数据信号的数据驱动电路以及为液晶显示面板提供扫描信号的扫描驱动电路，数据驱动电路和扫描驱动电路分别包括移位寄存器，以控制数据信号和扫描信号的输出时序，移位寄存器具有多个移位寄存单元，每一移位寄存单元包括接收并暂时存储前级讯号的存储电路、电位控制电路和为液晶显示面板的扫描线充电和放电的反相电路，电位控制电路和反相电路之间具有第一节点，存储电路和电位控制电路之间具有第二节点，存储电路用于在第一时序信号的控制下选择性将接收的电平信号反相后输出至第二节点，电位控制电路用于为第一节点提供低电平信号，反相电路用于在第二时序信号的控制下选择性将电位控制电路提供的低电平信号反相后输出。
通过上述技术方案，本发明实施例所产生的有益效果是：本发明实施例通过设计每一移位寄存单元仅包括存储电路、电位控制电路和反相电路，其中电位控制电路和反相电路之间具有第二节点，存储电路和电位控制电路之间具有第二节点，存储电路用于在第一时序信号的控制下选择性将接 收的电平信号反相后输出至第二节点，电位控制电路用于为第一节点提供低电平信号，反相电路用于在第二时序信号的控制下选择性将电位控制电路提供的低电平信号反相后输出，由于单个移位寄存单元的结构较为简单，使得多个移位寄存单元串联后形成的移位寄存器所占区域较大，因此有利于液晶显示面板的窄边框或无边框设计，并且简答的结构比较容易确保液晶显示面板的制程良率。
【附图说明】
图1是本发明优选实施例的液晶显示装置的结构示意图；
图2是本发明第一实施例的移位寄存单元的电路示意图；
图3是本发明第二实施例的移位寄存单元的电路示意图；
图4是图2所示移位寄存单元一优选实施例的连接示意图；
图5是施加于图4所示移位寄存单元的一实施例的讯号时序图。
【具体实施方式】
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，本发明以下所描述的实施例仅仅是本发明的一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其它实施例，都属于本发明保护的范围。
图1是本发明优选实施例的液晶显示装置的结构示意图，如图1所示，液晶显示装置10包括液晶显示面板11、为液晶显示面板11提供数据信号的数据驱动电路12以及为液晶显示面板11提供扫描信号的扫描驱动电路13，液晶显示装置10采用GOA(Gate Driver onArray)技术制得数据驱动电路12和扫描驱动电路13分别对应通过多根数据线和多根扫描线与液晶显示面板11连接。
扫描驱动电路13包括移位寄存器，并通过移位寄存器控制数据信号和扫描信号的输出时序。其中，扫描驱动电路13在移位寄存器的控制下依序输出高电平信号至多根扫描线，以逐列控制呈矩阵排布的薄膜晶体管的导通与关闭，从而实现显示画面。
移位寄存器具有多个结构相同且串联的移位寄存单元20，请参阅图2所示，每一移位寄存单元20包括接收并暂时存储前级讯号的存储电路31、电位控制电路32以及为液晶显示面板11的扫描线充电和放电的反相电路33。存储电路31和电位控制电路32之间具有第二节点P2，电位控制电路32和反相电路33之间具有第一节点P1，存储电路31用于在第一时序信号CK1的控制下选择性将接收的电平信号反相后输出至第二节点P2，电位控制电路32用于为第一节点P1提供低电平信号VGL，反相电路33用于在第二时序信号CK2的控制下选择性将电位控制电路32提供的低电平信号VGL反相后输出。在本实施例中：
存储电路31包括输入端V1N1、第一开关管T1、第二开关管T2、第一反相器311和第二反相器312。第一开关管T1和第一反相器311之间具有第三节点P3，第一开关管T1的控制端G1连接外部电路以接收第一时序信号CK1，第一开关管T1的第一端S1连接输入端V1N1以接收上一级移位寄存单元20的输出信号，第一开关管T1的第二端D1连接第三节点P3，第二开关管T2的控制端G2连接外部电路以接收第一时序信号CK1，第二开关管T2的第一端S2连接第二反相器312，第二开关管T2的第二端D2连接第三节点P3。其中，第一开关管T1的控制端G1和第二开关管T2的控制端G2连接同一或不同的外部电路。
其中，第一开关管T1为N型MOS管，第一开关管T1的控制端G1、第一端S1和第二端D1分别为N型MOS管的栅极、源极和漏极，第二开关管T2为P型MOS管，第二开关管T2的控制端G2、第一端S2和第二端D2分别为P型MOS管的栅极、源极和漏极。
本实施例优选第一反相器311由第三开关管T3和第四开关管T4构成，第二反相器312由第五开关管T5和第六开关管T6构成。其中：
第三开关管T3的控制端G3连接第三节点P3，第三开关管T3的第一端S3连接外部电路以接收高电平信号VGH，第三开关管T3的第二端D3连接第二节点P2。第四开关管T4的控制端G4连接第三节点P3，第四开关管T4的第一端S4连接外部电路以接收低电平信号VGL，第四开关管T4的第二端D4连接第二节点P2。第五开关管T5的控制端G5连接第二节点P2，第五开关管T5的第一端S5连接外部电路以接收高电平信号VGH，第五开关管T5 的第二端D5连接第二开关管T2的第二端D2。第六开关管T6的控制端G6连接第二节点P2，第六开关管T6的第一端S6连接外部电路以接收低电平信号VGL，第六开关管T6的第二端D6连接第二开关管T2的第二端D2。
本实施例优选地，第三开关管T3为P型MOS管，第三开关管T3的控制端G3、第一端S3和第二端D3分别为P型MOS管的栅极、源极和漏极，第四开关管T4为N型MOS管，第四开关管T4的控制端G4、第一端S4和第二端D4分别为N型MOS管的栅极、源极和漏极，第五开关管T5为P型MOS管，第五开关管T5的控制端G5、第一端S5和第二端D5分别为P型MOS管的栅极、源极和漏极，第六开关管T6为N型MOS管，第六开关管T6的控制端G6、第一端S6和第二端D6分别为N型MOS管的栅极、源极和漏极。
并且，第三开关管T3的第一端S3、第四开关管T4的第一端S4、第五开关管T5的第一端S5和第六开关管T6的第一端S6可以对应连接不同的外部电路，也可以组合连接不同的外部电路。
电位控制电路32包括第七开关管T7、第八开关管T8和第九开关管T9。第七开关管T7的控制端G7连接第二节点P2，第七开关管T7的第一端S7连接第二节点P2，第七开关管T7的第二端D7连接第一节点P1，第八开关管T8的控制端G8连接外部电路以接收第二时序信号CK2，第八开关管T8的第一端S8连接第二节点P2，第八开关管T8的第二端D8连接第一节点P1，第九开关管T9的控制端G9连接外部电路以接收第二时序信号CK2，第九开关管T9的第一端S9连接第二节点P2，第九开关管T9的第二端D9连接外部电路以接收高电平信号VGH。
本实施例优选地，第七开关管T7为N型MOS管，第七开关管T7的控制端G7、第一端S7和第二端D7分别为N型MOS管的栅极、源极和漏极，第八开关管T8为N型MOS管，第八开关管T8的控制端G8、第一端S8和第二端D8分别为N型MOS管的栅极、源极和漏极，第九开关管T9为P型MOS管，第九开关管T9的控制端G9、第一端S9和第二端D9分别为P型MOS管的栅极、源极和漏极。
反相电路33包括第十开关管T10、第十一开关管T11和输出端VOUT，第十开关管T10的控制端G10连接第一节点P1，第十开关管T10的第一端S10 连接输入端V1N1以接收上一级移位寄存单元的输出信号，第十开关管T10的第二端D10连接外部电路以接收高电平信号，第十一开关管T11的控制端G11连接第一节点P1，第十一开关管T11的第一端S11连接外部电路以接收低电平信号，第十一开关管T11的第二端D11连接输出端VOUT。
本实施例优选地，第十开关管T10为P型MOS管，第十开关管T10的控制端G10、第一端S10和第二端D10分别为P型MOS管的栅极、源极和漏极，第十一开关管T11为N型MOS管，第十一开关管T11的控制端G11、第一端S11和第二端D11分别为N型MOS管的栅极、源极和漏极。
在本实施例中，第十开关管T10和第十一开关管T11配合构成反相器，用于给液晶显示面板11的扫描线充电和放电，存储电路31用于暂时接收并存储自输入端V1N1接入的电量。第一时序信号CK1为高电位时第一开关管T1导通而第二开关管T2关闭，自输入端V1N1接入的高电位可以传至第三节点P3。第三节点P3为高电位后，由第三开关管T3和第四开关管T4构成的第一反相器311可将第二节点P2拉至低电位。当第一时序信号CK1由高电位变为低电位后，第二开关管T2导通而第一开关管T1关闭，由第三开关管T3、第四开关管T4、第五开关管T5、第六开关管T6、第二开关管T2组成的闭合回路可稳定维持第三节点P3的高电位和第二节点P2的低电位。
对于电位控制电路32，第二时序信号CK2为高电位时第八开关管T8导通而第九开关管T9关闭，第一节点P1可被第二节点P2拉低至低电位，第一节点P1经第十开关管T10和第十一开关管T11构成的反相器的反相作用后输出高电位至与移位寄存单元20连接的扫描线。第二时序信号CK2变为低电位后，第八开关管T8关闭而第九开关管T9导通，第一节点P1被高电平信号VGH拉高电位，输出低电位至与移位寄存单元20连接的扫描线。在非充电期间，第二节点P2处于高电位，第七开关管T7导通，第一节点P1连接第二节点P2而稳定处于高电位，可稳定输出低电位至与移位寄存单元20连接的扫描线。在充电期间，第二节点P2处于低电位，第七开关管T7断开，不影响第一节点P1的电位以及与移位寄存单元20连接的扫描线的充电。
需要说明的是，在本发明的其它实施例中，第七开关管T7还可以为图3所示的P型MOS管，此时第七开关管T7的控制端G7、第一端S7和第二 端D7分别为N型MOS管的栅极、源极和漏极。与图2所示实施例的不同之处在于，在非充电期间，第三节点P3处于低电位而第二节点P2处于高电位，第七开关管T7导通，可确保在非充电期间第一节点P1连接第二节点P2而处于高电位，从而可稳定输出低电位至与移位寄存单元20连接的扫描线。在充电期间，第三节点P3处于高电位，第七开关管T7关闭，不影响充电。
图4是图2所示移位寄存单元20一优选实施例的连接示意图。如图3所示，与第1，3，5...，n-1条等奇数项的扫描线连接的移位寄存单元20分布于液晶显示面板11的左侧，与第2，4，6...，n条等偶数项的扫描线连接的移位寄存单元20分布于液晶显示面板11的右侧。每一移位寄存单元20控制一条水平扫描线的电位，例如与第n条扫描线Gn连接的移位寄存单元20控制扫描线Gn的电位。液晶显示面板11两侧的移位寄存单元20与位于液晶显示面板11下部的驱动IC连接，以获得驱动讯号，相邻两个移位寄存单元20之间也通过讯号线连接，从而保证各个移位寄存单元20能逐列控制扫描线的充电和放电。
图5是施加于图4所示移位寄存单元的一实施例的讯号时序图。如图5所示，接通直流高电压源获得高电平信号VGH，接通直流低电压源获得低电平信号VGL，CK1_L和CK2_L为驱动液晶显示面板11左侧移位寄存单元20的时钟信号，CK1_R和CK2_R为液晶显示面板11右侧移位寄存单元20的时钟信号。
结合图2、图4和图5所示，t1～t3为第n-2条扫描线Gn-2在充电前的准备时间，t3～t4为扫描线Gn-2的充电时间，t3～t5为第n条扫描线Gn在充电前的准备时间，t5～t6为扫描线Gn的充电时间。t1时刻，CK2_L和扫描线Gn-4的电位开始提升，与扫描线Gn-2连接的移位寄存单元20的第三节点P3被充至高电位，第二节点P2被拉至低电位。t2时刻，CK2_L和扫描线Gn-4的电位下降，但移位寄存单元20中存储电路31存储的电量可使得扫描线Gn-2连接的移位寄存单元20的第三节点P3和第二节点P2的电位可暂时保存直至下一次CK2_L的电位抬升。t3时刻，CK1_L的电位抬升，与扫描线Gn-2连接的移位寄存单元20的第八开关管T8导通且第九开关管T9关闭，此时该移位寄存单元20的第一节点P1被第二节点P2至低电位，经第十开 关管T10和第十一开关管T11的反相后从输出端VOUT输出高电位至扫描线Gn-2。t4时刻，CK1_L的电位降低，与扫描线Gn-2连接的移位寄存单元20的第八开关管T8关闭且第九开关管T9导通，此时，该移位寄存单元20的第一节点P1被拉至高电位，扫描线Gn-4被拉至低电位。t5时刻，CK2_L的电位开始提升，但此时扫描线Gn-4已为低电位，与扫描线Gn-2连接的移位寄存单元20的第三节点P3被拉至低电位，其第二节点P2被拉至高电位。
同理，如图5所示，t3时刻，CK1_L和扫描线Gn-4的电位开始提升，与扫描线Gn连接的移位寄存单元20的第三节点P3被拉至高电位，其第二节点P2被拉至低电位。t5时刻，CK2_L的电位抬升，与扫描线Gn连接的移位寄存单元20的第八开关管T8导通且第九开关管T9关闭，该移位寄存单元20的第一节点P1被第二节点P2拉至低电位，经第十开关管T10和第十一开关管T11的反相后从输出端VOUT输出高电位至扫描线Gn-2。t6时刻，CK2_L的电位降低，与扫描线Gn连接的移位寄存单元20的第八开关管T8关闭且第九开关管T9导通，该移位寄存单元20的第一节点P1被拉至高电位，扫描线Gn被拉至低电位。
依据上述原理，与扫描线G1，G2，...Gn-1，Gn对应连接的各个移位寄存单元20可在时钟信号的适当驱动下逐列为扫描线G1，G2，...Gn-1，Gn充电和放电，使得液晶显示面板11正常显示画面。
综上所述，本发明实施例通过设计每一移位寄存单元仅包括接收并暂时存储前级讯号的存储电路、电位控制电路以及为液晶显示面板的扫描线充电和放电的反相电路，其中电位控制电路和反相电路之间具有第一节点，存储电路和电位控制电路之间具有第二节点，存储电路用于在第一时序信号的控制下选择性将接收的电平信号反相后输出至第二节点，电位控制电路用于为第一节点提供低电平信号，反相电路用于在第二时序信号的控制下选择性将电位控制电路提供的低电平信号反相后输出，由于单个移位寄存单元的结构较为简单，使得多个移位寄存单元串联后形成的移位寄存器所占区域较大，因此有利于液晶显示面板的窄边框或无边框设计，并且简答的结构比较容易确保液晶显示面板的制程良率。
再次说明，以上所述仅为本发明的实施例，并非因此限制本发明的专利范围，凡是利用本发明说明书及附图内容所作的等效结构或等效流程变 换，例如各实施例之间技术特征的相互结合，或直接或间接运用在其他相关的技术领域，均同理包括在本发明的专利保护范围内。

Claims (19)

  1. 一种移位寄存器，具有多个移位寄存单元，其中，每一所述移位寄存单元包括接收并暂时存储前级讯号的存储电路、电位控制电路以及为液晶显示面板的扫描线充电和放电的反相电路，所述电位控制电路和所述反相电路之间具有第一节点，所述存储电路和所述电位控制电路之间具有第二节点，所述存储电路用于在第一时序信号的控制下选择性将接收的电平信号反相后输出至所述第二节点，所述电位控制电路用于为所述第一节点提供低电平信号，所述反相电路用于在第二时序信号的控制下选择性将所述电位控制电路提供的低电平信号反相后输出；
    其中，所述存储电路包括输入端、第一开关管、第二开关管、第一反相器和第二反相器，所述第一开关管连接所述输入端，所述第一开关管和所述第一反相器之间具有第三节点，所述第二开关管连接所述第二反相器，所述电位控制电路包括第七开关管、第八开关管和第九开关管，所述第七开关管和所述第九开关管连接所述第二节点，所述第八开关管连接所述第一节点，所述反相电路包括第十开关管、第十一开关管和输出端，所述第十开关管和所述第十一开关管连接所述第一节点，所述第十一开关管的第二端连接所述输出端。
  2. 根据权利要求1所述的移位寄存器，其中，所述第一开关管的控制端连接外部电路以接收所述第一时序信号，所述第一开关管的第一端连接所述输入端以接收上一级移位寄存单元的输出信号，所述第一开关管的第二端连接所述第三节点，所述第二开关管的控制端连接所述外部电路以接收所述第一时序信号，所述第二开关管的第一端连接所述第二反相器，所述第二开关管的第二端连接所述第三节点。
  3. 根据权利要求2所述的移位寄存器，其中，所述第一开关管为N型MOS管，所述第一开关管的控制端、第一端和第二端分别为所述N型MOS管的栅极、源极和漏极，所述第二开关管为P型MOS管，所述第二开关管的控制端、第一端和第二端分别为所述P型MOS管的栅极、源极和漏极。
  4. 根据权利要求2所述的移位寄存器，其中，所述第一反相器包括第三开关管和第四开关管，所述第二反相器包括第五开关管和第六开关管， 所述第三开关管的控制端连接所述第三节点，所述第三开关管的第一端连接外部电路以接收高电平信号，所述第三开关管的第二端连接所述第二节点，所述第四开关管的控制端连接所述第三节点，所述第四开关管的第一端连接外部电路以接收低电平信号，所述第四开关管的第二端连接所述第二节点，所述第五开关管的控制端连接所述第二节点，所述第五开关管的第一端连接外部电路以接收高电平信号，所述第五开关管的第二端连接所述第二开关管的第二端，所述第六开关管的控制端连接所述第二节点，所述第六开关管的第一端连接外部电路以接收低电平信号，所述第六开关管的第二端连接所述第二开关管的第二端。
  5. 根据权利要求4所述的移位寄存器，其中，所述第三开关管为P型MOS管，所述第三开关管的控制端、第一端和第二端分别为所述P型MOS管的栅极、源极和漏极，所述第四开关管为N型MOS管，所述第四开关管的控制端、第一端和第二端分别为所述N型MOS管的栅极、源极和漏极，所述第五开关管为P型MOS管，所述第五开关管的控制端、第一端和第二端分别为所述P型MOS管的栅极、源极和漏极，所述第六开关管为N型MOS管，所述第六开关管的控制端、第一端和第二端分别为所述N型MOS管的栅极、源极和漏极。
  6. 根据权利要求1所述的移位寄存器，其中，所述第七开关管的控制端连接所述第二节点，所述第七开关管的第一端连接所述第二节点，所述第七开关管的第二端连接所述第一节点，所述第八开关管的控制端连接外部电路以接收所述第二时序信号，所述第八开关管的第一端连接所述第二节点，所述第八开关管的第二端连接所述第一节点，所述第九开关管的控制端连接所述外部电路以接收所述第二时序信号，所述第九开关管的第一端连接所述第二节点，所述第九开关管的第二端连接外部电路以接收高电平信号。
  7. 根据权利要求6所述的移位寄存器，其中，所述第七开关管为N型MOS管或P型MOS管，所述第七开关管的控制端、第一端和第二端分别为所述N型MOS管或所述P型MOS管的栅极、源极和漏极，所述第八开关管为N型MOS管，所述第八开关管的控制端、第一端和第二端分别为所述N型MOS管的栅极、源极和漏极，所述第九开关管为P型MOS管，所 述第九开关管的控制端、第一端和第二端分别为所述P型MOS管的栅极、源极和漏极。
  8. 根据权利要求1所述的移位寄存器，其中，所述第十开关管的控制端连接所述第一节点，所述第十开关管的第一端连接所述输入端以接收上一级移位寄存单元的输出信号，所述第十开关管的第二端连接外部电路以接收高电平信号，所述第十一开关管的控制端连接所述第一节点，所述第十一开关管的第一端连接外部电路以接收低电平信号，所述第十一开关管的第二端连接所述输出端。
  9. 根据权利要求8所述的移位寄存器，其中，所述第十开关管为P型MOS管，所述第十开关管的控制端、第一端和第二端分别为所述P型MOS管的栅极、源极和漏极，所述第十一开关管为N型MOS管，所述第十一开关管的控制端、第一端和第二端分别为所述N型MOS管的栅极、源极和漏极。
  10. 一种移位寄存器，具有多个移位寄存单元，其中，每一所述移位寄存单元包括接收并暂时存储前级讯号的存储电路、电位控制电路以及为液晶显示面板的扫描线充电和放电的反相电路，所述电位控制电路和所述反相电路之间具有第一节点，所述存储电路和所述电位控制电路之间具有第二节点，所述存储电路用于在第一时序信号的控制下选择性将接收的电平信号反相后输出至所述第二节点，所述电位控制电路用于为所述第一节点提供低电平信号，所述反相电路用于在第二时序信号的控制下选择性将所述电位控制电路提供的低电平信号反相后输出。
  11. 根据权利要求10所述的移位寄存器，其中，所述存储电路包括输入端、第一开关管、第二开关管、第一反相器和第二反相器，所述第一开关管和所述第一反相器之间具有第三节点，所述第一开关管的控制端连接外部电路以接收所述第一时序信号，所述第一开关管的第一端连接所述输入端以接收上一级移位寄存单元的输出信号，所述第一开关管的第二端连接所述第三节点，所述第二开关管的控制端连接所述外部电路以接收所述第一时序信号，所述第二开关管的第一端连接所述第二反相器，所述第二开关管的第二端连接所述第三节点。
  12. 根据权利要求11所述的移位寄存器，其中，所述第一开关管为N 型MOS管，所述第一开关管的控制端、第一端和第二端分别为所述N型MOS管的栅极、源极和漏极，所述第二开关管为P型MOS管，所述第二开关管的控制端、第一端和第二端分别为所述P型MOS管的栅极、源极和漏极。
  13. 根据权利要求11所述的移位寄存器，其中，所述第一反相器包括第三开关管和第四开关管，所述第二反相器包括第五开关管和第六开关管，所述第三开关管的控制端连接所述第三节点，所述第三开关管的第一端连接外部电路以接收高电平信号，所述第三开关管的第二端连接所述第二节点，所述第四开关管的控制端连接所述第三节点，所述第四开关管的第一端连接外部电路以接收低电平信号，所述第四开关管的第二端连接所述第二节点，所述第五开关管的控制端连接所述第二节点，所述第五开关管的第一端连接外部电路以接收高电平信号，所述第五开关管的第二端连接所述第二开关管的第二端，所述第六开关管的控制端连接所述第二节点，所述第六开关管的第一端连接外部电路以接收低电平信号，所述第六开关管的第二端连接所述第二开关管的第二端。
  14. 根据权利要求13所述的移位寄存器，其中，所述第三开关管为P型MOS管，所述第三开关管的控制端、第一端和第二端分别为所述P型MOS管的栅极、源极和漏极，所述第四开关管为N型MOS管，所述第四开关管的控制端、第一端和第二端分别为所述N型MOS管的栅极、源极和漏极，所述第五开关管为P型MOS管，所述第五开关管的控制端、第一端和第二端分别为所述P型MOS管的栅极、源极和漏极，所述第六开关管为N型MOS管，所述第六开关管的控制端、第一端和第二端分别为所述N型MOS管的栅极、源极和漏极。
  15. 根据权利要求10所述的移位寄存器，其中，所述电位控制电路包括第七开关管、第八开关管和第九开关管，所述第七开关管的控制端连接所述第二节点，所述第七开关管的第一端连接所述第二节点，所述第七开关管的第二端连接所述第一节点，所述第八开关管的控制端连接外部电路以接收所述第二时序信号，所述第八开关管的第一端连接所述第二节点，所述第八开关管的第二端连接所述第一节点，所述第九开关管的控制端连接所述外部电路以接收所述第二时序信号，所述第九开关管的第一端连接 所述第二节点，所述第九开关管的第二端连接外部电路以接收高电平信号。
  16. 根据权利要求15所述的移位寄存器，其中，所述第七开关管为N型MOS管或P型MOS管，所述第七开关管的控制端、第一端和第二端分别为所述N型MOS管或所述P型MOS管的栅极、源极和漏极，所述第八开关管为N型MOS管，所述第八开关管的控制端、第一端和第二端分别为所述N型MOS管的栅极、源极和漏极，所述第九开关管为P型MOS管，所述第九开关管的控制端、第一端和第二端分别为所述P型MOS管的栅极、源极和漏极。
  17. 根据权利要求10所述的移位寄存器，其中，所述反相电路包括第十开关管、第十一开关管和输出端，所述第十开关管的控制端连接所述第一节点，所述第十开关管的第一端连接所述输入端以接收上一级移位寄存单元的输出信号，所述第十开关管的第二端连接外部电路以接收高电平信号，所述第十一开关管的控制端连接所述第一节点，所述第十一开关管的第一端连接外部电路以接收低电平信号，所述第十一开关管的第二端连接所述输出端。
  18. 根据权利要求17所述的移位寄存器，其中，所述第十开关管为P型MOS管，所述第十开关管的控制端、第一端和第二端分别为所述P型MOS管的栅极、源极和漏极，所述第十一开关管为N型MOS管，所述第十一开关管的控制端、第一端和第二端分别为所述N型MOS管的栅极、源极和漏极。
  19. 一种液晶显示装置，包括液晶显示面板、为所述液晶显示面板提供数据信号的数据驱动电路以及为所述液晶显示面板提供扫描信号的扫描驱动电路，其中，所述数据驱动电路和所述扫描驱动电路分别包括移位寄存器，以控制所述数据信号和所述扫描信号的输出时序，所述移位寄存器具有多个移位寄存单元，每一所述移位寄存单元包括接收并暂时存储前级讯号的存储电路、电位控制电路以及为液晶显示面板的扫描线充电和放电的反相电路，所述电位控制电路和所述反相电路之间具有第一节点，所述存储电路和所述电位控制电路之间具有第二节点，所述存储电路用于在第一时序信号的控制下选择性将接收的电平信号反相后输出至所述第二节点，所述电位控制电路用于为所述第一节点提供低电平信号，所述反相电路用 于在第二时序信号的控制下选择性将所述电位控制电路提供的低电平信号反相后输出。
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Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104361860B (zh) * 2014-11-19 2017-02-22 京东方科技集团股份有限公司 一种移位寄存器、栅极驱动电路以及显示装置
CN104978922B (zh) * 2015-07-29 2017-07-18 京东方科技集团股份有限公司 移位寄存器、显示装置及移位寄存器驱动方法
KR102575564B1 (ko) * 2018-03-26 2023-09-08 삼성디스플레이 주식회사 주사 구동부
CN108320708B (zh) * 2018-05-10 2021-01-26 京东方科技集团股份有限公司 一种移位寄存器及其驱动方法、栅极驱动电路、显示装置
CN108962168A (zh) 2018-07-24 2018-12-07 武汉华星光电技术有限公司 单型goa电路
CN118747990B (zh) * 2024-08-21 2024-12-20 武汉华星光电半导体显示技术有限公司 显示装置及电子终端
CN119479545B (zh) * 2024-11-26 2025-12-09 厦门天马微电子有限公司 显示面板和显示装置

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101017656B (zh) * 2006-02-07 2010-12-15 株式会社日立显示器 显示装置
CN102270434A (zh) * 2010-06-03 2011-12-07 海帝士科技公司 显示驱动电路
CN103208251A (zh) * 2013-04-15 2013-07-17 京东方科技集团股份有限公司 一种移位寄存器单元、栅极驱动电路及显示装置
CN103280176A (zh) * 2012-10-26 2013-09-04 厦门天马微电子有限公司 一种垂直移位寄存器及其控制方法、ic芯片和tft面板
CN103985362A (zh) * 2013-10-31 2014-08-13 上海中航光电子有限公司 栅极驱动电路及液晶显示器件
CN104103244A (zh) * 2013-04-03 2014-10-15 瀚宇彩晶股份有限公司 液晶显示器及其双向移位暂存装置

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5598126B2 (ja) * 2010-07-09 2014-10-01 ソニー株式会社 固体撮像素子およびカメラシステム
JP5530344B2 (ja) * 2010-12-08 2014-06-25 ルネサスエレクトロニクス株式会社 レベルシフト回路及びそれを備えた駆動回路
TWI451383B (zh) * 2011-12-05 2014-09-01 Au Optronics Corp 平面顯示器、位移暫存器及其控制方法
CN102819998B (zh) * 2012-07-30 2015-01-14 京东方科技集团股份有限公司 移位寄存器和显示装置
CN103151010B (zh) * 2013-02-27 2014-12-10 京东方科技集团股份有限公司 一种移位寄存器和显示装置
CN103236272B (zh) * 2013-03-29 2016-03-16 京东方科技集团股份有限公司 移位寄存器单元及其驱动方法、栅极驱动装置与显示装置
KR20150087647A (ko) * 2014-01-22 2015-07-30 삼성디스플레이 주식회사 게이트 구동회로 및 이를 포함하는 표시장치
CN103761954B (zh) * 2014-02-17 2016-10-19 友达光电(厦门)有限公司 显示面板与栅极驱动器
CN104021769B (zh) * 2014-05-30 2016-06-15 京东方科技集团股份有限公司 一种移位寄存器、栅线集成驱动电路及显示屏

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101017656B (zh) * 2006-02-07 2010-12-15 株式会社日立显示器 显示装置
CN102270434A (zh) * 2010-06-03 2011-12-07 海帝士科技公司 显示驱动电路
CN103280176A (zh) * 2012-10-26 2013-09-04 厦门天马微电子有限公司 一种垂直移位寄存器及其控制方法、ic芯片和tft面板
CN104103244A (zh) * 2013-04-03 2014-10-15 瀚宇彩晶股份有限公司 液晶显示器及其双向移位暂存装置
CN103208251A (zh) * 2013-04-15 2013-07-17 京东方科技集团股份有限公司 一种移位寄存器单元、栅极驱动电路及显示装置
CN103985362A (zh) * 2013-10-31 2014-08-13 上海中航光电子有限公司 栅极驱动电路及液晶显示器件

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