WO2016078188A1 - 液晶显示面板及其驱动方法 - Google Patents

液晶显示面板及其驱动方法 Download PDF

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Publication number
WO2016078188A1
WO2016078188A1 PCT/CN2014/095574 CN2014095574W WO2016078188A1 WO 2016078188 A1 WO2016078188 A1 WO 2016078188A1 CN 2014095574 W CN2014095574 W CN 2014095574W WO 2016078188 A1 WO2016078188 A1 WO 2016078188A1
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Prior art keywords
voltage
switch tube
circuit
resistor
liquid crystal
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PCT/CN2014/095574
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English (en)
French (fr)
Inventor
曾德康
郭东胜
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深圳市华星光电技术有限公司
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Priority to US14/417,391 priority Critical patent/US20160365057A1/en
Publication of WO2016078188A1 publication Critical patent/WO2016078188A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3685—Details of drivers for data electrodes
    • G09G3/3688—Details of drivers for data electrodes suitable for active matrices only
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3696—Generation of voltages supplied to electrode drivers
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0439—Pixel structures
    • G09G2300/0452—Details of colour pixel setup, e.g. pixel composed of a red, a blue and two green components
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
    • G09G2310/0251—Precharge or discharge of pixel before applying new pixel voltage
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/027—Details of drivers for data electrodes, the drivers handling digital grey scale data, e.g. use of D/A converters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0233—Improving the luminance or brightness uniformity across the screen
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0242—Compensation of deficiencies in the appearance of colours
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0247—Flicker reduction other than flicker reduction circuits used for single beam cathode-ray tubes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/025—Reduction of instantaneous peaks of current

Definitions

  • the present invention relates to the field of liquid crystal display technologies, and in particular, to a liquid crystal display panel and a driving method thereof.
  • a liquid crystal display panel includes scan lines and data lines, the data lines are driven by a source driver, and the scan lines are driven by a gate driver.
  • the signal line from the source driver to the liquid crystal display panel is longer than the signal line from the source driver to the center of the panel, so that the WOA (Wire on Array) of the data line in the panel is made.
  • WOA Wire on Array
  • FIG. 1 is a schematic diagram of a conventional liquid crystal display panel using a three-gate (Tri-Gate) driving structure.
  • a liquid crystal display panel has a plurality of pixel units arranged in an array, wherein each pixel unit P includes sub-pixels R, G, and B (refer to FIG. 2) arranged in order along a column direction, and sub-pixels R and G.
  • B are electrically connected to corresponding scan lines (for example, G1 to G6 in FIG. 2) and data lines (for example, D1 to D5 in FIG. 2) through corresponding switching elements.
  • the driving architecture there is only one data line and three scanning lines for each pixel unit, that is, the data signal of each pixel unit is transmitted through one data line, and the switching elements of each sub-pixel are sequentially transmitted through three scanning lines.
  • the signal achieves a complete display of each pixel unit, thereby saving the number of source drivers and reducing the cost of the liquid crystal display panel.
  • One of the technical problems to be solved by the present invention is to provide a liquid crystal display panel capable of improving or eliminating color shift phenomenon.
  • a driving method of a liquid crystal display panel is also provided.
  • an embodiment of the present application first provides a liquid crystal display panel, including: a source driver for providing a data signal; and a gate driver for providing a gate signal according to a chamfer voltage; a pixel array electrically connected between the source driver and the gate driver, and configured to display an image according to the data signal and the gate signal; a chamfering circuit electrically connected to the gate a driver for providing the chamfering voltage, wherein the chamfering circuit is configured to be capable of stepping down the received DC voltage to a voltage value of the chamfering voltage within a set time to avoid flickering of the screen and maintaining The uniformity of each region of the liquid crystal display panel is uniform.
  • the chamfering circuit includes: a DC voltage input terminal; a chamfered voltage output terminal; and a first switching circuit connected to the DC voltage input terminal and Selectively conducting between the chamfered voltage output terminals under the control of the first timing signal, and selectively transmitting the DC voltage received by the DC voltage input terminal to the chamfered voltage output end; a second switching circuit that is selectively turned on under control of a second timing signal, the second timing signal and the first timing signal being mutually opposite pulse voltage signals; a discharge circuit coupled to the first Between the two switching circuits and the chamfered voltage output terminal, when the second switching circuit is turned on, the DC voltage transmitted to the output of the chamfering voltage is stepped down by a set discharge slope, thereby forming a chamfering voltage, wherein the discharge circuit includes a discharge resistor, and a discharge rate of the discharge resistor is capable of receiving the DC voltage input terminal within a time period of less than or equal to a quarter of
  • the resistance of the discharge resistor is 500 ⁇ or less.
  • the discharge circuit further includes a diode, a cathode of the diode is connected to the discharge resistor, and an anode of the diode is connected to the first Two switching circuits.
  • the first switching circuit includes a first switching transistor, a second switching transistor, a first resistor, and a second resistor, wherein a first end of the second switch tube is connected to the DC voltage input end, a second end of the second switch tube is connected to the chamfered voltage output end, and the first resistor and the second resistor are connected in series Between the DC voltage input end and the first end of the first switch tube, a control end of the second switch tube is connected between the first resistor and the second resistor, the first The control end of the switch tube is configured to receive the first timing signal, the second end of the first switch tube is grounded, the first switch tube is an N-type thin film transistor or an N-type field effect transistor, and the second switch The tube is a P-type thin film transistor or a P-type field effect transistor.
  • the second switching circuit includes a third switching transistor, the first end of the third switching transistor and the discharge circuit One end is connected, the second end of the third switch tube is grounded, and the control end of the third switch tube receives the second timing signal, and the third switch tube is an N-type thin film transistor or an N-type field effect transistor.
  • the voltage value of the chamfering voltage generated by the discharge circuit enables the degree of flicker of the liquid crystal display panel to be less than or equal to a certain threshold, and The uniformity of each region of the liquid crystal display panel is uniform.
  • a driving method of a liquid crystal display panel comprising: inputting a DC voltage to a DC voltage input end of a chamfering circuit in each charging cycle; toward the chamfering circuit
  • the first switching circuit inputs a first timing signal to turn on the first switching circuit, thereby transmitting a DC voltage received by the DC voltage input terminal to the output of the chamfering voltage; to the chamfering circuit
  • the second switching circuit inputs a second timing signal to turn on the second switching circuit, and the second timing signal and the first timing signal are mutually opposite pulse voltage signals; using the discharging circuit in the When the second switching circuit is turned on, the DC voltage transmitted to the output of the chamfering voltage is stepped down by a set discharge slope to form a chamfering voltage, wherein the discharging resistor in the discharging circuit is set to : discharging rate of the discharge resistor, capable of stepping down the DC voltage received by the DC voltage input terminal to a chamfered electric power in
  • the embodiment of the present application reduces the resistance of the discharge resistor in the chamfering circuit by adjusting the potential of the gate voltage VGH(off) without changing the gate on state, and adjusts the duty of the input pulse of the chamfering circuit.
  • the pixels on both sides of the display panel are During the charging time, it can also be charged to the target voltage value or close to the target voltage value, avoiding the panel flickering and improving the uniformity of each area of the panel, so that the display area of the panel middle area and the two sides of the panel tend to be consistent, and the improvement is improved.
  • the color shift problem of the liquid crystal display panel of the three-gate driving structure is provided.
  • FIG. 1 is a schematic diagram of a conventional liquid crystal display panel using a three-gate driving structure
  • FIG. 2 is a schematic diagram of a pixel unit
  • 3(a) and 3(b) are voltage waveform diagrams of the data line Dn/2 and the data line Dn, respectively, when the liquid crystal display panel shown in FIG. 1 displays a low grayscale mixed color picture;
  • FIG. 4 is a schematic diagram of a liquid crystal display panel according to an embodiment of the present application.
  • FIG. 5 is a schematic diagram of a chamfering circuit according to an embodiment of the present application.
  • FIG. 6 is a diagram showing an example of waveforms of an input signal and an output signal of a chamfering circuit according to an embodiment of the present application
  • FIG. 7 is a voltage waveform diagram of a data line Dn in a liquid crystal display panel according to an embodiment of the present application.
  • Fig. 8 is a graph showing the transfer characteristics of the switching element.
  • 3(a) and 3(b) are respectively a data line Dn/2 (data line located at the center of the panel) and a data line Dn (located on the panel) of the liquid crystal display panel shown in FIG. 1 when displaying a low grayscale mixed color picture Voltage waveform of the side data line).
  • a yellow gray picture of 128 gray scale is used as an example of the low gray color mixed color picture, and the gray scale values of the hue regions of red R, green G, and blue B are 128, 128, and 0, respectively.
  • VGH represents the gate on-state voltage
  • VGH(off) represents the gate off-state final off-point voltage (referred to as the chamfer voltage), which is a special voltage of the gate-on voltage
  • Gray scale 128 represents the voltage that displays the grayscale value 128. Since the resistance of the WOA trace of the data line Dn/2 located at the center of the panel is the smallest, the state of charge of the sub-pixel corresponding to the stripe data line can be regarded as an ideal state, that is, the charging voltages of the R sub-pixel and the G sub-pixel are not Any changes have occurred. Moreover, the charging time of the R sub-pixel and the G sub-pixel is the same, and both are T2. Thus, the area of the display panel corresponding to these sub-pixels displays the desired yellow picture without color shifting.
  • 90%* gray scale 128 represents an effective voltage showing a grayscale value of 128, which is 90% of the voltage value indicating the grayscale value 128. Of course, 90% or more of the voltage value is selected as effective.
  • the voltage can be. Since the resistance of the WOA trace of the data line Dn located on one side of the panel is large, the RC delay generated is also large, thus causing a change in the charging voltage of the R sub-pixel and the G sub-pixel, especially for the R sub-pixel. Due to the RC delay effect, the charging time of the R sub-pixel is also greatly reduced (as shown in FIG. 3(b), the effective charging time T1), which causes the R sub-pixel not to reach the required charging power, and accordingly, the corresponding display The screen displayed in the panel area will be greenish and the color shift will occur.
  • the effective charging time T1 of a certain sub-pixel does not change, in order to be able to charge the voltage value of the sub-pixel to the target voltage or close to the target voltage within a fixed effective charging time.
  • the inventors of the present application have studied the following embodiments to improve the charging ability of sub-pixels.
  • the embodiment of the present application reduces the time value of the input pulse GVON of the chamfering circuit by reducing the resistance of the discharge resistor in the chamfering circuit without changing the potential of the gate open state and finally closing the point voltage VGH(off). And the duty ratio, thereby increasing the discharge rate of the chamfering circuit and improving the charging capability of the sub-pixels, so that the pixels on both sides of the display panel can be charged to the target voltage value or close to the target voltage value during the effective charging time, thereby avoiding The panel flickers and improves the uniformity of each area of the panel, so that the display area between the middle area of the panel and the two sides of the panel tends to be consistent, which improves the color shift of the liquid crystal display panel of the three-gate driving structure.
  • the liquid crystal display device 10 includes a pixel array unit 100 having a plurality of pixels PX, a source driver 104, a gate driver 106, and a chamfer circuit 120.
  • the source driver 104 is used to provide a data signal to the pixel array unit 100.
  • the gate driver 106 is used to provide a gate signal to the pixel array unit 100 according to the chamfer voltage VGH(off) provided by the chamfer circuit 120, and the pixel array unit 100 displays an image based on the data signal and the gate signal.
  • the chamfering circuit 120 is electrically connected to the gate drive
  • the chamfering circuit 120 is configured to be capable of stepping down the received DC voltage to a voltage value of the chamfering voltage within a set time to avoid flickering of the screen and maintaining uniformity of various regions of the liquid crystal display panel.
  • Uniformity represents the brightness uniformity of the panel and the difference value between the points, and the specific expression is: the brightness of the darkest point/the brightness of the brightest point.
  • FIG. 5 is a schematic diagram of a chamfering circuit 120 of an embodiment of the present application.
  • the chamfering circuit 120 includes a DC voltage input terminal VGHP, a chamfered voltage output terminal VGH, a first switching circuit 1201, a second switching circuit 1203, and a discharging circuit 1205.
  • the first switch circuit 1201 is connected between the DC voltage input terminal VGHP and the chamfered voltage output terminal VGH, selectively turned on under the control of the first timing signal GVOFF, and receives the DC voltage received by the DC voltage input terminal VGHP. The voltage is selectively transmitted to the chamfered voltage output terminal VGH.
  • the second switch circuit 1203 is connected to the discharge circuit 1205 to be selectively turned on under the control of the second timing signal GVON.
  • the discharge circuit 1205 is connected between the second switch circuit 1203 and the chamfered voltage output terminal VGH to set a DC voltage transmitted to the chamfered voltage output terminal VGH through the discharge circuit 1205 when the second switch circuit 1203 is turned on.
  • the predetermined discharge slope is stepped down to form a chamfer voltage.
  • the first switch circuit 1201 includes a switch tube A, a switch tube Q1, a resistor R1, and a resistor R2.
  • the first end 1-S of the switch tube Q1 is connected to the DC voltage input terminal VGHP
  • the second end 1-D of the switch tube Q1 is connected to the chamfered voltage output terminal VGH
  • the resistor R1 and the resistor R2 are connected in series to the DC voltage input end.
  • the control terminal 1-G of the switch Q1 is connected between the resistor R1 and the resistor R2.
  • the control terminal A-G of the switch A is used to receive the first timing signal GVOFF, and the second end A-S of the switch A is grounded.
  • the switch transistor Q1 is a P-type thin film transistor or a P-type field effect transistor, and the first end 1-S, the second end 1-D, and the control end 1-G are respectively sources of the P-type switch tube. Pole, drain and gate.
  • the switch A is an N-type thin film transistor or an N-type field effect transistor, and the first end A-D, the second end A-S and the control end A-G are the drain, the source and the gate of the N-type switch tube, respectively.
  • the second switch circuit 1203 includes a switch tube B.
  • the first end B-D of the switch B is connected to one end of the discharge circuit 1205, the second end B-S of the switch B is grounded, and the control end B-G of the switch B receives the second timing signal GVON.
  • the switch tube B is an N-type thin film transistor or an N-type field effect transistor, and the first end BD, the second end BS, and the control end BG of the switch tube B are respectively the drain and the source of the N-type switch tube. And the gate.
  • first timing signal GVOFF and the second timing signal GVON are mutually inverted signals and are voltage signals, and the two signals can be generated by the timing controller and the inverter. Specifically, the timing controller generates a first timing signal GVOFF, and the first timing signal GVOFF generates a second timing signal GVON via the inverter. apart from In addition to the above methods, other methods may be employed to generate the first timing signal GVOFF and the second timing signal GVON.
  • the discharge circuit 1205 includes a discharge resistor R3 connected in series.
  • the discharge rate of the discharge resistor is capable of stepping down the DC voltage VGHP received by the DC voltage input terminal VGHP to the voltage value of the chamfering voltage VGH for a period of one quarter or less of the charging period.
  • the above discharge time is only a preferred example, and in some cases, the inventors of the art can select other discharge times.
  • the discharge circuit 1205 may further include a Zener diode ZD1 for voltage stabilization.
  • the anode of the Zener diode ZD1 is connected to the first end B-D of the switch B, and the cathode of the Zener diode ZD1 is connected to the discharge resistor R3.
  • the capacitance C shown in Fig. 5 is the parasitic capacitance of each scanning line in the panel.
  • the circuit configuration of the chamfering circuit 120 is only an example.
  • the switching circuit can also switch the operations of the first switching circuit and the second switching circuit to implement the function of the chamfering circuit, so that any other The chamfering circuit that discharges the received DC voltage to the voltage value of the chamfering voltage within the set time to eliminate the color shift phenomenon is within the protection scope of the present application.
  • FIG. 6 is a waveform example of an input signal (including a DC voltage VGHP, a first timing signal GVOFF, and a second timing signal GVON) and an output signal of a chamfering circuit according to an embodiment of the present application, and the chamfering circuit of the present application is described below with reference to FIG. The working principle is described in detail.
  • the timing controller increases the duty ratio (negative direction) of the second timing signal GVON from the existing 23% to 80%, and the first timing signal GVOFF
  • the duty cycle (negative direction) is reduced from 77% to 20%.
  • a DC voltage is input to the DC voltage input terminal VGHP, and a first timing signal GVOFF is input to the control terminal AG of the switching transistor A of the first switching circuit 1201 to the second switching circuit 1203.
  • the control terminal BG of the switch B inputs the second timing signal GVON.
  • the switch tube A and the switch tube Q1 are turned on, at this time, the second timing signal GVON is in a low level state, the switch tube B is turned off, and the chamfer voltage output terminal VGH is outputted at this time.
  • the voltage is the same as the voltage at the DC voltage input VGHP.
  • the switch tube B is turned on, the first timing signal GVOFF is in a low level state, the switch tube A and the switch tube Q1 are turned off, and at this time, the discharge resistor R3 is stepped down to form a chamfer.
  • the voltage is output to the chamfered voltage output terminal VGH.
  • the electric resistance R3 can also generate a chamfer voltage by controlling the correspondence relationship between the first timing signal GVOFF and the second timing signal GVON.
  • the resistance of the discharge resistor R3 in the present embodiment is preferably 500 ⁇ or less. In one example, the resistance of the discharge resistor R3 is 336 ⁇ . Thus, since the resistance of the discharge resistor R3 is much smaller than that of the discharge resistor of the prior art (generally 1.5 K ⁇ or more), the discharge rate of the chamfering circuit can be greatly increased, thereby being able to be 20%.
  • the buck is completed within the charging cycle time to reach the preset chamfer voltage.
  • the start-up time of the discharge circuit 120 at the beginning of each cycle is delayed from the Ta time to the Tb time, so that the time of the VGH high voltage (which is equal to the DC voltage VGHP of the DC voltage output terminal) can be prolonged.
  • the charging ability of the sub-pixel can be enhanced. This is because, for the switching element connected to the sub-pixel, the gate of the switching element corresponds to the scanning line, the source of the switching element corresponds to the data line, and the drain of the switching element corresponds to the pixel electrode. Under the control of the gate, the data line of the source is charged and discharged to the pixels of the drain through the switching element.
  • the function of the gate is to control the degree of conductivity of the switching element.
  • the switching element When the pixel needs to be charged and discharged, the switching element operates in an open state of a large current, and when the pixel is not charged or discharged, the switching element operates in a small current state. . Moreover, the large current in the on state assumes the function of charge and discharge, and the larger the current, the faster the charge and discharge are.
  • the results shown in Figure 8 are obtained.
  • the chamfering voltage VGH As shown in Fig. 8, as the chamfering voltage VGH is gradually increased, the on-state current of the switching elements connected to the pixels is larger, and therefore, in order to improve the charging capability, a higher VGH voltage will be selected.
  • the sub-pixel can be charged to the target voltage value or close to the target voltage value during the effective charging time T1 of the fixed sub-pixel, and when the low-gradation mixed color screen is displayed, for example, 128 is displayed.
  • the yellow screen of the gray scale does not appear reddish or greenish at both ends of the liquid crystal display panel, which improves the display quality.
  • the selection of the chamfering voltage is preferably configured to: make the flicker of the liquid crystal display panel less than or equal to a certain threshold, and the uniformity of each region of the liquid crystal display panel is uniform, wherein
  • the flicker is obtained by the following expression: (maximum brightness - minimum brightness) / average brightness. Taking 32 tri-gate as an example, the flicker threshold is 5, which makes the panel uniformity greater than 80%.
  • the optimum VGH(off) is equal to 20V, which can avoid the undesired color or miscellaneous color caused by the flickering phenomenon or the low level caused by the VGH(off) being too high when the TFT switch in the panel is turned off. News.

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Abstract

一种液晶显示面板，该液晶显示面板包括：源极驱动器（104）；栅极驱动器（106）；像素阵列（100），其电连接于源极驱动器（104）和栅极驱动器（106）之间，并用于根据数据信号和栅极信号来显示影像；削角电路（120），其电连接于栅极驱动器（106），用于提供削角电压VGH，其中，削角电路（120）被配置为能够在设定时间内将接收到的直流电压降压至削角电压VGH的电压值，以避免画面闪烁，保持液晶显示面板的各个区域的均齐度一致。还提供了一种液晶显示面板的驱动方法。

Description

液晶显示面板及其驱动方法
相关申请的交叉引用
本申请要求享有2014年11月20日提交的名称为“液晶显示面板及其驱动方法”的中国专利申请CN201410667208.9的优先权，其全部内容通过引用并入本文中。
技术领域
本发明涉及液晶显示技术领域，尤其涉及一种液晶显示面板及其驱动方法。
背景技术
为了满足人们对产品的高速度、高效能、且轻薄的要求，各电子零件皆积极地朝体积小型化发展。各种便携式电子装置也已渐成主流。对于便携式电子装置的影像显示面板而言，具有无辐射等优越特性的液晶显示面板，目前已被广为使用。
一般地，液晶显示面板包括扫描线和数据线，数据线通过源极驱动器来驱动，扫描线通过栅极驱动器来驱动。由于现有的大尺寸液晶面板中，从源极驱动器至液晶显示面板两端的信号线要比源极驱动器至面板中央的信号线要长，这样会使得面板中数据线的WOA(Wire on Array)走线在扇出(Fanout)区的阻值存在较大差异，而这样的电阻差异会导致面板的显示效果不佳，进而影响显示质量。
图1为现有一种使用三闸极(Tri-Gate)驱动架构的液晶显示面板示意图。请参照图1，液晶显示面板具有多个阵列排列的像素单元，其中每一像素单元P包括沿着列方向依序排列的子像素R、G、B(参照图2)，子像素R、G、B分别通过对应的开关元件与对应的扫描线(例如图2中G1～G6)以及数据线(例如图2中D1～D5)电性连接。由于该种驱动架构，对应每个像素单元只有一条数据线和三条扫描线，也就是说，每个像素单元的数据信号通过一条数据线传送，通过三条扫描线依次传送开启每个子像素的开关元件的信号，进而实现每个像素单元的完整显示，从而节省了源极驱动器的数量，降低了液晶显示面板的成本。
然而，以图1为例，假设源极驱动器只有一个，这样会使得面板中的数据线的WOA 走线在Fanout区的阻值存在较大差异。如图1所示，由于源极驱动器的输出到面板两端的WOA走线距离L1远大于源极驱动器输出到面板中央的距离L2，因此两侧的数据线的WOA走线的总阻值能够达到5KΩ～7KΩ，而中间数据线的WOA走线的阻值只有300～500Ω。这样，较大的WOA走线的阻值会使数据线在传输数据信号时会产生严重的RC延迟，液晶显示面板两端的像素的充电速度明显滞后面板中间的像素，面板各像素充电不均匀，会导致面板所显示的画面出现色偏现象，影响显示质量。
发明内容
本发明所要解决的技术问题之一是需要提供一种能够改善或消除色偏现象的液晶显示面板。另外，还提供了一种液晶显示面板的驱动方法。
1)为了解决上述技术问题，本申请的实施例首先提供了一种液晶显示面板，包括：源极驱动器，用于提供数据信号；栅极驱动器，用于根据削角电压以提供栅极信号；像素阵列，其电连接于所述源极驱动器和所述栅极驱动器之间，并用于根据所述数据信号和所述栅极信号来显示影像；削角电路，其电连接于所述栅极驱动器，用于提供所述削角电压，其中，所述削角电路被配置为能够在设定时间内将接收到的直流电压降压至削角电压的电压值，以避免画面的闪烁，保持所述液晶显示面板的各个区域的均齐度一致。
2)在本发明的第1)项的一个优选实施方式中，所述削角电路包括：直流电压输入端；削角电压输出端；第一开关电路，其连接于所述直流电压输入端与所述削角电压输出端之间，以在第一时序信号的控制下选择性导通，并将所述直流电压输入端接收的直流电压选择性地传输至所述削角电压输出端；第二开关电路，其以在第二时序信号控制下选择性导通，所述第二时序信号与所述第一时序信号互为极性相反的脉冲电压信号；放电电路，其连接于所述第二开关电路与所述削角电压输出端之间，以在所述第二开关电路导通时，将传输至所述削角电压输出端的直流电压以设定的放电斜率进行降压，进而形成削角电压，其中，所述放电电路包括放电电阻，所述放电电阻的放电速率，能够在小于等于四分之一的子像素充电周期的时间内将所述直流电压输入端接收的直流电压降压至削角电压的电压值。
3)在本发明的第1)项或第2)项中的一个优选实施方式中，所述放电电阻的阻值在500Ω以下。
4)在本发明的第1)至第3)项中的一个优选实施方式中，所述放电电路还包括二极管，所述二极管的阴极连接所述放电电阻，所述二极管的阳极连接所述第二开关电路。
5)在本发明的第1)至第4)项中的一个优选实施方式中，所述第一开关电路包括第一开关管、第二开关管、第一电阻和第二电阻，其中，所述第二开关管的第一端与所述直流电压输入端连接，所述第二开关管的第二端与所述削角电压输出端连接，所述第一电阻和所述第二电阻串联于所述直流电压输入端和所述第一开关管的第一端之间，所述第二开关管的控制端连接于所述第一电阻和所述第二电阻之间，所述第一开关管的控制端用于接收所述第一时序信号，所述第一开关管的第二端接地，所述第一开关管为N型薄膜晶体管或N型场效应晶体管，所述第二开关管为P型薄膜晶体管或P型场效应晶体管。
6)在本发明的第1)至第5)项中的一个优选实施方式中，所述第二开关电路包括第三开关管，所述第三开关管的第一端与所述放电电路的一端连接，所述第三开关管的第二端接地，所述第三开关管的控制端接收所述第二时序信号，所述第三开关管为N型薄膜晶体管或N型场效应晶体管。
7)在本发明的第1)至第6)项中的一个优选实施方式中，所述放电电路产生的削角电压的电压值能够使所述液晶显示面板的闪烁度小于等于一定阈值，且所述液晶显示面板的各个区域的均齐度一致。
8)在本发明的另一方面，还提供了一种液晶显示面板的驱动方法，包括：在每个充电周期中，向削角电路的直流电压输入端输入直流电压；向所述削角电路的第一开关电路输入第一时序信号，使所述第一开关电路导通，进而使所述直流电压输入端接收的直流电压传输至所述削角电压输出端；向所述削角电路的第二开关电路输入第二时序信号，使所述第二开关电路导通，所述第二时序信号与所述第一时序信号互为极性相反的脉冲电压信号；利用所述放电电路在所述第二开关电路导通时，将传输至所述削角电压输出端的直流电压以设定的放电斜率进行降压，进而形成削角电压，其中，所述放电电路中的放电电阻被设置为：所述放电电阻的放电速率，能够在小于等于四分之一的子像素充电周期的时间内将所述直流电压输入端接收的直流电压降压至削角电压的电压值。
9)在本发明的第1)项的一个优选实施方式中，所述放电电路削角电压的电压值被配置为：使所述液晶显示面板的闪烁度小于等于一定阈值，且所述液晶显示面板的各个区域的均齐度一致。
与现有技术相比，上述方案中的一个或多个实施例可以具有如下优点或有益效果：
本申请的实施例通过在不改变栅极开态最后关闭点电压VGH(off)的电位的情况下，减小削角电路中放电电阻的阻值，并调整削角电路的输入脉冲的占空比来减少放电时间，进而增大削角电路的放电速率、提高子像素的充电能力，使显示面板两侧区域的像素在有 效充电时间内也能被充电至目标电压值或接近目标电压值，避免面板闪烁并提高面板各个区域的均齐度，从而使面板中间区域与面板两侧区域的显示画面趋于一致，改善了三闸极驱动架构的液晶显示面板的色偏问题。
本发明的其它特征和优点将在随后的说明书中阐述，并且，部分地从说明书中变得显而易见，或者通过实施本发明的技术方案而了解。本发明的目的和其他优点可通过在说明书、权利要求书以及附图中所特别指出的结构和/或流程来实现和获得。
附图说明
附图用来提供对本申请的技术方案或现有技术的进一步理解，并且构成说明书的一部分。其中，表达本申请实施例的附图与本申请的实施例一起用于解释本申请的技术方案，但并不构成对本申请技术方案的限制。
图1为现有的一种使用三闸极驱动架构的液晶显示面板的示意图；
图2为像素单元的示意图；
图3(a)和图3(b)分别为图1所示的液晶显示面板在显示低灰阶混色画面时，数据线Dn/2和数据线Dn的电压波形图；
图4为本申请实施例的液晶显示面板的示意图；
图5为本申请实施例的削角电路的示意图；
图6为本申请实施例的削角电路的输入信号和输出信号的波形示例图；
图7为本申请实施例的液晶显示面板中数据线Dn的电压波形图；
图8为开关元件的转移特性曲线图。
具体实施方式
为使本发明的目的、技术方案和优点更加清楚，以下结合附图对本发明作进一步地详细说明。
图3(a)和图3(b)分别为图1所示的液晶显示面板在显示低灰阶混色画面时数据线Dn/2(位于面板中央的数据线)和数据线Dn(位于面板某侧的数据线)的电压波形图。此处，采用128灰阶的黄色画面作为低灰阶混色画面的一个例子，红R、绿G、蓝B各色相区域的灰阶值分别为128、128和0。
请参照图3(a)，VGH表示栅极开态电压，VGH(off)表示栅极开态最后关闭点电压(称为削角电压)，其为栅极开态电压的某一特殊电压，灰阶128表示显示灰阶值128的电压。由于位于面板中央的数据线Dn/2的WOA走线的阻值最小，因此可以将对应该条数据线的子像素的充电状态视为理想状态，即R子像素和G子像素的充电电压未发生任何变化。而且，R子像素和G子像素的充电时间相同，均为T2。这样，与这些子像素对应的显示面板的区域会显示所期望的黄色画面，不会出现色偏现象。
而在图3(b)中，90％*灰阶128表示显示灰阶值128的有效电压，其是显示灰阶值128的电压值的90％，当然，选择90％以上的电压值作为有效电压可以。由于位于面板一侧的数据线Dn的WOA走线的阻值很大，产生的RC延迟也较大，因此导致R子像素和G子像素的充电电压发生变化，尤其是对于R子像素来说，由于RC延迟效应，R子像素的充电时间也大大减小(如图3(b)中的有效充电时间T1)，这样会导致R子像素未达到所要求的充电电量，因此，对应的显示面板区域所显示的画面会偏绿，进而出现色偏现象。
综上，在采用现有的驱动方法来显示低灰阶混色画面时，例如显示128灰阶的黄色画面，液晶显示面板的两端易出现偏红或者偏绿的色偏现象。
需要说明的是，在一个显示面板设计完成后，某个子像素的有效充电时间T1是不会变化的，为了能够在固定的有效充电时间内将子像素的电压值充电至目标电压或接近目标电压，本申请的发明人研究了得出如下实施例，以提高子像素的充电能力。
本申请的实施例通过在不改变栅极开态最后关闭点电压VGH(off)的电位的情况下，减小削角电路中放电电阻的阻值，调整削角电路的输入脉冲GVON的时间起点和占空比，进而增大削角电路的放电速率、提高子像素的充电能力，使显示面板两侧区域的像素在有效充电时间内也能被充电至目标电压值或接近目标电压值，避免面板闪烁并提高面板各个区域的均齐度，从而使面板中间区域与面板两侧区域的显示画面趋于一致，改善了三闸极驱动架构的液晶显示面板的色偏问题。
下面，对本申请的实施例进行说明。
图4为本申请实施例的液晶显示装置的结构示意图。如图所示，液晶显示装置10包括具有多个像素PX的像素阵列单元100、源极驱动器104、栅极驱动器106以及削角电路120。其中，源极驱动器104用来提供数据信号至像素阵列单元100。栅极驱动器106用来根据削角电路120提供的削角电压VGH(off)以提供栅极信号至像素阵列单元100，而像素阵列单元100根据数据信号和栅极信号来显示影像。削角电路120电连接于栅极驱动 器106，削角电路120被配置为能够在设定时间内将接收到的直流电压降压至削角电压的电压值，以避免画面的闪烁，保持液晶显示面板的各个区域的均齐度。其中，均齐度(Uniformity)表示面板亮度一致性和各点间差异值，其具体表达式为：最暗点的亮度/最亮点的亮度。
图5是本申请实施例的削角电路120的示意图。如图5所示，削角电路120包括直流电压输入端VGHP、削角电压输出端VGH、第一开关电路1201、第二开关电路1203、放电电路1205。其中，第一开关电路1201连接于直流电压输入端VGHP与削角电压输出端VGH之间，以在的第一时序信号GVOFF的控制下选择性导通，并将直流电压输入端VGHP接收的直流电压选择性地传输至削角电压输出端VGH。
第二开关电路1203与放电电路1205连接，以在第二时序信号GVON的控制下选择性导通。
放电电路1205连接于第二开关电路1203和削角电压输出端VGH之间，以在第二开关电路1203导通时，将传输至削角电压输出端VGH的直流电压经该放电电路1205以设定的放电斜率进行降压，进而形成削角电压。
具体地，第一开关电路1201包括开关管A、开关管Q1、电阻R1和电阻R2。其中，开关管Q1的第一端1-S与直流电压输入端VGHP连接，开关管Q1的第二端1-D与削角电压输出端VGH连接，电阻R1和电阻R2串联于直流电压输入端VGHP和开关管A的第一端A-D之间，开关管Q1的控制端1-G连接于电阻R1和电阻R2之间。开关管A的控制端A-G用于接收第一时序信号GVOFF，开关管A的第二端A-S接地。
在本实施例中，开关管Q1为P型薄膜晶体管或P型场效应管，且其第一端1-S、第二端1-D和控制端1-G分别为P型开关管的源极、漏极和栅极。开关管A为N型薄膜晶体管或N型场效应管，且其第一端A-D、第二端A-S和控制端A-G分别为N型开关管的漏极、源极和栅极。
第二开关电路1203包括开关管B。该开关管B的第一端B-D与放电电路1205的一端连接，该开关管B的第二端B-S接地，该开关管B的控制端B-G接收第二时序信号GVON。在本实施例中，开关管B为N型薄膜晶体管或N型场效应管，开关管B的第一端B-D、第二端B-S和控制端B-G分别为N型开关管的漏极、源极和栅极。
需要说明的是，第一时序信号GVOFF和第二时序信号GVON互为反向信号且均为电压信号，可以通过时序控制器和反相器来产生这两种信号。具体地，时序控制器产生第一时序信号GVOFF，第一时序信号GVOFF经由反相器产生第二时序信号GVON。除了 上述方法以外，还可以采用其他的方法来产生第一时序信号GVOFF和第二时序信号GVON。
请再次参照图5，放电电路1205包括串联的放电电阻R3。该放电电阻的放电速率，能够在小于等于四分之一的充电周期的时间内将直流电压输入端VGHP接收的直流电压VGHP降压至削角电压VGH的电压值。当然，上述的放电时间仅为一个优选的例子，在某些情况下，本领域的发明人可以选择其他的放电时间。
容易理解，在其他实施例中，也可以采用其他具有开关作用的简单元器件进行电路设计，例如三极管、可控硅、继电器等，并不限于本申请实施例的P/N型开关管。
另外，放电电路1205还可以包括稳压二极管ZD1以进行稳压作用，稳压二极管ZD1的阳极与开关管B的第一端B-D连接，稳压二极管ZD1的阴极与放电电阻R3连接。图5中所示的电容C是各扫描线在面板中的寄生电容。
需要说明的是，上述削角电路120的电路结构仅为一个例子，例如还可以通过切换电路来切换第一开关电路和第二开关电路的动作进而实现削角电路的功能，因此其他任何能够在设定时间内将接收到的直流电压放电至削角电压的电压值，以消除色偏现象的削角电路均属于本申请的保护范围。
图6为本申请实施例的削角电路的输入信号(包括直流电压VGHP、第一时序信号GVOFF和第二时序信号GVON)和输出信号的波形示例，下面结合图6对本申请的削角电路的工作原理进行详细说明。
如图6所示，作为本实施例的一个例子，时序控制器将第二时序信号GVON的占空比(负向)由现有的23％增大到80％，将第一时序信号GVOFF的占空比(负向)由77％减小至20％。当然，还可以将时序信号的占空比设置为其他百分比，只要放电时间为小于等于四分之一的子像素充电周期的时间即可。
如图5所示，在每个充电周期内，向直流电压输入端VGHP输入直流电压，向第一开关电路1201的开关管A的控制端A-G输入第一时序信号GVOFF，向第二开关电路1203的开关管B的控制端B-G输入第二时序信号GVON。
当第一时序信号GVOFF处于高电平状态时，开关管A和开关管Q1导通，此时第二时序信号GVON处于低电平状态，开关管B截止，此时削角电压输出端VGH输出的电压与直流电压输入端VGHP的电压一致。当第二时序信号GVON处于高电平状态时，开关管B导通，第一时序信号GVOFF处于低电平状态，开关管A和开关管Q1截止，此时经放电电阻R3降压形成削角电压并输出至削角电压输出端VGH。当然也可以不设置放 电电阻R3，通过控制第一时序信号GVOFF和第二时序信号GVON的对应关系也能产生削角电压。
需要说明的是，本实施例中的放电电阻R3的阻值优选为小于等于500Ω，在一个例子中，放电电阻R3的阻值为336Ω。这样，由于放电电阻R3的阻值相比现有技术中的放电电阻的阻值(一般为1.5KΩ以上)要小得多，因此能够大大增加削角电路的放电速率，进而能够在20％的充电周期的时间内完成降压，达到预设的削角电压。
而且，如图7所示，放电电路120在每个周期开始进行放电的启动时间从Ta时刻推迟到Tb时刻，这样能够延长VGH高电压(此时等于直流电压输出端的直流电压VGHP)的时间，进而能够增强子像素的充电能力。这是因为，对于与子像素连接的开关元件来说，开关元件的栅极对应扫描线，开关元件的源极对应数据线，开关元件的漏极对应像素电极。在栅极的控制下，源极的数据线通过开关元件向漏极的像素实施充放电。而且，栅极的功能就是控制开关元件的导电程度，需要对像素充放电的时候，开关元件工作在大电流的开态，不需要对像素充放电的时候，开关元件工作在小电流的关态。而且，开态的大电流承担着充放电的功能，电流越大，充放电越快越充分。
通过对一些不同类型的开关元件进行测试，得到如图8所示结果。正如图8所示，随着削角电压VGH逐渐增加，连接像素的开关元件的开态电流越大，因此，为了提高充电能力，将会选择较高的VGH电压。这样的话，由于提高了充电能力，因此在固定的子像素的有效充电时间T1内，能够在将子像素充电至目标电压值或接近目标电压值，在显示低灰阶混色画面时，例如显示128灰阶的黄色画面，液晶显示面板的两端不会出现偏红或者偏绿的色偏现象，提高了显示品质。
另外，对于削角电压(栅极关态电压)的选择，优选地被配置为：使液晶显示面板的闪烁度小于等于一定阈值，且所述液晶显示面板的各个区域的均齐度一致，其中，闪烁度通过如下表达式得到：(最大亮度-最小亮度)/平均亮度。以32 tri-gate为例，闪烁度阈值为5，使得面板的均齐度大于80％。
在本实施例中，最佳的VGH(off)等于20V，这样能够避免面板中TFT开关关闭时因VGH(off)过高而导致的画面闪烁现象或者过低而引起的不期望的颜色或杂讯等。
以上所述，仅为本发明的具体实施案例，本发明的保护范围并不局限于此，任何熟悉本技术的技术人员在本发明所述的技术规范内，对本发明的修改或替换，都应在本发明的保护范围之内。

Claims (13)

  1. 一种液晶显示面板，包括：
    源极驱动器，用于提供数据信号；
    栅极驱动器，用于根据削角电压以提供栅极信号；
    像素阵列，其电连接于所述源极驱动器和所述栅极驱动器之间，并用于根据所述数据信号和所述栅极信号来显示影像；
    削角电路，其电连接于所述栅极驱动器，用于提供所述削角电压，
    其中，所述削角电路被配置为能够在设定时间内将接收到的直流电压降压至削角电压的电压值，以避免画面的闪烁，保持所述液晶显示面板的各个区域的均齐度一致。
  2. 根据权利要求1所述的液晶显示面板，其中，所述削角电路包括：
    直流电压输入端；
    削角电压输出端；
    第一开关电路，其连接于所述直流电压输入端与所述削角电压输出端之间，以在第一时序信号的控制下选择性导通，并将所述直流电压输入端接收的直流电压选择性地传输至所述削角电压输出端；
    第二开关电路，其以在第二时序信号控制下选择性导通，所述第二时序信号与所述第一时序信号互为极性相反的脉冲电压信号；
    放电电路，其连接于所述第二开关电路与所述削角电压输出端之间，以在所述第二开关电路导通时，将传输至所述削角电压输出端的直流电压以设定的放电斜率进行降压，进而形成削角电压，
    其中，所述放电电路包括放电电阻，所述放电电阻的放电速率，能够在小于等于四分之一的子像素充电周期的时间内将所述直流电压输入端接收的直流电压降压至削角电压的电压值。
  3. 根据权利要求1所述的液晶显示面板，其中，
    所述放电电阻的阻值在500Ω以下。
  4. 根据权利要求2所述的液晶显示面板，其中，
    所述放电电路还包括二极管，所述二极管的阴极连接所述放电电阻，所述二极管的阳极连接所述第二开关电路。
  5. 根据权利要求2所述的液晶显示面板，其中，
    所述第一开关电路包括第一开关管、第二开关管、第一电阻和第二电阻，
    其中，所述第二开关管的第一端与所述直流电压输入端连接，所述第二开关管的第二端与所述削角电压输出端连接，所述第一电阻和所述第二电阻串联于所述直流电压输入端和所述第一开关管的第一端之间，所述第二开关管的控制端连接于所述第一电阻和所述第二电阻之间，所述第一开关管的控制端用于接收所述第一时序信号，所述第一开关管的第二端接地，
    所述第一开关管为N型薄膜晶体管或N型场效应晶体管，所述第二开关管为P型薄膜晶体管或P型场效应晶体管。
  6. 根据权利要求3所述的液晶显示面板，其中，
    所述第一开关电路包括第一开关管、第二开关管、第一电阻和第二电阻，
    其中，所述第二开关管的第一端与所述直流电压输入端连接，所述第二开关管的第二端与所述削角电压输出端连接，所述第一电阻和所述第二电阻串联于所述直流电压输入端和所述第一开关管的第一端之间，所述第二开关管的控制端连接于所述第一电阻和所述第二电阻之间，所述第一开关管的控制端用于接收所述第一时序信号，所述第一开关管的第二端接地，
    所述第一开关管为N型薄膜晶体管或N型场效应晶体管，所述第二开关管为P型薄膜晶体管或P型场效应晶体管。
  7. 根据权利要求4所述的液晶显示面板，其中，
    所述第一开关电路包括第一开关管、第二开关管、第一电阻和第二电阻，
    其中，所述第二开关管的第一端与所述直流电压输入端连接，所述第二开关管的第二端与所述削角电压输出端连接，所述第一电阻和所述第二电阻串联于所述直流电压输入端和所述第一开关管的第一端之间，所述第二开关管的控制端连接于所述第一电阻和所述第二电阻之间，所述第一开关管的控制端用于接收所述第一时序信号，所述第一开关管的第二端接地，
    所述第一开关管为N型薄膜晶体管或N型场效应晶体管，所述第二开关管为P型薄膜晶体管或P型场效应晶体管。
  8. 根据权利要求2所述的液晶显示面板，其中，
    所述第二开关电路包括第三开关管，所述第三开关管的第一端与所述放电电路的一端连接，所述第三开关管的第二端接地，所述第三开关管的控制端接收所述第二时序信号，所述第三开关管为N型薄膜晶体管或N型场效应晶体管。
  9. 根据权利要求3所述的液晶显示面板，其中，
    所述第二开关电路包括第三开关管，所述第三开关管的第一端与所述放电电路的一端连接，所述第三开关管的第二端接地，所述第三开关管的控制端接收所述第二时序信号，所述第三开关管为N型薄膜晶体管或N型场效应晶体管。
  10. 根据权利要求4所述的液晶显示面板，其中，
    所述第二开关电路包括第三开关管，所述第三开关管的第一端与所述放电电路的一端连接，所述第三开关管的第二端接地，所述第三开关管的控制端接收所述第二时序信号，所述第三开关管为N型薄膜晶体管或N型场效应晶体管。
  11. 根据权利要求1所述的液晶显示面板，其中，
    所述放电电路产生的削角电压的电压值能够使所述液晶显示面板的闪烁度小于等于一定阈值，且所述液晶显示面板的各个区域的均齐度一致。
  12. 一种液晶显示面板的驱动方法，包括：
    在每个充电周期中，
    向削角电路的直流电压输入端输入直流电压；
    向所述削角电路的第一开关电路输入第一时序信号，使所述第一开关电路导通，进而使所述直流电压输入端接收的直流电压传输至所述削角电压输出端；
    向所述削角电路的第二开关电路输入第二时序信号，使所述第二开关电路导通，所述第二时序信号与所述第一时序信号互为极性相反的脉冲电压信号；
    在所述第二开关电路导通时，利用削角电路中的放电电路将传输至所述削角电压输出端的直流电压以设定的放电斜率进行降压，进而形成削角电压，
    其中，所述放电电路中的放电电阻被设置为：所述放电电阻的放电速率，能够在小于等于四分之一的子像素充电周期的时间内将所述直流电压输入端接收的直流电压降压至削角电压的电压值。
  13. 根据权利要求12所述的驱动方法，其中，
    所述放电电路削角电压的电压值被配置为：使得所述液晶显示面板的闪烁度小于等于一定阈值，且所述液晶显示面板的各个区域的均齐度一致。
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