WO2016026322A1 - 半浮栅功率器件及其制造方法 - Google Patents

半浮栅功率器件及其制造方法 Download PDF

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WO2016026322A1
WO2016026322A1 PCT/CN2015/077144 CN2015077144W WO2016026322A1 WO 2016026322 A1 WO2016026322 A1 WO 2016026322A1 CN 2015077144 W CN2015077144 W CN 2015077144W WO 2016026322 A1 WO2016026322 A1 WO 2016026322A1
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gallium nitride
floating gate
gate
layer
semi
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French (fr)
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王鹏飞
刘晓勇
黄泓帆
张卫
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Fudan University
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Fudan University
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Priority claimed from CN201410403932.0A external-priority patent/CN104167450B/zh
Priority claimed from CN201410402668.9A external-priority patent/CN104183651B/zh
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Priority to US15/129,958 priority Critical patent/US10388650B2/en
Publication of WO2016026322A1 publication Critical patent/WO2016026322A1/zh
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/811—Combinations of field-effect devices and one or more diodes, capacitors or resistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/015—Manufacture or treatment of FETs having heterojunction interface channels or heterojunction gate electrodes, e.g. HEMT
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/40—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels
    • H10D30/47—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having two-dimensional [2D] charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
    • H10D30/471—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT]
    • H10D30/475—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT] having wider bandgap layer formed on top of lower bandgap active layer, e.g. undoped barrier HEMTs such as i-AlGaN/GaN HEMTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/68—Floating-gate IGFETs
    • H10D30/6891—Floating-gate IGFETs characterised by the shapes, relative sizes or dispositions of the floating gate electrode
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/68—Floating-gate IGFETs
    • H10D30/6891—Floating-gate IGFETs characterised by the shapes, relative sizes or dispositions of the floating gate electrode
    • H10D30/6894—Floating-gate IGFETs characterised by the shapes, relative sizes or dispositions of the floating gate electrode having one gate at least partly in a trench
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D1/00—Resistors, capacitors or inductors
    • H10D1/60—Capacitors
    • H10D1/68—Capacitors having no potential barriers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/85—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group III-V materials, e.g. GaAs
    • H10D62/8503—Nitride Group III-V materials, e.g. AlN or GaN
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D8/00—Diodes
    • H10D8/60—Schottky-barrier diodes 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/05—Manufacture or treatment characterised by using material-based technologies using Group III-V technology

Definitions

  • the invention belongs to the technical field of semiconductor power devices, and in particular relates to a semi-floating gate power device and a manufacturing method thereof.
  • a 600V GaN power switch is usually composed of a normally-on GaN high electron mobility transistor device and a normally-off silicon-based device using a cascode connection.
  • FIG. 1 A well-known cascode GaN power switching circuit is shown in FIG. 1 , which includes a normally-on GaN transistor (M GaN ) and a normally-off silicon MOS transistor (M Si ) in a cascode configuration.
  • the silicon-based MOS transistor (M Si ) is actively controlled by the gate driver, and the gate driver generates a gate signal (V GM ).
  • the gallium nitride transistor (M GaN ) is indirectly controlled by a silicon-based MOS transistor (M Si ) because the drain-source voltage of the silicon-based MOS transistor (M Si ) is equal to the source of the gallium nitride transistor (M GaN ) - Gate voltage.
  • the cascoded GaN power switch consists of a normally-on GaN transistor (M GaN ) and a normally-off silicon-based MOS transistor (M Si ), which has a complicated structure and cascode power of the cascode.
  • M GaN normally-on GaN transistor
  • M Si normally-off silicon-based MOS transistor
  • the reliability of the switch is not high. Firstly, the cascode GaN transistor switch is easily broken down during dynamic avalanche. The low-voltage normally-off silicon-based MOS transistor is easily broken down. Secondly, the GaN transistor is also hit because of the voltage pulse in the dynamic operation. Wear, gate pn junction reverse conduction and other issues.
  • a semi-floating gate power device comprising a gallium nitride high electron mobility transistor further comprising:
  • a diode having an anode connected to a gate of the gallium nitride high electron mobility transistor, a cathode of the diode being connected to a source or a channel region of the gallium nitride high electron mobility transistor;
  • a capacitor having one end connected to the gate of the gallium nitride high electron mobility transistor and the other end of the capacitor connected to an external voltage signal.
  • the diode is a Schottky diode.
  • the present invention also provides the specific structure of five preferred semi-floating gate power devices using Schottky diodes for the above-described semi-floating gate power device:
  • the semi-floating gate power device of the present invention comprises a semiconductor substrate having a gallium nitride barrier layer thereon, and a gallium nitride channel layer is disposed on the gallium nitride barrier layer, the nitridation a gallium nitride aluminum isolation layer is disposed on the gallium channel layer; a gate dielectric layer is disposed on the gallium nitride aluminum isolation layer, and a floating gate is disposed on the gate dielectric layer, and the floating gate is disposed thereon
  • An interlayer dielectric layer is disposed above the interlayer dielectric layer, the control gate is coupled to the floating gate by capacitive coupling, and two sides of the control gate are respectively disposed in the gallium nitride trench a source and a drain above the track layer; the floating gate extends toward the source side and is connected to the gallium nitride aluminum isolation layer beyond the gate dielectric layer.
  • the semi-floating gate power device of the present invention comprises a semiconductor substrate having a gallium nitride barrier layer thereon, and a gallium nitride channel layer is disposed on the gallium nitride barrier layer, the nitridation a gallium nitride aluminum isolation layer is disposed on the gallium channel layer; a gate dielectric layer is disposed on the gallium nitride aluminum isolation layer, and a floating gate is disposed on the gate dielectric layer, and the floating gate is disposed thereon
  • An interlayer dielectric layer is disposed above the interlayer dielectric layer, the control gate is coupled to the floating gate by capacitive coupling, and two sides of the control gate are respectively disposed in the gallium nitride trench a source and a drain above the track layer; the floating gate is extended to the source side And extending beyond the gate dielectric layer and the gallium nitride aluminum isolation layer to the gallium nitride channel layer.
  • the semi-floating gate power device of the present invention comprises a semiconductor substrate having a gallium nitride barrier layer thereon, and a gallium nitride channel layer is disposed on the gallium nitride barrier layer, the nitridation a gallium nitride aluminum isolation layer is disposed on the gallium channel layer; a gate dielectric layer is disposed on the gallium nitride aluminum isolation layer, and a floating gate is disposed on the gate dielectric layer, and the floating gate is disposed thereon An interlayer dielectric layer is disposed above the interlayer dielectric layer, the control gate is coupled to the floating gate by capacitive coupling, and two sides of the control gate are respectively disposed in the gallium nitride trench a source and a drain above the track layer; the floating gate is connected to the gallium nitride channel layer through a first opening in the gate dielectric layer and the gallium nitride aluminum isolation layer.
  • the semi-floating gate power device of the present invention comprises a semiconductor substrate having a gallium nitride barrier layer thereon, and a gallium nitride channel layer is disposed on the gallium nitride barrier layer, the nitridation a gallium nitride aluminum isolation layer is disposed on the gallium channel layer; a gate dielectric layer is disposed on the gallium nitride aluminum isolation layer, and a floating gate is disposed on the gate dielectric layer, and the floating gate is disposed thereon An interlayer dielectric layer is disposed above the interlayer dielectric layer, the control gate is coupled to the floating gate by capacitive coupling, and two sides of the control gate are respectively disposed in the gallium nitride trench a source and a drain above the track layer; a first opening in the gate dielectric layer and the gallium nitride aluminum isolation layer under the floating gate, and a gallium nitride channel layer under the first opening a first recess having a
  • the semi-floating gate power device of the present invention comprises a semiconductor substrate having a gallium nitride barrier layer thereon, and a gallium nitride channel layer is disposed on the gallium nitride barrier layer, the nitridation a gallium nitride aluminum isolation layer is disposed on the gallium channel layer; a gate dielectric layer is disposed on the gallium nitride aluminum isolation layer, and a floating gate is disposed on the gate dielectric layer, and the floating gate is disposed thereon An interlayer dielectric layer is disposed above the interlayer dielectric layer, the control gate is coupled to the floating gate by capacitive coupling, and two sides of the control gate are respectively disposed in the gallium nitride trench a source and a drain above the track layer; a first opening in the gate dielectric layer and the gallium nitride aluminum isolation layer under the floating gate, and a gallium nitride aluminum isolation layer under the floating gate a second opening; a first opening in the
  • a gallium nitride aluminum barrier layer may be further disposed between the gallium nitride barrier layer and the gallium nitride channel layer.
  • the above five kinds of semi-floating gate power devices are made of chromium, or a nickel- or tungsten-containing alloy, or doped polysilicon; and the interlayer dielectric layer is silicon oxide or silicon nitride.
  • the control gate is a polysilicon control gate or a metal control gate.
  • a source and a drain are formed on the two sides of the control gate in contact with the gallium nitride aluminum isolation layer or the gallium nitride channel layer, respectively.
  • the semi-floating gate power device of the present invention works by connecting a gate of a gallium nitride high electron mobility transistor transistor to a source or a channel region through a diode, and clamping the diode to enable high electron mobility of gallium nitride.
  • the gate of the rate transistor becomes a semi-floating gate structure. If the gallium nitride high electron mobility transistor is a normally-on transistor, the half floating gate power device is in an on state at an initial state.
  • the external voltage signal (V CG ) acts on the semi-floating gate through a capacitor, when the external voltage signal is a positive voltage and the device is in an on state, a negative charge is stored in the semi-floating gate, causing the threshold voltage to rise.
  • the half floating gate voltage is negative (time is in the order of nanoseconds), and the half floating gate power device is in an off state.
  • the external voltage signal changes from 0V to a positive voltage again, the half floating gate power device is again in an on state. Therefore, by adjusting the pulse of the external voltage signal (V CG ), the semi-floating gate power device can be continuously turned on and off to form a switching power supply circuit or other circuits.
  • the gallium nitride high electron mobility transistor is a normally-off transistor, the half floating gate power device is turned off in an initial state. Since the external voltage signal (V CG ) acts on the semi-floating gate through a capacitor, when the external voltage signal is a positive voltage, a negative charge is stored in the semi-floating gate, which also causes the device threshold voltage to rise when the external voltage signal When the positive voltage is changed to 0V, the half floating gate voltage is negative (time is in the order of nanoseconds), and the half floating gate power device is in the off state. When the external voltage signal changes from 0V to a positive voltage again, the half floating gate power device is again in an on state. Therefore, by adjusting the pulse of the external voltage signal (V CG ), the semi-floating gate power device can be continuously turned on and off to form a switching power supply circuit or other circuits.
  • V CG the external voltage signal
  • the present invention has the significant advantages that: first, the semi-floating gate power device of the present invention adopts a semi-floating gate structure, and forms a control gate on the semi-floating gate, and the control gate acts on the semi-floating gate through capacitive coupling. This allows a semi-floating gate power device to implement the functions of two transistors in a cascode connection mode, simplifying the structure of the semiconductor power device.
  • the embedded diode between the gate and the source or channel region of the gallium nitride high electron mobility transistor can be clamped, and the external voltage signal can be used to control the instantaneous opening of the semi-floating gate power device through capacitive sensing, so that the half float
  • the gate power device is suitable for high voltage, high speed operation and high reliability.
  • the power semi-floating gate device structure can increase the threshold voltage of the gallium nitride high electron mobility transistor during operation, so that it can be better used as a power switch.
  • FIG. 1 is a schematic diagram of a cascode power switching circuit of a prior art cascode
  • FIG. 2 is a schematic diagram showing an equivalent circuit of an embodiment of a semi-floating gate power device according to the present invention
  • 3 to 5 are schematic cross-sectional views showing the structure of the first to third embodiments of the semi-floating gate power device proposed by the present invention.
  • Figure 6 is an equivalent circuit diagram of the semi-floating gate power devices of the first to third embodiments shown in Figures 3 to 5 of the present invention.
  • FIG. 7 to 9 are schematic cross-sectional views showing the structure of the fourth to sixth embodiments of the semi-floating gate power device proposed by the present invention.
  • Figure 10 is an equivalent circuit diagram of the fourth to sixth embodiments of the semi-floating gate power device of the present invention as shown in Figures 7-9.
  • 11 to 14 are process flow diagrams of one embodiment of a method of fabricating a semi-floating gate power device of the present invention.
  • the thickness of the layers and regions of the present invention are exaggerated for the purpose of clearly illustrating the embodiments of the present invention, and the size of the listed figures does not represent actual dimensions; the drawings are schematic The scope of the invention should not be limited.
  • the embodiments listed in the specification should not be limited to the specific shapes of the regions shown in the drawings, but include the resulting shapes such as manufacturing-induced deviations, etc., and the curves obtained by etching are usually curved or rounded, but In the embodiments of the present invention, they are all represented by rectangles.
  • the term substrate as used may be understood to include a semiconductor wafer being processed, possibly including other thin film layers prepared thereon.
  • the semi-floating gate power device of the present invention includes a gallium nitride high electron mobility transistor 100 including a source 101, a gate 103, and a drain 102.
  • the source 101 and the gate 103 of the gallium nitride high electron mobility transistor are connected by a diode 200 such that the gate 103 becomes a semi-floating gate structure, that is, the gate 103 of the gallium nitride high electron mobility transistor can be used as the present invention.
  • the floating gate 103 of the semi-floating gate power device is a gallium nitride high electron mobility transistor.
  • Diode 200 includes, but is not limited to, a Schottky diode, and the anode of diode 200 is coupled to gate 103, and the cathode of diode 200 is coupled to source 101.
  • the external voltage signal (V CG ) 400 is connected to the gate 103 through a capacitor 300, so that the external voltage signal (V CG ) 400 can control the gallium nitride high electron mobility transistor 100 to be turned on or off by capacitive sensing.
  • the cathode of the diode 200 may not be connected to the source of the gallium nitride high electron mobility transistor 100, and the channel of the gallium nitride high electron mobility transistor 100. Zone connection.
  • the semi-floating gate power device of the present invention can have a variety of configurations, and a preferred embodiment of the semi-floating gate power device of the present invention is described below.
  • the semi-floating gate power device of the present invention includes a semiconductor substrate 11 and a gallium nitride block on the semiconductor substrate 11.
  • a gallium nitride channel layer 14 and a gallium nitride aluminum spacer layer 15 are sequentially formed on the gallium nitride barrier layer 12.
  • a gate dielectric layer 501 is formed over the gallium nitride aluminum spacer layer 15, and a gate (ie, floating gate) 103 of a gallium nitride high electron mobility transistor is formed over the gate dielectric layer 501.
  • a source 101 and a drain 102 of a gallium nitride high electron mobility transistor are formed on both sides of the floating gate 103, and a source 101 and a drain 102 are formed on the gallium nitride aluminum spacer 15.
  • the floating gate 103 extends to one side of the source 101, and the floating gate 103 extends beyond the gate dielectric layer 501 and is in contact with the gallium nitride aluminum spacer layer 15, since the floating gate 103 is usually chromium-containing, or contains nickel or contains tungsten.
  • the alloy or doped polysilicon so that the floating gate 103 and the gallium nitride aluminum isolation layer 15 form a Schottky diode, that is, a Schottky diode is directly formed at the gate 103 and the source 101.
  • the width of the Schottky diode (perpendicular to the paper) is less than active The width of the region is such that the channel region of the high electron mobility device can be effectively connected to the source 101.
  • An interlayer dielectric layer 502 is formed over the floating gate 103.
  • the interlayer dielectric layer 502 is typically a high dielectric constant medium such as silicon dioxide, silicon nitride, hafnium oxide, or aluminum oxide or a laminate therebetween.
  • a control gate 104 is formed over the interlayer dielectric layer 502, and the control gate 104 is connected to the external voltage signal 400 and acts on the floating gate 103 by capacitive coupling.
  • FIG. 4 is a cross-sectional view showing a second embodiment of the semi-floating gate power device of the present invention. Compared with the semi-floating gate power device shown in FIG. 3, the semi-floating gate power device shown in FIG. 4 is only nitrided.
  • a gallium nitride aluminum barrier layer 103 is disposed between the gallium barrier layer 102 and the gallium nitride channel layer 104.
  • the aluminum gallium nitride barrier layer 103 structure is a common structure in a high electron mobility transistor, and is no longer in the embodiment of the present invention. Carry out a detailed description.
  • FIG. 5 is a cross-sectional view showing a third embodiment of the semi-floating gate power device of the present invention.
  • the semi-floating gate power device shown in FIG. 5 is etched off.
  • the gallium nitride aluminum isolation layer 15 on both sides of the dielectric layer 501 extends the floating gate 103 toward one side of the source electrode 101, and the floating gate 103 extends beyond the gate dielectric layer 501 and the gallium nitride aluminum isolation layer 15 and is combined with gallium nitride.
  • the aluminum channel layer 14 is in contact with a Schottky diode.
  • the source 101 and the drain 102 are formed directly on the gallium nitride channel layer 14.
  • FIG. 6 is an equivalent circuit diagram of a semi-floating gate power device of the first to third embodiments shown in Figures 3 to 5 of the present invention.
  • the semi-floating gate power device of the present invention includes a gallium nitride high electron mobility transistor 100, the gate of the gallium nitride high electron mobility transistor 100 (ie, the floating of the semi-floating gate power device of the present invention).
  • the gate 103 is connected to the source 101 through a Schottky diode 200 such that the gate 103 is a semi-floating gate structure, and the control gate 400 acts on the floating gate 103 by capacitive coupling.
  • the semi-floating gate power device of the present invention includes a semiconductor substrate 11 and a semiconductor substrate 11.
  • the gallium nitride barrier layer 12 is further formed with a gallium nitride channel layer 14 and a gallium nitride aluminum spacer layer 15 in this order over the gallium nitride barrier layer 12.
  • a gate dielectric layer 501 is formed over the gallium nitride aluminum spacer layer 15, and a gate (ie, floating gate) 103 of a gallium nitride high electron mobility transistor is formed over the gate dielectric layer 501.
  • a source 101 and a drain 102 of a gallium nitride high electron mobility transistor are formed on both sides of the floating gate 103, and a source 101 and a drain 102 are formed on the aluminum gallium nitride channel layer 14.
  • the floating gate 103 is in contact with the gallium nitride channel layer 14 through a first opening in the gate dielectric 501 and the aluminum gallium nitride spacer 15, since the floating gate 103 is typically chromium-containing, or contains nickel, or contains tungsten.
  • the alloy or doped polysilicon thus the floating gate 103 and the gallium nitride channel layer 14 form a Schottky diode, that is, a Schottky diode is formed between the floating gate 103 and the channel region.
  • the width of the Schottky diode (perpendicular to the paper) is less than the width of the active region such that the channel region of the high electron mobility device can be effectively connected to the source 101.
  • An interlayer dielectric layer 502 is formed over the floating gate 103.
  • the interlayer dielectric layer 502 is typically a high dielectric constant medium such as silicon dioxide, silicon nitride, hafnium oxide, or aluminum oxide or a laminate therebetween.
  • a control gate 104 is formed over the interlayer dielectric layer 502, and the control gate 104 is connected to the external voltage signal 400 and capacitively coupled to the floating gate 103.
  • FIG. 8 is a cross-sectional view showing a fifth embodiment of the semi-floating gate power device of the present invention, which is an optimized structure of the semi-floating gate power device shown in FIG. 7 and formed in the gallium nitride channel layer 14 a first recess below the first opening in the gate dielectric 501 and the gallium nitride aluminum isolation layer 15, and a bottom of the first recess is located at the bottom of the gallium nitride channel layer 14, that is, The bottom of the recess is located on the surface of the gallium nitride barrier layer 12, and the floating gate 103 fills the first recess. Further, the bottom of the first recess may be located at any depth of the gallium nitride channel layer 14.
  • the floating gate 103 and the gallium nitride channel layer 14 may be conveniently adjusted.
  • the turn-on voltage of the Schottky diode The deeper the first groove is, the lower the on-voltage is. On the contrary, the shallower the first groove is, the higher the on-voltage is.
  • FIG. 9 is a cross-sectional view showing a sixth embodiment of the semi-floating gate power device of the present invention, which is based on a half floating gate power device as shown in FIG. 7 and a gallium nitride trench on the side close to the drain 102.
  • a second recess having the same depth as the first recess is formed in the track layer 14, the gate dielectric layer 501 covers the surface of the second recess to expose the first recess, and the floating gate 103 simultaneously fills the first recess a groove and a second groove.
  • FIGS. 7 to 9 shows an equivalent circuit diagram of the semi-floating gate power device of the fourth to sixth embodiments shown in FIGS. 7 to 9, in which the gate of the gallium nitride high electron mobility transistor 100 (ie, the half float of the present invention)
  • the floating gate) 103 of the gate power device is connected to the channel region of the gallium nitride high electron mobility transistor 100 through a Schottky diode 200, and the control gate 400 acts on the floating gate 103 by capacitive coupling.
  • FIG. 14 are process flow diagrams of one embodiment of a method of fabricating a gallium nitride half floating gate power device as shown in FIG. 9 according to the present invention.
  • a gallium nitride barrier layer 12, a gallium nitride channel layer 14, and a gallium nitride aluminum spacer layer 15 are sequentially deposited on the semiconductor substrate 11, followed by photolithography and sequential etch nitridation.
  • a gallium aluminum isolation layer 15 and a gallium nitride channel layer 14 form a first recess 701 and a second recess 702 in the gallium nitride channel layer 14.
  • a gate dielectric layer 501 is deposited over the above-described formed structure and photolithography and etching are performed to form a floating gate opening 703 in the gate dielectric layer 501, and the opening of the floating gate opening 703 The width is greater than the opening width of the second groove 702 such that the floating gate opening 703 exposes the second groove 702.
  • a first conductive film, a first insulating film, and a second conductive film are sequentially deposited over the above-described formed structure, followed by photolithography and sequentially etching the second conductive film.
  • a second insulating film and a first conductive film form a floating gate 103 covering the first recess and the second recess, and an interlayer dielectric layer 502 and a control gate 104 over the floating gate 103.
  • a gate spacer 60 is formed on both sides of the gate 104, and then the exposed gate dielectric layer 501 is etched away, and then formed on both sides of the control gate 104 by a well-known process in the industry.
  • the source 101 and the drain 102 are in contact with the gallium nitride channel layer 14.

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Abstract

一种半浮栅功率器件，包括一个氮化镓高电子迁移率晶体管（100）、一个二极管（200）和一个电容器（300），二极管的阳极与氮化镓高电子迁移率晶体管的栅极（103）连接，二极管的阴极与氮化镓高电子迁移率晶体管的源极（101）或沟道区连接；电容器的一端与氮化镓高电子迁移率晶体管的栅极连接，电容器的一端与外部电压信号连接。半浮栅功率器件结构简单、易于制造，适合高压、高速操作并且具有很高的可靠性，半浮栅功率器件还能够提高半浮栅功率器件在工作状态时的阈值电压，使其能够更好的作为功率开关管使用。

Description

半浮栅功率器件及其制造方法 技术领域
本发明属于半导体功率器件技术领域，特别是涉及半浮栅功率器件及其制造方法。
背景技术
高电子迁移率的宽禁带器件比如氮化镓高电子迁移率晶体管相对于传统的硅器件具有耐高温、高效率、高速度等优点，已被广泛使用。目前，600V的氮化镓高电子迁移率器件很难做成常关型，即使做成常关型器件，其阈值电压也接近0V，容易被误开启。因此600V的氮化镓功率开关通常由一个常开型氮化镓高电子迁移率晶体管器件和一个常关型硅基器件用共源共栅连接方式组成。
公知的共源共栅的氮化镓功率开关电路如图1所示，包括共源共栅配置的常开型氮化镓晶体管(MGaN)和常关型硅基MOS晶体管(MSi)，其中，硅基MOS晶体管(MSi)主动地被栅极驱动器控制，栅极驱动器产生栅极信号(VGM)。氮化镓晶体管(MGaN)是间接的通过硅基MOS晶体管(MSi)控制，因为硅基MOS晶体管(MSi)的漏极-源极电压等于氮化镓晶体管(MGaN)的源极-栅极电压。共源共栅的氮化镓功率开关的优点是可以使用现有标准的栅极驱动器，因此共源共栅的氮化镓功率开关可以被用来直接替换硅基MOS晶体管开关。然而共源共栅的氮化镓功率开关由常开型氮化镓晶体管(MGaN)和常关型硅基MOS晶体管(MSi)组成，结构复杂，而且共源共栅的氮化镓功率开关的可靠性不高。首先共源共栅的氮化镓晶体管开关在动态雪崩时，低压的常关型硅基MOS晶体管容易被击穿；其次，氮化镓晶体管由于在动态操作中存在电压脉冲，因此也存在被击穿、栅极pn结反向导通等问题。
发明内容
本发明的目的是提供一种半浮栅功率器件，能够简化氮化镓功率器件的结构并提高其可靠性。
本发明的目的将通过以下技术方案实现：
一种半浮栅功率器件，包括一个氮化镓高电子迁移率晶体管，还包括：
一个二极管，该二极管的阳极与所述氮化镓高电子迁移率晶体管的栅极连接，该二极管的阴极与所述氮化镓高电子迁移率晶体管的源极或沟道区连接；
一个电容器，该电容器的一端与所述氮化镓高电子迁移率晶体管的栅极连接，该电容器的另一端与外部电压信号连接。
优选的，上述的一种半浮栅功率器件，所述二极管为肖特基二极管。
本发明针对上述半浮栅功率器件还提供了五种优选的采用肖基特二极管的半浮栅功率器件的具体结构：
第一种结构：本发明的半浮栅功率器件包括一个半导体基底，该半导体基底上设有氮化镓阻挡层，该氮化镓阻挡层之上设有氮化镓沟道层，该氮化镓沟道层之上设有氮化镓铝隔离层；所述氮化镓铝隔离层之上设有栅介质层，所述栅介质层之上设有浮栅，所述浮栅之上设有层间介质层，所述层间介质层之上设有控制栅，所述控制栅通过电容耦合作用于所述浮栅，所述控制栅的两侧分别设有位于所述氮化镓沟道层之上的源极和漏极；所述浮栅向所述源极一侧延伸并超出所述栅介质层与所述氮化镓铝隔离层连接。
第二种结构：本发明的半浮栅功率器件包括一个半导体基底，该半导体基底上设有氮化镓阻挡层，该氮化镓阻挡层之上设有氮化镓沟道层，该氮化镓沟道层之上设有氮化镓铝隔离层；所述氮化镓铝隔离层之上设有栅介质层，所述栅介质层之上设有浮栅，所述浮栅之上设有层间介质层，所述层间介质层之上设有控制栅，所述控制栅通过电容耦合作用于所述浮栅，所述控制栅的两侧分别设有位于所述氮化镓沟道层之上的源极和漏极；所述浮栅向所述源极一侧延 伸并超出所述栅介质层和氮化镓铝隔离层与所述氮化镓沟道层连接。
第三种结构：本发明的半浮栅功率器件包括一个半导体基底，该半导体基底上设有氮化镓阻挡层，该氮化镓阻挡层之上设有氮化镓沟道层，该氮化镓沟道层之上设有氮化镓铝隔离层；所述氮化镓铝隔离层之上设有栅介质层，所述栅介质层之上设有浮栅，所述浮栅之上设有层间介质层，所述层间介质层之上设有控制栅，所述控制栅通过电容耦合作用于所述浮栅，所述控制栅的两侧分别设有位于所述氮化镓沟道层之上的源极和漏极；所述浮栅通过所述栅介质层和氮化镓铝隔离层中的第一开孔与所述氮化镓沟道层连接。
第四种结构：本发明的半浮栅功率器件包括一个半导体基底，该半导体基底上设有氮化镓阻挡层，该氮化镓阻挡层之上设有氮化镓沟道层，该氮化镓沟道层之上设有氮化镓铝隔离层；所述氮化镓铝隔离层之上设有栅介质层，所述栅介质层之上设有浮栅，所述浮栅之上设有层间介质层，所述层间介质层之上设有控制栅，所述控制栅通过电容耦合作用于所述浮栅，所述控制栅的两侧分别设有位于所述氮化镓沟道层之上的源极和漏极；所述浮栅下方的栅介质层和氮化镓铝隔离层中设有第一开孔，所述第一开口下方的氮化镓沟道层内设有第一凹槽，该第一凹槽的底部位于所述氮化镓沟道层的任意深度内或者延伸至所述氮化镓沟道层的底部，所述浮栅填满所述第一凹槽。
第五种结构：本发明的半浮栅功率器件包括一个半导体基底，该半导体基底上设有氮化镓阻挡层，该氮化镓阻挡层之上设有氮化镓沟道层，该氮化镓沟道层之上设有氮化镓铝隔离层；所述氮化镓铝隔离层之上设有栅介质层，所述栅介质层之上设有浮栅，所述浮栅之上设有层间介质层，所述层间介质层之上设有控制栅，所述控制栅通过电容耦合作用于所述浮栅，所述控制栅的两侧分别设有位于所述氮化镓沟道层之上的源极和漏极；所述浮栅下方的栅介质层和氮化镓铝隔离层中设有第一开孔，所述浮栅下方的氮化镓铝隔离层中还设有第二开孔；所述第一开口和第二开口下方的氮化镓沟道层内分别设有第一凹槽和 第二凹槽，该第一凹槽和第二凹槽的底部位于所述氮化镓沟道层的任意深度内或者延伸至所述氮化镓沟道层的底部，所述第二凹槽靠近所述漏极一侧且其深度与所述第一凹槽的深度相同，所述栅介质层覆盖所述第二凹槽的内表面且将所述第一凹槽暴露出来，所述浮栅填满所述第一凹槽和第二凹槽。
优选的，上述的五种半浮栅功率器件，所述氮化镓阻挡层与氮化镓沟道层之间还可以设有氮化镓铝阻挡层。
优选的，上述的五种半浮栅功率器件，所述浮栅的材质为铬、或者含镍或含钨的合金、或者掺杂的多晶硅；所述层间介质层为氧化硅、氮化硅、氮氧化硅中的一种或几种；所述控制栅为多晶硅控制栅或者金属控制栅。
基于上述第五种结构的半浮栅功率器件的制造方法，包括在提供的半导体基底上依次形成氮化镓阻挡层、氮化镓沟道层和氮化镓铝隔离层；
还包括：
进行光刻和刻蚀，在所述氮化镓沟道层内形成第一凹槽和第二凹槽；
淀积一层栅介质层并进行光刻和刻蚀，在所述栅介质层中形成一个浮栅开口，该浮栅开口将所述第一凹槽暴露出来；
覆盖上述形成的结构淀积第一层导电薄膜；
在所述第一层导电薄膜之上形成第一层绝缘薄膜；
在所述第一层绝缘薄膜之上形成第二层导电薄膜；
进行光刻并依次刻蚀所述第二层导电薄膜、第二层绝缘薄膜和第一层导电薄膜，形成覆盖所述第一凹槽和第二凹槽的浮栅以及位于浮栅之上的层间介质层和控制栅；
在所述控制栅的两侧分别形成于与所述氮化镓铝隔离层或者氮化镓沟道层接触的源极和漏极。
本发明的半浮栅功率器件是工作原理是：将氮化镓高电子迁移率晶体管管的栅极与源极或沟道区通过一个二极管连接，通过二极管钳位，使得氮化镓高 电子迁移率晶体管的栅极成为半浮栅结构，如果氮化镓高电子迁移率晶体管是常开型晶体管，则半浮栅功率器件在初始状态处于导通状态。同时，由于外部电压信号(VCG)通过一个电容器作用于半浮栅之上，当外部电压信号为正电压且器件处于开启状态时，半浮栅内会存入负电荷，使得阈值电压上升，当外部电压信号由正电压变为0V时，半浮栅电压为负(时间为纳秒级)，半浮栅功率器件处于截止状态。当外部电压信号再次由0V变为正电压时，半浮栅功率器件再次处于导通状态。因此通过调节外部电压信号(VCG)的脉冲，可以使半浮栅功率器件不断处于开、关状态，组成开关电源电路或者其他电路。
如果氮化镓高电子迁移率晶体管是常关型晶体管，则半浮栅功率器件在初始状态处于关闭状态。由于外部电压信号(VCG)通过一个电容器作用于半浮栅之上，当外部电压信号为正电压时，半浮栅内会存入负电荷，也会使得器件阈值电压上升，当外部电压信号由正电压变为0V时，半浮栅电压为负(时间为纳秒级)，半浮栅功率器件处于截止状态。当外部电压信号再次由0V变为正电压时，半浮栅功率器件再次处于导通状态。因此通过调节外部电压信号(VCG)的脉冲，可以使半浮栅功率器件不断处于开、关状态，组成开关电源电路或者其他电路。
本发明与现有技术相比其显著优点在于：首先，本发明的半浮栅功率器件采用半浮栅结构,并在半浮栅之上形成控制栅，控制栅通过电容耦合作用于半浮栅，使得一个半浮栅功率器件就可以实现共源共栅连接方式的两个晶体管的功能，简化半导体功率器件的结构。其次，氮化镓高电子迁移率晶体管的栅极与源极或沟道区之间的嵌入式二极管可以钳位，外部电压信号可以通过电容感应控制半浮栅功率器件的瞬间开启，使得半浮栅功率器件适合高压、高速操作并且具有很高的可靠性。最后，这种功率半浮栅器件结构可以提高氮化镓高电子迁移率晶体管在工作状态时的阈值电压，使其能够更好地作为功率开关管使用。
附图说明
图1是现有技术的共源共栅的氮化镓功率开关电路示意图；
图2是本发明提出的半浮栅功率器件的一个实施例的等效电路示意图；
图3-图5是本发明提出的半浮栅功率器件的第一至第三实施例的结构剖面示意图；
图6是本发明如图3-图5所示的第一至第三实施例半浮栅功率器件的一种等效电路图。
图7-图9是本发明提出的半浮栅功率器件的第四至第六实施例的结构剖面示意图；
图10是本发明如图7-图9所示的半浮栅功率器件第四至第六实施例的等效电路图。
图11至图14是本发明的半浮栅功率器件的制造方法的一个实施例的工艺流程图。
具体实施方式
为清楚地说明本发明的具体实施方式，说明书附图中所列示图，放大了本发明所述的层和区域的厚度，且所列图形大小并不代表实际尺寸；附图是示意性的，不应限定本发明的范围。说明书中所列实施例不应仅限于附图中所示区域的特定形状，而是包括所得到的形状如制造引起的偏差等、再如刻蚀得到的曲线通常具有弯曲或圆润的特点，但在本发明实施例中均以矩形表示。同时在下面的描述中，所使用的术语衬底可以理解为包括正在工艺加工中的半导体晶片，可能包括在其上所制备的其它薄膜层。
下面结合附图和实施例对本发明的具体实施方式作进一步详细的说明。
图2是本发明提出的半浮栅功率器件的一个实施例的等效电路示意图。如图2所示，本发明的半浮栅功率器件包括一个氮化镓高电子迁移率晶体管 100，氮化镓高电子迁移率晶体管包括源极101、栅极103和漏极102。氮化镓高电子迁移率晶体管的源极101和栅极103通过一个二极管200连接，使得栅极103成为一个半浮栅结构，即氮化镓高电子迁移率晶体管的栅极103可以作为本发明的半浮栅功率器件的浮栅103。二极管200包括但不局限于为肖特基二极管，且二极管200的阳极与栅极103连接，二极管200的阴极与源极101连接。外部电压信号(VCG)400通过一个电容器300与栅极103连接，从而外部电压信号(VCG)400可以通过电容感应控制氮化镓高电子迁移率晶体管100开启或者关闭。
可选的，本发明的半浮栅功率器件中，二极管200的阴极也可以不与氮化镓高电子迁移率晶体管100的源极连接，而与氮化镓高电子迁移率晶体管100的沟道区连接。
本发明的半浮栅功率器件可以有多种结构，以下描述的是本发明的半浮栅功率器件的优选实施例。
第一实施例
图3是本发明提出的半浮栅功率器件的第一实施例的剖面示意图，如图3所示，本发明的半浮栅功率器件包括半导体基底11和半导体基底11之上的氮化镓阻挡层12，在氮化镓阻挡层12之上还依次形成有氮化镓沟道层14和氮化镓铝隔离层15。在氮化镓铝隔离层15之上形成有栅介质层501，在栅介质层501之上形成有氮化镓高电子迁移率晶体管的栅极(即浮栅)103。在浮栅103的两侧分别形成有氮化镓高电子迁移率晶体管的源极101和漏极102，源极101和漏极102形成于氮化镓铝隔离层15之上。浮栅103向源极101的一侧延伸,浮栅103延伸后超出栅介质层501并与氮化镓铝隔离层15接触，由于浮栅103通常为含铬、或者含镍、或者含钨的合金或者掺杂后的多晶硅，因此浮栅103与氮化镓铝隔离层15形成肖特基二极管，也就是在栅极103和源极101直接形成一个肖特基二极管。通常肖特基二极管的(垂直于纸面)宽度小于有源 区的宽度，这样使得该高电子迁移率器件的沟道区可以有效地连接到源极101。在浮栅103之上形成有层间介质层502，层间介质层502通常为二氧化硅、氮化硅、氧化铪、氧化铝等高介电常数介质或者为它们之间的叠层。在层间介质层502之上形成有控制栅104，控制栅104与外部电压信号400连接、且通过电容耦合作用于浮栅103。
第二实施例
图4是本发明提出的半浮栅功率器件的第二实施例的剖面示意图，与图3所示的半浮栅功率器件相比，图4所示的半浮栅功率器件仅是在氮化镓阻挡层102与氮化镓沟道层104之间设有氮化镓铝阻挡层103，氮化镓铝阻挡层103结构是高电子迁移率晶体管中的常用结构，本发明实施例中不再进行详细描述。
第三实施例
图5是本发明提出的半浮栅功率器件的第三实施例的剖面示意图，与图3所示的半浮栅功率器件相比，图5所示的半浮栅功率器件是刻蚀掉栅介质层501两侧的氮化镓铝隔离层15，使得浮栅103向源极101的一侧延伸,浮栅103延伸后超出栅介质层501和氮化镓铝隔离层15并与氮化镓铝沟道层14接触成肖特基二极管。源极101和漏极102直接形成于氮化镓沟道层14之上。
图6为本发明如图3-图5所示的第一至第三实施例的半浮栅功率器件的一种等效电路图。如图6所示，本发明的半浮栅功率器件包括一个氮化镓高电子迁移率晶体管100，氮化镓高电子迁移率晶体管100的栅极(即本发明的半浮栅功率器件的浮栅)103通过一个肖特基二极管200与源极101连接，从而栅极103为一个半浮栅结构,控制栅400通过电容耦合作用于浮栅103之上。
第四实施例
图7为本发明提出的半浮栅功率器件的第四实施例的剖面示意图，，如图7所示，本发明的半浮栅功率器件包括半导体基底11和半导体基底11之上的 氮化镓阻挡层12，在氮化镓阻挡层12之上还依次形成有氮化镓沟道层14和氮化镓铝隔离层15。在氮化镓铝隔离层15之上形成有栅介质层501，在栅介质层501之上形成有氮化镓高电子迁移率晶体管的栅极(即浮栅)103。在浮栅103的两侧分别形成有氮化镓高电子迁移率晶体管的源极101和漏极102，源极101和漏极102形成于氮化镓铝沟道层14之上。浮栅103通过在栅极介质501和氮化镓铝隔离层15内的第一开孔与氮化镓沟道层14接触，由于浮栅103通常为含铬、或者含镍、或者含钨的合金或者掺杂后的多晶硅，因此浮栅103与氮化镓沟道层14形成肖特基二极管，也就是在浮栅103和沟道区之间形成一个肖特基二极管。通常肖特基二极管的(垂直于纸面)宽度小于有源区的宽度，这样使得该高电子迁移率器件的沟道区可以有效地连接到源极101。在浮栅103之上形成有层间介质层502，层间介质层502通常为二氧化硅、氮化硅、氧化铪、氧化铝等高介电常数介质或者为它们之间的叠层。在层间介质层502之上形成有控制栅104，该控制栅104与外部电压信号400连接、且通过电容耦合作用于浮栅103
第五实施例
图8为本发明的半浮栅功率器件的第五实施例的剖面示意图，它是如图7所示的半浮栅功率器件的一种优化结构，在氮化镓沟道层14内形成有第一凹槽，该凹槽位于栅极介质501和氮化镓铝隔离层15内的第一开口的下方，且该第一凹槽的底部位于氮化镓沟道层14的底部，即该凹槽的底部位于氮化镓阻挡层12的表面，浮栅103填满所述第一凹槽。进一步可选的，第一凹槽的底部可以位于氮化镓沟道层14的任意深度内，通过调整第一凹槽的深度，可以方便的调节浮栅103与氮化镓沟道层14之间的肖特基二极管的导通电压。第一凹槽深度越深，则导通电压越低；反之第一凹槽深度越浅，则导通电压越高。
第六实施例
图9为本发明的半浮栅功率器件的第六实施例的剖面示意图，它是在如图7所示的半浮栅功率器件的基础上，在靠近漏极102一侧的氮化镓沟道层14内形成和所述第一凹槽具有相同深度的第二凹槽，栅介质层501覆盖第二凹槽的表面而将第一凹槽暴露出来，浮栅103同时填满第一凹槽和第二凹槽。
图10展示了图7至图9所示的第四至第六实施例的半浮栅功率器件的等效电路图,其中氮化镓高电子迁移率晶体管100的栅极(即本发明的半浮栅功率器件的浮栅)103通过一个肖特基二极管200与氮化镓高电子迁移率晶体管100的沟道区连接，控制栅400通过电容耦合作用于浮栅103之上。
图11-图14是本发明提出的如图9所示的氮化镓半浮栅功率器件的制造方法的一个实施例的工艺流程图。
首先，如图11所示，在半导体基底11上依次淀积形成氮化镓阻挡层12、氮化镓沟道层14和氮化镓铝隔离层15，之后进行光刻并依次刻蚀氮化镓铝隔离层15和氮化镓沟道层14，在氮化镓沟道层14内形成第一凹槽701和第二凹槽702。
接下来，如图12所示，覆盖上述形成的结构淀积一层栅介质层501并进行光刻和刻蚀，在栅介质层501中形成一个浮栅开口703，该浮栅开口703的开口宽度大于第二凹槽702的开口宽度，从而浮栅开口703将第二凹槽702暴露出来。
接下来，如图13所示，覆盖上述形成的结构依次淀积第一层导电薄膜、第一层绝缘薄膜和第二层导电薄膜，之后进行光刻并依次刻蚀所述第二层导电薄膜、第二层绝缘薄膜和第一层导电薄膜，形成覆盖所述第一凹槽和第二凹槽的浮栅103以及位于浮栅103之上的层间介质层502和控制栅104。
最后，如图14所示，在栅极104的两侧形成栅极侧墙60，之后刻蚀掉暴露出的栅介质层501，然后利用业界所熟知的工艺在控制栅104的两侧分别形成于与氮化镓沟道层14接触的源极101和漏极102。
本发明的具体实施方式中凡未涉到的说明属于本领域的公知技术，可参考公知技术加以实施。
以上具体实施方式及实施例是对本发明提出的半浮栅功率器件技术思想的具体支持，不能以此限定本发明的保护范围，凡是按照本发明提出的技术思想，在本技术方案基础上所做的任何等同变化或等效的改动，均仍属于本发明技术方案保护的范围。

Claims (11)

  1. 一种半浮栅功率器件，包括一个氮化镓高电子迁移率晶体管，其特征在于，还包括：
    一个二极管，该二极管的阳极与所述氮化镓高电子迁移率晶体管的栅极连接，该二极管的阴极与所述氮化镓高电子迁移率晶体管的源极或沟道区连接；
    一个电容器，该电容器的一端与所述氮化镓高电子迁移率晶体管的栅极连接，该电容器的另一端与外部电压信号连接。
  2. 根据权利要求1所述的一种半浮栅功率器件，其特征在于所述二极管为肖特基二极管。
  3. 根据权利要求2所述的一种半浮栅功率器件，其特征在于，所述半浮栅功率器件包括一个半导体基底，该半导体基底上设有氮化镓阻挡层，该氮化镓阻挡层之上设有氮化镓沟道层，该氮化镓沟道层之上设有氮化镓铝隔离层；
    所述氮化镓铝隔离层之上设有栅介质层，所述栅介质层之上设有浮栅，所述浮栅之上设有层间介质层，所述层间介质层之上设有控制栅，所述控制栅通过电容耦合作用于所述浮栅，所述控制栅的两侧分别设有源极和漏极。
  4. 根据权利要求3所述的一种半浮栅功率器件，其特征在于，所述氮化镓阻挡层与氮化镓沟道层之间设有氮化镓铝阻挡层。
  5. 根据权利要求3或4所述的一种半浮栅功率器件，其特征在于，所述浮栅向所述源极一侧延伸并超出所述栅介质层与所述氮化镓铝隔离层连接。
  6. 根据权利要求3或4所述的一种半浮栅功率器件，其特征在于，所述浮栅向所述源极一侧延伸并超出所述栅介质层和氮化镓铝隔离层与氮化镓沟道层连接。
  7. 根据权利要求3或4所述的一种半浮栅功率器件，其特征在于，所述浮栅通过所述栅介质层和氮化镓铝隔离层中的第一开孔与所述氮化镓沟道层连 接。
  8. 根据权利要求7所述的一种半浮栅功率器件，其特征在于，在所述氮化镓沟道层内设有第一凹槽，该第一凹槽位于所述第一开孔下方且该第一凹槽的底部位于所述氮化镓沟道层的任意深度内或者延伸至所述氮化镓沟道层的底部，所述浮栅填满所述第一凹槽。
  9. 根据权利要求8所述的一种半浮栅功率器件，其特征在于，所述氮化镓铝隔离层中设有第二开孔，所述第二开孔下方的氮化镓沟道层内设有第二凹槽，所述第二凹槽靠近所述漏极一侧且其深度与所述第一凹槽的深度相同，所述栅介质层覆盖所述第二凹槽的内表面，所述浮栅填满所述第一凹槽。
  10. 根据权利要求3所述的一种半浮栅功率器件，其特征在于，所述浮栅的材质为铬、或者含镍或含钨的合金、或者掺杂的多晶硅；所述层间介质层为氧化硅、氮化硅、氮氧化硅中的一种或几种；所述控制栅为多晶硅控制栅或者金属控制栅。
  11. 如权利要求9所述的半浮栅功率器件的制造方法，包括在提供的半导体基底上依次形成氮化镓阻挡层、氮化镓沟道层和氮化镓铝隔离层；
    其特征在于还包括：
    进行光刻和刻蚀，在所述氮化镓沟道层内形成第一凹槽和第二凹槽；
    淀积一层栅介质层并进行光刻和刻蚀，在所述栅介质层中形成一个浮栅开口，该浮栅开口将所述第一凹槽暴露出来；
    覆盖上述形成的结构淀积第一层导电薄膜；
    在所述第一层导电薄膜之上形成第一层绝缘薄膜；
    在所述第一层绝缘薄膜之上形成第二层导电薄膜；
    进行光刻并依次刻蚀所述第二层导电薄膜、第二层绝缘薄膜和第一层导电薄膜，形成覆盖所述第一凹槽和第二凹槽的浮栅以及位于浮栅之上的层间介质层和控制栅；
    在所述控制栅的两侧分别形成于与所述氮化镓铝隔离层或者氮化镓沟道层接触的源极和漏极。
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