WO2016019766A1 - 氮化硅薄膜及mim电容的制作方法 - Google Patents

氮化硅薄膜及mim电容的制作方法 Download PDF

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Publication number
WO2016019766A1
WO2016019766A1 PCT/CN2015/082248 CN2015082248W WO2016019766A1 WO 2016019766 A1 WO2016019766 A1 WO 2016019766A1 CN 2015082248 W CN2015082248 W CN 2015082248W WO 2016019766 A1 WO2016019766 A1 WO 2016019766A1
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Prior art keywords
deposition
silicon nitride
nitride film
metal layer
electrode metal
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PCT/CN2015/082248
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English (en)
French (fr)
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雷天飞
秦仁刚
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无锡华润上华半导体有限公司
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Publication of WO2016019766A1 publication Critical patent/WO2016019766A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/0217—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors

Definitions

  • the present invention relates to the field of semiconductor technology, and in particular to a method for fabricating a silicon nitride film and a MIM capacitor.
  • Capacitors are widely used in semiconductor integrated circuits as storage charges, couplings, and filter devices.
  • metal-insulator-metal (MIM) capacitors have become the mainstream in RF integrated circuits, especially in the mixing/RF CMOS process.
  • MIM metal-insulator-metal
  • MIM capacitors are usually located in the upper layer of a multi-layer device structure in an integrated circuit, and their structure is closer to a capacitor of a typical meaning, that is, a capacitor having a dielectric between metal electrode plates.
  • the conventional MIM capacitor includes a lower electrode 101, an upper electrode 103, and an insulating layer 102 between the two plates, and the structure thus formed can realize a charge storage function.
  • This prior art MIM capacitor typically uses a high dielectric constant silicon nitride film to form an insulating layer. The silicon nitride film has a great influence on the electrical properties of the capacitor. If the quality of the formed silicon nitride film is poor, the performance of the capacitor is affected, for example, the leakage current of the capacitor is high.
  • the main disadvantages of the existing 0.18 ⁇ m process MIM capacitors are the lower breakdown voltage and higher leakage.
  • the MIM capacitor fabricated according to the current process has a capacitance leakage of 1 ⁇ A at a voltage of approximately 20V. It is no longer suitable when applied to the 0.18 ⁇ m high pressure process or the BCD process. Therefore, there is a great need for process improvements for silicon nitride films used in the fabrication of 0.18 ⁇ m process MIM capacitors.
  • the pre-deposition having a lower deposition rate
  • the main deposition is performed until a predetermined thickness of the silicon nitride film is reached, which has a higher deposition rate.
  • a method for manufacturing a MIM capacitor comprising:
  • Pre-deposition is performed, the pre-deposition having a lower deposition rate
  • the silicon nitride film and the lower electrode metal layer are etched to form a capacitor insulator and a metal lower electrode.
  • the silicon nitride film deposited by the above method has high compactness and reduces the probability of occurrence of voids in the silicon nitride film.
  • the deposited silicon nitride film has high compactness, reduces the probability of occurrence of a hollow hole of the silicon nitride film, significantly increases the breakdown voltage, and reduces the leakage current, thereby improving the reliability and goodness of the device. rate.
  • FIG. 1 is a schematic diagram of a basic structure of a conventional MIM capacitor
  • FIG. 2 is a flow chart of a method of fabricating a silicon nitride film according to an embodiment
  • FIG. 3 is a flow chart of a method of fabricating a MIM capacitor according to an embodiment
  • FIG. 4 is a graph showing a breakdown voltage curve of a MIM capacitor fabricated using the prior art and a breakdown voltage curve of a MIM capacitor formed according to the method of Embodiment 2 of the present invention.
  • Spatial relationship terms such as “under”, “below”, “below”, “under”, “above”, “above”, etc. This description may be used to describe the relationship of one element or feature shown in the figures to the other elements or features. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and operation in addition to the orientation shown in the figures. For example, if the device in the figures is turned “on” or “below” or “below” or “under” the element or feature is to be “on” the other element or feature. Thus, the exemplary terms “below” and “include” can include both the above and the The device may be otherwise oriented (rotated 90 degrees or other orientation) and the spatial descriptors used herein interpreted accordingly.
  • composition and/or “comprising”, when used in the specification, is used to determine the presence of the features, integers, steps, operations, components and/or components, but does not exclude one or more The presence or addition of features, integers, steps, operations, components, components, and/or groups.
  • the term “and/or” includes any and all combinations of the associated listed items.
  • Embodiment 1 of the present invention introduces a new method for fabricating a silicon nitride film
  • FIG. 2 is a flow chart of a method for fabricating a silicon nitride film according to Embodiment 1 of the present invention, and Embodiment 1 of the present invention is described in detail below with reference to FIG. Introduction.
  • Step 201 providing a substrate.
  • the substrate provided in this embodiment may be a simple silicon substrate, a silicon substrate on which a metal oxide semiconductor transistor has been formed, or a substrate on which an underlying metal wiring structure has been formed.
  • Step 202 depositing a silicon nitride film in two steps by using a plasma enhanced chemical vapor deposition method on the substrate, including:
  • Step 1 Pre-deposition, the pre-deposition having a lower deposition rate.
  • the lower deposition rate is 17 to 19 ⁇ /s.
  • the pre-deposition parameter settings include: temperature of 380 ⁇ 420 ° C, pressure of 3.8 ⁇ 4.6 Torr, nitrogen flow range of about 4500 ⁇ 5500sccm, silane flow range of about 70 ⁇ 90sccm, ammonia flow range of about 60 ⁇ 90sccm
  • the high frequency power range is 430 ⁇ 470W, and the distance between the plates is 560 ⁇ 580mils.
  • Step 2 Perform main deposition until a predetermined thickness of the silicon nitride film is reached, the main deposition having a higher deposition rate.
  • the predetermined thickness of the silicon nitride film has different values for different practical application devices. For example, when the silicon nitride film is applied to the insulating layer of the MIM capacitor device, the thickness may be 300 to 700 angstroms, so The predetermined thickness is not specifically limited.
  • the higher deposition rate is 48 to 52 ⁇ /s.
  • the parameters of the main deposition include: temperature of 380 ⁇ 420 ° C, pressure of 3.8 ⁇ 4.6 Torr, nitrogen flow range of about 4500 ⁇ 5500sccm, silane flow range of about 200 ⁇ 239sccm, ammonia flow range of about 60 ⁇ 90sccm
  • the high frequency power range is 430 ⁇ 470W.
  • a high-density silicon nitride is first deposited using a pre-deposition process having a lower deposition rate, and then a main deposition step is performed until a predetermined thickness of the silicon nitride film is obtained.
  • the high density of the silicon nitride film reduces the probability of occurrence of voids in the silicon nitride film.
  • a substrate is provided.
  • the substrate may be a simple silicon substrate, a silicon substrate on which a metal oxide semiconductor transistor has been formed, or a substrate on which an underlying metal wiring structure has been formed.
  • step 302 a lower electrode metal layer is formed on the substrate.
  • the material of the lower electrode metal layer is selected from an alloy of one or more of metals such as copper, aluminum, gold, silver, tungsten, and the like.
  • the lower electrode metal layer has a thickness of 4000 to 6000 angstroms, for example, 3000 ⁇ , 5000 ⁇ .
  • the lower electrode metal layer may be formed by any method known to those skilled in the art, such as electrochemical plating, magnetron sputtering or physical deposition.
  • step 303 a silicon nitride film is deposited in a two-step process on the lower electrode metal layer by plasma enhanced chemical vapor deposition to serve as a capacitor insulating layer.
  • the silicon nitride film is deposited by a PECVD method.
  • the silicon nitride film has a thickness ranging from 300 to 700 angstroms.
  • the thickness of the deposited film can be determined by the specific MIM capacitance value requirements. For example, for a 1.5FF/ ⁇ m2 MIM capacitor process, the thickness of the silicon nitride film is approximately 420. ⁇ . Dividing the deposition process into two steps includes: step one, performing pre-deposition, the pre-deposition having a lower deposition rate; and step two, performing main deposition until a predetermined thickness of the silicon nitride film is reached, the main deposition having Higher deposition rate.
  • the thickness of the predetermined deposited silicon nitride film is about 350 ⁇ . Then, the deposition method of the silicon nitride film of the present invention is adopted, and the steps thereof include:
  • pre-deposition is performed.
  • the pre-deposition temperature is 380 to 420 ° C, for example 400 ° C.
  • the pressure is 3.8 ⁇ 4.6Torr, for example 4.2 Torr.
  • the deposition rate is controlled at 17 to 19 ⁇ /s, for example 1819 ⁇ /s.
  • the deposition time is 2 ⁇ 4s, for example 3s.
  • the nitrogen flow range is about 4500 to 5500 sccm
  • the silane flow range is about 70 to 90 sccm
  • the ammonia flow range is about 60 to 90 sccm
  • the high frequency power range is 430 to 470 W
  • the plate spacing is 560 to 580 mils.
  • Step 2 Perform main deposition.
  • the main deposition temperature is 380 to 420 ° C and the pressure is 3.8 to 4.6 Torr.
  • the deposition rate is controlled at 48 ⁇ 52 ⁇ /s, for example 50.43 ⁇ /s.
  • the deposition time is 5.5 ⁇ 6.2s, for example 5.9s.
  • the nitrogen flow rate ranges from about 4500 to 5500 sccm
  • the silane flow rate ranges from about 200 to 239 sccm
  • the ammonia gas flow rate ranges from about 60 to 90 sccm
  • the high frequency power range from 430 to 470 W.
  • a high-density silicon nitride is first deposited using a pre-deposition process having a lower deposition rate, and then a main deposition step is performed until a predetermined thickness of the silicon nitride film is obtained.
  • the high density of the silicon nitride film reduces the probability of occurrence of voids in the silicon nitride film.
  • step 304 an upper electrode metal layer is formed on the silicon nitride film.
  • the upper electrode metal layer has a thickness of 750 to 2300 angstroms.
  • the material of the upper electrode metal layer is selected from an alloy of one or more of metals such as copper, aluminum, gold, silver, tungsten, etc., such as copper aluminum alloy.
  • an etching rate may be formed on the capacitive insulating layer to be different from the etching rate of the upper electrode metal layer.
  • a far upper etch stop layer which layer may be formed of a material such as silicon nitride or nitrogen-containing silicon carbide.
  • step 305 the upper electrode metal layer is etched to form a metal upper electrode.
  • a mask pattern of the metal upper electrode is formed on the upper electrode metal layer by photolithography, and the upper electrode metal layer is etched by etching to form a metal upper electrode.
  • step 306 the silicon nitride film and the lower electrode metal layer are etched to form a capacitor insulator and a metal lower electrode.
  • the structure of the MIM capacitor has been basically completed, with the metal upper and lower electrodes and the middle insulating layer. However, after that, it is necessary to make a metal electrical connection structure for the like, and no further description is made here.
  • FIG. 4 is a graph showing a breakdown voltage of a MIM capacitor formed by a method according to Embodiment 2 of the present invention, wherein a curve 401 in the figure is a breakdown voltage curve of a MIM capacitor fabricated by the prior art, and a curve 402 is implemented in the present invention.
  • the breakdown voltage curve of the MIM capacitor obtained in the example can be found to significantly increase the breakdown voltage according to the method of the present invention.
  • the deposited silicon nitride film has high compactness, reduces the probability of occurrence of voids in the silicon nitride film, significantly increases the breakdown voltage, and reduces the leakage current, thereby improving the device. Reliability and yield.

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Abstract

本发明提供一种氮化硅薄膜的制作方法，包括：提供衬底；在所述衬底上采用等离子增强型化学气相沉积法分两步沉积氮化硅薄膜，包括：步骤一、预沉积，所述预沉积具有较低的沉积速率；步骤二、进行主沉积直到达到氮化硅薄膜的预定厚度，所述主沉积具有较高的沉积速率。本发明还提供一种MIM电容的制作方法，其采用上述方法制作氮化硅薄膜作为电容绝缘层。

Description

氮化硅薄膜及MIM电容的制作方法
【技术领域】
本发明涉及半导体技术领域，具体而言涉及氮化硅薄膜及MIM电容的制作方法。
【背景技术】
电容作为存储电荷、耦合以及滤波器件被广泛应用于半导体集成电路中。现有的集成电路电容中，金属-绝缘体-金属型（MIM，Metal-Isolation-Metal）电容逐渐成为射频集成电路中的主流，尤其在混频/射频CMOS制程上的应用已非常普遍。原因在于，其通常制作在金属互连层中，既与集成电路工艺相兼容，又与衬底间距离较远，可以克服许多其他类型的电容具有的寄生电容大、器件性能随频率增大而明显下降的缺点。
MIM电容在集成电路中通常位于多层器件结构的上层，其结构更接近与典型意义的电容，即在金属电极板之间具有电介质的电容。如图1所示，现有的MIM电容包括下电极101、上电极103以及位于两个极板之间的绝缘层102，这样形成的结构能实现电荷存储功能。该现有技术的MIM电容通常采用高介电常数的氮化硅薄膜形成绝缘层。而氮化硅薄膜对电容的电学特性有很大的影响，如果生成的氮化硅薄膜的质量差，则会影响电容的性能，例如使电容的漏电电流较高等。现有的0.18μm工艺的MIM电容的主要缺点表现在电容击穿电压较低以及漏电较大。按照目前工艺制作的MIM电容在大约20V的电压下其电容漏电就达到1μA。当运用到0.18μm高压工艺或BCD工艺时就不再适用。因此，对用于在0.18μm工艺MIM电容制造过程中氮化硅薄膜的工艺改进有很大的需求。
【发明内容】
在发明内容部分中引入了一系列简化形式的概念，这将在具体实施方式部分中进一步详细说明。本发明的发明内容部分并不意味着要试图限定出所要求保护的技术方案的关键特征和必要技术特征，更不意味着试图确定所要求保护的技术方案的保护范围。
有鉴于此，有必要提供一种质量较高的氮化硅薄膜的制作方法，包括：
提供衬底；
在所述衬底上采用等离子增强型化学气相沉积法分两步沉积氮化硅薄膜，包括：
预沉积，所述预沉积具有较低的沉积速率；
进行主沉积直到达到氮化硅薄膜的预定厚度，所述主沉积具有较高的沉积速率。
一种MIM电容的制作方法，包括：
提供衬底；
在所述衬底上形成下电极金属层；
在所述下电极金属层上采用等离子增强型化学气相沉积法分两步沉积氮化硅薄膜，包括：
进行预沉积，所述预沉积具有较低的沉积速率；
进行主沉积直到达到氮化硅薄膜的预定厚度，所述主沉积具有较高的沉积速率；
在所述氮化硅薄膜上形成上电极金属层；
刻蚀所述上电极金属层，形成金属上电极；
刻蚀所述氮化硅薄膜和所述下电极金属层，形成电容绝缘体及金属下电极。
综上所述，采用上述方法沉积的氮化硅薄膜的致密性高，降低了氮化硅薄膜中空洞出现的几率。采用上述制作MIM电容的方法，其沉积的氮化硅薄膜的致密性高，降低了氮化硅薄膜中空洞出现的几率，显著提高击穿电压，并降低漏电电流，进而提高器件的可靠性和良率。
【附图说明】
本发明的下列附图在此作为本发明的一部分用于理解本发明。附图中示出了本发明的实施例及其描述，用来解释本发明的原理。
附图中：
图1为现有MIM电容的基本结构示意图；
图2为根据一实施例的氮化硅薄膜的制作方法的流程图；
图3为根据一实施例的MIM电容的制作方法的流程图;
图4示出了采用现有技术制作的MIM电容的击穿电压曲线和根据本发明实施例二的方法形成的MIM电容的击穿电压曲线图。
【具体实施方式】
在下文的描述中，给出了大量具体的细节以便提供对本发明更为彻底的理解。然而，对于本领域技术人员而言显而易见的是，本发明可以无需一个或多个这些细节而得以实施。在其他的例子中，为了避免与本发明发生混淆，对于本领域公知的一些技术特征未进行描述。
应当理解的是，本发明能够以不同形式实施，而不应当解释为局限于这里提出的实施例。相反地，提供这些实施例将使公开彻底和完全，并且将本发明的范围完全地传递给本领域技术人员。在附图中，为了清楚，层和区的尺寸以及相对尺寸可能被夸大。自始至终相同附图标记表示相同的元件。
应当明白，当元件或层被称为“在...上”、“与...相邻”、“连接到”或“耦合到”其它元件或层时，其可以直接地在其它元件或层上、与之相邻、连接或耦合到其它元件或层，或者可以存在居间的元件或层。相反，当元件被称为“直接在...上”、“与...直接相邻”、“直接连接到”或“直接耦合到”其它元件或层时，则不存在居间的元件或层。应当明白，尽管可使用术语第一、第二、第三等描述各种元件、部件、区、层和/或部分，这些元件、部件、区、层和/或部分不应当被这些术语限制。这些术语仅仅用来区分一个元件、部件、区、层或部分与另一个元件、部件、区、层或部分。因此，在不脱离本发明教导之下，下面讨论的第一元件、部件、区、层或部分可表示为第二元件、部件、区、层或部分。
空间关系术语例如“在...下”、“在...下面”、“下面的”、“在...之下”、“在...之上”、“上面的”等，在这里可为了方便描述而被使用从而描述图中所示的一个元件或特征与其它元件或特征的关系。应当明白，除了图中所示的取向以外，空间关系术语意图还包括使用和操作中的器件的不同取向。例如，如果附图中的器件翻转，然后，描述为“在其它元件下面”或“在其之下”或“在其下”元件或特征将取向为在其它元件或特征“上”。因此，示例性术语“在...下面”和“在...下”可包括上和下两个取向。器件可以另外地取向(旋转90度或其它取向)并且在此使用的空间描述语相应地被解释。
在此使用的术语的目的仅在于描述具体实施例并且不作为本发明的限制。在此使用时，单数形式的“一”、“一个”和“所述/该”也意图包括复数形式，除非上下文清楚指出另外的方式。还应明白术语“组成”和/或“包括”，当在该说明书中使用时，确定所述特征、整数、步骤、操作、元件和/或部件的存在，但不排除一个或更多其它的特征、整数、步骤、操作、元件、部件和/或组的存在或添加。在此使用时，术语“和/或”包括相关所列项目的任何及所有组合。
为了彻底理解本发明，将在下列的描述中提出详细的步骤，以便阐释本发明提出的技术方案。本发明的较佳实施例详细描述如下，然而除了这些详细描述外，本发明还可以具有其他实施方式。
本发明实施例一介绍了一种新的氮化硅薄膜的制作方法，图2为本发明实施例一中氮化硅薄膜制作方法的流程图，下面结合图2对本发明的实施例一进行详细介绍。
步骤201，提供衬底。
本实施例中所提供的衬底可以是单纯的硅衬底，也可以是已形成有金属氧化物半导体晶体管的硅衬底，还可以是已形成底层金属连线结构的衬底。
步骤202，在所述衬底上采用等离子增强型化学气相沉积法分两步沉积氮化硅薄膜，包括：
步骤一、预沉积，所述预沉积具有较低的沉积速率。可选地，所述较低的沉积速率为17~19Å/s。所述预沉积的参数设置包括：温度为380~420℃，压力为3.8~4.6Torr，氮气流量范围约为4500~5500sccm，硅烷流量范围约为70~90sccm，氨气流量范围约为60~90sccm，高频功率范围为430~470W，极板间距范围为560~580mils。
步骤二、进行主沉积直到达到氮化硅薄膜的预定厚度，所述主沉积具有较高的沉积速率。所述氮化硅薄膜的预定厚度对于不同的实际应用器件具有不同的数值，例如，当氮化硅薄膜应用于MIM电容器件的绝缘层时，其厚度可以为300至700埃，故在此对其预定厚度不做具体限制。可选地，所述较高的沉积速率为48~52Å/s。所述主沉积的参数设置包括：温度为380~420℃，压力为3.8~4.6Torr，氮气流量范围约为4500~5500sccm，硅烷流量范围约为200~239sccm，氨气流量范围约为60~90sccm，高频功率范围为430~470W。
根据上述沉积氮化硅薄膜的方法，首先使用具有较低沉积速率的预沉积工艺，沉积一层致密性高的氮化硅，之后再进行主沉积步骤直到达到氮化硅薄膜的预定厚度，得到的氮化硅薄膜的致密性高，降低了氮化硅薄膜中空洞出现的几率。
下面结合图3对本发明实施例二的MIM电容的制作方法进行描述。
首先，步骤301，提供衬底。所述衬底可以是单纯的硅衬底，也可以是已形成有金属氧化物半导体晶体管的硅衬底，还可以是已形成底层金属连线结构的衬底。
接着，步骤302，在所述衬底上形成下电极金属层。
可选地，所述下电极金属层的材料选自铜、铝、金、银、钨等金属中的一种或几种的合金。下电极金属层的厚度为4000至6000埃，例如3000Å、5000Å。可采用本领域技术人员熟知的任何方法形成所述下电极金属层，例如电化学镀，磁控溅射或物理沉积等方法。
接着，步骤303，在所述下电极金属层上采用等离子增强型化学气相沉积法分两步沉积氮化硅薄膜，用作电容绝缘层。
在本实施例中，采用PECVD方法沉积所述氮化硅薄膜。可选地，所述氮化硅薄膜的厚度范围为300~700埃。所沉积的薄膜的厚度可以由具体的MIM电容值需求决定。例如，对于1.5fF/μm2的MIM电容工艺，氮化硅薄膜的厚度大约为420 Å。将所述沉积过程分为两步包括：步骤一、进行预沉积，所述预沉积具有较低的沉积速率；步骤二、进行主沉积直到达到氮化硅薄膜的预定厚度，所述主沉积具有较高的沉积速率。
在一个示例中，预定沉积氮化硅薄膜的厚度约为350 Å。则采用本发明的氮化硅薄膜的沉积方法，其步骤包括：
步骤一，进行预沉积。可选地，所述预沉积的温度为380~420℃，例如400℃。压力为3.8~4.6Torr，例如4.2 Torr。沉积速率控制在17~19Å/s，例如1819Å/s。沉积时间2~4s，例如3s。氮气流量范围约为4500~5500sccm，硅烷流量范围约为70~90sccm，氨气流量范围约为60~90sccm，高频功率范围为430~470W，极板间距范围为560~580mils。
步骤二、进行主沉积。所述主沉积的温度为380~420℃，压力为3.8~4.6Torr。沉积速率控制在48~52Å/s，例如50.43 Å/s。沉积时间5.5~6.2s，例如5.9s。氮气流量范围约为4500~5500sccm，硅烷流量范围约为200~239sccm，氨气流量范围约为60~90sccm，高频功率范围为430~470W。
根据上述沉积氮化硅薄膜的方法，首先使用具有较低沉积速率的预沉积工艺，沉积一层致密性高的氮化硅，之后再进行主沉积步骤直到达到氮化硅薄膜的预定厚度，得到的氮化硅薄膜的致密性高，降低了氮化硅薄膜中空洞出现的几率。
接着，步骤304，在所述氮化硅薄膜上形成上电极金属层。
可选地，所述上电极金属层的厚度为750至2300埃。所述上电极金属层的材料选自铜、铝、金、银、钨等金属中的一种或几种的合金，例如铜铝合金。
为了确保在刻蚀该上电极金属层时不损伤下层结构，在本发明的其它实施例中，还可以在电容绝缘层之上形成一层刻蚀速率与上电极金属层的刻蚀速率相差较远的上层刻蚀停止层，该层可以由氮化硅或含氮的碳化硅等材料形成。
接着，步骤305，刻蚀所述上电极金属层，形成金属上电极。
先利用光刻技术在上电极金属层上形成金属上电极的掩膜图形，再利用刻蚀的方法对该上电极金属层进行刻蚀，形成了金属上电极。
接着，步骤306，刻蚀所述氮化硅薄膜和所述下电极金属层，形成电容绝缘体及金属下电极。
至此，MIM电容的结构已基本完成，具有了金属上、下电极和中间的绝缘层。不过，在此之后还需要为其制作金属电连线结构等，在此不做赘述。
图4示出了根据本发明实施例二的方法形成的MIM电容的击穿电压曲线图，其中图中曲线401为采用现有技术制作的MIM电容的击穿电压曲线，曲线402为本发明实施例所获得MIM电容的击穿电压曲线，对比可发现，根据本发明的方法，其击穿电压显著提高。
综上所述，根据本发明实施例的方法，沉积的氮化硅薄膜的致密性高，降低了氮化硅薄膜中空洞出现的几率，显著提高击穿电压，并降低漏电电流，进而提高器件的可靠性和良率。
本发明已经通过上述实施例进行了说明，但应当理解的是，上述实施例只是用于举例和说明的目的，而非意在将本发明限制于所描述的实施例范围内。此外本领域技术人员可以理解的是，本发明并不局限于上述实施例，根据本发明的教导还可以做出更多种的变型和修改，这些变型和修改均落在本发明所要求保护的范围以内。本发明的保护范围由附属的权利要求书及其等效范围所界定。

Claims (9)

  1. 一种氮化硅薄膜的制作方法，包括：
    提供衬底；
    在所述衬底上采用等离子增强型化学气相沉积法分两步沉积氮化硅薄膜，包括：
    进行预沉积，所述预沉积具有较低的沉积速率；及
    进行主沉积直到达到氮化硅薄膜的预定厚度，所述主沉积具有较高的沉积速率。
  2. 根据权利要求1所述的方法，其特征在于，所述较低的沉积速率为17~19Å/s。
  3. 根据权利要求1所述的方法，其特征在于，所述较高的沉积速率为48~52Å/s。
  4. 根据权利要求1所述的方法，其特征在于，所述预沉积的参数设置为：温度为380~420℃，压力为3.8~4.6Torr，氮气流量范围为4500~5500sccm，硅烷流量范围为70~90sccm，氨气流量范围为60~90sccm，高频功率范围为430~470W，极板间距范围为560~580mils。
  5. 根据权利要求1所述的方法，其特征在于，所述主沉积的参数设置为：温度为380~420℃，压力为3.8~4.6Torr，氮气流量范围为4500~5500sccm，硅烷流量范围为200~239sccm，氨气流量范围为60~90sccm，高频功率范围为430~470W。
  6. 一种MIM电容的制作方法，其特征在于，包括：
    提供衬底；
    在所述衬底上形成下电极金属层；
    在所述下电极金属层上采用等离子增强型化学气相沉积法分两步沉积氮化硅薄膜，包括：
    进行预沉积，所述预沉积具有较低的沉积速率；
    进行主沉积直到达到氮化硅薄膜的预定厚度，所述主沉积具有较高的沉积速率；
    在所述氮化硅薄膜上形成上电极金属层；
    刻蚀所述上电极金属层，形成金属上电极；
    刻蚀所述氮化硅薄膜和所述下电极金属层，形成电容绝缘体及金属下电极。
  7. 根据权利要求6所述的方法，其特征在于，所述氮化硅薄膜的厚度范围为300~700埃。
  8. 根据权利要求6所述的方法，其特征在于，所述下电极金属层的厚度为4000~6000埃，所述上电极金属层的厚度为750~2300埃。
  9. 根据权利要求6所述的方法，其特征在于，所述上电极金属层和所述下电极金属层的材料选自铜、铝、金、银、钨中的一种或几种的合金。
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