WO2016019652A1 - 薄膜晶体管及其制备方法、阵列基板和显示装置 - Google Patents

薄膜晶体管及其制备方法、阵列基板和显示装置 Download PDF

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WO2016019652A1
WO2016019652A1 PCT/CN2014/091883 CN2014091883W WO2016019652A1 WO 2016019652 A1 WO2016019652 A1 WO 2016019652A1 CN 2014091883 W CN2014091883 W CN 2014091883W WO 2016019652 A1 WO2016019652 A1 WO 2016019652A1
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insulating layer
gate insulating
active region
film transistor
forming
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PCT/CN2014/091883
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English (en)
French (fr)
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姜春生
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京东方科技集团股份有限公司
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Priority to US14/762,076 priority Critical patent/US9640553B2/en
Priority to EP14882168.9A priority patent/EP3179516B1/en
Publication of WO2016019652A1 publication Critical patent/WO2016019652A1/zh

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    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
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    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
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    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
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    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4908—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET for thin film semiconductor, e.g. gate of TFT
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
    • H01L2029/42388—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor characterised by the shape of the insulating material

Definitions

  • Embodiments of the present invention relate to a thin film transistor, a method of fabricating the same, an array substrate, and a display device.
  • Thin film transistors have been widely used in flat panel display devices due to their good switching characteristics.
  • the thin film transistor includes a gate, an active region, a source and a drain, and the source and the drain are respectively disposed at both ends of the active region and are respectively in contact with the active region. For example, when the gate voltage is above its threshold voltage, the source and drain are turned on through the active region, and carriers flow from the source to the drain or from the drain to the source.
  • the active region of the thin film transistor can be made of ZnON (zinc oxynitride) material.
  • ZnON zinc oxynitride
  • the ZnON material has high mobility in the process of conduction, and the nitrogen vacancy has a high mobility, which can greatly improve the film.
  • the conductivity of the transistor since the ZnON material is inexpensive compared to the IGZO (indium gallium zinc oxide) material, the use of the ZnON material in the active region can greatly reduce the fabrication cost of the thin film transistor.
  • the active region may move the nitrogen element into the adjacent gate insulating layer or the passivation layer due to the diffusion effect, thereby reducing the mobility of the nitrogen vacancies in the active region, resulting in a subthreshold of the thin film transistor.
  • the swing increases, and the increase in the subthreshold swing can seriously affect the semiconductor characteristics of the thin film transistor.
  • Embodiments of the present invention provide a thin film transistor, a method of fabricating the same, an array substrate, and a display device.
  • the method for fabricating a thin film transistor of the embodiment of the present invention improves the content of nitrogen in the gate insulating layer by controlling the material for forming the gate insulating layer while forming the gate insulating layer, thereby enabling the thin film transistor to be in operation.
  • the gate insulating layer can continuously supplement the active region with nitrogen, the mobility of the nitrogen vacancies in the active region is greatly improved, thereby reducing the thin film transistor.
  • the subthreshold swing increases the semiconductor characteristics of the thin film transistor.
  • At least one embodiment of the present invention provides a method of fabricating a thin film transistor including forming a gate, a gate insulating layer, an active region, a source, and a drain on a base substrate, the active region being formed of a ZnON material, The material forming the gate insulating layer is subjected to a control process while forming the gate insulating layer such that the subthreshold swing of the thin film transistor is ⁇ 0.5 mV/dec.
  • the gate insulating layer includes a first gate insulating layer and a second gate insulating layer, and the second gate insulating layer is formed between the first gate insulating layer and the active region.
  • controlling the material forming the gate insulating layer while forming the gate insulating layer may include: 140 to 180 sccm according to SiN x , 1 2 2 to 2 250 sccm for N 2 (nitrogen), and NH 3 (ammonia) Providing gas SiN x , N 2 and NH 3 for a gas volume flow of 700 to 900 sccm to deposit the first gate insulating layer;
  • the thickness of the first gate insulating layer may be The thickness of the second gate insulating layer may be
  • controlling the material forming the gate insulating layer while forming the gate insulating layer may include: using SiH 4 (silane) and NH 3 and following a gas volume of SiH 4 :NH 3 ⁇ 1:90 The flow ratio is deposited to form the gate insulating layer.
  • controlling the material forming the gate insulating layer while forming the gate insulating layer may include: first, according to SiN x of 140 to 180 sccm, N 2 of 1750 to 2250 sccm, and NH 3 of 700 to 900 sccm.
  • the gas volume flow provides gases SiN x , N 2 and NH 3 for deposition to form the gate insulating layer, wherein X ranges from 1 to 4/3; then, NH 3 is ionized and nitrogen is generated after ionization Ions are bombarded onto the surface of the gate insulating layer facing the active region.
  • the thickness of the gate insulating layer may be
  • the active region and before forming the source and the drain may further include forming an etch barrier layer in the etch barrier layer and corresponding to the active region Forming a first via and a second via, respectively, the source is connected to the active region through the first via, and the drain passes through the second via and the active region connection.
  • the active region is formed over the gate, or the gate is formed in the Above the source area.
  • Another embodiment of the present invention also provides a thin film transistor fabricated using any of the above fabrication methods.
  • Another embodiment of the present invention also provides an array substrate including any of the above thin film transistors.
  • Another embodiment of the present invention also provides a display device including any of the above array substrates.
  • Embodiment 1 is a step of forming a gate in Embodiment 1 of the present invention.
  • Embodiment 2 is a step of forming a first gate insulating layer in Embodiment 1 of the present invention
  • Embodiment 3 is a step of forming a second gate insulating layer in Embodiment 1 of the present invention.
  • Embodiment 4 is a step of forming an active region in Embodiment 1 of the present invention.
  • FIG. 5 is a step of forming an etch barrier layer, a first via hole, and a second via hole in Embodiment 1 of the present invention
  • Figure 6 is a view showing the steps of forming a source and a drain in Embodiment 1 of the present invention.
  • This embodiment provides a method for fabricating a thin film transistor, as shown in FIGS. 1-6, including a substrate.
  • a gate electrode 2, a gate insulating layer 3, an active region 4, a source 5 and a drain electrode 6 are formed on the substrate 1.
  • the active region 4 is formed of a ZnON material, and the gate insulating layer 3 is formed while forming the gate insulating layer 3.
  • the material is subjected to control processing such that when the thin film transistor is in operation, the gate insulating layer 3 can continuously supplement the active region 4 with nitrogen to make the subthreshold swing of the thin film transistor ⁇ 0.5 mV/dec.
  • the subthreshold swing is the slope of this portion of the curve from the off state (off state) to the on state (on state) in the semiconductor output characteristic curve.
  • the operating state of the thin film transistor means that the thin film transistor is in a linear state and a saturated state.
  • the active region 4 is formed over the gate electrode 2, and the gate electrode 2, the gate insulating layer 3, the active region 4, the source electrode 5, and the drain electrode 6 are sequentially formed on the base substrate 1, that is,
  • the thin film transistor in this embodiment has a bottom gate type structure.
  • the gate 2, the active region 4, the source 5, and the drain 6 may be formed using a conventional patterning process, which will not be described in detail herein.
  • the gate insulating layer 3 may include a first gate insulating layer 31 and a second gate insulating layer 32, and the second gate insulating layer 32 is formed between the first gate insulating layer 31 and the active region 4;
  • the material forming the gate insulating layer 3 is subjected to control processing while forming the gate insulating layer 3.
  • An example of this control processing method is as follows.
  • SiN x , N 2 and NH 3 Providing gas SiN x , N 2 and NH 3 according to a gas volume flow rate of SiN x of 140 to 180 sccm, N 2 of 1750 to 2250 sccm, and NH 3 of 700 to 900 sccm to deposit a first gate insulating layer 31; according to SiN x 140 to 180 sccm, N 2 is ⁇ 3500 sccm, and NH 3 is a gas volume flow rate of ⁇ 1400 sccm to supply gases SiN x , N 2 and NH 3 to deposit a second gate insulating layer 32.
  • the value of X ranges from 1 to 4/3.
  • the first gate insulating layer 31 and the second gate insulating layer 32 are formed by a chemical vapor deposition method.
  • the method comprises: filling a N 2 and NH 3 according to the volume flow rate of the gas in a chemical vapor deposition chamber, and then filling the SiN x , N 2 and NH 3 according to the volume flow rate of the gas in the deposition atmosphere to deposit a SiN x layer; Finally, the first gate insulating layer 31 and the second gate insulating layer 32 having different nitrogen element contents are formed.
  • the nitrogen atoms in the second gate insulating layer 32 when the thin film transistor is in operation The element can be continuously replenished into the active region 4 and in an active conductive position in the active region 4.
  • the nitrogen element in the effective conductive position can further increase the mobility of the nitrogen vacancies in the active region 4, that is, further increase the mobility of the carriers in the active region 4, thereby reducing the subthreshold swing of the thin film transistor, thereby further The semiconductor characteristics of the thin film transistor are improved.
  • the effective conductive position refers to the position of the effective vacancy in the active region 4 of the ZnON material.
  • the nitrogen element in the effective vacancy position can quickly drive away from the effective vacancy position, so that the position of the effective vacancy is released, so that the active region 4 can quickly realize the half space.
  • the bit is electrically conductive. This enables the thin film transistor to achieve fast turn-on under energization, ie, rapidly transitioning from an off state to an on state. This not only reduces the subthreshold swing of the thin film transistor, but also enhances the semiconductor characteristics of the thin film transistor.
  • the thickness of the first gate insulating layer 31 may range
  • the thickness of the second gate insulating layer 32 may range Provided in this way, not only the gate insulating layer 3 between the gate electrode 2 and the active region 4 is well insulated, but also the gate insulating layer 3 is continuously extended to the active region when the thin film transistor is in operation. 4 supplement nitrogen.
  • the formation of the etch stop layer 7 may be further included.
  • a first via 8 and a second via 9 are formed in the etch barrier layer 7 and corresponding to both ends of the active region 4, respectively.
  • the source 5 is connected to the active region 4 through the first via 8
  • the drain 6 is connected to the active region 4 through the second via 9.
  • the etch stop layer 7 is capable of protecting the active region 4 from etching damage when etching forms the source 5 and the drain 6.
  • an etch stop layer may not be formed between the active region 4 and the source 5 and the drain 6 as long as it is ensured that the active region 4 is not caused when the source 5 and the drain 6 are formed by etching. The etching can be damaged.
  • the present embodiment provides a method for fabricating a thin film transistor.
  • the control treatment of the material for forming the gate insulating layer while forming the gate insulating layer includes: using SiH 4 and NH 3 , and according to SiH 4 : A gas volume flow ratio of NH 3 ⁇ 1:90 is deposited to form a gate insulating layer.
  • the thickness of the gate insulating layer may be
  • the conventional gate insulating layer is usually formed by depositing a gas volume flow ratio of SiH 4 and NH 3 of 1:30, the gas volume flow ratio of SiH 4 and NH 3 in this embodiment can make the nitrogen in the gate insulating layer formed.
  • the element content is greatly increased.
  • the nitrogen element in the gate insulating layer can be continuously replenished into the active region and in an active conductive region in the active region.
  • the nitrogen element in the effective conductive position greatly increases the mobility of nitrogen vacancies in the active region, which greatly increases the mobility of carriers in the active region, thereby reducing the subthreshold swing of the thin film transistor and improving the film.
  • the semiconductor properties of the transistor is usually formed by depositing a gas volume flow ratio of SiH 4 and NH 3 of 1:30, the gas volume flow ratio of SiH 4 and NH 3 in this embodiment can make the nitrogen in the gate insulating layer formed.
  • the element content is greatly increased.
  • the nitrogen element in the gate insulating layer can be continuously replenished into the active region and in
  • the present embodiment provides a method of fabricating a thin film transistor, which is different from Embodiment 1-2 in that a control process for forming a material of the gate insulating layer while forming a gate insulating layer is as follows.
  • gas SiN x of 140 to 180 sccm, N 2 of 1750 to 2250 sccm, and NH 3 of 700 to 900 sccm
  • gas SiN x , N 2 and NH 3 are supplied to deposit a gate insulating layer, wherein X is taken.
  • the value ranges from 1 to 4/3; then, NH 3 is ionized and the nitrogen ions generated after ionization are bombarded to the surface of the gate insulating layer facing the active region.
  • the amount of nitrogen ions bombarded to the surface of the gate insulating layer can reach 10 15 /cm 2 or more, which can greatly increase the content of nitrogen elements in the gate insulating layer.
  • the nitrogen element in the gate insulating layer can be continuously replenished into the active region and in an effective conductive position in the active region.
  • the nitrogen element in the effective conductive position greatly increases the mobility of nitrogen vacancies in the active region, that is, the mobility of carriers in the active region is greatly improved, thereby reducing the subthreshold swing of the thin film transistor.
  • the semiconductor characteristics of the thin film transistor are improved.
  • the present embodiment provides a method for fabricating a thin film transistor.
  • the difference from the embodiment 1-3 is that the gate is formed over the active region, that is, the thin film transistor in this embodiment has a top gate structure.
  • the content of nitrogen element in the gate insulating layer is greatly improved by controlling the material for forming the gate insulating layer while forming the gate insulating layer.
  • the nitrogen element greatly increases the mobility of nitrogen vacancies in the active region, which greatly increases the mobility of carriers in the active region, thereby reducing the subthreshold swing of the thin film transistor and improving the semiconductor characteristics of the thin film transistor.
  • the present embodiment provides a thin film transistor which is fabricated by the preparation method of any of Embodiments 1-4.
  • the thin film transistor fabricated by the preparation method of any of Embodiments 1 to 4 has a subthreshold swing of ⁇ 0.5 mV/dec, and the subthreshold swing is greatly reduced and the semiconductor characteristics are also obtained as compared with the conventional thin film transistor. Great improvement.
  • This embodiment provides an array substrate including any of the thin film transistors described in Embodiment 5.
  • the performance of the array substrate is further improved.
  • This embodiment provides a display device including any of the array substrates described in Embodiment 6.
  • the performance of the display device is further improved.
  • the display device provided by the embodiment of the present invention may be any product or component having a display function such as a liquid crystal panel, a liquid crystal television, a display, an OLED panel, an OLED television, a mobile phone, a navigator, a watch, or the like.
  • a display function such as a liquid crystal panel, a liquid crystal television, a display, an OLED panel, an OLED television, a mobile phone, a navigator, a watch, or the like.
  • the display device provided by the embodiment of the present invention further improves the performance of the display device by using any of the above array substrates.

Abstract

一种薄膜晶体管及其制备方法、阵列基板和显示装置。该薄膜晶体管的制备方法包括在衬底基板(1)上形成栅极(2)、栅绝缘层(3)、有源区(4)、源极(5)和漏极(6)，有源区(4)采用ZnON材料形成，在形成栅绝缘层(3)的同时对形成栅绝缘层(3)的材料进行控制处理，以使薄膜晶体管的亚阈值摆幅≤0.5mV/dec。该制备方法降低了薄膜晶体管的亚阈值摆幅，提升了薄膜晶体管的半导体特性。

Description

薄膜晶体管及其制备方法、阵列基板和显示装置 技术领域
本发明的实施例涉及一种薄膜晶体管及其制备方法、阵列基板和显示装置。
背景技术
薄膜晶体管(TFT)由于其良好的开关特性，目前已广泛应用于平板显示装置。通常，薄膜晶体管包括栅极、有源区、源极和漏极，源极和漏极分设于有源区的两端且分别与有源区接触。例如，当栅极电压高于其阈值电压时，源极和漏极通过有源区导通，载流子从源极流向漏极或者从漏极流向源极。
薄膜晶体管的有源区可以采用ZnON(锌氮氧化物)材料，相对于IGZO(铟镓锌氧化物)，ZnON材料在导电过程中，其中的氮空位具有较高的迁移率，能够大大提高薄膜晶体管的导电性能。另外，由于ZnON材料相对于IGZO(铟镓锌氧化物)材料价格低廉，所以有源区采用ZnON材料能够大大降低薄膜晶体管的制备成本。
但是，形成有源区的ZnON材料中氮元素含量不同会导致不同的迁移率，而且在薄膜晶体管的导通过程中以及在显示装置的显示基板(如阵列基板)的ITO(铟锡氧化物)的退火过程中，有源区会因为扩散效应导致其中的氮元素移动到相邻的栅绝缘层或钝化层中，从而降低了有源区中氮空位的迁移率，导致薄膜晶体管的亚阈值摆幅增大，而亚阈值摆幅的增大会严重影响薄膜晶体管的半导体特性。
发明内容
本发明的实施例提供了一种薄膜晶体管及其制备方法、阵列基板和显示装置。本发明实施例的薄膜晶体管的制备方法通过在形成栅绝缘层的同时对形成栅绝缘层的材料进行控制处理，使栅绝缘层中的氮元素含量大大提高，由此使得在薄膜晶体管处于工作状态时，栅绝缘层能持续地向有源区中补充氮元素，从而大大提高了有源区中氮空位的迁移率，进而降低了薄膜晶体管 的亚阈值摆幅，提升了薄膜晶体管的半导体特性。
本发明的至少一个实施例提供一种薄膜晶体管的制备方法，包括在衬底基板上形成栅极、栅绝缘层、有源区、源极和漏极，所述有源区采用ZnON材料形成，在形成所述栅绝缘层的同时对形成所述栅绝缘层的材料进行控制处理，以使所述薄膜晶体管的亚阈值摆幅≤0.5mV/dec。
例如，所述栅绝缘层包括第一栅绝缘层和第二栅绝缘层，所述第二栅绝缘层形成于所述第一栅绝缘层与所述有源区之间。
例如，在形成所述栅绝缘层的同时对形成所述栅绝缘层的材料进行控制处理可以包括：按照SiNx为140～180sccm，N2(氮气)为1750～2250sccm，NH3(氨气)为700～900sccm的气体体积流量提供气体SiNx、N2和NH3，以沉积形成所述第一栅绝缘层；
按照SiNx为140～180sccm，N2为≥3500sccm，NH3为≥1400sccm的气体体积流量提供气体SiNx、N2和NH3，以沉积形成所述第二栅绝缘层，其中，X的取值范围为1～4/3。
例如，所述第一栅绝缘层的厚度范围可以为
Figure PCTCN2014091883-appb-000001
所述第二栅绝缘层的厚度范围可以为
Figure PCTCN2014091883-appb-000002
例如，在形成所述栅绝缘层的同时对形成所述栅绝缘层的材料进行控制处理可以包括：采用SiH4(硅烷)和NH3，并按照SiH4：NH3≤1：90的气体体积流量比沉积形成所述栅绝缘层。
例如，在形成所述栅绝缘层的同时对形成所述栅绝缘层的材料进行控制处理可以包括：首先，按照SiNx为140～180sccm，N2为1750～2250sccm，NH3为700～900sccm的气体体积流量提供气体SiNx、N2和NH3，以沉积形成所述栅绝缘层，其中，X的取值范围为1～4/3；然后，将NH3电离并将电离后产生的氮离子轰击到所述栅绝缘层的朝向所述有源区的表面。
例如，所述栅绝缘层的厚度范围可以为
Figure PCTCN2014091883-appb-000003
例如，在形成所述有源区之后并在形成所述源极和所述漏极之前，还可可以包括形成刻蚀阻挡层，在所述刻蚀阻挡层中并对应所述有源区的两端分别形成第一过孔和第二过孔，所述源极通过所述第一过孔与所述有源区连接，所述漏极通过所述第二过孔与所述有源区连接。
例如，所述有源区形成于所述栅极上方，或者，所述栅极形成于所述有 源区上方。
本发明的另一个实施例还提供一种薄膜晶体管，所述薄膜晶体管采用任一上述制备方法制成。
本发明的另一个实施例还提供一种阵列基板，其包括任一上述薄膜晶体管。
本发明的另一个实施例还提供一种显示装置，其包括任一上述阵列基板。
附图说明
为了更清楚地说明本发明实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本发明的一些实施例，而非对本发明的限制。
图1为本发明实施例1中形成栅极的步骤；
图2为本发明实施例1中形成第一栅绝缘层的步骤；
图3为本发明实施例1中形成第二栅绝缘层的步骤；
图4为本发明实施例1中形成有源区的步骤；
图5为本发明实施例1中形成刻蚀阻挡层、第一过孔和第二过孔的步骤；
图6为本发明实施例1中形成源极和漏极的步骤。
附图标记：
1.衬底基板；2.栅极；3.栅绝缘层；31.第一栅绝缘层；32.第二栅绝缘层；4.有源区；5.源极；6.漏极；7.刻蚀阻挡层；8.第一过孔；9.第二过孔。
具体实施方式
为使本领域的技术人员更好地理解本发明的技术方案，下面结合附图和具体实施方式对本发明所提供的一种薄膜晶体管及其制备方法、阵列基板和显示装置作进一步详细描述。显然，所描述的实施例是本发明的一部分实施例，而不是全部的实施例。基于所描述的本发明的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本发明保护的范围。
实施例1
本实施例提供一种薄膜晶体管的制备方法，如图1-6所示，包括在衬底 基板1上形成栅极2、栅绝缘层3、有源区4、源极5和漏极6，有源区4采用ZnON材料形成，在形成栅绝缘层3的同时对形成栅绝缘层3的材料进行控制处理，使得薄膜晶体管处于工作状态时，栅绝缘层3能持续地向有源区4中补充氮元素，以使薄膜晶体管的亚阈值摆幅≤0.5mV/dec。
亚阈值摆幅为半导体输出特性曲线中从关态(截止状态)到开态(导通状态)的这部分曲线的斜率。该斜率越小，表示薄膜晶体管从关态到开态的响应速度越快，相应地亚阈值摆幅特性越好，薄膜晶体管的性能也越好；该斜率越大，表示薄膜晶体管从关态到开态的响应速度越慢，相应地亚阈值摆幅特性较差，薄膜晶体管的性能也较差。
需要说明的是，薄膜晶体管的工作状态指薄膜晶体管处于线性状态和饱和状态。
例如，本实施例中，有源区4形成于栅极2上方，且栅极2、栅绝缘层3、有源区4、源极5和漏极6依次形成在衬底基板1上，即本实施例中的薄膜晶体管为底栅型结构。例如，栅极2、有源区4、源极5和漏极6可以采用传统的构图工艺形成，这里不再详述。
例如，本实施例中，栅绝缘层3可以包括第一栅绝缘层31和第二栅绝缘层32，第二栅绝缘层32形成于第一栅绝缘层31与有源区4之间；在形成栅绝缘层3的同时对形成栅绝缘层3的材料进行控制处理。该控制处理方法的一个示例如下所述。
按照SiNx为140～180sccm，N2为1750～2250sccm，NH3为700～900sccm的气体体积流量提供气体SiNx、N2和NH3，以沉积形成第一栅绝缘层31；按照SiNx为140～180sccm，N2为≥3500sccm，NH3为≥1400sccm的气体体积流量提供气体SiNx、N2和NH3，以沉积形成第二栅绝缘层32。这里，X的取值范围为1～4/3。
例如，第一栅绝缘层31和第二栅绝缘层32采用化学气相沉积方法形成。该方法包括：在化学气相沉积室内，先按照上述气体体积流量充入N2和NH3，然后在该沉积氛围中按上述气体体积流量充入SiNx、N2和NH3以沉积SiNx层，最终形成氮元素含量不同的第一栅绝缘层31和第二栅绝缘层32。
由于第二栅绝缘层32紧贴有源区4，而且第二栅绝缘层32中氮元素含量相对较高，所以当薄膜晶体管处于工作状态时，第二栅绝缘层32中的氮元 素能够持续地补充至有源区4中，并在有源区4中处于有效导电位置。处于有效导电位置的氮元素能够进一步提高有源区4中氮空位的迁移率，也即进一步提高了有源区4中载流子的迁移率，从而降低了薄膜晶体管的亚阈值摆幅，进而提升了薄膜晶体管的半导体特性。
需要说明的是，有效导电位置指ZnON材料的有源区4中有效空位的位置。当薄膜晶体管通电时，在栅极电场的作用下，处于有效空位位置的氮元素能够快速驱离该有效空位的位置，使有效空位的位置被让出来，从而使有源区4能够快速实现半空位导电。这使得薄膜晶体管在通电的情况下能够实现快速导通，即快速地从关态发展到开态。这不仅降低了薄膜晶体管的亚阈值摆幅，同时还提升了薄膜晶体管的半导体特性。
例如，第一栅绝缘层31的厚度范围可以为
Figure PCTCN2014091883-appb-000004
第二栅绝缘层32的厚度范围可以为
Figure PCTCN2014091883-appb-000005
如此设置，不仅使位于栅极2和有源区4之间的栅绝缘层3起到很好的绝缘作用，而且在薄膜晶体管处于工作状态时，能使栅绝缘层3持续地向有源区4中补充氮元素。
例如，本实施例中，在形成有源区4之后、并在形成源极5和漏极6之前，还可包括形成刻蚀阻挡层7。在刻蚀阻挡层7中并对应有源区4的两端分别形成第一过孔8和第二过孔9。源极5通过第一过孔8与有源区4连接，漏极6通过第二过孔9与有源区4连接。刻蚀阻挡层7能够在刻蚀形成源极5和漏极6时保护有源区4免受刻蚀损坏。
需要说明的是，在有源区4与源极5和漏极6之间也可以不形成刻蚀阻挡层，只要确保在刻蚀形成源极5和漏极6时不要对有源区4造成刻蚀损坏即可。
实施例2
本实施例提供一种薄膜晶体管的制备方法，与实施例1不同的是，在形成栅绝缘层的同时对形成栅绝缘层的材料进行的控制处理包括：采用SiH4和NH3，并按照SiH4：NH3≤1：90的气体体积流量比沉积形成栅绝缘层。
例如，本实施例中，栅绝缘层的厚度范围可以为
Figure PCTCN2014091883-appb-000006
由于传统的栅绝缘层通常按照SiH4和NH3的气体体积流量比为1:30沉积形成，所以本实施例中SiH4和NH3的气体体积流量比能够使形成的栅绝缘层中的氮元素含量大大提高。由此，在薄膜晶体管处于工作状态时，栅绝缘 层中的氮元素能够持续地补充至有源区中，并在有源区中处于有效导电位置。处于有效导电位置的氮元素大大提高了有源区中氮空位的迁移率，也即大大提高了有源区中载流子的迁移率，从而降低了薄膜晶体管的亚阈值摆幅，提升了薄膜晶体管的半导体特性。
本实施例中薄膜晶体管的其他结构的制备方法与实施例1中相同，此处不再赘述。
实施例3
本实施例提供一种薄膜晶体管的制备方法，与实施例1-2不同的是，在形成栅绝缘层的同时对形成栅绝缘层的材料进行的控制处理例如如下所述。
首先，按照SiNx为140～180sccm，N2为1750～2250sccm，NH3为700～900sccm的气体体积流量提供气体SiNx、N2和NH3，以沉积形成栅绝缘层，其中，X的取值范围为1～4/3；然后，将NH3电离并将电离后产生的氮离子轰击到栅绝缘层的朝向有源区的表面。
通常，轰击到栅绝缘层表面的氮离子的数量能够达到1015个/cm2以上，这能使栅绝缘层中氮元素的含量大大提高。从而在薄膜晶体管处于工作状态时，栅绝缘层中的氮元素能够持续地补充至有源区中，并在有源区中处于有效导电位置。由此，处于有效导电位置的氮元素大大提高了有源区中氮空位的迁移率，也即大大提高了有源区中载流子的迁移率，从而降低了薄膜晶体管的亚阈值摆幅，提升了薄膜晶体管的半导体特性。
本实施例中薄膜晶体管的其他结构的制备方法与实施例1-2中的任一个相同，此处不再赘述。
实施例4
本实施例提供一种薄膜晶体管的制备方法，与实施例1-3不同的是，栅极形成于有源区上方，即本实施例中的薄膜晶体管为顶栅型结构。
本实施例中薄膜晶体管的其他结构的制备方法与实施例1-3中的任一个相同，此处不再赘述。
实施例1-4中所提供的薄膜晶体管的制备方法，通过在形成栅绝缘层的同时对形成栅绝缘层的材料进行控制处理，使栅绝缘层中的氮元素含量大大提高。这使得在薄膜晶体管处于工作状态时，栅绝缘层能持续地向有源区中补充氮元素，并使氮元素在有源区中处于有效导电位置。处于有效导电位置 的氮元素大大提高了有源区中氮空位的迁移率，也即大大提高了有源区中载流子的迁移率，从而降低了薄膜晶体管的亚阈值摆幅，提升了薄膜晶体管的半导体特性。
实施例5
本实施例提供一种薄膜晶体管，该薄膜晶体管采用实施例1-4任意一个中的制备方法制成。
通过采用实施例1-4任意一个中的制备方法制成的薄膜晶体管，其亚阈值摆幅≤0.5mV/dec，与通常的薄膜晶体管相比，其亚阈值摆幅大大降低，半导体特性也得到了极大提升。
实施例6
本实施例提供一种阵列基板，其包括实施例5中所述的任一薄膜晶体管。
通过采用实施例5中所述的任一薄膜晶体管，使该阵列基板的性能得到了进一步提升。
实施例7
本实施例提供一种显示装置，包括实施例6中所述的任一阵列基板。
通过采用实施例6中所述的任一阵列基板，进一步提升了该显示装置的性能。
例如，本发明的实施例所提供的显示装置可以为液晶面板、液晶电视、显示器、OLED面板、OLED电视、手机、导航仪、手表等任何具有显示功能的产品或部件。
本发明的实施例所提供的显示装置，通过采用任一上述阵列基板，进一步提升了该显示装置的性能。
以上所述仅是本发明的示范性实施方式，而非用于限制本发明的保护范围，本发明的保护范围由所附的权利要求确定。
本专利申请要求于2014年8月5日递交的中国专利申请第201410381849.8号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。

Claims (13)

  1. 一种薄膜晶体管的制备方法，包括在衬底基板上形成栅极、栅绝缘层、有源区、源极和漏极，
    其中，所述有源区采用ZnON材料形成，
    在形成所述栅绝缘层的同时对形成所述栅绝缘层的材料进行控制处理，以使所述薄膜晶体管的亚阈值摆幅≤0.5mV/dec。
  2. 根据权利要求1所述的制备方法，其中，所述栅绝缘层包括第一栅绝缘层和第二栅绝缘层，所述第二栅绝缘层形成于所述第一栅绝缘层与所述有源区之间。
  3. 根据权利要求2所述的制备方法，其中所述在形成所述栅绝缘层的同时对形成所述栅绝缘层的材料进行控制处理包括：
    按照SiNx为140～180sccm，N2为1750～2250sccm，NH3为700～900sccm的气体体积流量提供气体SiNx、N2和NH3，以沉积形成所述第一栅绝缘层；
    按照SiNx为140～180sccm，N2为≥3500sccm，NH3为≥1400sccm的气体体积流量提供气体SiNx、N2和NH3，以沉积形成所述第二栅绝缘层，
    其中，X的取值范围为1～4/3。
  4. 根据权利要求3所述的制备方法，其中，第一栅绝缘层和第二栅绝缘层采用化学气相沉积方法形成，在化学气相沉积室内，先按照所述气体体积流量充入N2和NH3，然后按所述气体体积流量充入SiNx、N2和NH3以沉积SiNx层，最终形成氮元素含量不同的第一栅绝缘层和第二栅绝缘层。
  5. 根据权利要求2-4任一所述的制备方法，其中，所述第一栅绝缘层的厚度范围为
    Figure PCTCN2014091883-appb-100001
    所述第二栅绝缘层的厚度范围为
    Figure PCTCN2014091883-appb-100002
  6. 根据权利要求1所述的制备方法，其中，在形成所述栅绝缘层的同时对形成所述栅绝缘层的材料进行控制处理包括：
    采用SiH4和NH3，并按照SiH4：NH3≤1：90的气体体积流量比沉积形成所述栅绝缘层。
  7. 根据权利要求1所述的制备方法，其中，在形成所述栅绝缘层的同时对形成所述栅绝缘层的材料进行控制处理包括：
    首先，按照SiNx为140～180sccm，N2为1750～2250sccm，NH3为 700～900sccm的气体体积流量提供气体SiNx、N2和NH3，以沉积形成所述栅绝缘层，其中，X的取值范围为1～4/3；
    然后，将NH3电离并将电离后产生的氮离子轰击到所述栅绝缘层的朝向所述有源区的表面。
  8. 根据权利要求6或7所述的制备方法，其中，所述栅绝缘层的厚度范围为
    Figure PCTCN2014091883-appb-100003
  9. 根据权利要求1-8任一所述的制备方法，在形成所述有源区之后、并在形成所述源极和所述漏极之前，还包括形成刻蚀阻挡层，在所述刻蚀阻挡层中并对应所述有源区的两端分别形成第一过孔和第二过孔，其中，所述源极通过所述第一过孔与所述有源区连接，所述漏极通过所述第二过孔与所述有源区连接。
  10. 根据权利要求1-9任一所述的制备方法，其中，所述有源区形成于所述栅极上方，或者所述栅极形成于所述有源区上方。
  11. 一种薄膜晶体管，其采用权利要求1-10任一所述的制备方法制成。
  12. 一种阵列基板，其包括权利要求11所述的薄膜晶体管。
  13. 一种显示装置，其包括权利要求12所述的阵列基板。
PCT/CN2014/091883 2014-08-05 2014-11-21 薄膜晶体管及其制备方法、阵列基板和显示装置 WO2016019652A1 (zh)

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