WO2016008197A1 - 阵列基板及其制造方法 - Google Patents

阵列基板及其制造方法 Download PDF

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Publication number
WO2016008197A1
WO2016008197A1 PCT/CN2014/084834 CN2014084834W WO2016008197A1 WO 2016008197 A1 WO2016008197 A1 WO 2016008197A1 CN 2014084834 W CN2014084834 W CN 2014084834W WO 2016008197 A1 WO2016008197 A1 WO 2016008197A1
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Prior art keywords
patterned
layer
metal pattern
floating metal
metal layer
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PCT/CN2014/084834
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English (en)
French (fr)
Inventor
柴立
Original Assignee
深圳市华星光电技术有限公司
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Priority to US14/416,314 priority Critical patent/US9859269B2/en
Publication of WO2016008197A1 publication Critical patent/WO2016008197A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0288—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using passive elements as protective elements, e.g. resistors, capacitors, inductors, spark-gaps
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/133345—Insulating layers
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/13439—Electrodes characterised by their electrical, optical, physical properties; materials therefor; method of making
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136204—Arrangements to prevent high voltage or static electricity failures
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1255—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs integrated with passive devices, e.g. auxiliary capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1262—Multistep manufacturing methods with a particular formation, treatment or coating of the substrate
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/12—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode
    • G02F2201/123—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode pixel

Definitions

  • the present invention relates to the field of liquid crystal display technologies, and in particular, to an array substrate and a method of fabricating the same. Background technique
  • Electrostatic discharge (ESD) protection has always been one of the important topics in the field of thin film transistor liquid crystal display (TFT-LCD) manufacturing.
  • the concept of ESD protection is mainly caused by a series of process steps (for example, dry I* engraving) on the surface of the substrate of the display, which accumulates a lot of static charges on the substrate, and these static charges are accumulated to a certain extent. When it is randomly discharged, it will destroy part of the pixel structure, causing display defects and even destroying the entire display.
  • the substrate is divided into a display area and a peripheral area, and the display area includes a first region as a thin film transistor and a second region as a storage capacitor.
  • a first metal layer is first formed on the substrate, and patterned by the first photomask to form the gate electrode 11A of the first region and the lower electrode of the second region (the storage capacitor Electrode) 11B.
  • the channel layer 13 and the ohmic contact layer 4 are formed in the first region by patterning with a second photomask.
  • a protective layer 7 is formed on the above structure and patterned by a fourth photomask to form a via hole to expose a portion of the drain electrode 15 of the thin film transistor.
  • a conductive layer is formed, and the conductive layer is patterned by a fifth photomask, and the patterned conductive layer 18 serves as a pixel electrode, and is electrically connected to the drain electrode 15 through the via hole, and serves as an upper electrode of the second region.
  • the machine line and the data line in the array substrate are generally single metal.
  • the data line is the third layer of the entire process and is the second layer of the metal layer forming process.
  • the PV layer is first etched away, so that the metal layer where the data line is located is exposed to the DRY plasma, and the insulating layer is continuously etched. In the process, the plasma will continue to bombard the data line.
  • the metal layer which causes the metal layer to continuously accumulate static electricity and is prone to ESD phenomenon, and in severe cases, breakdown occurs, thereby causing the array substrate to be scrapped.
  • One of the problems to be solved by the present invention is to provide a method of piercing an array substrate which can reduce the risk of electrostatic breakdown during the manufacturing process.
  • the present invention also provides an array substrate.
  • the present invention provides a method for fabricating an array substrate, comprising: providing a substrate having a display region on the substrate: forming a plurality of pixel structures in the display region, and manufacturing the at least one pixel structure
  • the method includes: sequentially forming a patterned first metal layer, a gate insulating layer, and a patterned second metal layer on the substrate, wherein the patterned first metal layer includes a machine line and an insulating layer and the gate line a floating metal pattern, the patterned second metal layer including a data line, a source and a drain, the data line being disposed corresponding to the floating metal pattern via the substantially insulating layer; and the patterned second metal Forming a patterned protective layer on the layer, the patterned protective layer having a via hole exposing a portion of the drain; forming a patterned conductive layer on the patterned protective layer as a pixel electrode, wherein the pixel electrode passes through A hole is electrically connected to the drain.
  • the floating metal pattern is disposed such that there is a space between the substantially line direction and the outline.
  • the width of the floating metal pattern is less than or equal to the width of the data line.
  • the floating metal pattern is made of any one of tantalum, molybdenum rhenium, chromium, aluminum, titanium aluminum titanium, aluminum molybdenum, molybdenum tantalum, and molybdenum tungsten.
  • an array substrate including: a substrate having a display area thereon; a plurality of pixel structures formed on the display area, the at least one pixel structure comprising: a patterned first a metal layer, the patterned first metal layer includes a machine line and a floating metal pattern insulated from the gate line; a pole insulating layer disposed on the patterned first metal layer; patterning the second metal a layer disposed on the gate insulating layer, the patterned second metal layer includes a data line, a source and a drain, and the data line is disposed corresponding to the floating metal pattern via the gate insulating layer a patterned protective layer disposed on the patterned second metal layer, wherein the patterned protective layer has a via hole exposing a portion of the drain; a patterned conductive layer disposed on the patterned protective layer And as a pixel electrode, the pixel electrode is electrically connected to the drain through the via.
  • the floating metal pattern is perpendicular to the gate line direction and spaced apart from the gate line. In one embodiment, when the floating metal pattern is a rectangular pattern, the width of the floating metal pattern is less than or equal to the width of the data line. In one embodiment, the floating metal pattern is made of any one of materials such as tantalum, aluminum tantalum, chromium, aluminum, tantalum aluminum titanium, aluminum aluminum, aluminum tantalum, and aluminum tungsten.
  • one or more embodiments of the present invention may have the following advantages - since the array substrate of the embodiment of the present invention adds a floating metal pattern under the data line, thereby indirectly increasing the capacitance on the data line. Therefore, it is possible to increase the capacitance for storing the static electricity generated by bombarding the second metal layer by the plasma, and to prevent electrostatic breakdown due to insufficient capacitance storage capability.
  • Figure is a cross-sectional view of an array substrate in the prior art
  • FIG. 2 is a cross-sectional view of an array substrate according to an embodiment of the present invention
  • FIG. 3A and FIG. 3C are a series of top views showing a process of forming an array substrate according to a preferred embodiment of the present invention
  • FIG. 4 is an array substrate according to an embodiment of the present invention. Schematic diagram of the manufacturing method
  • Figure 5 is a cross-sectional view taken along line AA' of Figure 3C.
  • the array substrate of the embodiment of the present invention includes the following structure: a substrate 21 having a display area thereon; a plurality of pixel structures formed on the display area, the at least one pixel structure comprising: a patterned first metal layer 22; a pole insulating layer 23 disposed on the patterned first metal layer 22; a patterned second metal layer 24 disposed on the gate insulating layer 23; and a patterned second metal layer
  • the patterned first metal layer includes a poplar line 221 and a floating metal pattern 222 insulated from the gate line 221.
  • the patterned second metal layer includes a data line 241, a source 242, and a drain 243, and the data line 24 is disposed corresponding to the floating metal pattern 222 through the drain insulating layer 23 (refer to FIG. 5).
  • the patterned protective layer 25 has a via hole exposing a portion of the drain.
  • the patterned conductive layer 26 serves as a pixel electrode, and the pixel electrode is electrically connected to the drain electrode 243 through a via hole.
  • a floating metal pattern 222 is provided in the patterned first metal layer 22.
  • the floating metal pattern 222 is separately present on the bismuth glass substrate and is not in contact with other conductive lines or conductive elements, and is spaced apart from the data line 241 by an insulating layer 23.
  • the floating metal pattern 222 is disposed to have a vertical ⁇ line 22 direction ⁇ and a gap between the gate lines 22.
  • the size of the floating metal pattern 222 is not particularly limited, and may be designed according to actual needs, but preferably, in order to better share the static electricity generated by the dry plasma bombardment without affecting the transmittance, the floating metal pattern The 222 can be completely covered by the data line 241 via the gate insulating layer 23 (refer to FIG. 5).
  • the floating metal pattern 222 is a rectangular pattern as shown in FIG. 3A, the width of the floating metal pattern 222 is less than or equal to the width of the data line 241.
  • the arrangement of the floating metal pattern 222 does not affect the existing process, and it is only necessary to add a metal pattern to the same process.
  • the floating metal pattern 222 is obtained by using conventional photolithography, etching or deposition. However, it is convenient to have the floating metal pattern 222 and the twisted wire 221 obtained in the same material in the process of manufacturing the twisted wire.
  • the floating metal pattern 222 is punctured with any one of tantalum, molybdenum tantalum, chromium, aluminum, titanium titanium, aluminum aluminum, molybdenum tantalum, and molybdenum tungsten.
  • the floating metal pattern 222 is added under the data line 241, the capacitance on the data line 241 is indirectly increased, so that the static electricity generated by bombarding the second metal layer by the plasma can be increased. Store the capacitor to prevent electrostatic breakdown due to insufficient capacitance storage capability.
  • the design of the embodiment of the present invention is simple, and there is no complicated circuit design. Only the floating metal pattern 222 can achieve the purpose of electrostatic protection, saving manufacturing cost and reducing the complexity of the process.
  • FIG. 4 is a flow chart showing a method of staking an array substrate according to an embodiment of the invention. As shown in FIG. 4, the manufacturing method specifically includes the following steps.
  • step S410 a substrate 21 is provided.
  • the substrate 21 has a display region and a peripheral region, wherein the display region includes a region as a thin film transistor and a region as a storage capacitor.
  • the material of the substrate is generally an inorganic material such as light transmissive (such as glass, quartz or the like) or opaque (such as wafer, ceramic or the like), or a flexible material such as plastic or rubber.
  • the substrate 21 is a glass substrate.
  • Step S420 forming a plurality of pixel structures in the display area. Specifically, for the fabrication of a pixel structure, the step specifically includes the following sub-steps.
  • Sub-step S421, a patterned first metal layer 22, a gate insulating layer 23, and a patterned second metal layer 24 are sequentially formed on the substrate 21.
  • the patterned first metal layer 22 includes a pole line 221 and a floating metal pattern 222 insulated from the gate line 221
  • the patterned second metal layer 24 includes a data line 241, a source 242 and a drain 243, and the data line 241 is via
  • the outline insulating layer 23 is provided corresponding to the floating metal pattern 222.
  • FIGS. 3A-3C are a series of top views showing the flow of forming an array substrate in accordance with a preferred embodiment of the present invention. It is to be noted that Figs. 3A to 3C show only the first to third processes in the flow of the thin film transistor forming the array substrate.
  • a first metal layer is deposited on the entire surface of the glass substrate by a sputtering method, and then the first metal layer is patterned by a first photolithography technique.
  • the first metal layer may be selected from any of materials such as germanium, germanium, chromium, aluminum, titanium aluminum titanium, aluminum aluminum, tantalum, and aluminum tungsten.
  • Photolithography is performed on the first metal layer pattern, specifically including the following steps: first, the glass substrate on which the metal layer is evaporated is washed, and then the photoresist sensitive to ultraviolet rays is applied thereon. In order to harden the photoresist, prebaking is performed at a certain temperature. Next, a mask is placed over the photoresist and irradiated with ultraviolet light. During the ultraviolet irradiation, the portion of the image on the mask cannot pass through the purple, and the unirradiated photoresist hardens. On the other hand, the unpatterned portion of the mask passes through the ultraviolet rays, and the irradiated photoresist becomes soft.
  • the removal method may be a wet stripping method, a dry stripping method, or the like.
  • a patterned first metal layer as shown in Fig. 3A is obtained, and the patterned first metal layer includes a floating metal pattern 222 and a polar line 22. Since the floating metal pattern 222 is formed in the same process as the gate line 221, although a metal pattern is added, no additional manufacturing steps are added.
  • the gate insulating layer may be an organic material such as an organosilicon compound, or an inorganic material such as silicon nitride, silicon oxide, silicon oxynitride or the like.
  • a channel layer and an ohmic contact layer are formed on the gate insulating layer, and the channel layer is generally a semiconductor layer such as amorphous silicon, polycrystalline silicon, microcrystalline silicon or single crystal silicon.
  • the formation may be chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), rapid thermal chemical vapor deposition (RTCVD), ultra-high vacuum chemical vapor deposition (UHV/CVD) or molecular beam epitaxy. (MBE).
  • CVD chemical vapor deposition
  • PECVD plasma enhanced chemical vapor deposition
  • RTCVD rapid thermal chemical vapor deposition
  • UHV/CVD ultra-high vacuum chemical vapor deposition
  • MBE molecular beam epitaxy.
  • the ohmic contact layer is generally doped silicon, and it may be necessary to select a type or a p-type doping as the case may be.
  • the formed ohmic contact layer and channel layer are the silicon islands 231 shown in FIG. 3B.
  • a second metal layer is formed by sputtering or other physical vapor deposition, and the second metal layer is patterned by the above photolithography technique.
  • the second metal layer may be a metal, an alloy or the like, and any one of ruthenium, molybdenum ruthenium, chromium, aluminum, titanium aluminum titanium, aluminum molybdenum, molybdenum ruthenium and aluminum tungsten may be used.
  • the specific lithography step will not be described again.
  • the resulting patterned second metal layer includes the source 242 and the drain 243 of the thin film transistor and the data line 241.
  • the data line 241 is disposed corresponding to the floating metal pattern 222 due to the added floating metal pattern 222. It does not occupy other space on the substrate, so it does not reduce the transmittance of the pixel structure due to the space it occupies.
  • the above data line 241 is electrically connected to the source 242 of the thin film transistor.
  • the structure of the gate line 221, the data line 241, the thin film transistor, and the like has been completed on the substrate.
  • FIG. 5 is a cross-sectional view of AA' in FIG. 3C.
  • the data line 241 is disposed corresponding to the floating metal 222 through the insulating layer 23.
  • the capacitance on the data line is indirectly increased, so that the capacitance for storing the static electricity generated by bombarding the second metal layer by the dry plasma can be increased. , to prevent electrostatic breakdown caused by insufficient capacitance storage capacity.
  • the embodiment of the present invention is simple in design, has no complicated circuit design, but can still achieve the purpose of electrostatic protection.
  • Sub-step S422 forming a patterned protective layer 25 on the patterned second metal layer 24.
  • the patterned protective layer 25 has a via hole exposing a portion of the drain.
  • the pixel structure is not limited to the layout structure as described above.
  • Other layouts or architectures that employ the principles of the present invention to enhance the occurrence of reduced electrostatic breakdown can be applied to the present invention, such as pixel structures having a main pixel region and a sub-pixel region.

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Abstract

一种阵列基板及其制造方法，该制造方法包括：提供一基板（21）；形成多个像素结构在显示区域，至少一个像素结构的制造方法包括：在基板（21）上依次形成图案化第一金属层（22）、栅极绝缘层（23）以及图案化第二金属层（24），其中，图案化第一金属层（22）包括栅线（221）和与栅线（221）绝缘设置的浮动金属图案（222），图案化第二金属层（24）包括数据线（241）、源极（242）和漏极（243），数据线（241）经由栅极绝缘层（23）与浮动金属图案（222）对应设置。该阵列基板能够增大对由干刻电浆轰击第二金属层（24）所产生的静电进行存储的电容，防止由电容存储能力不足而导致静电击穿。

Description

阵列基板及其制造方法
本申请要求享有 2014年 7月 17日提交的名称为 "阵列基板及其制造方法" 的中国专 利申请 CN201410342978.6的优先权， 其全部内容通过引用并入本文中。
技术领域
本发明涉及液晶显示器技术领域， 尤其涉及一种阵列基板及其制造方法。 背景技术
在薄膜晶体管液晶显示器 （TFT- LCD ) 的制造过程中， 静电放电 （Eiectro- Siatk Discharge, ESD) 保护一直是本领域中的重要课题之一。 ESD 保护观念的产生， 主要是 因为在对显示器的基板表面进行一连串的工艺步骤（例如， 干法 I*刻）时， 会在基板上累 积不少静电荷， 这些静电荷在累积至一定程度而随意放电时， 会破坏部分像素结构， 造成 显示缺陷， 甚至造成整个显示器损毁。
在现有技术中， 形成 TFT阵列基板需要进行五道光掩膜。 如图 1所示， 基板分为显 示区域和外围区域，显示区域包括作为薄膜晶体管的第 I区和作为储存电容的第 II区。在 阵列基板的制作过程中， 首先在基板上形成第一金属层， 并以第一道光掩模使其图案化， 形成第 I区的栅极 11A和第 II区的下电极 （储存电容的电极） 11B。 接着， 形成绝缘层 12后， 以第二道光掩模图案化在第 I区形成沟道层 13和欧姆接触层 4。在形成第二金属 层后， 以第 道光掩模进行图案化使第二金属层形成漏极 5， 并对部分的欧姆接触层 14 进行蚀刻以漏出沟道层 13。在上述结构上形成保护层 7，并以第四道光掩模进行图案化， 形成过孔 （Via hole) 以露出薄膜晶体管的部分漏极 15。 之后形成导电层， 在以第五道光 掩模图案化导电层，图案化的导电层 18而作为像素电极，使其透过过孔与漏极 15电连接， 并作为第 II区的上电极。 经上述步骤， 即形成如图 1所示的结构。
由上述制造过程可知， 阵列基板中機线和数据线一般都是单层金属 （single metal) 。 旦数据线为整个工艺制程的第三层， 且为金属层形成工艺的第二层。 由于在第四步骤中， 即在蚀刻过孔的过程中， 首先是将 PV层蚀刻掉， 这样数据线所在金属层会暴露在千刻电 浆 （DRY plasma) 中， 在持续对绝缘层进行蚀刻的过程中， 电浆会不断轰击数据线所在 金属层， 由此就会造成该金属层持续积累静电并很容易发生 ESD现象， 严重情况就会发 生击穿现象， 从而导致阵列基板报废。
因此， 亟需提供一种解决方案， 以降低在蚀刻过孔的过程中发生静电击穿的风险。
发明内容
本发明所要解决的技术 题之一是需要提供一种阵列基板的刺造方法，该方法能够能 够降低制造过程中发生静电击穿的风险。 另外， 本发明还提供了一种阵列基板。
为了解决上述技术问题，本发明提供了一种阵列基板的制造方法，包括：提供一基板， 所述基板上具有显示区域： 形成多个像素结构在所述显示区域，至少一个像素结构的制造 方法包括:在所述基板上依次形成图案化第一金属层、栅极绝缘层以及图案化第二金属层， 其中，所述图案化第一金属层包括機线和与所述栅线绝缘设置的浮动金属图案，所述图案 化第二金属层包括数据线、源极和漏极，所述数据线经由所述概极绝缘层与所述浮动金属 图案对应设置；在所述图案化第二金属层上形成图案化保护层，所述图案化保护层上具有 露出部分漏极的过孔；在所述图案化保护层上形成图案化导电层而作为像素电极，所述像 素电极通过所述过孔与所述漏极电连接。
在一个实施例中， 所述浮动金属图案被设置为垂直所述概线方向旦与所述概线之间 存在间隔。
在一个实施例中，所述浮动金属图案为矩形图案时，所述浮动金属图案的宽度小于或 等于所述数据线的宽度。
在一个实施例中， 采用钽、 钼锃、 铬、 铝、 钛铝钛、 铝钼、 钼钽和钼钨中的任一种材 料制成所述浮动金属图案。
根据本发明的另一方面， 还提供了一种阵列基板， 包括： 基板， 所述基板上具有显示 区域；形成在所述显示区域的多个像素结构，至少一个像素结构包括：图案化第一金属层， 所述图案化第一金属层包括機线和与所述栅线绝缘设置的浮动金属图案；極极绝缘层，其 设置在所述图案化第一金属层上； 图案化第二金属层， 其设置在所述栅极绝缘层上， 所述 图案化第二金属层包括数据线、源极和漏极，所述数据线经由所述栅极绝缘层与所述浮动 金属图案对应设置； 图案化保护层， 其设置在所述图案化第二金属层上， 且所述图案化保 护层上具有露出部分漏极的过孔； 图案化导电层， 其设置在所述图案化保护层上， 且作为 像素电极， 所述像素电极通过所述过孔与所述漏极电连接。
在一个实施例中， 所述浮动金属图案垂直所述栅线方向且与所述栅线之间存在间隔。 在一个实施例中，所述浮动金属图案为矩形图案时，所述浮动金属图案的宽度小于或 等于所述数据线的宽度。 在一个实施例中， 所述浮动金属图案采 ^钽、 铝钽、 铬、 铝、 钕铝钛、 铝铝、 铝钽和 铝钨中的任一种材料制成。
与现有技术相比， 本发明的一个或多个实施例可以具有如下优点 - 由于本发明实施例的阵列基板在数据线的下方增设了浮动金属图案,进而间接增加了 数据线上的电容，因此能够增大对由千刻电浆轰击第二金属层所产生的静电进行存储的电 容， 防止由电容存储能力不足而导致静电击穿。
本发明的其它特征和优点将在随后的说明书中阐述，并且，部分地从说明书中变得显 而易见， 或者通过实施本发明而了解。本发明的目的和其他优点可通过在说明书、权利要 求书以及 »图中所特别指出的结构来实现和获得。
图说明
附图用来提供对本发明的进一步理解，并且构成说明书的一部分，与本发明的实施例 共同用于解释本发明， 并不构成对本发明的限制。 在附图中；
图 是现有技术中阵列基板的截面图；
图 2是根据本发明一实施例的阵列基板的剖视图； 图 3A图 3C是一系列俯视图， 显示本发明优选实施例的形成阵列基板的过程； 图 4是根据本发明一实施例的阵列基板的制造方法的流程示意图；
图 5是图 3C中 AA'线处的剖视图。
具体实施方式
为使本发明的目的、技术方案和优点更加清楚， 以下结合 图对本发明作进一步地详 细说明。
图 2是根据本发明一实施 ί到的阵列基板的概略剖视图，该图仅是粗略地显示了本发明 实施例的阵列基板的结构以及各层结构之间的位置关系。如图 2所示，本发明实施例的阵 列基板包括如下结构： 基板 21 , 该基板上具有显示区域； 形成在该显示区域的多个像素 结构， 至少一个像素结构包括： 图案化第一金属层 22; 设置在图案化第一金属层 22的極 极绝缘层 23 ;设置在栅极绝缘层 23上的图案化第二金属层 24;设置在图案化第二金属层 24上的图案化保护层 25和设置在图案化保护层 25上的图案化导电层 26。
如图 3A所示， 图案化第一金属层包括楊线 221和与栅线 221绝缘设置的浮动金属图 案 222。 如图 3C所示， 图案化第二金属层包括数据线 241、 源极 242和漏极 243 , 数据线 24 通过榲极绝缘层 23与浮动金属图案 222对应设置 （参考图 5 ) 。 图案化保护层 25上 具有露出部分漏极的过孔。图案化导电层 26作为像素电极，像素电极通过过孔与漏极 243 电连接。
鉴于背景技术的描述， 在本发明实施例中， 在图案化第一金属层 22中特设了一浮动 金属图案 222。浮动金属图案 222单独存在亍玻璃基板上， 不与其他导电性线路或导电性 元件接触， 与数据线 241间隔一层绝缘层 23。 优选地， 浮动金属图案 222被设置为垂直 搠线 22 方向 ϋ与栅线 22 之间存在间隔。另夕卜，浮动金属图案 222的大小也无特别限制， 可以根据实际需要来设计，但优选地，为了更好地分担干刻电浆轰击所产生的静电且不影 响透过率， 浮动金属图案 222能够被数据线 241经由栅极绝缘层 23而完全覆盖 （参考图 5 ) 。 举例而言， 在浮动金属图案 222为如图 3Α所示的矩形图案时， 浮动金属图案 222 的宽度小于或等于数据线 241的宽度。
浮动金属图案 222的设置并不影响现有的工艺，仅在同一个工艺中增加一个金属图案 的制作即可。浮动金属图案 222 以采用现有的光刻、刻蚀或沉积而得到。但较方便的是 使浮动金属图案 222与榲线 221以相同材料在制造榲线的工艺中得到。而且， 优选地， 浮 动金属图案 222采用钽、钼钽、铬、铝、钛铠钛、铝铝、钼钽和钼钨中的任一种材料刺成。
相比现有技术， 由于在数据线 241的下方增加了浮动金属图案 222, 进而间接增加了 数据线 241上的电容,从而能够增大对由千刻电浆轰击第二金属层所产生的静电进行存储 的电容， 防止由电容存储能力不足而导致静电击穿。而且， 本发明实施例的设计简单， 没 有复杂电路设计，仅利用该浮动金属图案 222就可以达到静电保护的目的，节省制作成本 和降低工艺制成的复杂度。
图 4是根据本发明一实施例的阵列基板的刺造方法的流程示意图。如图 4所示，该制 造方法具体包括以下几个歩骤。
步骤 S410, 提供一基板 21。
需要说明的是， 该基板 21具有显示区域和外围区域， 其中， 显示区域包括作为薄膜 晶体管的区域和作为储存电容的区域。基板的材料一般为透光（如玻璃、石英或类似材料) 或不透光 （如晶片、 陶瓷或类似材料） 等无机材料， 也可以为塑料、 橡胶等可挠性材料。 在本实施例中， 基板 21为玻璃基板。
步骤 S420, 形成多个像素结构在该显示区域。 具体地， 针对一个像素结构的制造， 该步骤具体包括以下子步骤。
子步骤 S421 , 在该基板 21上依次形成图案化第一金属层 22、 栅极绝缘层 23以及图 案化第二金属层 24。该图案化第一金属层 22包括極线 221和与栅线 221绝缘设置的浮动 金属图案 222，该图案化第二金属层 24包括数据线 241、源极 242和漏极 243 ,数据线 241 经由概极绝缘层 23与浮动金属图案 222对应设置。
为了更好说明该子歩骤， 下面一边参考图 3A-图 3C, —边说明该步骤。
图 3A-图 3C是一系列俯视图， 显示本发明优选实施例的形成阵列基板的流程。 需要 说明的是图 3A-图 3C只显示了形成阵列基板的薄膜晶体管的流程中的前—三道工序。 首先， 利用戮射镀膜法在玻璃基板的整个表面上沉积第一层金属层， 然后， 利用第一 道光刻技术图案化第一金属层。 第一金属层可选^钽、 讓、 铬、 铝、 钛铝钛、 铝铝、 钽和铝钨中的任一种材料。 在对第一层金属层图案进行光刻 B寸，具体包括以下操作：首先对蒸镀有金属层的玻璃 基板进行洗净， 而后在其上涂布对紫外线感光的光刻胶。为使光刻胶硬化， 则在一定温.度 下进行预烘烤。 下一步， 在光刻胶上方放置掩膜板， 并用紫外线照射。在紫外线照射过程 中， 掩膜板上有图像的部分不能透过紫夕卜线， 未受到照射的光刻胶变硬。 另一方靣， 掩膜 板上无图形的部分透过紫外线， 被照射的光刻胶变软。下一步， 为了去除光刻胶， 需要在 显像液中浸泡以去除光刻胶的软化部分。而后， 再次烘烤使构成图形的光刻胶坚固化。接 着， 为了去除不需要的金属膜部分， 需要在蚀刻液中处理（湿式刻铍） , 或者利用减压气 体放电的放电气体进行处理（干式刻蚀） 。 最后， 为了得到最终的图形， 需要将不需要的 光刻胶去除， 去除方法可以采用湿式剥离、 干式剥离方法等。
这样， 经过上述步骤得到如图 3A所示的图案化第一金属层， 该图案化第一金属层包 括包括浮动金属图案 222和極线 22 。由于浮动金属图案 222与栅线 221在同一工艺中制 成， 因此虽然增设了金属图案， 但是没有额外增加其他制造步骤。
接着， 在上述结构上形成栅极绝缘层。 栅极绝缘层可为有机材料， 例如有机硅化物， 或为无机材料如氮化硅、氧化硅、氮氧化硅等。之后在栅极绝缘层上形成沟道层和欧姆接 触层， 沟道层一般为半导体层如非晶硅、 多晶硅、 微晶硅或单晶硅等材料。 形成方式可以 为化学气相'沉积 ( CVD ) 、 等离子增强化学气相 '沉积 （PECVD ) 、 快热式化学气相沉积 ( RTCVD ) 、 超高真空化学气相'沉积 （UHV/CVD ) 或分子束外延成长法 （MBE ) 。 欧 姆接触层一般为掺杂硅，可视情况需要选择 ίΐ型或 p性掺杂。形成的欧姆接触层和沟道层 为图 3B所示的硅岛 231。 然后， 以溅射或其他物理气相沉积形成第二金属层，并采用上述光刻技术图案化第二 金属层。
第二金属层可为金属、 合金等材料， 可选用钽、 钼钽、 铬、 铝、 钛铝钛、 铝钼、 钼钽 和铝钨中的任一种材料。具体光刻步骤不再赘述，最终得到的图案化第二金属层包括薄膜 晶体管的源极 242和漏极 243以及数据线 241 , 数据线 241对应浮动金属图案 222设置， 由于增加的浮动金属图案 222没有占用基板上的其他空间，因此在其发挥静电保护作用的 同 ， 也不会由于其所占据的空间而降低像素结构的透 ϋ率。 如图 3C所示， 上述的数据 线 241 电连接薄膜晶体管的源极 242。 至此在该基板上己完成栅极线 221、 数据线 241、 薄膜晶体管等结构。
图 5是图 3C中 AA'的截面图， 如图 5所示， 数据线 241通过绝缘层 23与浮动金属 222对应设置。 相比现有技术， 由于在数据线的下方增加了浮动金属图案， 间接增加了数 据线上的电容， 从而能够增大对由干刻电浆轰击第二金属层所产生的静电进行存储的电 容， 防止由电容存储能力不足而导致静电击穿。 而且， 本发明实施例的设 简单， 没有复 杂电路设计， 但是仍可以达到静电保护的目的。
子歩骤 S422 , 在图案化第二金属层 24上形成图案化保护层 25。 该图案化保护层 25 上具有露出部分漏极的过孔。
一般， 为了提高后面歩骤形成的像素电极和过孔下的金属层之间的电学连接特性，需 要对该层保护层进行充分的过刻处理。由于在数据线的下方增设了浮动金属图案， 因此在 进行过孔刻蚀时，千刻电浆轰击数据线所在金属层所产生的静电能够被存储至浮动金属图 案中， 进而降低了静电击穿现象的产生。
子步骤 S423 , 在图案化保护层上形成图案化导电层而作为像素电极， 该像素电极通 过子步骤 S422形成的过孔与漏极电连接。 值的一提的是， 在本发明中， 像素结构不限于如上所述的布局结构。其他采用本发明 的原理以提升降低静电击穿现象发生的布局方式或是架构都可以应用亍本发明,例如具有 主像素区和次像素区的像素结构。
以上所述， 仅为本发明的具体实施案例， 本发明的保护范围并不局限于此， 何熟悉 本技术的技术人员在本发明所述的技术规范内，对本发明的修改或替换，都应在本发明的 保护范围之内。

Claims

权利要求书 一种阵列基板的制造方法， 包括：
提供一基板， 所述基板上具有显示区域- 形成多个像素结构在所述显示区域， 至少一个像素结构的制造方法包括- 在所述基板上依次形成图案化第一金属层、栅极绝缘层以及图案化第二金属层， 其中， 所述图案化第一金属层包括極线和与所述機线绝缘设置的浮动金属图案， 所 述图案化第二金属层包括数据线、 源极和漏极， 所述数据线经由所述栅极绝缘层与 所述浮动金属图案对应设置；
在所述图案化第二金属层上形成图案化保护层， 所述图案化保护层上具有露出 部分漏极的过孔：
在所述图案化保护层上形成图案化导电层而作为像素电极， 所述像素电极通过 所述过孔与所述漏极电连接。
2、 根据权利要求 1所述的制造方法， 其中， 所述浮动金属图案被设置为垂直所述極 线方向且与所述栅线之间存在间隔。
3、 根据权利要求 1所述的制造方法， 其中， 所述浮动金属图案为矩形图案时， 所述 浮动金属图案的宽度小于或等于所述数据线的宽度。
4、 根据权利要求 2所述的刺造方法， 其中， 所述浮动金属图案为矩形图案时， 所述 浮动金属图案的宽度小亍或等于所述数据线的宽度。
5、 根据权利要求 1所述的制造方法， 其中， 采^钽、 钼钽、 铬、 铝、 钛铝钛、 铝钼、 钼钽和铝钨中的任一种材料制成所述浮动金属图案。
6、 一种阵列基板， 包括：
基板， 所述基板上具有显示区域；
形成在所述显示区域的多个像素结构， 至少一个像素结构包括：
图案化第一金属层， 所述图案化第一金属层包括機线和与所述搠线绝缘设置的 浮动金属图案；
栅极绝缘层， 其设置在所述图案化第一金属层上； 图案化第二金属层， 其设置在所述栅极绝缘层上， 所述图案化第二金属层包括 数据线、 源极和漏极， 所述数据线经由所述栅极绝缘层与所述浮动金属图案对应设 且；
图案化保护层， 其设置在所述图案化第二金属层上， 旦所述图案化保护层上具 有露出部分漏极的过孔；
图案化导电层， 其设置在所述图案化保护层上， 且作为像素电极， 所述像素电 极通过所述过孔与所述漏极电连接。
Ί、 根据权利要求 6所述的阵列基板， 其中， 所述浮动金属图案垂直所述栅线方向且 与所述栅线之间存在间隔。
8、 根据权利要求 6所述的阵列基板， 其中， 所述浮动金属图案为矩形图案时， 所述 浮动金属图案的宽度小亍或等于所述数据线的宽度。
9、 根据权利要求 7所述的阵列基板， 其中， 所述浮动金属图案为矩形图案时， 所述 浮动金属图案的宽度小于或等于所述数据线的宽度。
10、 根据权利要求 6所述的阵列基板， 其中， 所述浮动金属图案采用钽、 钼钽、 铬、 铝、 钹铝钛、 铠钼、 钼钽和钼钨中的任一种材料制成。
PCT/CN2014/084834 2014-07-17 2014-08-20 阵列基板及其制造方法 WO2016008197A1 (zh)

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