WO2015192628A1 - ITO薄膜的沉积方法及GaN基LED芯片 - Google Patents

ITO薄膜的沉积方法及GaN基LED芯片 Download PDF

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WO2015192628A1
WO2015192628A1 PCT/CN2014/095085 CN2014095085W WO2015192628A1 WO 2015192628 A1 WO2015192628 A1 WO 2015192628A1 CN 2014095085 W CN2014095085 W CN 2014095085W WO 2015192628 A1 WO2015192628 A1 WO 2015192628A1
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ito
depositing
thin film
sputtering
buffer layer
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French (fr)
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耿波
王厚工
赵梦欣
文莉辉
夏威
陈鹏
刘建生
丁培军
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北京北方微电子基地设备工艺研究中心有限责任公司
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Priority to KR1020167030918A priority Critical patent/KR20160141833A/ko
Publication of WO2015192628A1 publication Critical patent/WO2015192628A1/zh

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    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
    • C23C14/06—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the coating material
    • C23C14/08—Oxides
    • C23C14/086—Oxides of zinc, germanium, cadmium, indium, tin, thallium or bismuth
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
    • C23C14/22—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the process of coating
    • C23C14/34—Sputtering
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
    • C23C14/0021—Reactive sputtering or evaporation
    • C23C14/0036—Reactive sputtering
    • C23C14/0057—Reactive sputtering using reactive gases other than O2, H2O, N2, NH3 or CH4
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
    • C23C14/02—Pretreatment of the material to be coated
    • C23C14/024—Deposition of sublayers, e.g. to promote adhesion of the coating
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
    • C23C14/22—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the process of coating
    • C23C14/34—Sputtering
    • C23C14/35—Sputtering by application of a magnetic field, e.g. magnetron sputtering
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
    • C23C14/22—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the process of coating
    • C23C14/54—Controlling or regulating the coating process
    • C23C14/542—Controlling the film thickness or evaporation rate

Definitions

  • the present invention relates to the field of semiconductor manufacturing, and in particular to a method for depositing an indium tin oxide (ITO) film and a GaN-based LED chip.
  • ITO indium tin oxide
  • GaN-based LED chips are widely used in high-power lighting, automotive instrument display, large-area outdoor display, signal lights and general lighting.
  • ITO thin films are widely used in transparent conductive layers of GaN-based LED chips due to their advantages of high visible light transmittance, good electrical conductivity, abrasion resistance and corrosion resistance.
  • the ITO film prepared by the magnetron sputtering technology can not only improve the light extraction efficiency of the LED chip, but also reduce the production cost.
  • the ITO film prepared by magnetron sputtering has the advantages of lower resistivity, higher transmittance, higher refractive index and more compactness. Therefore, an ITO transparent conductive layer is generally deposited on the surface of the epitaxial layer P-GaN by magnetron sputtering to prepare an LED.
  • a direct current (DC) sputtering method is generally employed. After the substrate (such as P-GaN substrate) is transferred to the chamber of the magnetron sputtering device, vacuum is applied, then the process gas is introduced, and DC power is applied to the target to initiate sputtering until the ITO film is deposited. thickness.
  • DC direct current
  • the negative bias of the target is too high (about -1000 V), and the bias of the target is still high (about -260 V) while maintaining sputtering. Since magnetron sputtering mainly relies on the deposition of sputtered particles to form a film, the higher instantaneous voltage and sustain voltage will cause the sputtered particles to be too high in the instant of initiation and sputtering, and the bombardment of the P-GaN substrate is larger.
  • the present invention provides a method for depositing an ITO film, which effectively reduces damage to the surface of the substrate during deposition of the ITO film. Meanwhile, the present invention also provides a GaN-based LED chip.
  • the present invention provides:
  • a method for depositing an ITO film comprising the steps of:
  • the bias voltage of the target is -5V to -150V.
  • the radio frequency power is 100W to 600W
  • the DC power is 5W to 50W.
  • the DC power is 300 to 800 W.
  • the ratio of the deposited thickness of the ITO buffer layer to the ITO thin film layer is 1:1.6-20.
  • the ITO buffer layer has a deposition thickness of 10 nm to 50 nm, and the ITO thin film layer has a deposition thickness of 80 nm to 200 nm.
  • Oxygen and argon are introduced into the reaction chamber; wherein the flow rate of oxygen supplied is 1 sccm ⁇ At 10 sccm, the flow rate of the argon gas introduced was 150 sccm to 250 sccm.
  • the oxygen flow rate is 5 sccm
  • the argon flow rate is 200 sccm
  • the DC power is 10 W
  • the RF power is 300 W.
  • the oxygen flow rate is 5 sccm
  • the argon flow rate is 200 sccm
  • the DC power is 500 W.
  • the ITO buffer layer has a thickness of 20 nm, and the ITO film layer has a thickness of 100 nm.
  • the present invention also provides a GaN-based LED chip comprising an ITO transparent electrode, which is prepared by the above-described deposition method of an ITO film.
  • the deposition method of the ITO film of the invention adopts a magnetron sputtering process for depositing an ITO film: firstly, a layer of ITO buffer is deposited on the surface of the substrate by radio frequency (RF) and direct current (DC) co-sputtering. The layer was then deposited by sputtering with a layer of ITO film on the surface of the ITO buffer layer.
  • RF radio frequency
  • DC direct current
  • the present invention increases the steps of forming an ITO buffer layer by RF and DC co-sputtering before forming an ITO thin film layer by direct current, which is generated by radio frequency induction.
  • a large number of charged particles increase the current density of the plasma generated by sputtering.
  • the ignition voltage during sputtering deposition of ITO film is greatly reduced, and the particle energy is greatly reduced, so that the particles are on the substrate.
  • the bombardment is small; in the subsequent deposition of the ITO film layer by DC sputtering, the surface of the substrate is isolated due to the presence of the ITO buffer layer, effectively reducing the high-energy sputtering particles on the surface of the substrate.
  • the damage caused; in addition, the RF and DC co-sputtering in the present invention can effectively reduce the probability of the target producing a tumor.
  • the present invention also provides a GaN-based LED chip, the ITO transparent electrode of which is prepared by the deposition method of the ITO film of the present invention.
  • the energy consumption of the LED chip increases the photoelectric conversion efficiency of the LED chip and improves the life of the LED chip.
  • FIG. 1 is a flow chart of a method of depositing an ITO film of the present invention.
  • the invention provides a method for depositing an ITO film, which is deposited by a magnetron sputtering process.
  • the method of depositing an ITO film of the present invention comprises the following steps:
  • S100 depositing an ITO buffer layer on the surface of the substrate by using radio frequency (RF) and direct current (DC) co-sputtering;
  • RF radio frequency
  • DC direct current
  • the substrate may be a GaN film, or a GaAs film, a GdS film or a SiO 2 film.
  • the film formation mechanism of magnetron sputtering is that the process gas in the reaction chamber is discharged at a certain voltage to generate a plasma, and the plasma bombards the target to produce sputtered particles, and the sputtered particles are deposited on the surface of the substrate to form a thin film.
  • step S100 will be described in detail below.
  • an ITO buffer layer is deposited on the surface of the substrate by RF and DC co-sputtering.
  • the so-called RF and DC co-sputtering means that an RF bias and a DC bias are simultaneously applied to the target. Due to the induction of RF bias, a large number of charged particles are generated around the target, greatly increasing the target.
  • the current density of the sputtered particles around the material, compared with pure DC sputtering, the deposition method of the ITO film provided by the present invention at the same power greatly reduces the ignition voltage and the bias of the target during the sputtering process.
  • the energy of the sputtered particles is reduced, the bombardment intensity of the sputtered particles on the substrate is reduced, and the damage caused by the sputtered particles on the surface of the substrate is effectively reduced, and the sputtered particles are prevented from being mixed on the surface of the substrate. Destruction of the hybrid structure.
  • the target in the process of forming an ITO thin film by direct current sputtering, the target is prone to "poisoning" to produce a nodule, and the RF and DC co-sputtering in the present invention can effectively reduce the "poisoning" of the target. probability.
  • the bias of the target directly affects the energy of the sputtered particles.
  • the bias of the target is preferably -5 V to -150 V.
  • step S100 the RF power and the DC power are adjustable, and the bias of the target can be adjusted by adjusting the ratio of the RF power to the DC power.
  • the RF power is 100 W to 600 W
  • the DC power is 5 W to 50 W.
  • the deposited ITO buffer layer is affected by the bias of the surface of the substrate. If the bias of the surface of the substrate affects the stress of the deposited ITO buffer layer, in general, the lower the bias of the surface of the substrate, the lower the stress of the deposited ITO buffer layer. Therefore, the bias of the surface of the substrate should be minimized during magnetron sputtering.
  • the RF power produces a forward bias on the substrate, and the DC power produces a negative bias on the substrate.
  • the bias on the surface of the substrate can be zero or small. In one of the embodiments, when the RF power is 300 W and the DC power is 10 W, the bias voltage of the surface of the substrate is 0 V to 5 V.
  • the ITO buffer layer deposited on the surface of the substrate mainly serves as a buffer and a protective effect.
  • the thickness of the ITO buffer layer should be not less than 10 nm, and the specific thickness ranges from 10 nm to 50 nm.
  • the thickness and electrical properties of the ITO buffer layer can also be adjusted by adjusting process parameters such as buffer layer temperature, oxygen content, deposition rate, and deposition time during deposition of the ITO buffer layer, thereby reducing ITO.
  • process parameters such as buffer layer temperature, oxygen content, deposition rate, and deposition time during deposition of the ITO buffer layer, thereby reducing ITO.
  • the buffer layer temperature refers to the temperature of the buffer layer deposited on the substrate, and the temperature requirement can be met by the heater carrying the substrate or the base with the heating function, and the temperature has a great influence on the electric resistance and the density of the ITO buffer layer.
  • the step S200 will be described in detail below.
  • ITO film layer was deposited on the surface of the ITO buffer layer by DC sputtering.
  • the ITO film layer is isolated from the surface of the substrate due to the presence of the ITO buffer layer, thereby preventing the substrate surface from being bombarded with high-energy sputtered particles during the deposition of the ITO film layer. Therefore, damage to the surface of the substrate caused by sputtering particle bombardment is greatly reduced or even completely avoided.
  • the DC power is preferably 300 W to 800 W.
  • the ITO film layer is deposited to a thickness of 80 nm to 200 nm.
  • the ratio of the deposition thickness of the ITO buffer layer to the ITO film layer is 1:1.6-20.
  • the target used in the magnetron sputtering is unchanged, that is, the same target is used for the ITO buffer layer and the ITO film layer. product. Due to the same target, the composition of the ITO buffer layer and the ITO film layer are the same, both containing indium, tin and oxygen; however, due to the influence of process parameters such as oxygen content and sputtering voltage, the ITO buffer layer and the ITO film layer The microstructure can be consistent or inconsistent.
  • the process gas is argon, which has stable chemical properties and is not easily reacted with other substances.
  • the ITO material contains oxygen, and the oxygen atom is relatively active and not easily deposited, oxygen is added during the deposition process to increase the concentration of oxygen atoms. Therefore, as an embodiment, during the deposition of the ITO buffer layer and the ITO thin film layer, oxygen and argon gas are introduced into the reaction chamber as a process gas, wherein the flow rate of the oxygen supplied is 1 sccm to 10 sccm. The flow rate of the argon gas introduced was from 150 sccm to 250 sccm.
  • the ITO film of the present invention is first deposited by depositing an ITO buffer layer on the substrate by DC and RF co-sputtering, and depositing an ITO film layer by DC sputtering.
  • the damage caused by the sputtering particles on the surface of the substrate is effectively reduced.
  • the deposition of the ITO thin film is carried out by using a magnetron sputtering apparatus.
  • the method of using the magnetron sputtering apparatus is generally used by those skilled in the art, and thus will not be described in detail in the present invention.
  • a P-GaN substrate is used for depositing an ITO film, which includes the following four steps:
  • the oxygen flow rate is 5 sccm, and the argon flow rate is 200 sccm;
  • a layer of ITO with a thickness of 20 nm is deposited on the surface of the P-GaN substrate.
  • the buffer layer is deposited on the surface of the P-GaN substrate.
  • the bias of the target is -15 V, which effectively avoids damage to the surface of the P-GaN substrate caused by excessive energy of the sputtered particles;
  • the bias voltage of the P-GaN substrate is 0-5V, which makes the deposited ITO buffer layer have lower stress, which increases the film quality of the ITO buffer layer; and, when DC power At 10 W, the RF power is 300 W, and the deposited ITO buffer layer has a lower ohmic contact resistance with the P-GaN substrate.
  • the DC and RF co-sputtering is converted into DC sputtering, the bias of the target is increased, and the sputtering ion energy is also increased, but, due to the ITO
  • the protection of the buffer layer enables high-energy sputter ions to be directly bombarded onto the surface of the P-GaN substrate, thereby effectively preventing surface damage of the P-GaN substrate and facilitating the production of products with excellent performance.
  • Example 1 the DC power, the RF power, the argon flow rate, the oxygen flow rate, and the thickness of the ITO buffer layer and the thickness of the ITO film layer can be adjusted according to the process requirements.
  • the invention also provides a GaN-based LED chip, the electrode of which uses an ITO transparent electrode, and the ITO transparent electrode is prepared by the deposition method of the ITO film of the invention.
  • the deposition method of the ITO thin film of the present invention effectively reduces the damage caused by the sputtered particles on the surface bombardment of the GaN substrate, thereby reducing the contact between the ITO transparent electrode and the GaN substrate.
  • the resistor further reduces the energy consumption of the LED chip, increases the photoelectric conversion efficiency of the LED chip, and improves the life of the LED chip.

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Abstract

本发明公开了一种ITO薄膜的沉积方法，采用磁控溅射工艺进行ITO薄膜的沉积，包括以下步骤：利用射频和直流共溅射在基片表面沉积ITO缓冲层；利用DC溅射在所述ITO缓冲层表面沉积ITO薄膜层。其通过射频和直流共溅射，有效降低了溅射粒子对基片表面轰击造成的损伤。本发明还提供了一种GaN基LED芯片，该芯片的ITO透明电极采用本发明ITO薄膜的沉积方法制备而成。在进行ITO透明电极的沉积时，由于采用本发明的ITO薄膜的沉积方法，有效降低了溅射粒子对GaN基片表面轰击造成的损伤，降低ITO透明电极与GaN基片之间的接触电阻，降低了LED芯片的能耗，增加LED芯片的光电转化效率，提高了LED芯片的寿命。

Description

ITO薄膜的沉积方法及GaN基LED芯片 技术领域
本发明涉及半导体制造领域，特别是涉及一种ITO(indium tin oxide，氧化铟锡)薄膜的沉积方法及GaN基LED芯片。
背景技术
近年来，随着发光二极管(light emitting diode，LED)技术的不断成熟，GaN基LED芯片被广泛应用于大功率照明、汽车仪表显示、大面积的户外显示屏、信号灯以及普通照明等不同领域。在LED芯片的制造过程中，ITO薄膜由于具有可见光透过率高、导电性好、抗磨损及耐腐蚀等优点被广泛应用于GaN基LED芯片的透明导电层。
在ITO薄膜的制备方面，与传统的蒸镀工艺相比，磁控溅射技术制备的ITO薄膜不仅能够提升LED芯片的出光效率，而且能够降低生产消耗。此外，磁控溅射制备的ITO薄膜还具有更低的电阻率、更高的透过率、更高的折射率及更致密等优点。因此，一般用磁控溅射技术在外延层P-GaN表面沉积ITO透明导电层来制备LED。
在传统的磁控溅射ITO薄膜沉积中，一般采取直流(Direct Current，DC)溅射方式。基片(如P-GaN基片)传输至磁控溅射仪的腔室后，抽真空，然后通入工艺气体，在靶材上施加DC功率启辉溅射，直至沉积ITO薄膜至所需厚度。
然而,在上述传统的ITO薄膜沉积过程中，启辉瞬间靶材的负偏压过高(约为-1000V)，维持溅射时靶材的偏压依然很高(约-260V)。由于磁控溅射主要是依靠溅射粒子沉积成膜，较高的瞬时电压和维持电压会使启辉瞬间和溅射过程中溅射粒子能量过高，对P-GaN基片的轰击较大，从而损伤P-GaN基片表面，导致ITO薄膜与P-GaN的欧姆接触 电阻升高，而较高的欧姆接触电阻会导致LED芯片具有较高的驱动电压并使LED芯片产生更多的热量，最终造成LED芯片能耗过高、电光转换效率降低甚至造成LED芯片的报废；此外，较高的瞬时电压和维持电压容易使靶材发生“中毒”而产生节瘤Nodule。因此，如何降低溅射过程中的电压成为了利用磁控溅射方式制备优良ITO薄膜所需要克服的技术难点之一。
发明内容
基于上述问题，本发明提供了一种ITO薄膜的沉积方法，有效减小了ITO薄膜沉积过程中对基片表面造成的损伤。同时，本发明还提供了一种GaN基LED芯片。
为达到上述技术效果，本发明提供了：
一种ITO薄膜的沉积方法，包括以下步骤：
S100，利用射频和直流共溅射在基片表面沉积ITO缓冲层；
S200，利用直流溅射在所述ITO缓冲层表面沉积ITO薄膜层。
作为一种可实施方式，所述步骤S100中，靶材的偏压为-5V～-150V。
作为一种可实施方式，所述步骤S100中，射频功率为100W～600W，直流功率为5W～50W；
所述步骤S200中，直流功率为300～800W。
作为一种可实施方式，所述ITO缓冲层与所述ITO薄膜层的沉积厚度之比为1:1.6～20。
作为一种可实施方式，所述ITO缓冲层的沉积厚度为10nm～50nm，所述ITO薄膜层的沉积厚度为80nm～200nm。
作为一种可实施方式，在所述步骤S100和S200中，还包括以下步骤：
向反应腔室中通入氧气和氩气；其中，通入的氧气流量为1sccm～ 10sccm，通入的氩气流量为150sccm～250sccm。
作为一种可实施方式，在所述步骤S100中，采用如下工艺参数：通入的氧气流量为5sccm，通入的氩气流量为200sccm；使用的直流功率为10W，使用的射频功率为300W。
作为一种可实施方式，在所述步骤S200中，采用如下工艺参数：通入的氧气流量为5sccm，通入的氩气流量为200sccm；使用的直流功率为500W。
作为一种可实施方式，所述ITO缓冲层的厚度为20nm，所述ITO薄膜层的厚度为100nm。
本发明还提供一种GaN基LED芯片，包括ITO透明电极，所述ITO透明电极采用上述的ITO薄膜的沉积方法制备而成。
本发明的有益效果如下：
本发明的ITO薄膜的沉积方法，采用磁控溅射工艺进行ITO薄膜的沉积：首先利用射频(Radio Frequency，RF)和直流(Direct Current，DC)共溅射在基片表面沉积一层ITO缓冲层，然后再利用直流溅射在ITO缓冲层表面沉积一层ITO薄膜层。相对于现有技术中利用直流直接溅射形成ITO薄膜的方式而言，本发明在利用直流形成ITO薄膜层之前，增加了射频与直流共溅射形成ITO缓冲层的步骤，由于射频的感应产生大量带电粒子，从而增加了溅射产生的等离子体的电流密度，在同等功率下，大大降低了溅射沉积ITO薄膜过程中的启辉电压，大大减小了粒子能量，从而使粒子在基片成膜时轰击很小；而在后续的利用直流溅射沉积ITO薄膜层的过程中，由于ITO缓冲层的存在，将基片表面隔绝，有效降低了高能量的溅射粒子对基片表面轰击造成的损伤；此外，本发明中射频与直流共溅射可有效降低靶材产生节瘤的几率。
此外，本发明还提供了一种GaN基LED芯片，该芯片的ITO透明电极采用本发明的ITO薄膜的沉积方法制备而成。在进行ITO透明电 极的沉积时，由于采用本发明的ITO薄膜的沉积方法，有效降低了溅射粒子对GaN基片表面轰击造成的损伤，从而降低了ITO透明电极与GaN基片之间的接触电阻，进而降低了LED芯片的能耗，增加了LED芯片的光电转化效率，提高了LED芯片的寿命。
附图说明
图1为本发明ITO薄膜的沉积方法的流程图。
具体实施方式
下面将结合实施例来详细说明本发明。需要说明的是，在不冲突的情况下，本申请中的实施例及实施例中的特征可以相互组合。
本发明提供了一种ITO薄膜的沉积方法，采用磁控溅射工艺进行ITO薄膜的沉积。参见图1，本发明的ITO薄膜的沉积方法包括以下步骤：
S100：利用射频(RF)和直流(DC)共溅射在基片表面沉积一层ITO缓冲层；
S200，利用DC溅射在ITO缓冲层表面沉积一层ITO薄膜层。
其中，基片可为GaN薄膜，也可为GaAs薄膜、GdS薄膜或SiO2薄膜等。
磁控溅射的成膜机理为：反应腔室中的工艺气体在一定的电压下放电产生等离子体，等离子体轰击靶材产生溅射粒子，溅射粒子沉积在基片的表面，形成薄膜。
以下对步骤S100进行详细介绍。
步骤S100中，通过RF和DC共溅射在基片表面沉积一层ITO缓冲层，所谓RF和DC共溅射是指在靶材上同时施加RF偏压和DC偏压。由于RF偏压的感应，在靶材周围产生了大量带电粒子，大大增加了靶 材周围溅射粒子的电流密度，与纯粹的DC溅射相比，同等功率下，本发明提供的ITO薄膜的沉积方法大幅度减小了启辉电压和溅射过程中靶材的偏压，从而减小了溅射粒子的能量，降低了溅射粒子在基片上沉积时的轰击力度，进而有效降低了溅射粒子对基片表面造成的损伤，防止了溅射粒子对基片表面的掺杂结构的破坏。
此外，在现有技术利用直流直接溅射形成ITO薄膜的过程中，靶材容易发生“中毒”而产生节瘤Nodule，本发明中的RF和DC共溅射可有效降低靶材“中毒”的几率。
步骤S100中，靶材的偏压直接影响到溅射粒子的能量。靶材偏压越大，溅射粒子的能量越高，沉积时对基片表面的轰击力度越大；靶材偏压越小，溅射粒子的能量越低，沉积时对基片表面的轰击力度越小。为了避免溅射粒子对基片表面造成损伤，作为优选，靶材的偏压为-5V～-150V。
步骤S100中，RF功率和DC功率可调，通过调整RF功率和DC功率的比值可调整靶材的偏压。一般情况下，RF功率越大，靶材的偏压越小；DC功率越小，靶材的偏压也越小。为了保证靶材的偏压维持在较低的水平，步骤S100中，RF功率为100W～600W，DC功率为5W～50W。
步骤S100中，所沉积的ITO缓冲层会受到基片表面的偏压的影响。如基片表面的偏压会影响所沉积的ITO缓冲层的应力，一般情况下，基片表面的偏压越小，沉积的ITO缓冲层的应力越低。因此，在磁控溅射过程中应尽量将基片表面的偏压调至最低。RF功率会在基片上产生一个正向偏压，DC功率会在基片上产生一个负向偏压，通过调整RF功率和DC功率的比值可使基片表面的偏压为零或者很小。在其中一个实施例中，当RF功率为300W，DC功率为10W时，基片表面的偏压为0V～5V。
步骤S100中，在基片表面沉积的ITO缓冲层主要起到缓冲和保护作用。优选地，为确保能够有效地防止在后续步骤S200中对基片表面的损伤，ITO缓冲层的厚度应不少于10nm，具体厚度范围为10nm～50nm。
需要说明的是，在步骤S100中，还可通过调整ITO缓冲层沉积时的缓冲层温度、氧含量、沉积速率和沉积时间等工艺参数来调整ITO缓冲层的厚度和电学性质，从而达到降低ITO缓冲层与基片之间的欧姆接触电阻的目的。其中，缓冲层温度是指沉积在基片上的缓冲层的温度，可通过承载基片的加热器或者带加热功能的底座达到该温度要求，该温度对ITO缓冲层的电阻和致密度影响较大，在一定范围内，温度越高，ITO缓冲层的方块电阻越小，致密度越高；氧含量主要控制ITO缓冲层的成分，从而影响缓冲层的性能；沉积速率主要通过RF/DC的功率来进行调整，一般情况下，RF/DC的功率越大，沉积速率越大。
以下对步骤S200进行详细介绍。
在ITO缓冲层沉积完毕后，将RF与DC共溅射转换为DC溅射，利用DC溅射在ITO缓冲层的表面沉积一层ITO薄膜层。在ITO薄膜层的沉积过程中，由于ITO缓冲层的存在，将ITO薄膜层与基片的表面隔绝，可防止在ITO薄膜层沉积过程中使基片表面受到高能量的溅射粒子的轰击，因此，大大减小甚至完全避免了溅射粒子轰击对基片表面造成的损伤。
步骤S200中，为满足工艺需求，DC功率优选为300W～800W。
在其中一个实施例中，ITO薄膜层的沉积厚度为80nm～200nm。较佳地，作为一种可实施方式，ITO缓冲层与所述ITO薄膜层的沉积厚度之比为1:1.6～20。
作为一种可实施方式，在上述步骤S100和S200中，磁控溅射所使用的靶材不变，即采用同一个靶材进行ITO缓冲层和ITO薄膜层的沉 积。由于采用同一个靶材，ITO缓冲层和ITO薄膜层的成分一致，均含有铟、锡和氧元素；但是，由于受到氧含量、溅射电压等工艺参数的影响，ITO缓冲层和ITO薄膜层的微观结构可以一致，也可以不一致。
在上述步骤S100和S200中，需要向反应腔室中通入气体来完成ITO缓冲层和ITO薄膜层的沉积。一般情况下，工艺气体为氩气，其具有稳定的化学性质，不易与其它物质发生反应。另外，由于ITO材质中含有氧元素，而氧原子性质较为活泼而不易沉积，因此，在沉积过程中，需要补充氧气来增加氧原子的浓度。因此，作为一种可实施方式，在ITO缓冲层和ITO薄膜层的沉积过程中，向反应腔室中通入氧气和氩气作为工艺气体，其中，通入的氧气流量为1sccm～10sccm，通入的氩气流量为150sccm～250sccm。
与传统方法相比，本发明的ITO薄膜的沉积方法，首先通过直流和射频共溅射在基片上沉积一层ITO缓冲层，再利用直流溅射沉积一层ITO薄膜层。在利用直流溅射沉积ITO薄膜层的过程中，由于ITO缓冲层的存在，有效降低了溅射粒子对基片表面轰击造成的损伤。
以下通过一个具体的实施例来详细说明本发明。
实施例1
利用磁控溅射设备来进行ITO薄膜的沉积，磁控溅射设备的使用方法为本技术领域人员通用手段，因而在本发明中不做赘述。本实施例中采用P-GaN基片来进行ITO薄膜的沉积，包括以下四个步骤：
(1)向工艺腔室中通入氧气和氩气，氧气流量为5sccm，氩气流量为200sccm；
(2)沉积ITO缓冲层：持续向腔室内通入5sccm的氧气和200sccm的氩气；同时在靶材上施加DC功率和RF功率，其中，DC功率为10W，RF功率为300W；
该工艺参数下，在P-GaN基片的表面沉积一层厚度为20nm的ITO 缓冲层。
(3)沉积ITO薄膜层：持续向腔室内通入5sccm的氧气和200sccm的氩气；同时在靶材上施加500W的DC功率；在ITO缓冲层的表面沉积厚度为100nm的ITO薄膜层；
(4)工艺完毕，停止通气，同时切断电源。
步骤(2)中，当DC功率为10W，RF功率为300W时，靶材的偏压为-15V，有效避免了溅射粒子能量过高对P-GaN基片表面造成的损伤；同时，当DC功率为10W，RF功率为300W时，P-GaN基片的偏压为0～5V，使得沉积的ITO缓冲层具有较低的应力，增加了ITO缓冲层的薄膜质量；并且，当DC功率为10W，RF功率为300W时，所沉积的ITO缓冲层与P-GaN基片之间具有较低的欧姆接触电阻。
步骤(3)中，在进行ITO薄膜层的沉积时，由DC和RF共溅射转变为DC溅射，靶材的偏压升高，溅射离子能量也随之升高，但是，由于ITO缓冲层的保护作用，使得高能量的溅射离子不能直接轰击到P-GaN基片表面，因此，有效防止了P-GaN基片的表面损伤，有利于得到性能优异的产品。
需要说明的是，在实施例1中，DC功率、RF功率、氩气流量、氧气流量以及ITO缓冲层的厚度和ITO薄膜层的厚度均可根据工艺需要进行调整。
本发明还提供了一种GaN基LED芯片，其电极采用ITO透明电极，且该ITO透明电极利用本发明的ITO薄膜的沉积方法制备而成。在进行ITO透明电极的沉积时，由于采用本发明的ITO薄膜的沉积方法，有效降低了溅射粒子对GaN基片表面轰击造成的损伤，从而降低了ITO透明电极与GaN基片之间的接触电阻，进而降低了LED芯片的能耗，增加了LED芯片的光电转化效率，提高了LED芯片的寿命。
以上所述实施例仅表达了本发明的几种实施方式，其描述较为具体 和详细，但并不能因此而理解为对本发明专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本发明构思的前提下，还可以做出若干变形和改进，这些都属于本发明的保护范围。因此，本发明专利的保护范围应以所附权利要求为准。

Claims (10)

  1. 一种ITO薄膜的沉积方法，其特征在于，包括以下步骤：
    S100，利用射频和直流共溅射在基片表面沉积ITO缓冲层；
    S200，利用直流溅射在所述ITO缓冲层表面沉积ITO薄膜层。
  2. 根据权利要求1所述的ITO薄膜的沉积方法，其特征在于，所述步骤S100中，靶材的偏压为-5V～-150V。
  3. 根据权利要求1所述的ITO薄膜的沉积方法，其特征在于，所述步骤S100中，射频功率为100W～600W，直流功率为5W～50W；
    所述步骤S200中，直流功率为300～800W。
  4. 根据权利要求1所述的ITO薄膜的沉积方法，其特征在于，所述ITO缓冲层与所述ITO薄膜层的沉积厚度之比为1:1.6～20。
  5. 根据权利要求1所述的ITO薄膜的沉积方法，其特征在于，所述ITO缓冲层的沉积厚度为10nm～50nm，所述ITO薄膜层的沉积厚度为80nm～200nm。
  6. 根据权利要求1所述的ITO薄膜的沉积方法，其特征在于，在所述步骤S100和S200中，还包括以下步骤：
    向反应腔室中通入氧气和氩气；其中，通入的氧气流量为1sccm～10sccm，通入的氩气流量为150sccm～250sccm。
  7. 根据权利要求6所述的ITO薄膜的沉积方法，其特征在于，在所述步骤S100中，采用如下工艺参数：通入的氧气流量为5sccm，通入的氩气 流量为200sccm；使用的直流功率为10W，使用的射频功率为300W。
  8. 根据权利要求6所述的ITO薄膜的沉积方法，其特征在于，
    在所述步骤S200中，采用如下工艺参数：通入的氧气流量为5sccm，通入的氩气流量为200sccm；使用的直流功率为500W。
  9. 根据权利要求7或8所述的ITO薄膜的沉积方法，其特征在于，所述ITO缓冲层的厚度为20nm，所述ITO薄膜层的厚度为100nm。
  10. 一种GaN基LED芯片，包括ITO透明电极，其特征在于，所述ITO透明电极采用权利要求1～9任一项所述的ITO薄膜的沉积方法制备而成。
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