WO2015192552A1 - 低温多晶硅薄膜的制造方法、tft、阵列基板及显示装置 - Google Patents

低温多晶硅薄膜的制造方法、tft、阵列基板及显示装置 Download PDF

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WO2015192552A1
WO2015192552A1 PCT/CN2014/088417 CN2014088417W WO2015192552A1 WO 2015192552 A1 WO2015192552 A1 WO 2015192552A1 CN 2014088417 W CN2014088417 W CN 2014088417W WO 2015192552 A1 WO2015192552 A1 WO 2015192552A1
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temperature polysilicon
amorphous silicon
silicon layer
layer
low temperature
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王志强
康峰
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BOE Technology Group Co Ltd
Ordos Yuansheng Optoelectronics Co Ltd
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BOE Technology Group Co Ltd
Ordos Yuansheng Optoelectronics Co Ltd
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/29—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by the substrates
    • H10P14/2901—Materials
    • H10P14/2921—Materials being crystalline insulating materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • H10D30/6731—Top-gate only TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6741—Group IV materials, e.g. germanium or silicon carbide
    • H10D30/6743—Silicon
    • H10D30/6745—Polycrystalline or microcrystalline silicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/421—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/34—Deposited materials, e.g. layers
    • H10P14/3402—Deposited materials, e.g. layers characterised by the chemical composition
    • H10P14/3404—Deposited materials, e.g. layers characterised by the chemical composition being Group IVA materials
    • H10P14/3411—Silicon, silicon germanium or germanium
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/34—Deposited materials, e.g. layers
    • H10P14/3451—Structure
    • H10P14/3452—Microstructure
    • H10P14/3456—Polycrystalline
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/36—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by treatments done before the formation of the materials

Definitions

  • Embodiments of the present invention relate to a method of fabricating a low temperature polysilicon film, a TFT, an array substrate, and a display device.
  • the TFT-LCD is limited by the temperature of the glass substrate and cannot be subjected to a high temperature process.
  • the amorphous silicon layer can be crystallized by a XeCl laser. Because the amorphous silicon layer has a strong absorption efficiency for a laser of 308 nm wavelength, and the laser has a penetration depth of only 20 nm inside the amorphous silicon layer, which can effectively protect the substrate (such as a glass substrate), the excimer laser crystal It has become one of the mainstream technologies of Low Temperature Poly-silicon (LTPS) and has been widely used.
  • LTPS Low Temperature Poly-silicon
  • Embodiments of the present invention provide a method for fabricating a low-temperature polysilicon film, comprising forming an amorphous silicon layer on a substrate, protecting a region of the source electrode and the drain electrode on the amorphous silicon layer with a mask, and patterning by dry etching After the crystallization treatment, a low temperature polysilicon layer is formed.
  • the crystallization is laterally induced crystallization.
  • an amorphous silicon layer is formed on a substrate by vapor deposition (PECVD).
  • PECVD vapor deposition
  • the amorphous silicon layer has a thickness of 48-52 nm.
  • the thickness of the amorphous silicon layer is 50 nm.
  • the dry etching has a depth of 3-5 nm.
  • the substrate is a glass substrate or a quartz substrate.
  • the substrate is a glass substrate.
  • the method further includes post-processing that planarizes the surface of the low temperature polysilicon layer.
  • the post-treatment includes, but is not limited to, a mask plate prepared by pre-processing with an amorphous silicon layer, and dry etching is performed with a reverse PR paste to planarize the surface of the low-temperature polysilicon layer.
  • Embodiments of the present invention provide a low temperature polysilicon film produced by the above method.
  • Embodiments of the present invention also provide a low temperature polysilicon thin film transistor including a substrate, an amorphous silicon layer formed on the substrate, and a low temperature polysilicon layer, which protects the source electrode and the leakage current on the amorphous silicon layer through the mask
  • the region where the electrode is located is patterned by dry etching and then formed by crystallization.
  • the thin film transistor further includes a gate insulating layer, a gate electrode, an interlayer insulating layer, and a source electrode and a drain electrode which are sequentially formed over the low temperature polysilicon layer, and the source electrode and the drain electrode respectively pass through the through layer
  • the interlayer insulating layer and the gate insulating layer via are connected to both ends of the low temperature polysilicon layer.
  • Embodiments of the present invention also provide an array substrate including the low temperature polysilicon thin film transistor.
  • Embodiments of the present invention also provide a display device including the above array substrate.
  • Figure 1 is a plan view of a mask pattern of the present invention
  • FIG. 2 is a schematic view showing the structure of an amorphous silicon layer after patterning according to the present invention.
  • the use of an additional insulating layer (SiO 2 ) and an increase in the external temperature to increase the grain size of the amorphous silicon layer are mainly utilized.
  • a crystallization temperature gradient is used to control the size of the grain growth.
  • the above method does not mention how to control the size and number of crystal grains in the TFT channel layer, and how to solve the local electrical characteristics in the large-area device.
  • the local electrical characteristics are not uniform in large-area devices, mainly referring to the integration. In TFT devices, the distribution of crystal grains in each channel has a certain randomness.
  • a method for laterally inducing crystallization of a low temperature polysilicon film according to an embodiment of the present invention
  • the crystalline silicon layer is pretreated, that is, the amorphous silicon layer is first subjected to a mask and dry etching process to make a specific pattern, and the region where the source electrode and the drain electrode are located (SD region) is protected, so that the region is slightly higher than other regions (this When SD is not formed, only the position of SD is made.
  • a seed crystal can be formed under the SD region and grown in the channel direction to achieve uniformity of grain growth.
  • This embodiment provides a method for producing a low-temperature polysilicon film (transverse induced crystallization) to achieve uniform growth of crystal grains.
  • the method includes forming an amorphous silicon layer 2 on a substrate 1, and protecting a region 3 (see FIGS. 1 and 2) of the source electrode and the drain electrode on the amorphous silicon layer 2 by using a mask, and patterning by dry etching. After the crystallization treatment, a low temperature polysilicon layer is formed.
  • the amorphous silicon under the pattern is nearly completely melted, while the other portions are completely melted, and Si grows along the seed crystal under the pattern, which can improve the uniformity of grain growth in each region.
  • the depth of the dry etching can be controlled to be 3-5 nm, and the existing process can be used to implement the process, which is not particularly limited in the present invention.
  • the embodiment of the present invention changes the surface morphology of the amorphous silicon layer by dry etching, and designs a special mask pattern for the conductivity characteristics of each channel layer, and can electrically conduct the whole of the large-area device after the crystallization of the excimer laser.
  • the design of the mask pattern is designed according to the region where the source electrode and the drain electrode are located, such that the source electrode and the drain electrode region 3 are protected non-exposed regions, and the TFT channel region and other portions are designed as the exposure region 4, In order to better promote the grain growth along the seed crystal orientation under the non-exposed area, a high quality low temperature polysilicon layer is obtained.
  • Embodiments of the present invention form an amorphous silicon layer on a substrate by vapor deposition.
  • the forming means can adopt an existing process, and the thickness of the amorphous silicon layer can be selected from 48 to 52 nm, for example, 50 nm.
  • the substrate 1 can be selected from a variety of substrates which can be used for the formation of a polysilicon film, such as a glass substrate, a quartz substrate, etc., and the thickness thereof can be a conventional size.
  • the method further includes post-processing for planarizing the surface of the low temperature polysilicon layer.
  • the planarization process may adopt various specific embodiments, including but not limited to: using a mask plate pretreated with an amorphous silicon layer, and performing dry etching with a reflective PR glue (in reverse manner) ), the surface of the low-temperature polysilicon layer is returned to a flat state, and then the LTPS is followed.
  • the special design of the mask pattern of the embodiment of the invention can ensure the growth of the crystal grain, and at the same time, can simultaneously control the uniformity of the grain size of a large area, and can control the grain size and the number of the channel layer of the TFT. .
  • the low-temperature polysilicon film prepared in the present embodiment has an ideal electrical property.
  • the uniformity of the seed crystal determines the uniformity of the polycrystalline silicon growth (long-range order).
  • the uniform growth of the channel layer crystallized silicon greatly contributes to the stability of the device.
  • the size and number of seed crystals can be adjusted, thereby affecting the size and number of polycrystals after laser crystallization.
  • This embodiment discloses a thin film transistor (TFT) including a substrate and an amorphous silicon layer formed on the substrate.
  • TFT thin film transistor
  • the low-temperature polysilicon thin film transistor described in this embodiment protects the region where the source electrode and the drain electrode are on the amorphous silicon layer by using a mask, forms a pattern by dry etching, and forms a low-temperature polysilicon layer after crystallization treatment.
  • the thin film transistor of this embodiment further includes a gate insulating layer, a gate electrode, an interlayer insulating layer, and a source electrode and a drain electrode which are sequentially formed over the low temperature polysilicon layer, and the source electrode and the drain electrode respectively pass through An interlayer insulating layer and a gate insulating layer via are connected to both ends of the low temperature polysilicon layer.
  • a one-step mask is added before the crystallization process of the amorphous silicon layer, so that the Si outside the pattern grows along the seed crystal under the pattern during the crystallization process, thereby improving the uniformity of grain growth in each region.
  • the electrical characteristics of the thin film transistor are more uniform, such as ensuring convergence of the turn-on voltage, and higher electron mobility.
  • the embodiment provides an array substrate comprising the low temperature polysilicon thin film transistor described in Embodiment 2.
  • the electrical characteristics can be further improved, and the array substrate is suitable for use in Source matrix organic light emitting diode display (AMOLED), low temperature polysilicon thin film transistor liquid crystal display (LTPS TFT-LCD) and other fields.
  • AMOLED Source matrix organic light emitting diode display
  • LTPS TFT-LCD low temperature polysilicon thin film transistor liquid crystal display
  • This embodiment provides a display device including the array substrate described in Embodiment 3.
  • the display device of this embodiment may be an active matrix organic light emitting diode display (AMOLED) or a liquid crystal display or the like. Since the low-temperature polysilicon thin film transistor described in Embodiment 2 is used in the display device, the electrical performance is greatly improved compared with the existing products, and the opening speed of the device (large grain growth of the channel) can be improved, and the image can be applied to 3D. Show the industry to improve the competitiveness of the display device.
  • AMOLED active matrix organic light emitting diode display
  • the advantage of the method is that the low-temperature polysilicon film prepared in the first embodiment is used as an experimental group, and the low-temperature polysilicon film prepared by the conventional method is prepared (that is, the amorphous silicon layer is not pretreated, no mask is added, and the amorphous layer is directly formed.
  • the silicon layer was crystallized to obtain a low-temperature polysilicon layer, and other operating conditions were the same.
  • As a control group the crystallization effects of the experimental group and the control group were compared.
  • the optimized adjustment of the preparation method based on the embodiment of the present invention makes the prepared low-temperature polysilicon film have ideal electrical properties. From a physical point of view, the uniformity of the seed crystal determines the uniformity of the polycrystalline silicon growth (long-range order). The uniform growth of the channel layer crystallized silicon greatly contributes to the stability of the device. By controlling the height difference of the pattern of the region where the source electrode and the drain electrode are located after the dry etching (ie, the SD region), the size and number of the seed crystals can be adjusted, thereby affecting the size and number of polycrystals after laser crystallization. While the invention has been described with respect to the embodiments of the embodiments of the embodiments of the invention It is intended to fall within the scope defined by the appended claims.

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Abstract

一种低温多晶硅薄膜的制造方法、TFT、阵列基板及显示装置。所述低温多晶硅薄膜的制造方法，包括在衬底（1）上形成非晶硅层（2），利用掩膜板保护非晶硅层上源电极和漏电极所在区域（3），经干蚀刻形成图案，再经晶化处理后形成低温多晶硅层。通过对非晶硅层进行预处理，使其形成特定的图案，从而使得在晶化过程中硅沿着图案下的籽晶生长，提高区域晶粒生长的均匀性。

Description

低温多晶硅薄膜的制造方法、TFT、阵列基板及显示装置 技术领域
本发明的实施例涉及一种低温多晶硅薄膜的制造方法、TFT、阵列基板及显示装置。
背景技术
TFT-LCD受玻璃基板温度的限制，不能采用高温工艺。鉴于传统成膜方式温度过高的缺点，可以采用XeCl激光使非晶硅层晶化。因为非晶硅层对308nm波长的激光有很强的吸收效率，并且激光在非晶硅层内部仅有20nm的穿透深度，能够有效的保护衬底(如玻璃基板)，所以准分子激光晶化成为低温多晶硅技术(LTPS，Low Temperature Poly-silicon)的主流技术之一，已被广泛应用。
发明内容
本发明的实施例提供了一种低温多晶硅薄膜的制造方法，包括在衬底上形成非晶硅层，利用掩膜板保护非晶硅层上源电极和漏电极所在区域，经干蚀刻形成图案，再经晶化处理后形成低温多晶硅层。
在一个示例中，所述晶化为横向诱导晶化。
在一个示例中，利用气相沉积法(PECVD)在衬底上形成非晶硅层。
在一个示例中，非晶硅层的厚度为48-52nm。例如非晶硅层的厚度为50nm。
在一个示例中，干蚀刻(曝光处理)的深度为3-5nm。在一个示例中，所述衬底为玻璃基板或石英基板。例如衬底为玻璃基板。
在一个示例中，所述方法还包括对低温多晶硅层表面进行平整化的后处理。所述后处理包括但并不局限于：采用非晶硅层预处理时的掩膜板，以反性PR胶再进行干蚀刻，使低温多晶硅层表面平整化。
本发明的实施例提供了上述方法制作的低温多晶硅薄膜。
本发明的实施例还提供了一种低温多晶硅薄膜晶体管，包括衬底，在衬底上形成的非晶硅层，以及低温多晶硅层，其通过掩膜板保护非晶硅层上源电极和漏电极所在区域，经干蚀刻形成图案，再经晶化处理后形成。
在一个示例中，薄膜晶体管还包括在所述低温多晶硅层的上方依次形成的栅绝缘层、栅电极、层间绝缘层，以及源电极和漏电极，所述源电极和漏电极分别通过贯穿层间绝缘层和栅绝缘层过孔与所述低温多晶硅层的两端相连。
本发明的实施例还提供了一种阵列基板，包含所述低温多晶硅薄膜晶体管。
本发明的实施例还提供了含有上述阵列基板的显示装置。
附图说明
图1为本发明掩膜图案设计图；
图2为本发明形成图案后的非晶硅层结构示意图。
具体实施方式
为了更清楚的描述本方案，以下结合具体的实施例对本发明技术方案作详细说明。显然，所描述的实施例是本发明的一部分实施例，而不是全部的实施例。基于所描述的本发明的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其它实施例，都属于本发明保护的范围。
除非另作定义，本文使用的技术术语或者科学术语应当为本发明所属领域内具有一般技能的人士所理解的通常意义。本发明专利申请说明书以及权利要求书中使用的“一个”、“一”或者“该”等类似词语也不表示数量限制，而是表示存在至少一个。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其它元件或者物件。“上”、“下”、等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
为了尽量使Si晶粒成长为比较接近单晶硅的状态，人们多采用外加保温层(SiO2)和提高外界温度的方法使非晶硅层的晶粒度增加，这两种技术主要是利用晶化温度梯度来控制晶粒生长的大小。但上述方法没有提到如何控制TFT沟道层中晶粒的大小和个数，以及如何解决大面积器件中局部电学特性不均匀(大面积器件中局部电学特性不均匀，主要是指在集成的TFT器件中，每一个沟道中的晶粒的分布都有一定的随机性)的技术缺陷。
根据本发明的实施例的横向诱导晶化低温多晶硅薄膜的方法，通过对非 晶硅层进行预处理，即对非晶硅层先进行一次掩膜和干蚀刻工艺做出特定图案，保护源电极和漏电极所在区域(SD区)，使该区域略高于其它区域(此时SD并未形成，只是做出SD的位置)，通过预处理可以在SD区下方形成籽晶并沿沟道方向生长，实现晶粒生长的均一性。
以下结合具体的实施例对本发明技术方案作详细说明。
实施例1
本实施例提供了一种低温多晶硅薄膜的制造方法(横向诱导晶化)，以实现晶粒的均匀生长。所述方法包括在衬底1上形成非晶硅层2，利用掩膜板保护非晶硅层2上源电极和漏电极所在区域3(见图1和图2)，经干蚀刻形成图案，再经晶化处理后形成低温多晶硅层。
在非晶硅晶化的过程中，图案下的非晶硅接近完全熔融，而其它部分完全熔融，Si沿着图案下的籽晶生长，可以提高各区域晶粒生长的均匀性。
例如，本实施例可以控制干蚀刻的深度为3-5nm，实现工艺可以采用现有工艺，本发明对此不作特别限定。
本发明的实施例通过干蚀刻来改变非晶硅层表面的形貌，针对各沟道层导电的特性设计了特殊的掩膜图案，在准分子激光晶化后可以对大面积器件整体的导电特性有所改善。对于掩膜图案的设计是依据源电极和漏电极所在区域来设计的，使源电极和漏电极所在区域3为受保护的非曝光区域，TFT沟道区和其他部分则设计为曝光区4，以更好地促成晶粒沿非曝光区域下方的籽晶定向均匀生长，得到高质量的低温多晶硅层。
本发明的实施例利用气相沉积法在衬底上形成非晶硅层。形成手段可以采用现有工艺，非晶硅层的厚度可选48-52nm，例如为50nm。
衬底1可以选择多种可用于多晶硅薄膜形成的衬底，如玻璃基板、石英基板等，其厚度可以采用常规尺寸。
此外，所述方法还包括对低温多晶硅层的表面进行平整化的后处理。所述平整化处理可采用多种具体实施方案，包括但并不局限于：采用非晶硅层预处理时的掩膜板，以反性PR胶(photoresist)再进行干蚀刻(按反方式进行)，使低温多晶硅层表面回归到平坦的状态，再进行LTPS后续工作。
本发明的实施例对掩膜图案的特殊设计，使晶粒的增长能够得到保证，同时还能兼顾到大面积晶粒均匀性的控制，同时能够控制TFT沟道层中晶粒大小和个数。
基于本实施例对制备方法的改进，本实施例制备得到的低温多晶硅薄膜具有理想的电学性能，从物理角度考虑，籽晶的均匀性，决定了以后多晶硅生长的均匀性(长程有序)。沟道层晶化硅的均匀生长对器件的稳定性有很大帮助。通过控制干蚀刻后SD区图形的高度差，可以调整籽晶的大小和个数，从而影响激光晶化后多晶的大小和个数。
实施例2
本实施例公开了一种薄膜晶体管(TFT)，该薄膜晶体管包括衬底，以及在衬底上形成的非晶硅层。本实施例所述的低温多晶硅薄膜晶体管利用掩膜板保护非晶硅层上源电极和漏电极所在区域，经干蚀刻形成图案，再经晶化处理后形成低温多晶硅层。
本实施例所述的薄膜晶体管还包括在所述低温多晶硅层的上方依次形成的栅绝缘层、栅电极、层间绝缘层，以及源电极和漏电极，所述源电极和漏电极分别通过贯穿层间绝缘层和栅绝缘层过孔与所述低温多晶硅层的两端相连。
本实施例在非晶硅层的晶化过程前先加设一步掩膜，使晶化过程中，图案外的Si沿着图案下的籽晶生长，提高各区域的晶粒生长的均匀性。应用至薄膜晶体管后，使薄膜晶体管(大面积)电学特性更均一，如保证开启电压的收敛性，同时具有更高的电子迁移率等。
实施例3
本实施例提供了一种阵列基板，该阵列基板包括实施例2中所述的低温多晶硅薄膜晶体管，由此形成的阵列基板用于显示器背板中时，能够进一步改善其电学特性，适用于有源矩阵有机发光二极管显示器(AMOLED)、低温多晶硅薄膜晶体管液晶显示器(LTPS TFT-LCD)等领域。
实施例4
本实施例提供一种显示装置，该显示装置包括实施例3中所述的阵列基板。本实施例的显示装置，可以为有源矩阵有机发光二极管显示器(AMOLED)或者液晶显示器等。由于该显示装置中采用了实施例2所述的低温多晶硅薄膜晶体管，在电学性能方面较现有产品有很大改善，能够提高器件的开启速度(沟道大晶粒生长)，可应用于3D显示行业，提高该显示装置的竞争能力。
试验例1
为了进一步验证本发明的实施例所述横向诱导晶化低温多晶硅薄膜的方 法的优势，以实施例1所制备得到的低温多晶硅薄膜作为实验组，以常规方法制备得到的低温多晶硅薄膜(即对非晶硅层不进行预处理，不加设掩膜，直接对非晶硅层进行晶化处理得到低温多晶硅层，其他操作条件相同)作为对照组，进行实验组与对照组的晶化效果对比。
利用扫描电镜(SEM)进行观察(先利用重铬酸和氢氟酸进行表面处理，使晶界更清晰，再用SEM观察表面形貌)，观察后的结果表明，实验组晶粒在每一栅极(Gate)对应的多晶硅(P-Si)位置集中分布且晶粒较大，而对照组发现晶粒呈无归分布方式且晶粒大小无法在特定区域控制。
基于本发明的实施例对制备方法的优化调整，使所制备得到的低温多晶硅薄膜具有理想的电学性能。从物理角度考虑，籽晶的均匀性，决定了以后多晶硅生长的均匀性(长程有序)。沟道层晶化硅的均匀生长对器件的稳定性有很大帮助。通过控制干蚀刻后源电极和漏电极所在区域(即SD区)图形的高度差，可以调整籽晶的大小和个数，从而影响激光晶化后多晶的大小和个数。虽然结合附图描述了本发明的示例性实施例，但是本领域普通技术人员在不脱离本发明的精神和范围的情况下可以作出各种修改和变型，这样的修改和变型及其等同方式均落入由所附权利要求所限定的范围之内。
本申请要求于2014年06月20日提交的名称为“低温多晶硅薄膜的制造方法、TFT、阵列基板及显示装置”的中国专利申请No.201410281754.9的优先权，其全文以引用方式合并于本文。

Claims (11)

  1. 一种低温多晶硅薄膜的制造方法，包括：
    在衬底上形成非晶硅层，
    利用掩膜板保护非晶硅层上源电极和漏电极所在区域，经干蚀刻形成图案，再经晶化处理后形成低温多晶硅层。
  2. 根据权利要求1所述的制造方法，其中所述非晶硅层的厚度为48-52nm。
  3. 根据权利要求1或2所述的制造方法，其中所述非晶硅层的厚度为50nm。
  4. 根据权利要求1所述的制造方法，其中所述干蚀刻的深度为3-5nm。
  5. 根据权利要求1-4任一项所述的制造方法，其中所述衬底为玻璃基板或石英基板。
  6. 根据权利要求1-5任一项所述的制造方法，还包括对低温多晶硅层表面进行平整化的后处理。
  7. 根据权利要求6所述的制造方法，所述后处理包括：采用非晶硅层预处理时的掩膜板，以反性PR胶再进行干蚀刻，使低温多晶硅层表面平整化。
  8. 一种低温多晶硅薄膜晶体管，包括：
    衬底，
    在衬底上形成的非晶硅层，以及
    低温多晶硅层，其通过掩膜板保护非晶硅层上源电极和漏电极所在区域，经干蚀刻形成图案，再经晶化处理后形成。
  9. 根据权利要求8所述的低温多晶硅薄膜晶体管，还包括在所述低温多晶硅层的上方依次形成的栅绝缘层、栅电极、层间绝缘层，以及源电极和漏电极，其中所述源电极和漏电极分别通过贯穿层间绝缘层和栅绝缘层过孔与所述低温多晶硅层的两端相连。
  10. 一种阵列基板，包含权利要求8或9所述的低温多晶硅薄膜晶体管。
  11. 一种显示装置，包含权利要求10所述的阵列基板。
PCT/CN2014/088417 2014-06-20 2014-10-11 低温多晶硅薄膜的制造方法、tft、阵列基板及显示装置 Ceased WO2015192552A1 (zh)

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