WO2015190852A1 - Fet à canal contraint à plusieurs nanofeuilles cristallines et leurs procédés de fabrication - Google Patents

Fet à canal contraint à plusieurs nanofeuilles cristallines et leurs procédés de fabrication Download PDF

Info

Publication number
WO2015190852A1
WO2015190852A1 PCT/KR2015/005902 KR2015005902W WO2015190852A1 WO 2015190852 A1 WO2015190852 A1 WO 2015190852A1 KR 2015005902 W KR2015005902 W KR 2015005902W WO 2015190852 A1 WO2015190852 A1 WO 2015190852A1
Authority
WO
WIPO (PCT)
Prior art keywords
gate
layer
layers
channel
crystalline
Prior art date
Application number
PCT/KR2015/005902
Other languages
English (en)
Inventor
Borna J OBRADOVIC
Robert C. Bowen
Mark S RODDER
Original Assignee
Samsung Electronics Co., Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US14/729,652 external-priority patent/US9570609B2/en
Application filed by Samsung Electronics Co., Ltd. filed Critical Samsung Electronics Co., Ltd.
Priority to CN201580029454.4A priority Critical patent/CN106463543B/zh
Publication of WO2015190852A1 publication Critical patent/WO2015190852A1/fr

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312Gate electrodes for field effect devices
    • H01L29/42316Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42384Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
    • H01L29/42392Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor fully surrounding the channel, e.g. gate-all-around
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/786Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78696Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel

Abstract

L'invention concerne un transistor à effet de champ qui inclut une couche de corps comportant une zone de canal semi-conductrice cristalline contrainte, et un empilement de grille sur la zone de canal. L'empilement de grille inclut une couche de grille semi-conductrice cristalline dont le réseau cristallin est différent de celui de la zone de canal, et une couche diélectrique de grille cristalline entre la couche de grille et la zone de canal. L'invention concerne également des dispositifs et procédés de fabrication associés.
PCT/KR2015/005902 2014-06-11 2015-06-11 Fet à canal contraint à plusieurs nanofeuilles cristallines et leurs procédés de fabrication WO2015190852A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201580029454.4A CN106463543B (zh) 2014-06-11 2015-06-11 结晶多纳米片应变沟道fet及其制造方法

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US201462010585P 2014-06-11 2014-06-11
US62/010,585 2014-06-11
US14/729,652 2015-06-03
US14/729,652 US9570609B2 (en) 2013-11-01 2015-06-03 Crystalline multiple-nanosheet strained channel FETs and methods of fabricating the same

Publications (1)

Publication Number Publication Date
WO2015190852A1 true WO2015190852A1 (fr) 2015-12-17

Family

ID=54833856

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/KR2015/005902 WO2015190852A1 (fr) 2014-06-11 2015-06-11 Fet à canal contraint à plusieurs nanofeuilles cristallines et leurs procédés de fabrication

Country Status (4)

Country Link
KR (1) KR102223971B1 (fr)
CN (1) CN106463543B (fr)
TW (1) TWI685972B (fr)
WO (1) WO2015190852A1 (fr)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9905643B1 (en) 2016-08-26 2018-02-27 International Business Machines Corporation Vertically aligned nanowire channels with source/drain interconnects for nanosheet transistors
CN108695377A (zh) * 2017-04-05 2018-10-23 三星电子株式会社 半导体装置
CN109427871A (zh) * 2017-08-29 2019-03-05 三星电子株式会社 半导体装置
US10651291B2 (en) 2017-08-18 2020-05-12 Globalfoundries Inc. Inner spacer formation in a nanosheet field-effect transistor
EP3719851A3 (fr) * 2019-03-13 2020-12-30 United Microelectronics Corp. Structure semi-conductrice et procédé associé
WO2023010980A1 (fr) * 2021-08-05 2023-02-09 International Business Machines Corporation Dispositifs à transistors à effet de champ complémentaires
US11705504B2 (en) 2021-12-02 2023-07-18 International Business Machines Corporation Stacked nanosheet transistor with defect free channel

Families Citing this family (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9461114B2 (en) * 2014-12-05 2016-10-04 Samsung Electronics Co., Ltd. Semiconductor devices with structures for suppression of parasitic bipolar effect in stacked nanosheet FETs and methods of fabricating the same
CN106409907B (zh) * 2015-08-03 2021-06-08 三星电子株式会社 用于半导体装置的堆叠件及其形成方法
KR102435521B1 (ko) * 2016-02-29 2022-08-23 삼성전자주식회사 반도체 소자
US9978833B2 (en) * 2016-03-11 2018-05-22 Samsung Electronics Co., Ltd. Methods for varied strain on nano-scale field effect transistor devices
JP6780015B2 (ja) 2016-04-25 2020-11-04 アプライド マテリアルズ インコーポレイテッドApplied Materials,Incorporated 水平ゲートオールアラウンドデバイスのナノワイヤの空隙スペーサ形成
US9882000B2 (en) * 2016-05-24 2018-01-30 Northrop Grumman Systems Corporation Wrap around gate field effect transistor (WAGFET)
US9853114B1 (en) * 2016-10-24 2017-12-26 Samsung Electronics Co., Ltd. Field effect transistor with stacked nanowire-like channels and methods of manufacturing the same
US10008603B2 (en) * 2016-11-18 2018-06-26 Taiwan Semiconductor Manufacturing Co., Ltd. Multi-gate device and method of fabrication thereof
EP3369702A1 (fr) * 2017-03-03 2018-09-05 IMEC vzw Espaceurs internes pour dispositifs semi-conducteurs à nanofils
US9947804B1 (en) * 2017-07-24 2018-04-17 Globalfoundries Inc. Methods of forming nanosheet transistor with dielectric isolation of source-drain regions and related structure
CN207458949U (zh) * 2017-09-26 2018-06-05 京东方科技集团股份有限公司 薄膜晶体管、阵列基板和显示装置
US10566330B2 (en) * 2017-12-11 2020-02-18 Samsung Electronics Co., Ltd. Dielectric separation of partial GAA FETs
US10304833B1 (en) * 2018-02-19 2019-05-28 Globalfoundries Inc. Method of forming complementary nano-sheet/wire transistor devices with same depth contacts
US11101359B2 (en) 2018-11-28 2021-08-24 Taiwan Semiconductor Manufacturing Company, Ltd. Gate-all-around (GAA) method and devices
US11348803B2 (en) * 2019-05-20 2022-05-31 Applied Materials, Inc. Formation of bottom isolation
KR102183131B1 (ko) * 2019-06-24 2020-11-26 포항공과대학교 산학협력단 에피텍셜 구조를 갖는 소스/드레인 영역이 축소된 전계효과 트랜지스터 및 이의 제조방법
CN112582265B (zh) * 2019-09-27 2023-06-02 中芯国际集成电路制造(上海)有限公司 半导体结构及其形成方法
CN112885901B (zh) * 2021-04-29 2021-07-30 中芯集成电路制造(绍兴)有限公司 高电子迁移率晶体管及其形成方法
CN113284806B (zh) * 2021-05-18 2022-04-05 复旦大学 环栅器件及其源漏制备方法、器件制备方法、电子设备
WO2022241630A1 (fr) * 2021-05-18 2022-11-24 复旦大学 Dispositif à grille enrobante et son procédé de préparation de source/drain, procédé de préparation de dispositif et dispositif électronique
WO2023035269A1 (fr) * 2021-09-13 2023-03-16 上海集成电路制造创新中心有限公司 Dispositif à grille enrobante et son procédé de préparation de source/drain, procédé de préparation de dispositif et dispositif électronique
US11837604B2 (en) 2021-09-22 2023-12-05 International Business Machine Corporation Forming stacked nanosheet semiconductor devices with optimal crystalline orientations around devices
US20230086888A1 (en) * 2021-09-23 2023-03-23 International Business Machines Corporation Dual strained semiconductor substrate and patterning

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060043421A1 (en) * 2004-09-01 2006-03-02 International Business Machines Corporation Multi-gate device with high k dielectric for channel top surface
JP2006093717A (ja) * 2004-09-25 2006-04-06 Samsung Electronics Co Ltd 変形されたチャンネル層を有する電界効果トランジスタ及びその製造方法
US20080258203A1 (en) * 2007-04-19 2008-10-23 Thomas Happ Stacked sonos memory
US20100068862A1 (en) * 2005-03-24 2010-03-18 Samsung Electronics Co., Ltd. Semiconductor device having a round-shaped nano-wire transistor channel and method of manufacturing same
US20130270607A1 (en) * 2012-04-11 2013-10-17 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor Device Channel System and Method

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1555688B1 (fr) * 2004-01-17 2009-11-11 Samsung Electronics Co., Ltd. Procédé de fabrication de transistor FinFET avec un canal comportant de multiples faces
US7385247B2 (en) 2004-01-17 2008-06-10 Samsung Electronics Co., Ltd. At least penta-sided-channel type of FinFET transistor
KR100674914B1 (ko) * 2004-09-25 2007-01-26 삼성전자주식회사 변형된 채널층을 갖는 모스 트랜지스터 및 그 제조방법
KR101258864B1 (ko) * 2004-12-07 2013-04-29 썬더버드 테크놀로지스, 인코포레이티드 긴장된 실리콘, 게이트 엔지니어링된 페르미-fet
US20080112784A1 (en) * 2006-11-13 2008-05-15 Rogers Theodore W Load port door with simplified FOUP door sensing and retaining mechanism
TW200913149A (en) * 2007-09-13 2009-03-16 United Microelectronics Corp Fabricating method of semiconductor device
JP4919123B2 (ja) * 2010-03-08 2012-04-18 Tdk株式会社 処理基板収納ポッド及び処理基板収納ポッドの蓋開閉システム
US8889494B2 (en) * 2010-12-29 2014-11-18 Globalfoundries Singapore Pte. Ltd. Finfet
US9214538B2 (en) * 2011-05-16 2015-12-15 Eta Semiconductor Inc. High performance multigate transistor
US8604518B2 (en) * 2011-11-30 2013-12-10 Taiwan Semiconductor Manufacturing Company, Ltd. Split-channel transistor and methods for forming the same
DE112011105926T5 (de) * 2011-12-09 2014-09-18 Intel Corporation Belastungskompensation in Transistoren

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060043421A1 (en) * 2004-09-01 2006-03-02 International Business Machines Corporation Multi-gate device with high k dielectric for channel top surface
JP2006093717A (ja) * 2004-09-25 2006-04-06 Samsung Electronics Co Ltd 変形されたチャンネル層を有する電界効果トランジスタ及びその製造方法
US20100068862A1 (en) * 2005-03-24 2010-03-18 Samsung Electronics Co., Ltd. Semiconductor device having a round-shaped nano-wire transistor channel and method of manufacturing same
US20080258203A1 (en) * 2007-04-19 2008-10-23 Thomas Happ Stacked sonos memory
US20130270607A1 (en) * 2012-04-11 2013-10-17 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor Device Channel System and Method

Cited By (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9905643B1 (en) 2016-08-26 2018-02-27 International Business Machines Corporation Vertically aligned nanowire channels with source/drain interconnects for nanosheet transistors
US9985138B2 (en) 2016-08-26 2018-05-29 International Business Machines Corporation Vertically aligned nanowire channels with source/drain interconnects for nanosheet transistors
US10141445B2 (en) 2016-08-26 2018-11-27 International Business Machines Corporation Vertically aligned nanowire channels with source/drain interconnects for nanosheet transistors
US10249762B2 (en) 2016-08-26 2019-04-02 International Business Machines Corporation Vertically aligned nanowire channels with source/drain interconnects for nanosheet transistors
CN108695377A (zh) * 2017-04-05 2018-10-23 三星电子株式会社 半导体装置
CN108695377B (zh) * 2017-04-05 2024-02-23 三星电子株式会社 半导体装置
US10651291B2 (en) 2017-08-18 2020-05-12 Globalfoundries Inc. Inner spacer formation in a nanosheet field-effect transistor
US11908952B2 (en) 2017-08-29 2024-02-20 Samsung Electronics Co., Ltd. Semiconductor devices and manufacturing methods thereof
CN109427871A (zh) * 2017-08-29 2019-03-05 三星电子株式会社 半导体装置
EP3719851A3 (fr) * 2019-03-13 2020-12-30 United Microelectronics Corp. Structure semi-conductrice et procédé associé
US11527652B2 (en) 2019-03-13 2022-12-13 United Microelectronics Corp. Semiconductor process
WO2023010980A1 (fr) * 2021-08-05 2023-02-09 International Business Machines Corporation Dispositifs à transistors à effet de champ complémentaires
US11705504B2 (en) 2021-12-02 2023-07-18 International Business Machines Corporation Stacked nanosheet transistor with defect free channel

Also Published As

Publication number Publication date
TW201607039A (zh) 2016-02-16
CN106463543A (zh) 2017-02-22
TWI685972B (zh) 2020-02-21
CN106463543B (zh) 2020-04-07
KR20150142632A (ko) 2015-12-22
KR102223971B1 (ko) 2021-03-10

Similar Documents

Publication Publication Date Title
WO2015190852A1 (fr) Fet à canal contraint à plusieurs nanofeuilles cristallines et leurs procédés de fabrication
US9570609B2 (en) Crystalline multiple-nanosheet strained channel FETs and methods of fabricating the same
US9484423B2 (en) Crystalline multiple-nanosheet III-V channel FETs
US11062937B2 (en) Dielectric isolation for nanosheet devices
US8802531B2 (en) Split-channel transistor and methods for forming the same
US9530777B2 (en) FinFETs of different compositions formed on a same substrate
US10163677B2 (en) Electrically insulated fin structure(s) with alternative channel materials and fabrication methods
US9853026B2 (en) FinFET device and fabrication method thereof
US10396185B2 (en) Integration of strained silicon germanium PFET device and silicon NFET device for finFET structures
US20150228672A1 (en) Finfet device
US9536795B2 (en) Multiple threshold voltage trigate devices using 3D condensation
KR102135020B1 (ko) 다중 델타 도핑막을 가지는 퀀텀 웰 전계 효과 트랜지스터 제조 방법
US9460971B2 (en) Method to co-integrate oppositely strained semiconductor devices on a same substrate
US9911601B2 (en) Epitaxial silicon germanium fin formation using sacrificial silicon fin templates
US20190341452A1 (en) Iii-v-segmented finfet free of wafer bonding
US9755078B2 (en) Structure and method for multi-threshold voltage adjusted silicon germanium alloy devices with same silicon germanium content
US20230142609A1 (en) Integrated circuit devices including stacked transistors and methods of forming the same
US9142674B2 (en) FINFET devices having a body contact and methods of forming the same
US20090085114A1 (en) Semiconductor Structure

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 15806432

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 15806432

Country of ref document: EP

Kind code of ref document: A1