WO2015182038A1 - Rc-igbt drive circuit - Google Patents

Rc-igbt drive circuit Download PDF

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Publication number
WO2015182038A1
WO2015182038A1 PCT/JP2015/002229 JP2015002229W WO2015182038A1 WO 2015182038 A1 WO2015182038 A1 WO 2015182038A1 JP 2015002229 W JP2015002229 W JP 2015002229W WO 2015182038 A1 WO2015182038 A1 WO 2015182038A1
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switch circuit
circuit
gate
igbt
terminal
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PCT/JP2015/002229
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French (fr)
Japanese (ja)
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昌弘 山本
岩村 剛宏
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株式会社デンソー
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    • HELECTRICITY
    • H02GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02MAPPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00Details of apparatus for conversion
    • H02M1/08Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K17/00Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/04Modifications for accelerating switching
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K17/00Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices

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  • the present disclosure relates to a drive circuit that drives a reverse conducting insulated gate bipolar transistor (RC-IGBT) that can be turned off at high speed by including two gate electrodes.
  • RC-IGBT reverse conducting insulated gate bipolar transistor
  • Patent Document 1 discloses an RC-IGBT (hereinafter simply referred to as IGBT) having two gate electrodes.
  • IGBT RC-IGBT
  • a turn-on voltage is applied to both gate electrodes.
  • a turn-off voltage is applied to one gate electrode and then a turn-off voltage is applied to the other gate electrode. As a result, turn-off can be performed at a higher speed.
  • RC-IGBT drive circuit when the RC-IGBT including the first gate and the second gate is a driving target and the RC-IGBT is turned off from the turned-on state, An RC-IGBT driving circuit for applying a turn-off voltage to the first gate after applying a negative turn-off voltage to the second gate, the second gate terminal, an emitter terminal, two capacitance connection terminals, A plurality of switch circuits and a control circuit.
  • the second gate terminal is connected to the second gate.
  • the emitter terminal is connected to the emitter of the RC-IGBT.
  • a capacitor element is connected to the capacitor connection terminal.
  • the plurality of switch circuits are connected between any of the second gate terminal, the emitter terminal, and the capacitor connection terminal.
  • the RC-IGBT drive circuit charges the capacitor element with the charge charged in the second gate-emitter capacitor of the RC-IGBT that is turned on, and then reverses the charge to the capacitor element.
  • the second gate can be set to a negative voltage by connecting to the emitter and the second gate of the RC-IGBT so as to be polar. Therefore, even if a power supply for applying a negative voltage is not separately prepared, the second gate of the RC-IGBT can be set to a negative voltage for fast turn-off.
  • FIG. 1 is a diagram showing a configuration of an RC-IGBT drive circuit according to the first embodiment.
  • FIG. 2A is a diagram showing an on / off state of each switch circuit in phase IIA of the turn-off sequence according to the first embodiment.
  • FIG. 2B is a diagram illustrating an on / off state of each switch circuit in phase IIB of the turn-off sequence according to the first embodiment.
  • FIG. 2C is a diagram showing an on / off state of each switch circuit in phase IIC of the turn-off sequence according to the first embodiment.
  • FIG. 2D is a diagram illustrating an on / off state of each switch circuit in the phase IID of the turn-off sequence according to the first embodiment.
  • FIG. 2E is a diagram showing an on / off state of each switch circuit in phase IIE of the turn-off sequence according to the first embodiment.
  • FIG. 3 is a timing chart corresponding to FIGS. 2A to 2E.
  • FIG. 4 is a timing chart including a turn-on operation.
  • FIG. 5A is a diagram illustrating an on / off state of each switch circuit in the phase VA of the turn-off sequence according to the second embodiment.
  • FIG. 5B is a diagram showing an on / off state of each switch circuit in the phase VB of the turn-off sequence according to the second embodiment.
  • FIG. 5C is a diagram illustrating an on / off state of each switch circuit in the phase VC of the turn-off sequence according to the second embodiment.
  • FIG. 5D is a diagram illustrating an on / off state of each switch circuit in the phase VD of the turn-off sequence according to the second embodiment.
  • FIG. 6 is a timing chart corresponding to FIGS. 5A to 5D.
  • FIG. 7 is a diagram showing a configuration of an RC-IGBT drive circuit according to the third embodiment.
  • FIG. 8 is a diagram illustrating a specific configuration of each switch circuit of the control gate driving unit according to the fourth embodiment.
  • FIG. 9 is a diagram illustrating a specific configuration of each switch circuit of the control gate driving unit according to the fifth embodiment.
  • FIG. 10 is a diagram illustrating a specific configuration of each switch circuit of the control gate driving unit according to the sixth embodiment.
  • FIG. 11A is a timing chart when the IGBTs are alternately turned on and turned off in the seventh embodiment.
  • FIG. 11B is a timing chart when the IGBTs are alternately turned on and turned off in the second embodiment.
  • the drive circuit 1 includes an RC-IGBT (hereinafter simply referred to as IGBT) 2 including a main gate G (first gate) and a control gate CG (second gate).
  • IGBT RC-IGBT
  • the IGBT 2 to be driven is the same as the semiconductor device disclosed in Patent Document 1. That is, as shown in FIG. 4, when the PWM control signal becomes a high level and the IGBT 2 is turned on, a turn-on voltage (high level drive voltage) is applied to the main gate G and the control gate CG simultaneously.
  • the drive circuit 1 includes a control signal generation unit 3 (control circuit), a control gate drive unit 4 and a main gate drive unit 5.
  • the drive circuit 1 is supplied with a drive power supply 7 (voltage VB, for example, about 20 V) via a power supply terminal 6, and PWM is supplied from the outside (a microcomputer as a host control device) via a signal input terminal 8.
  • a control signal is input.
  • the control gate connection terminals 9a and 9b (second gate terminals) of the drive circuit 1 are connected to the control gate CG via external resistance elements RGP and RGN, respectively.
  • the main gate connection terminals 10a and 10b are connected to the main gate G through external resistance elements RGP and RGN, respectively.
  • the resistance values of the resistance elements RGP and RGN are appropriately determined according to the settings of the turn-on and turn-off speeds of the gates CG and G.
  • the emitter connection terminal 11 (emitter terminal) is connected to the emitter of the IGBT 2 and the ground terminal 12 is connected to the ground. However, since the emitter is connected to the ground, the emitter connection terminal 11 and the ground terminal 12 have the same potential. Yes.
  • a capacitor 14 (capacitance element) is externally connected to the capacitance connection terminals 13a and 13b.
  • the switch circuit SW1 is connected between the power supply terminal 6 and the control gate connection terminal 9a, and the switch circuit SW2 (first switch circuit) is connected to the control gate connection terminal 9b and the emitter connection terminal. 11 is connected.
  • the switch circuit SW3 (second switch circuit) is connected between the control gate connection terminal 9b and the capacitor connection terminal 13a, and the switch circuit SW4 (fifth switch circuit) is connected to the capacitor connection terminal 13b and the emitter connection terminal 11. Connected between and.
  • the switch circuit SW5 (third switch circuit) is connected between the control gate connection terminal 9b and the capacitor connection terminal 13b, and the switch circuit SW6 (fourth switch circuit) is connected to the capacitor connection terminal 13a and the emitter connection terminal 11. Connected between and.
  • the switch circuit SW7 is connected between the power supply terminal 6 and the main gate connection terminal 10a, and the switch circuit SW8 is connected between the main gate connection terminal 10b and the ground terminal 12. ing.
  • a PWM control signal is input to the control signal generation unit 3 via the signal input terminal 8, and the control signal generation unit 3 controls on / off of each of the switch circuits SW1 to SW8 according to the change of the PWM control signal.
  • the control signal generation unit 3 turns on the switch circuits SW1 and SW7.
  • the gate capacitance on the main gate G side and the gate capacitance on the control gate CG side are charged to the voltage VB via the respective resistance elements RGP (see Phase IIA in FIGS. 2A and 3). Since the charge is from 0V to 20V, the drive loss is the same as that of the positive voltage drive.
  • the control signal generator 3 turns off the switch circuit SW1 and then turns on the switch circuits SW3 and SW4. Then, the capacitor 14 is charged by the charge charged in the gate capacitance on the control gate CG side (see Phase IIB in FIG. 2B and FIG. 3).
  • control signal generator 3 turns off the switch circuits SW3 and SW4 and then turns on the switch circuit SW2.
  • the voltage of the control gate CG becomes 0 V, which is the same potential as the emitter (see Phase IIC in FIGS. 2C and 3).
  • the switch circuit SW2 is turned off and then the switch circuits SW5 and SW6 are turned on. Then, the positive potential side terminal (+) of the capacitor 14 is connected to the emitter, and the negative potential side terminal ( ⁇ ) is connected to the control gate CG. As a result, a negative voltage is applied to the control gate CG (see the phase IID in FIGS. 2D and 3).
  • control signal generator 3 turns off the switch circuit SW7 and then turns on the switch circuit SW8 to discharge the capacitance on the main gate G side and turn off the IGBT2.
  • the drive circuit 1 includes the plurality of switch circuits SW2 to SW2 connected between any one of the control gate connection terminals 9a and 9b, the emitter connection terminal 11, and the capacitance connection terminals 13a and 13b.
  • SW6 is provided.
  • the control signal generation unit 3 controls on / off of the plurality of switch circuits SW2 to SW6, and when the IGBT 2 is turned off from the turned on state, the charge charged in the capacitance between the control gate CG and the emitter is After forming a charging path for charging the capacitor 14 connected to the capacitor connection terminals 13a and 13b, the positive potential side terminal and the negative potential side terminal of the capacitor 14 are connected to the emitter and the second gate, respectively. An application path is formed.
  • the capacitor 14 is connected to the emitter and control of the IGBT 2 so that the charged charge has a reverse polarity.
  • the control gate CG can be set to a negative voltage. Therefore, the IGBT 2 can be turned off at high speed without separately preparing a power supply for applying a negative voltage.
  • the switch circuit SW2 is connected between the control gate connection terminal 9b and the emitter connection terminal 11, and the switch circuit SW3 is connected between the control gate connection terminal 9b and the capacitor connection terminal 13a, thereby connecting the control gate.
  • the switch circuit SW5 is connected between the terminal 9b and the capacitor connection terminal 13b, the switch circuit SW6 is connected between the capacitor connection terminal 13a and the emitter connection terminal 11, and between the capacitor connection terminal 13b and the emitter connection terminal 11. Is connected to the switch circuit SW4.
  • the control signal generation unit 3 turns on the switch circuits SW3 and SW4 to form a charging path, and charges the capacitor element with the charge charged in the control gate CG. Then, when the switch circuits SW3 and SW4 are turned off, the switch circuit SW2 is turned on, and the control gate CG is set to 0 V having the same potential as the emitter. Thereafter, when the switch circuit SW2 is turned off, the switch circuits SW5 and SW6 are turned on to form a negative voltage application path, and the control gate CG is set to a negative voltage.
  • the control gate CG is once set to 0 V and then set to a negative voltage. Therefore, the negative potential of the control gate CG can be increased, and the IGBT 2 can be turned off faster. Can be done.
  • the switch circuits SW5 and SW6 are turned off and then the switch circuit SW2 is turned on, so that the potential of the control gate CG is set to 0V. Can be done to drive loss.
  • phase VA in FIGS. 5A and 6 corresponds to phase IIA in FIGS. 2A and 3
  • phase VB in FIGS. 5B and 6 corresponds to phase IIB in FIGS. 2B and 3
  • 5D and 6 corresponds to the phase IIE in FIGS. 2E and 3.
  • a negative voltage is immediately applied to the control gate CG without setting the potential of the control gate CG to 0 V in the next phase VC.
  • the control signal generator 3 can easily control each switch circuit. However, since the negative voltage is applied from the state where the potential of the control gate CG exceeds 0 V, the negative potential applied is smaller than that in the first embodiment.
  • the drive circuit 21 of the third embodiment adds a switch circuit SW9 between the power supply terminal 6 and the capacitor connection terminal 13a, and the control signal generation unit 22 replacing the control signal generation unit 3 includes:
  • the on / off of the switch circuit SW9 is also controlled.
  • the control signal generator 22 turns on the switch circuits SW9 and SW4 to form a startup charging path so that the capacitor 14 is charged to a preset voltage.
  • a negative voltage having a sufficient potential can be applied to the control gate CG from the first turn-off sequence, and the turn-off sequence can be stably performed.
  • the control gate drive unit 31 of the fourth embodiment shows a specific configuration of the switch circuits SW1 to SW6.
  • the switch circuit SW1 is composed of a P-channel MOSFET M1
  • the switch circuit SW6 is composed of an N-channel MOSFET M6.
  • the other switch circuits SW2 to SW5 are each constituted by a bidirectional switch in which the sources of two N-channel MOSFETs are connected in common (M21 and M22, M31 and M32, M41 and M42, M51 and M52, respectively).
  • the switch circuit SW7 of the main gate driving unit 5 may be a P-channel MOSFET and the switch circuit SW8 may be an N-channel MOSFET.
  • the control gate drive unit 32 of the fifth embodiment has a switch circuit SW2 in the control gate drive unit 31 of the fourth embodiment connected in series in the opposite direction to the N-channel MOSFET M21 and its parasitic diode.
  • the switch circuit SW4 includes an N-channel MOSFET M41 and a diode D4 connected in series in the opposite direction to the parasitic diode.
  • the switch circuits SW2 and SW4 replaced in this way are realized with a simple circuit configuration, although the potential of the negative voltage applied to the control gate CG is reduced by the forward voltage of the diodes D2 and D4 compared to the bidirectional switch. it can.
  • the control gate drive unit 33 of the sixth embodiment is obtained by replacing the switch circuit SW2 in the control gate drive unit 31 of the fourth embodiment with a resistance element R2.
  • the speed when discharging the control gate CG is slower than that of the first embodiment due to the time constant including the resistance value of the resistance element R2.
  • the switch circuit SW2 is turned on and the control gate CG is set to 0 V at the end of the turn-off operation.
  • the switch circuit SW2 is not turned on last and the next turn-on is performed. Take action immediately.
  • FIG. 11B shows a case where the IGBTs 2 are alternately turned on and turned off in the second embodiment.
  • the switch circuit SW7 is immediately turned on and the IGBT 2 is turned on as shown in FIG. 11A. According to the seventh embodiment as described above, the turn-off control can be simplified.
  • the drive power supply voltage is not limited to 20V. It is not always necessary to provide the turn-on resistance element RGP and the turn-off resistance element RGN, and a common resistance element may be used if there is no problem in the respective operation speeds.
  • a CMOS transfer gate may be used for the switch circuit.
  • the capacity of the capacitor 14 is not necessarily limited to 10 times or more of the capacity of the control gate CG, and may be appropriately changed according to the individual design.

Abstract

This RC-IGBT drive circuit is provided with: a plurality of switch circuits (SW2-SW6) connected between any from among a second gate terminal (9), an emitter terminal (11), and capacitor connection terminals (13); and a control circuit (3). When an RC-IGBT is turned off, the control circuit controls the on-off states of the plurality of switch circuits, and, as a result, forms a charging path which causes the electric charge charging a capacitor between a second gate and an emitter of the RC-IGBT to charge a capacitative element, and subsequently forms a negative voltage application path respectively connecting, to the emitter and the second gate, a positive-potential-side terminal and a negative-potential-side terminal of the capacitative element.

Description

RC-IGBT駆動回路RC-IGBT drive circuit 関連出願の相互参照Cross-reference of related applications
 本開示は、2014年5月27日に出願された日本出願番号2014-109055号に基づくもので、ここにその記載内容を援用する。 This disclosure is based on Japanese Patent Application No. 2014-109055 filed on May 27, 2014, the contents of which are incorporated herein.
 本開示は、2つのゲート電極を備えることでターンオフを高速に行うことを可能にした逆導通絶縁ゲートバイポーラトランジスタ(RC-IGBT)を駆動する駆動回路に関する。 The present disclosure relates to a drive circuit that drives a reverse conducting insulated gate bipolar transistor (RC-IGBT) that can be turned off at high speed by including two gate electrodes.
 特許文献1には、2つのゲート電極を備えるRC-IGBT(以下、単にIGBTと称す)が開示されている。このIGBTをターンオンさせる場合は、両方のゲート電極に対してターンオン電圧を印加し、ターンオフさせる際には、一方のゲート電極にターンオフ電圧を印加した後に他方のゲート電極にターンオフ電圧を印加する。これにより、ターンオフをより高速に行うことを可能にしている。 Patent Document 1 discloses an RC-IGBT (hereinafter simply referred to as IGBT) having two gate electrodes. When the IGBT is turned on, a turn-on voltage is applied to both gate electrodes. When the IGBT is turned off, a turn-off voltage is applied to one gate electrode and then a turn-off voltage is applied to the other gate electrode. As a result, turn-off can be performed at a higher speed.
 特許文献1におけるIGBTを高速にターンオフさせるには、一方のゲート電極に負電圧を印加するのが望ましい。しかしながら、そのために別途負電源を用意するとコストがアップし、駆動損失も増大する。 In order to turn off the IGBT in Patent Document 1 at high speed, it is desirable to apply a negative voltage to one gate electrode. However, if a separate negative power supply is prepared for this purpose, the cost increases and the drive loss also increases.
特開2013-98415号公報JP 2013-98415 A
 本開示は、負電源を用いなくても、RC-IGBTを迅速にターンオフさせることが可能なRC-IGBT駆動回路を提供することにある。 It is an object of the present disclosure to provide an RC-IGBT driving circuit that can quickly turn off an RC-IGBT without using a negative power supply.
 本開示の一態様に係るRC-IGBT駆動回路は、第1ゲート及び第2ゲートを備えてなるRC-IGBTを駆動対象とし、前記RC-IGBTをターンオンしている状態からターンオフさせる場合は、前記第2ゲートに対して負のターンオフ電圧を印加した後に、前記第1ゲートにターンオフ電圧を印加するRC-IGBT駆動回路であって、第2ゲート端子と、エミッタ端子と、2つの容量接続端子と、複数のスイッチ回路と、制御回路とを備える。 In the RC-IGBT drive circuit according to one aspect of the present disclosure, when the RC-IGBT including the first gate and the second gate is a driving target and the RC-IGBT is turned off from the turned-on state, An RC-IGBT driving circuit for applying a turn-off voltage to the first gate after applying a negative turn-off voltage to the second gate, the second gate terminal, an emitter terminal, two capacitance connection terminals, A plurality of switch circuits and a control circuit.
 前記第2ゲート端子は、前記第2ゲートに接続される。前記エミッタ端子は、前記RC-IGBTのエミッタに接続される。前記容量接続端子は、容量素子が接続される。前記複数のスイッチ回路は、前記第2ゲート端子、前記エミッタ端子、前記容量接続端子の何れかの間に接続される。前記制御回路は、前記複数のスイッチ回路のオンオフを制御することで、前記RC-IGBTをターンオフさせる際に、前記RC-IGBTの第2ゲート-エミッタ間容量に充電されている電荷を前記容量素子に充電させる充電経路を形成してから、前記容量素子の正電位側端子、負電位側端子を、前記エミッタ、前記第2ゲートにそれぞれ接続させる負電圧印加経路を形成する。 The second gate terminal is connected to the second gate. The emitter terminal is connected to the emitter of the RC-IGBT. A capacitor element is connected to the capacitor connection terminal. The plurality of switch circuits are connected between any of the second gate terminal, the emitter terminal, and the capacitor connection terminal. When the RC-IGBT is turned off by controlling on / off of the plurality of switch circuits, the control circuit transfers the charge charged in the second gate-emitter capacitance of the RC-IGBT to the capacitive element. After forming a charging path for charging, a negative voltage application path for connecting the positive potential side terminal and the negative potential side terminal of the capacitive element to the emitter and the second gate is formed.
 前記RC-IGBT駆動回路は、ターンオンしている前記RC-IGBTの第2ゲート-エミッタ間容量に充電されている前記電荷を前記容量素子に充電させた後、前記容量素子を、充電電荷が逆極性となるように前記RC-IGBTの前記エミッタ、前記第2ゲートに接続して、前記第2ゲートを負電圧にできる。したがって、負電圧印加用の電源を別途用意せずとも、前記RC-IGBTの前記第2ゲートを負電圧にしてターンオフを高速に行うことができる。 The RC-IGBT drive circuit charges the capacitor element with the charge charged in the second gate-emitter capacitor of the RC-IGBT that is turned on, and then reverses the charge to the capacitor element. The second gate can be set to a negative voltage by connecting to the emitter and the second gate of the RC-IGBT so as to be polar. Therefore, even if a power supply for applying a negative voltage is not separately prepared, the second gate of the RC-IGBT can be set to a negative voltage for fast turn-off.
 本開示における上記あるいは他の目的、構成、利点は、下記の図面を参照しながら、以下の詳細説明から、より明白となる。図面において、
図1は、第1実施形態に係るRC-IGBT駆動回路の構成を示す図である。 図2Aは、第1実施形態に係るターンオフシーケンスのフェーズIIAにおける各スイッチ回路のオンオフ状態を示す図である。 図2Bは、第1実施形態に係るターンオフシーケンスのフェーズIIBにおける各スイッチ回路のオンオフ状態を示す図である。 図2Cは、第1実施形態に係るターンオフシーケンスのフェーズIICにおける各スイッチ回路のオンオフ状態を示す図である。 図2Dは、第1実施形態に係るターンオフシーケンスのフェーズIIDにおける各スイッチ回路のオンオフ状態を示す図である。 図2Eは、第1実施形態に係るターンオフシーケンスのフェーズIIEにおける各スイッチ回路のオンオフ状態を示す図である。 図3は、図2A~図2Eに対応するタイミングチャートである。 図4は、ターンオン動作を含むタイミングチャートである。 図5Aは、第2実施形態に係るターンオフシーケンスのフェーズVAにおける各スイッチ回路のオンオフ状態を示す図である。 図5Bは、第2実施形態に係るターンオフシーケンスのフェーズVBにおける各スイッチ回路のオンオフ状態を示す図である。 図5Cは、第2実施形態に係るターンオフシーケンスのフェーズVCにおける各スイッチ回路のオンオフ状態を示す図である。 図5Dは、第2実施形態に係るターンオフシーケンスのフェーズVDにおける各スイッチ回路のオンオフ状態を示す図である。 図6は、図5A~図5Dに対応するタイミングチャートである。 図7は、第3実施形態に係るRC-IGBT駆動回路の構成を示す図である。 図8は、第4実施形態に係るコントロールゲート駆動部の各スイッチ回路の具体構成を示す図である。 図9は、第5実施形態に係るコントロールゲート駆動部の各スイッチ回路の具体構成を示す図である。 図10は、第6実施形態に係るコントロールゲート駆動部の各スイッチ回路の具体構成を示す図である。 図11Aは、第7実施形態において、IGBTを交互にターンオン、ターンオフさせる場合のタイミングチャートである。 図11Bは、第2実施形態において、IGBTを交互にターンオン、ターンオフさせる場合のタイミングチャートである。
The above and other objects, configurations, and advantages of the present disclosure will become more apparent from the following detailed description with reference to the following drawings. In the drawing
FIG. 1 is a diagram showing a configuration of an RC-IGBT drive circuit according to the first embodiment. FIG. 2A is a diagram showing an on / off state of each switch circuit in phase IIA of the turn-off sequence according to the first embodiment. FIG. 2B is a diagram illustrating an on / off state of each switch circuit in phase IIB of the turn-off sequence according to the first embodiment. FIG. 2C is a diagram showing an on / off state of each switch circuit in phase IIC of the turn-off sequence according to the first embodiment. FIG. 2D is a diagram illustrating an on / off state of each switch circuit in the phase IID of the turn-off sequence according to the first embodiment. FIG. 2E is a diagram showing an on / off state of each switch circuit in phase IIE of the turn-off sequence according to the first embodiment. FIG. 3 is a timing chart corresponding to FIGS. 2A to 2E. FIG. 4 is a timing chart including a turn-on operation. FIG. 5A is a diagram illustrating an on / off state of each switch circuit in the phase VA of the turn-off sequence according to the second embodiment. FIG. 5B is a diagram showing an on / off state of each switch circuit in the phase VB of the turn-off sequence according to the second embodiment. FIG. 5C is a diagram illustrating an on / off state of each switch circuit in the phase VC of the turn-off sequence according to the second embodiment. FIG. 5D is a diagram illustrating an on / off state of each switch circuit in the phase VD of the turn-off sequence according to the second embodiment. FIG. 6 is a timing chart corresponding to FIGS. 5A to 5D. FIG. 7 is a diagram showing a configuration of an RC-IGBT drive circuit according to the third embodiment. FIG. 8 is a diagram illustrating a specific configuration of each switch circuit of the control gate driving unit according to the fourth embodiment. FIG. 9 is a diagram illustrating a specific configuration of each switch circuit of the control gate driving unit according to the fifth embodiment. FIG. 10 is a diagram illustrating a specific configuration of each switch circuit of the control gate driving unit according to the sixth embodiment. FIG. 11A is a timing chart when the IGBTs are alternately turned on and turned off in the seventh embodiment. FIG. 11B is a timing chart when the IGBTs are alternately turned on and turned off in the second embodiment.
 (第1実施形態)
 本開示の第1実施形態に係る駆動回路1について、図1~図4を参照して説明する。図1に示すように、本実施形態の駆動回路1は、メインゲートG(第1ゲート)と、コントロールゲートCG(第2ゲート)とを備えるRC-IGBT(以下、単にIGBTと称す)2を駆動対象とするもので、IGBT2は、特許文献1に開示されている半導体装置と同じものである。すなわち、図4に示すように、PWM制御信号がハイレベルとなりIGBT2をターンオンさせる場合には、メインゲートG及びコントロールゲートCGに対して同時にターンオン電圧(ハイレベル駆動電圧)を印加する。
(First embodiment)
The drive circuit 1 according to the first embodiment of the present disclosure will be described with reference to FIGS. As shown in FIG. 1, the drive circuit 1 of this embodiment includes an RC-IGBT (hereinafter simply referred to as IGBT) 2 including a main gate G (first gate) and a control gate CG (second gate). The IGBT 2 to be driven is the same as the semiconductor device disclosed in Patent Document 1. That is, as shown in FIG. 4, when the PWM control signal becomes a high level and the IGBT 2 is turned on, a turn-on voltage (high level drive voltage) is applied to the main gate G and the control gate CG simultaneously.
 一方、PWM制御信号がローレベルとなりIGBT2をターンオフさせる場合には、先にコントロールゲートCGの電位を低下させてから(0V→負電圧)、メインゲートGにターンオフ電圧(ローレベル駆動電圧)を印加するように制御する。このように、先にコントロールゲートCGの電位を低下させることで、ドリフト層に蓄積されている正孔又は電子の一部が予め引き抜かれるため、メインゲートGにターンオフ電圧を印加した際に残留している正孔又は電子の引き抜きが短時間で完了するようになる(特許文献1,段落[0013]参照)。したがって、IGBT2のスイッチング速度が向上し、損失の低減を図ることができる。 On the other hand, when the PWM control signal becomes low level and the IGBT 2 is turned off, the potential of the control gate CG is first lowered (0V → negative voltage) and then the turn-off voltage (low level driving voltage) is applied to the main gate G. Control to do. Thus, by lowering the potential of the control gate CG first, some of the holes or electrons accumulated in the drift layer are extracted in advance, and therefore remain when the turn-off voltage is applied to the main gate G. The extraction of holes or electrons is completed in a short time (see Patent Document 1, paragraph [0013]). Therefore, the switching speed of the IGBT 2 is improved, and loss can be reduced.
 駆動回路1は、制御信号生成部3(制御回路)、コントロールゲート駆動部4及びメインゲート駆動部5を備えている。また、駆動回路1には、電源端子6を介して駆動電源7(電圧VB、例えば20V程度)が供給され、信号入力端子8を介して外部(上位の制御装置であるマイクロコンピュータ等)よりPWM制御信号が入力される。駆動回路1のコントロールゲート接続端子9a,9b(第2ゲート端子)は、それぞれ外付けの抵抗素子RGP,RGNを介してコントロールゲートCGに接続されている。また、メインゲート接続端子10a,10bは、それぞれ外付けの抵抗素子RGP,RGNを介してメインゲートGに接続されている。尚、抵抗素子RGP,RGNの抵抗値は、各ゲートCG、Gのターンオン,ターンオフ速度の設定に応じて適宜決定される。 The drive circuit 1 includes a control signal generation unit 3 (control circuit), a control gate drive unit 4 and a main gate drive unit 5. The drive circuit 1 is supplied with a drive power supply 7 (voltage VB, for example, about 20 V) via a power supply terminal 6, and PWM is supplied from the outside (a microcomputer as a host control device) via a signal input terminal 8. A control signal is input. The control gate connection terminals 9a and 9b (second gate terminals) of the drive circuit 1 are connected to the control gate CG via external resistance elements RGP and RGN, respectively. The main gate connection terminals 10a and 10b are connected to the main gate G through external resistance elements RGP and RGN, respectively. The resistance values of the resistance elements RGP and RGN are appropriately determined according to the settings of the turn-on and turn-off speeds of the gates CG and G.
 エミッタ接続端子11(エミッタ端子)はIGBT2のエミッタに接続され、グランド端子12はグランドに接続されるが、エミッタはグランドに接続されているのでエミッタ接続端子11及びグランド端子12は同電位となっている。そして、容量接続端子13a、13bには、コンデンサ14(容量素子)が外付けで接続されている。 The emitter connection terminal 11 (emitter terminal) is connected to the emitter of the IGBT 2 and the ground terminal 12 is connected to the ground. However, since the emitter is connected to the ground, the emitter connection terminal 11 and the ground terminal 12 have the same potential. Yes. A capacitor 14 (capacitance element) is externally connected to the capacitance connection terminals 13a and 13b.
 コントロールゲート駆動部4において、スイッチ回路SW1は、電源端子6とコントロールゲート接続端子9aとの間に接続されており、スイッチ回路SW2(第1スイッチ回路)は、コントロールゲート接続端子9bとエミッタ接続端子11との間に接続されている。スイッチ回路SW3(第2スイッチ回路)は、コントロールゲート接続端子9bと容量接続端子13aとの間に接続されており、スイッチ回路SW4(第5スイッチ回路)は、容量接続端子13bとエミッタ接続端子11との間に接続されている。スイッチ回路SW5(第3スイッチ回路)は、コントロールゲート接続端子9bと容量接続端子13bとの間に接続されており、スイッチ回路SW6(第4スイッチ回路)は、容量接続端子13aとエミッタ接続端子11との間に接続されている。 In the control gate driver 4, the switch circuit SW1 is connected between the power supply terminal 6 and the control gate connection terminal 9a, and the switch circuit SW2 (first switch circuit) is connected to the control gate connection terminal 9b and the emitter connection terminal. 11 is connected. The switch circuit SW3 (second switch circuit) is connected between the control gate connection terminal 9b and the capacitor connection terminal 13a, and the switch circuit SW4 (fifth switch circuit) is connected to the capacitor connection terminal 13b and the emitter connection terminal 11. Connected between and. The switch circuit SW5 (third switch circuit) is connected between the control gate connection terminal 9b and the capacitor connection terminal 13b, and the switch circuit SW6 (fourth switch circuit) is connected to the capacitor connection terminal 13a and the emitter connection terminal 11. Connected between and.
 メインゲート駆動部5において、スイッチ回路SW7は、電源端子6とメインゲート接続端子10aとの間に接続されており、スイッチ回路SW8は、メインゲート接続端子10bとグランド端子12との間に接続されている。制御信号生成部3には、信号入力端子8を介してPWM制御信号が入力され、制御信号生成部3は、そのPWM制御信号の変化に応じて各スイッチ回路SW1~SW8のオンオフを制御する。 In the main gate drive unit 5, the switch circuit SW7 is connected between the power supply terminal 6 and the main gate connection terminal 10a, and the switch circuit SW8 is connected between the main gate connection terminal 10b and the ground terminal 12. ing. A PWM control signal is input to the control signal generation unit 3 via the signal input terminal 8, and the control signal generation unit 3 controls on / off of each of the switch circuits SW1 to SW8 according to the change of the PWM control signal.
 次に、本実施形態のターンオフシーケンスについて説明する。PWM制御信号がハイレベルになりIGBT2をターンオンさせる場合、制御信号生成部3は、スイッチ回路SW1及びSW7をオンする。これにより、それぞれの抵抗素子RGPを介してメインゲートG側のゲート容量及びコントロールゲートCG側のゲート容量を電圧VBに充電する(図2Aおよび図3のフェーズIIA参照)。なお、0Vから20Vへのチャージなので駆動損失は正電圧駆動と同じである。 Next, the turn-off sequence of this embodiment will be described. When the PWM control signal becomes high level to turn on the IGBT 2, the control signal generation unit 3 turns on the switch circuits SW1 and SW7. As a result, the gate capacitance on the main gate G side and the gate capacitance on the control gate CG side are charged to the voltage VB via the respective resistance elements RGP (see Phase IIA in FIGS. 2A and 3). Since the charge is from 0V to 20V, the drive loss is the same as that of the positive voltage drive.
 そして、PWM制御信号がローレベルになりIGBT2をターンオフさせる場合、制御信号生成部3は、スイッチ回路SW1をオフさせてからスイッチ回路SW3及びSW4をオンさせる。すると、コントロールゲートCG側のゲート容量に充電されていた電荷によって、コンデンサ14が充電される(図2Bおよび図3のフェーズIIB参照)。 When the PWM control signal becomes a low level and turns off the IGBT 2, the control signal generator 3 turns off the switch circuit SW1 and then turns on the switch circuits SW3 and SW4. Then, the capacitor 14 is charged by the charge charged in the gate capacitance on the control gate CG side (see Phase IIB in FIG. 2B and FIG. 3).
 次に、制御信号生成部3は、スイッチ回路SW3及びSW4をオフさせてからスイッチ回路SW2をオンさせる。これにより、コントロールゲートCGの電圧はエミッタと同電位の0Vになる(図2Cおよび図3のフェーズIIC参照)。 Next, the control signal generator 3 turns off the switch circuits SW3 and SW4 and then turns on the switch circuit SW2. As a result, the voltage of the control gate CG becomes 0 V, which is the same potential as the emitter (see Phase IIC in FIGS. 2C and 3).
 続いて、スイッチ回路SW2をオフさせてからスイッチ回路SW5及びSW6をオンさせる。すると、コンデンサ14の正電位側端子(+)がエミッタに、負電位側端子(-)がコントロールゲートCGに接続される。これにより、コントロールゲートCGには負電圧が印加される(図2Dおよび図3のフェーズIID参照)。 Subsequently, the switch circuit SW2 is turned off and then the switch circuits SW5 and SW6 are turned on. Then, the positive potential side terminal (+) of the capacitor 14 is connected to the emitter, and the negative potential side terminal (−) is connected to the control gate CG. As a result, a negative voltage is applied to the control gate CG (see the phase IID in FIGS. 2D and 3).
 またこの時、制御信号生成部3は、スイッチ回路SW7をオフさせてからスイッチ回路SW8をオンさせて、メインゲートG側の容量を放電させてIGBT2をターンオフさせる。 At this time, the control signal generator 3 turns off the switch circuit SW7 and then turns on the switch circuit SW8 to discharge the capacitance on the main gate G side and turn off the IGBT2.
 最後に、スイッチ回路SW5及びSW6をオフさせてからスイッチ回路SW2をオンさせて、コントロールゲートCGの電位を0Vにすることでターンオフシーケンスが終了する(図2Eおよび図3のフェーズIIE参照)。 Finally, after turning off the switch circuits SW5 and SW6, the switch circuit SW2 is turned on and the potential of the control gate CG is set to 0 V, thereby completing the turn-off sequence (see Phase IIE in FIGS. 2E and 3).
 尚、図2Dに示した工程において、コントロールゲートCGに印加される負電圧をVとすると、以下の式で表される。なお、負電圧Vは、フェーズIIDで時間が無限大に経過したことを仮定した場合の電圧である。コンデンサ14の容量をCCHG、コントロールゲートCGの容量をCCGとすると、 Incidentally, in the step shown in FIG. 2D, when a negative voltage applied to the control gate CG and V ∞, is expressed by the following equation. Note that the negative voltage V∞ is a voltage when it is assumed that the time has passed infinitely in the phase IID. Capacity C CHG of the capacitor 14 and the capacitance of the control gate CG and C CG,
Figure JPOXMLDOC01-appb-M000001
となる。そして、上式に記載しているように、IGBT2を安定した状態でターンオフさせるため、負電圧をVを駆動電源電圧VBの凡そ1/2にすることを目標にすると、CCHG≫CCGとなる条件が必要であり、そのためには、例えば容量CCHGを容量CCGの10倍以上に設定すれば十分である。
Figure JPOXMLDOC01-appb-M000001
It becomes. Then, as described in the above formula, in order to turn off the IGBT 2 in a stable state, assuming that the negative voltage is set to V approximately ½ of the drive power supply voltage VB, C CHG >> C CG For this purpose, for example, it is sufficient to set the capacity C CHG to 10 times the capacity C CG or more.
 以上のように本実施形態によれば、駆動回路1は、コントロールゲート接続端子9a、9b、エミッタ接続端子11、容量接続端子13a、13bの何れかの間に接続される複数のスイッチ回路SW2~SW6を備える。そして、制御信号生成部3は、複数のスイッチ回路SW2~SW6のオンオフを制御し、IGBT2をターンオンしている状態からターンオフさせる際に、コントロールゲートCG-エミッタ間容量に充電されている電荷を、容量接続端子13a、13bに接続されているコンデンサ14に充電させる充電経路を形成してから、コンデンサ14の正電位側端子、負電位側端子を、エミッタ、第2ゲートにそれぞれ接続させて負電圧印加経路を形成する。 As described above, according to the present embodiment, the drive circuit 1 includes the plurality of switch circuits SW2 to SW2 connected between any one of the control gate connection terminals 9a and 9b, the emitter connection terminal 11, and the capacitance connection terminals 13a and 13b. SW6 is provided. Then, the control signal generation unit 3 controls on / off of the plurality of switch circuits SW2 to SW6, and when the IGBT 2 is turned off from the turned on state, the charge charged in the capacitance between the control gate CG and the emitter is After forming a charging path for charging the capacitor 14 connected to the capacitor connection terminals 13a and 13b, the positive potential side terminal and the negative potential side terminal of the capacitor 14 are connected to the emitter and the second gate, respectively. An application path is formed.
 これにより、ターンオンしているIGBT2のコントロールゲートCG-エミッタ間容量に充電されている電荷をコンデンサ14に充電させた後、そのコンデンサ14を、充電電荷が逆極性となるようにIGBT2のエミッタ、コントロールゲートCGに接続して、コントロールゲートCGを負電圧にできる。したがって、負電圧印加用の電源を別途用意せずとも、IGBT2のターンオフを高速に行うことができる。 As a result, after charging the capacitor 14 with the charge charged in the capacitance between the control gate CG and the emitter of the IGBT 2 that is turned on, the capacitor 14 is connected to the emitter and control of the IGBT 2 so that the charged charge has a reverse polarity. By connecting to the gate CG, the control gate CG can be set to a negative voltage. Therefore, the IGBT 2 can be turned off at high speed without separately preparing a power supply for applying a negative voltage.
 具体的には、コントロールゲート接続端子9bとエミッタ接続端子11との間にスイッチ回路SW2を接続し、コントロールゲート接続端子9bと容量接続端子13aとの間にスイッチ回路SW3を接続し、コントロールゲート接続端子9bと容量接続端子13bとの間にスイッチ回路SW5を接続し、容量接続端子13aとエミッタ接続端子11との間にスイッチ回路SW6を接続し、容量接続端子13bとエミッタ接続端子11との間にスイッチ回路SW4を接続する。 Specifically, the switch circuit SW2 is connected between the control gate connection terminal 9b and the emitter connection terminal 11, and the switch circuit SW3 is connected between the control gate connection terminal 9b and the capacitor connection terminal 13a, thereby connecting the control gate. The switch circuit SW5 is connected between the terminal 9b and the capacitor connection terminal 13b, the switch circuit SW6 is connected between the capacitor connection terminal 13a and the emitter connection terminal 11, and between the capacitor connection terminal 13b and the emitter connection terminal 11. Is connected to the switch circuit SW4.
 そして、制御信号生成部3は、スイッチ回路SW3及びSW4をオンさせて充電経路を形成し、コントロールゲートCGに充電されている電荷を容量素子に充電させる。それから、スイッチ回路SW3及びSW4をオフさせると、スイッチ回路SW2をオンさせて、コントロールゲートCGをエミッタと同電位の0Vにする。その後、スイッチ回路SW2をオフさせると、スイッチ回路SW5及びSW6をオンさせて負電圧印加経路を形成し、コントロールゲートCGを負電圧にする。 Then, the control signal generation unit 3 turns on the switch circuits SW3 and SW4 to form a charging path, and charges the capacitor element with the charge charged in the control gate CG. Then, when the switch circuits SW3 and SW4 are turned off, the switch circuit SW2 is turned on, and the control gate CG is set to 0 V having the same potential as the emitter. Thereafter, when the switch circuit SW2 is turned off, the switch circuits SW5 and SW6 are turned on to form a negative voltage application path, and the control gate CG is set to a negative voltage.
 これにより、コントロールゲートCGの充電電荷を放電させた後、コントロールゲートCGを一旦0Vにしてから負電圧にするので、コントロールゲートCGの負電位をより大きくすることができ、IGBT2のターンオフをより高速に行うことができる。また、コントロールゲートCGを負電圧にした後に、スイッチ回路SW5及びSW6をオフにしてからスイッチ回路SW2をオンさせて、コントロールゲートCGの電位を0Vにするので、次回のIGBT2のターンオンを高速且つ低駆動損失に行うことができる。 As a result, after the charge of the control gate CG is discharged, the control gate CG is once set to 0 V and then set to a negative voltage. Therefore, the negative potential of the control gate CG can be increased, and the IGBT 2 can be turned off faster. Can be done. In addition, after the control gate CG is set to a negative voltage, the switch circuits SW5 and SW6 are turned off and then the switch circuit SW2 is turned on, so that the potential of the control gate CG is set to 0V. Can be done to drive loss.
 (第2実施形態)
 以下、第1実施形態と同一部分には同一符号を付して説明を省略し、異なる部分について説明する。図5A~図5D及び図6に示すように、第2実施形態のターンオフシーケンスは、第1実施形態のターンオフシーケンスからフェーズIICを削除したものである。図5Aおよび図6のフェーズVAが図2Aおよび図3のフェーズIIAに対応し、図5Bおよび図6のフェーズVBが図2Bおよび図3のフェーズIIBに対応し、図5Cおよび図6のフェーズVCが図2Dおよび図3のフェーズIIDに対応し、図5Dおよび図6のフェーズVDが図2Eおよび図3のフェーズIIEに対応する。そして、フェーズVBでコンデンサ14を充電すると、次のフェーズVCでコントロールゲートCGの電位を0Vにすることなく、直ちにコントロールゲートCGに負電圧を印加する。
(Second Embodiment)
Hereinafter, the same parts as those in the first embodiment are denoted by the same reference numerals, description thereof will be omitted, and different parts will be described. As shown in FIGS. 5A to 5D and FIG. 6, the turn-off sequence of the second embodiment is obtained by deleting phase IIC from the turn-off sequence of the first embodiment. Phase VA in FIGS. 5A and 6 corresponds to phase IIA in FIGS. 2A and 3, phase VB in FIGS. 5B and 6 corresponds to phase IIB in FIGS. 2B and 3, and phase VC in FIGS. 5C and 6. Corresponds to the phase IID in FIGS. 2D and 3, and the phase VD in FIGS. 5D and 6 corresponds to the phase IIE in FIGS. 2E and 3. When the capacitor 14 is charged in the phase VB, a negative voltage is immediately applied to the control gate CG without setting the potential of the control gate CG to 0 V in the next phase VC.
 このような第2実施形態によれば、制御信号生成部3による各スイッチ回路の制御が簡単になる。但し、コントロールゲートCGの電位が0Vを超えている状態から負電圧を印加するので、印加される負側の電位は第1実施形態に比較して小さくなる。 According to the second embodiment, the control signal generator 3 can easily control each switch circuit. However, since the negative voltage is applied from the state where the potential of the control gate CG exceeds 0 V, the negative potential applied is smaller than that in the first embodiment.
 (第3実施形態)
 図7に示すように、第3実施形態の駆動回路21は、電源端子6と容量接続端子13aとの間にスイッチ回路SW9を追加し、制御信号生成部3に替わる制御信号生成部22が、スイッチ回路SW9のオンオフも併せて制御する。制御信号生成部22は、IGBT2を最初にターンオンさせる前に、スイッチ回路SW9及びSW4をオンさせてスタートアップ充電経路を形成し、コンデンサ14を予め設定した電圧まで充電させるようにする。これにより、最初のターンオフシーケンスからコントロールゲートCGに十分な電位の負電圧を印加することが可能になり、ターンオフシーケンスを安定して行うことができる。
(Third embodiment)
As shown in FIG. 7, the drive circuit 21 of the third embodiment adds a switch circuit SW9 between the power supply terminal 6 and the capacitor connection terminal 13a, and the control signal generation unit 22 replacing the control signal generation unit 3 includes: The on / off of the switch circuit SW9 is also controlled. Before the IGBT 2 is turned on for the first time, the control signal generator 22 turns on the switch circuits SW9 and SW4 to form a startup charging path so that the capacitor 14 is charged to a preset voltage. As a result, a negative voltage having a sufficient potential can be applied to the control gate CG from the first turn-off sequence, and the turn-off sequence can be stably performed.
 (第4実施形態)
 図8に示すように、第4実施形態のコントロールゲート駆動部31は、スイッチ回路SW1~SW6の具体構成を示す。スイッチ回路SW1はPチャネルMOSFET M1で、スイッチ回路SW6はNチャネルMOSFET M6でそれぞれ構成する。その他のスイッチ回路SW2~SW5は、何れも2つのNチャネルMOSFETのソースを共通に接続した(それぞれM21及びM22、M31及びM32、M41及びM42、M51及びM52)双方向スイッチで構成する。尚、図示しないが、メインゲート駆動部5のスイッチ回路SW7はPチャネルMOSFETで、スイッチ回路SW8はNチャネルMOSFETでそれぞれ構成すれば良い。
(Fourth embodiment)
As shown in FIG. 8, the control gate drive unit 31 of the fourth embodiment shows a specific configuration of the switch circuits SW1 to SW6. The switch circuit SW1 is composed of a P-channel MOSFET M1, and the switch circuit SW6 is composed of an N-channel MOSFET M6. The other switch circuits SW2 to SW5 are each constituted by a bidirectional switch in which the sources of two N-channel MOSFETs are connected in common (M21 and M22, M31 and M32, M41 and M42, M51 and M52, respectively). Although not shown, the switch circuit SW7 of the main gate driving unit 5 may be a P-channel MOSFET and the switch circuit SW8 may be an N-channel MOSFET.
 (第5実施形態)
 図9に示すように、第5実施形態のコントロールゲート駆動部32は、第4実施形態のコントロールゲート駆動部31におけるスイッチ回路SW2を、NチャネルMOSFET M21と、その寄生ダイオードと逆方向に直列接続されるダイオードD2とで構成し、スイッチ回路SW4を同様に、NチャネルMOSFET M41と、その寄生ダイオードと逆方向に直列接続されるダイオードD4とで構成している。このように置き換えたスイッチ回路SW2、SW4は、双方向スイッチに比較してダイオードD2、D4の順方向電圧分だけコントロールゲートCGに印加する負電圧の電位が低下するが、簡易な回路構成で実現できる。
(Fifth embodiment)
As shown in FIG. 9, the control gate drive unit 32 of the fifth embodiment has a switch circuit SW2 in the control gate drive unit 31 of the fourth embodiment connected in series in the opposite direction to the N-channel MOSFET M21 and its parasitic diode. Similarly, the switch circuit SW4 includes an N-channel MOSFET M41 and a diode D4 connected in series in the opposite direction to the parasitic diode. The switch circuits SW2 and SW4 replaced in this way are realized with a simple circuit configuration, although the potential of the negative voltage applied to the control gate CG is reduced by the forward voltage of the diodes D2 and D4 compared to the bidirectional switch. it can.
 (第6実施形態)
 図10に示すように、第6実施形態のコントロールゲート駆動部33は、第4実施形態のコントロールゲート駆動部31におけるスイッチ回路SW2を、抵抗素子R2に置き換えたものである。このように構成すれば、例えば図3に示すタイミングチャートにおけるフェーズIIC、IIEにおいて、コントロールゲートCGを放電する際の速度が、抵抗素子R2の抵抗値を含む時定数によって第1実施形態よりも遅くなるが、簡易な回路構成で実現できる。
(Sixth embodiment)
As shown in FIG. 10, the control gate drive unit 33 of the sixth embodiment is obtained by replacing the switch circuit SW2 in the control gate drive unit 31 of the fourth embodiment with a resistance element R2. With this configuration, for example, in the phases IIC and IIE in the timing chart shown in FIG. 3, the speed when discharging the control gate CG is slower than that of the first embodiment due to the time constant including the resistance value of the resistance element R2. However, it can be realized with a simple circuit configuration.
 (第7実施形態)
 例えば第1、第2実施形態では、ターンオフ動作の最後にスイッチ回路SW2をオンしてコントロールゲートCGを0Vにしていたが、第7実施形態では最後にスイッチ回路SW2をオンせず、次のターンオン動作を直ちに行うようにする。図11Bは、第2実施形態においてIGBT2を交互にターンオン、ターンオフさせた場合である。これに対して第7実施形態では、図6に示すフェーズVCからスイッチ回路SW5及びSW6をオフにすると、図11Aに示すように直ちにスイッチ回路SW7をオンしてIGBT2のターンオンに移行する。以上のような第7実施形態によれば、ターンオフ制御をより簡単にできる。
(Seventh embodiment)
For example, in the first and second embodiments, the switch circuit SW2 is turned on and the control gate CG is set to 0 V at the end of the turn-off operation. However, in the seventh embodiment, the switch circuit SW2 is not turned on last and the next turn-on is performed. Take action immediately. FIG. 11B shows a case where the IGBTs 2 are alternately turned on and turned off in the second embodiment. In contrast, in the seventh embodiment, when the switch circuits SW5 and SW6 are turned off from the phase VC shown in FIG. 6, the switch circuit SW7 is immediately turned on and the IGBT 2 is turned on as shown in FIG. 11A. According to the seventh embodiment as described above, the turn-off control can be simplified.
 本開示は上記した、又は図面に記載した実施形態にのみ限定されるものではなく、以下のような変形又は拡張が可能である。 The present disclosure is not limited to the embodiment described above or illustrated in the drawings, and the following modifications or expansions are possible.
 例えば、駆動電源電圧は20Vに限らない。必ずしもターンオン用の抵抗素子RGPと、ターンオフ用の抵抗素子RGNとを設ける必要はなく、それぞれの動作速度に問題がなければ共通の抵抗素子を用いても良い。スイッチ回路に、CMOSトランスファゲートを用いても良い。コンデンサ14の容量は、必ずしもコントロールゲートCGの容量の10倍以上に限ることなく、個別の設計に応じて適宜変更すれば良い。 For example, the drive power supply voltage is not limited to 20V. It is not always necessary to provide the turn-on resistance element RGP and the turn-off resistance element RGN, and a common resistance element may be used if there is no problem in the respective operation speeds. A CMOS transfer gate may be used for the switch circuit. The capacity of the capacitor 14 is not necessarily limited to 10 times or more of the capacity of the control gate CG, and may be appropriately changed according to the individual design.

Claims (12)

  1.  第1ゲート(G)及び第2ゲート(CG)を備えてなる逆導通絶縁ゲートバイポーラトランジスタ(RC-IGBT)(2)を駆動対象とし、前記RC-IGBTをターンオンしている状態からターンオフさせる場合は、前記第2ゲートに対して負のターンオフ電圧を印加した後に、前記第1ゲートにターンオフ電圧を印加するRC-IGBT駆動回路であって、
     前記第2ゲートに接続される第2ゲート端子(9)と、
     前記RC-IGBTのエミッタに接続されるエミッタ端子(11)と、
     容量素子が接続される2つの容量接続端子(13a、13b)と、
     前記第2ゲート端子、前記エミッタ端子、前記容量接続端子の何れかの間に接続される複数のスイッチ回路(SW2~SW6)と、
     前記複数のスイッチ回路のオンオフを制御することで、前記RC-IGBTをターンオフさせる際に、前記RC-IGBTの第2ゲート-エミッタ間容量に充電されている電荷を前記容量素子に充電させる充電経路を形成してから、前記容量素子の正電位側端子、負電位側端子を、前記エミッタ、前記第2ゲートにそれぞれ接続させる負電圧印加経路を形成する制御回路(3)とを備えるRC-IGBT駆動回路。
    When the reverse conducting insulated gate bipolar transistor (RC-IGBT) (2) including the first gate (G) and the second gate (CG) is driven, and the RC-IGBT is turned off from the turn-on state. Is an RC-IGBT driving circuit that applies a turn-off voltage to the first gate after a negative turn-off voltage is applied to the second gate,
    A second gate terminal (9) connected to the second gate;
    An emitter terminal (11) connected to the emitter of the RC-IGBT;
    Two capacitor connection terminals (13a, 13b) to which the capacitor element is connected;
    A plurality of switch circuits (SW2 to SW6) connected between any one of the second gate terminal, the emitter terminal, and the capacitor connection terminal;
    When the RC-IGBT is turned off by controlling on / off of the plurality of switch circuits, a charge path for charging the capacitor element with the charge charged in the second gate-emitter capacitor of the RC-IGBT And a control circuit (3) for forming a negative voltage application path for connecting the positive potential side terminal and the negative potential side terminal of the capacitive element to the emitter and the second gate, respectively. Driving circuit.
  2.  前記複数のスイッチ回路は、
     前記第2ゲート端子と前記エミッタ端子との間に接続される第1スイッチ回路(SW2)と、
     前記第2ゲート端子と前記容量接続端子の一方との間に接続される第2スイッチ回路(SW3)と、
     前記第2ゲート端子と前記容量接続端子の他方との間に接続される第3スイッチ回路(SW5)と、
     前記容量接続端子の一方と前記エミッタ端子との間に接続される第4スイッチ回路(SW6)と、
     前記容量接続端子の他方と前記エミッタ端子との間に接続される第5スイッチ回路(SW4)とからなる請求項1記載のRC-IGBT駆動回路。
    The plurality of switch circuits are:
    A first switch circuit (SW2) connected between the second gate terminal and the emitter terminal;
    A second switch circuit (SW3) connected between the second gate terminal and one of the capacitor connection terminals;
    A third switch circuit (SW5) connected between the second gate terminal and the other of the capacitor connection terminals;
    A fourth switch circuit (SW6) connected between one of the capacitor connection terminals and the emitter terminal;
    The RC-IGBT drive circuit according to claim 1, further comprising a fifth switch circuit (SW4) connected between the other of the capacitor connection terminals and the emitter terminal.
  3.  前記制御回路は、前記第2スイッチ回路及び前記第5スイッチ回路をオンさせて前記充電経路を形成し、
     前記第2スイッチ回路及び前記第5スイッチ回路をオフさせると、前記第1スイッチ回路をオンさせて、
     前記第1スイッチ回路をオフさせると、前記第3スイッチ回路及び前記第4スイッチ回路をオンさせて前記負電圧印加経路を形成する請求項2記載のRC-IGBT駆動回路。
    The control circuit turns on the second switch circuit and the fifth switch circuit to form the charging path,
    When the second switch circuit and the fifth switch circuit are turned off, the first switch circuit is turned on,
    3. The RC-IGBT drive circuit according to claim 2, wherein when the first switch circuit is turned off, the third switch circuit and the fourth switch circuit are turned on to form the negative voltage application path.
  4.  前記制御回路は、前記第2スイッチ回路及び前記第5スイッチ回路をオンさせて前記充電経路を形成し、
     前記第2スイッチ回路及び前記第5スイッチ回路をオフさせると、前記第3スイッチ回路及び前記第4スイッチ回路をオンさせて前記負電圧印加経路を形成する請求項2記載のRC-IGBT駆動回路。
    The control circuit turns on the second switch circuit and the fifth switch circuit to form the charging path,
    3. The RC-IGBT drive circuit according to claim 2, wherein when the second switch circuit and the fifth switch circuit are turned off, the third switch circuit and the fourth switch circuit are turned on to form the negative voltage application path.
  5.  前記制御回路は、前記第3スイッチ回路及び前記第4スイッチ回路をオフさせると、前記第1スイッチ回路をオンさせる請求項3又は4記載のRC-IGBT駆動回路。 5. The RC-IGBT drive circuit according to claim 3, wherein the control circuit turns on the first switch circuit when the third switch circuit and the fourth switch circuit are turned off.
  6.  前記制御回路(22)は、前記RC-IGBTをターンオンさせる前に、駆動電源により設定電圧まで前記容量素子を充電するスタートアップ充電経路を形成する請求項2から5の何れか一項に記載のRC-IGBT駆動回路。 The RC circuit according to any one of claims 2 to 5, wherein the control circuit (22) forms a start-up charging path for charging the capacitive element to a set voltage by a driving power supply before turning on the RC-IGBT. -IGBT drive circuit.
  7.  駆動電源が接続される電源端子と、前記充電経路の形成時に前記正電位側端子となる容量接続端子との間に接続される第6スイッチ回路(SW9)をさらに備え、
     前記制御回路(22)は、前記RC-IGBTをターンオンさせる前に前記第5スイッチ回路及び前記第6スイッチ回路をオンさせて、前記駆動電源により設定電圧まで前記容量素子を充電するスタートアップ充電経路を形成する請求項2から5の何れか一項に記載のRC-IGBT駆動回路。
    A sixth switch circuit (SW9) connected between a power supply terminal to which a drive power supply is connected and a capacitor connection terminal that becomes the positive potential side terminal when the charging path is formed;
    The control circuit (22) turns on the fifth switch circuit and the sixth switch circuit before turning on the RC-IGBT, and sets up a startup charging path for charging the capacitive element to a set voltage by the driving power supply. The RC-IGBT drive circuit according to any one of claims 2 to 5, which is formed.
  8.  前記第1スイッチ回路、前記第2スイッチ回路、前記第3スイッチ回路及び前記第5スイッチ回路の各々を2つのMOSFET(M21及びM22、M31及びM32、M41及びM42、M51及びM52)を寄生ダイオードが互いに逆方向となるように直列に接続したスイッチ回路で構成した請求項2から5又は7の何れか一項に記載のRC-IGBT駆動回路。 Each of the first switch circuit, the second switch circuit, the third switch circuit, and the fifth switch circuit includes two MOSFETs (M21 and M22, M31 and M32, M41 and M42, M51 and M52), and a parasitic diode. 8. The RC-IGBT drive circuit according to claim 2, wherein the RC-IGBT drive circuit is configured by switch circuits connected in series so as to be opposite to each other.
  9.  前記第2スイッチ回路及び前記第3スイッチ回路の各々を、2つのMOSFET(M31及びM32、M51及びM52)を寄生ダイオードが互いに逆方向となるように直列に接続したスイッチ回路で構成し、
     前記第1スイッチ回路及び第5スイッチ回路の少なくとも一方を、MOSFET(M21、M41)と、前記MOSFETの寄生ダイオードと逆方向に、前記MOSFETに直列接続されるダイオード(D2、D4)とからなるスイッチ回路で構成した請求項2から5又は7の何れか一項に記載のRC-IGBT駆動回路。
    Each of the second switch circuit and the third switch circuit is constituted by a switch circuit in which two MOSFETs (M31 and M32, M51 and M52) are connected in series so that the parasitic diodes are opposite to each other.
    At least one of the first switch circuit and the fifth switch circuit is a switch comprising a MOSFET (M21, M41) and a diode (D2, D4) connected in series to the MOSFET in a direction opposite to the parasitic diode of the MOSFET. 8. The RC-IGBT drive circuit according to claim 2, wherein the RC-IGBT drive circuit is configured by a circuit.
  10.  前記第2ゲート端子と前記エミッタ端子との間に接続される抵抗素子(R2)をさらに備え、
     前記複数のスイッチ回路は、
     前記第2ゲート端子と前記容量接続端子の一方との間に接続される第1スイッチ回路(SW3)と、
     前記第2ゲート端子と前記容量接続端子の他方との間に接続される第2スイッチ回路(SW5)と、
     前記容量接続端子の一方と前記エミッタ端子との間に接続される第3スイッチ回路(SW6)と、
     前記容量接続端子の他方と前記エミッタ端子との間に接続される第4スイッチ回路(SW4)とからなる請求項1記載のRC-IGBT駆動回路。
    A resistance element (R2) connected between the second gate terminal and the emitter terminal;
    The plurality of switch circuits are:
    A first switch circuit (SW3) connected between the second gate terminal and one of the capacitor connection terminals;
    A second switch circuit (SW5) connected between the second gate terminal and the other of the capacitor connection terminals;
    A third switch circuit (SW6) connected between one of the capacitor connection terminals and the emitter terminal;
    The RC-IGBT drive circuit according to claim 1, comprising a fourth switch circuit (SW4) connected between the other of the capacitor connection terminals and the emitter terminal.
  11.  前記制御回路は、前記第1スイッチ回路及び前記第4スイッチ回路をオンさせて前記充電経路を形成し、
     前記第1スイッチ回路及び前記第4スイッチ回路をオフさせると、前記第2スイッチ回路及び前記第3スイッチ回路をオンさせて前記負電圧印加経路を形成し、
     前記第2スイッチ回路及び前記第3スイッチ回路をオフさせるように制御する請求項10記載のRC-IGBT駆動回路。
    The control circuit turns on the first switch circuit and the fourth switch circuit to form the charging path,
    When the first switch circuit and the fourth switch circuit are turned off, the second switch circuit and the third switch circuit are turned on to form the negative voltage application path,
    The RC-IGBT drive circuit according to claim 10, wherein the second switch circuit and the third switch circuit are controlled to be turned off.
  12.  前記容量接続端子に、前記第2ゲート-エミッタ間容量の10倍以上の容量を有する容量素子を接続した請求項1から11の何れか一項に記載のRC-IGBT駆動回路。 The RC-IGBT drive circuit according to any one of claims 1 to 11, wherein a capacitive element having a capacitance of 10 times or more of the second gate-emitter capacitance is connected to the capacitance connection terminal.
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