KR102284188B1 - GATE DRIVING CIRCUIT FOR SiC MOSFET - Google Patents

Abstract

The present invention relates to a gate driving circuit for a SiC MOSFET, and a first driving circuit for generating a first driving current for driving a turn-on operation of a power switch according to a pulse width control signal output from a PWM control unit. ; a second driving circuit for generating a second driving current for driving a turn-off operation of the power switch according to the pulse width control signal; and a negative voltage generator for generating a negative voltage for turning off the power switch using a switched capacitor.

Description

Gate driving circuit for SiC MOSFET

The present invention relates to a gate driving circuit for a SiC MOSFET, and more particularly, to a gate driving circuit for a SiC MOSFET capable of generating a negative voltage for performing a turn-off operation of a SiC MOSFET using a switched capacitor.

In general, a power device is a semiconductor device that converts or controls power, and a rectifier diode, a power transistor, a triac, etc. are used in various fields such as industry, information, communication, transportation, power, and home.

Typical power devices include metal oxide semiconductor field effect transistors (MOSFETs), insulated gate bipolar transistors (IGBTs), and power integrated circuits (ICs). is attracting attention. The MOSFET includes a silicon (Si)-based MOSFET and a silicon carbide (SiC)-based MOSFET.

Compared to conventional silicon-based power semiconductor devices, SiC MOSFETs have excellent device stability at high temperatures and high voltages due to their wide energy bandwidth, high breakdown voltage characteristics, fast saturation electron speed, and excellent thermal conductivity, and operate at high operating frequencies. This makes it possible to improve the reliability of the existing electric/electronic system, increase the power conversion efficiency, and reduce the weight of the system.

However, the SiC MOSFET, as shown in FIG. 1 , has a characteristic that is not turned off completely when _{the gate voltage (V GS ) is 0V due to the interfacial defect characteristic.} The reason is that in the case of the initial SiC wafer, electrons are kept trapped in the lower region of the gate G due to interfacial defects, and through this, a channel is formed and current flows without being completely blocked. . As such, in order to completely remove electrons trapped in the lower region of the gate G, a negative voltage must be applied as the _{gate voltage V GS .}

SUMMARY OF THE INVENTION The present invention aims to solve the above and other problems. Another object of the present invention is to provide a gate driving circuit for a SiC MOSFET capable of generating a negative voltage for performing a turn-off operation of the SiC MOSFET using a switched capacitor.

According to one aspect of the present invention in order to achieve the above or other object, according to a pulse width control signal output from the PWM control unit, a first driving current for driving a turn-on operation of the power switch is generated 1 driving circuit; a second driving circuit for generating a second driving current for driving a turn-off operation of the power switch according to the pulse width control signal; and a negative voltage generator for generating a negative voltage for turning off the power switch using a switched capacitor.

More preferably, the first driving circuit includes a pre-driver and a P-type transistor, and the second driving circuit includes a pre-driver and an N-type transistor.

More preferably, the negative voltage generating unit includes a control signal generating unit generating a control signal for controlling the operation of the switched capacitor, and a switched capacitor unit charging the negative voltage in the capacitor and outputting it to the gate of the power switch. characterized.

More preferably, the control signal generator includes a NOT gate, a delay circuit, a comparator, an AND gate, and an S-R latch.

More preferably, the control signal generating unit is characterized in that, during the turn-off operation, the control signal of the on state is outputted after a specific time point when the switching noise of the power switch is generated.

More preferably, the switched capacitor includes a first switch and a second switch to which a first control signal is input, a third switch and a fourth switch to which a second control signal is input, a first and a fourth switch and the second and and a capacitor disposed between the third switches.

More preferably, when the pulse width control signal is in an on state, the switched capacitor closes the first switch and the second switch according to the first control signal, and the second switch according to the second control signal. It is characterized in that the third switch and the fourth switch are opened.

More preferably, when the pulse width control signal is in an off state, the switched capacitor opens the first switch and the second switch according to a first control signal, and the second switch according to the second control signal. It is characterized in that the third switch and the fourth switch are closed.

The effects of the gate driving circuit for SiC MOSFETs according to embodiments of the present invention will be described as follows.

According to at least one of the embodiments of the present invention, a circuit for driving a negative voltage gate can be implemented inside the driving IC, and when the driving capacity is large, the function can be implemented by installing only a low-capacity capacitor outside the driving IC. There is this.

In addition, according to at least one of the embodiments of the present invention, by sensing the _{gate voltage (V G ) of the SiC MOSFET and controlling the switched capacitor after the V DS} peak time, there is an advantage that a negative voltage can be driven with a low-capacity capacitor. .

In addition, according to at least one of the embodiments of the present invention, there is an advantage in that it is possible to prevent additional switching noise from being generated by controlling the switched capacitor after _{the V DS peak point at which the switching noise is maximally generated.}

However, effects that can be achieved by the gate driving circuit for SiC MOSFETs according to the embodiments of the present invention are not limited to those mentioned above, and other effects not mentioned may be found in the technical field to which the present invention belongs from the description below. It will be clearly understood by those of ordinary skill in the art.

1 is a diagram referenced to explain negative voltage driving of a general SiC MOSFET;
2 is a diagram showing the configuration of a power switch control circuit according to an embodiment of the present invention;
3 is a diagram illustrating a configuration of a first driving circuit and a waveform of a driving voltage according to an embodiment of the present invention;
4 is a diagram illustrating a configuration of a second driving circuit and a waveform of a driving voltage according to an embodiment of the present invention;
5 is a diagram illustrating a configuration of a negative voltage generator according to an embodiment of the present invention;
6A is a diagram illustrating a configuration of a control signal generator according to an embodiment of the present invention;
FIG. 6B is a diagram showing a waveform of a control signal output from the control signal generator of FIG. 6A;
7 is a diagram illustrating a configuration of a switched capacitor unit according to an embodiment of the present invention;
8 is a diagram referenced for explaining an operation of a switched capacitor unit according to a control signal;
9A is a diagram illustrating a detailed configuration of a gate driving circuit according to an embodiment of the present invention;
Fig. 9B is a diagram showing waveforms of signals output from the gate driving circuit of Fig. 9A;

Hereinafter, the embodiments disclosed in the present specification will be described in detail with reference to the accompanying drawings, but the same or similar components are assigned the same reference numerals regardless of reference numerals, and overlapping descriptions thereof will be omitted. The suffixes "module" and "part" for the components used in the following description are given or mixed in consideration of only the ease of writing the specification, and do not have a meaning or role distinct from each other by themselves.

In addition, in describing the embodiments disclosed in the present specification, if it is determined that detailed descriptions of related known technologies may obscure the gist of the embodiments disclosed in the present specification, the detailed description thereof will be omitted. In addition, the accompanying drawings are only for easy understanding of the embodiments disclosed in the present specification, and the technical spirit disclosed herein is not limited by the accompanying drawings, and all changes included in the spirit and scope of the present invention , should be understood to include equivalents or substitutes.

The present invention proposes a gate driving circuit for a SiC MOSFET capable of generating a negative voltage for performing a turn-off operation of the SiC MOSFET using a switched capacitor.

Hereinafter, various embodiments of the present invention will be described in detail with reference to the drawings.

2 is a diagram illustrating a configuration of a power switch control circuit according to an embodiment of the present invention.

Referring to FIG. 2 , the power switch control circuit 100 according to an embodiment of the present invention may include a power switch 110 , a PWM control unit 120 , and a gate driving circuit 130 . The components shown in FIG. 2 are not essential for implementing the power switch control circuit 100, so the power switch control circuit described herein may have more or fewer components than those listed above. can

The power switch 110 is a silicon carbide (SiC)-based power semiconductor device, and may include a SiC MOSFET including a gate (G), a drain (D), and a source (S). The SiC MOSFET 110 has characteristics of high speed, high voltage, low resistance, and high current driving characteristics. There are two types of the SiC MOSFET 110: an N-channel MOSFET that uses an N-type semiconductor between drain and source, and a P-channel MOSFET that uses a P-type semiconductor between the drain and source.

The SiC MOSFET 110 is turned on by the _{gate voltage V G} having a high level, and is turned off by the _{gate voltage V G having a low level.} off). In particular, the SiC MOSFET 110 needs to be driven with a negative voltage due to an interface defect characteristic during a turn-off operation.

The PWM controller 120 may generate a pulse width control signal V _PWM for controlling the switching operation of the power switch 110 .

For example, the PWM controller 120 may output a logic level signal having a low voltage (eg, 3V to 5V) or a logic level signal having a high voltage (eg, 15V or more). When the PWM control unit 120 outputs low voltage signals, the gate driving circuit 130 includes a level shifter for boosting the low voltage signals to high voltage signals for driving the power switch 110 . may additionally include.

The gate driving circuit 130 may generate a driving voltage V _G and a driving current I _G for driving the switching operation of the power switch 110 . For example, the gate driving circuit 130 may increase the driving voltage V _{G in synchronization with the rising edge of the pulse width control signal and decrease the driving voltage V G} in synchronization with the falling edge of the pulse width control signal. can

The gate driving circuit 130 may include a dead time generating unit 131 , a first driving circuit 132 , a second driving circuit 133 , and a negative voltage generating unit 134 . In this case, the dead time generator 131 is not necessarily a necessary component of the gate driving circuit 130 and may be selectively employed.

The dead time generator 131 is configured to provide a dead time ( dead time) can be set. In this case, the dead time may be set to 100ns to 200ns, but is not limited thereto.

The first driving circuit 132 may perform a function of generating a _{first driving current I G, source} for driving the power switch 110 during a turn-on operation.

The first driving circuit 132 may include a level shifter 310 , a pre-driver 320 , and a P-type transistor 330 as shown in FIG. 3A . there is.

An input terminal of the level shifter 310 may be connected to an output terminal of the dead time generator 131 , and an output terminal of the level shifter 310 may be connected to an input terminal of the predriver 320 . The level shifter 310 may boost the low voltage signal output from the PWM control unit 120 into a high voltage signal for driving the power switch 110 .

The predriver 320 is connected between the level shifter 310 and the P-type transistor 330 , and may output _{a first driving voltage V OUT _H for driving the P-type transistor 330 .} For example, as shown in FIG. 3B , the first driving voltage V _{OUT _H} output from the predriver 320 is higher than _{the pulse width control signal V PWM} due to the level shifter 310 . have voltage. In addition, the on timing of the first driving voltage V _{OUT _H} is a predetermined time difference (eg, 100 ns) from the on timing _{of the pulse width control signal V PWM} due to the dead time generator 131 . to 200 ns). In addition, an off timing of the first driving voltage V _{OUT _H coincides with} an off timing of the pulse width control signal V _PWM .

The P-type transistor 330 is connected between the pre-driver 320 and the power switch 110 , and can generate _{a first driving current I G, source for driving the switching operation of the power switch 110 .} there is. The P-type transistor 330 may be a P-type MOSFET device or a P-type BJT device.

Meanwhile, in this embodiment, one P-type transistor 330 is exemplified to be installed in the first driving circuit 132 , but this is not limited thereto, and a plurality of P-type transistors are installed in the corresponding driving circuit 132 . It will be apparent to those skilled in the art that it may be configurable.

The second driving circuit 133 may perform a function of generating a _{second driving current I G, sink} for driving the power switch 110 during a turn-off operation.

The second driving circuit 133 may include a level shifter 410 , a pre-driver 420 , and an N-type transistor 430 as shown in FIG. 4A .

An input terminal of the level shifter 410 may be connected to an output terminal of the dead time generator 131 , and an output terminal of the level shifter 410 may be connected to an input terminal of the predriver 420 . The level shifter 410 may boost the low voltage signal output from the PWM control unit 120 into a high voltage signal for driving the power switch 110 .

The predriver 420 is connected between the level shifter 410 and the N-type transistor 430 , and may generate _{a second driving voltage V OUT _L for driving the N-type transistor 430 .} For example, as shown in FIG. 4B , the second driving voltage V _{OUT _L} output from the predriver 420 is higher than _{the pulse width control signal V PWM} due to the level shifter 410 . have voltage. In addition, the on timing of the second driving voltage V _{OUT _L} is a predetermined time difference (eg, 200 ns) from the off timing _{of the pulse width control signal V PWM} due to the dead time generator 131 . to 300 ns). In addition, an off timing of the second driving voltage V _{OUT _L} coincides with an on timing of the pulse width control signal V _{PWM .}

The N-type transistor 430 is connected between the pre-driver 420 and the power switch 110 , and can generate _{a second driving current I G, sink for driving a switching operation of the power switch 110 .} there is. Here, the N-type transistor 430 may be an N-type MOSFET device or an N-type BJT device.

The negative voltage generator 134 may generate a negative voltage for turning off the power switch 110 using the switched capacitor.

The negative voltage generator 134 performs a turn-off operation of the power switch 110 and the control signal generator 510 that generates a control signal for controlling the operation of the switched capacitor, as shown in FIG. 5 . It may include a switched capacitor unit 520 for generating a negative voltage for

6A is a diagram illustrating a configuration of a control signal generator according to an embodiment of the present invention, and FIG. 6B is a diagram illustrating a waveform of a control signal output from the control signal generator of FIG. 6A.

Referring to FIG. 6A , the control signal generator 510 according to the present invention includes a NOT gate (or inverter, 610), a delay circuit 620, a comparator 630, an AND gate 640, an SR latch 650, and the like. may include. The components shown in FIG. 6A are not essential for implementing the control signal generation unit 510, so the control signal generation unit described herein may have more or fewer components than those listed above. there is.

An input terminal of the NOT gate 610 may be connected to an output terminal of the PWM control unit 120 , and an output terminal of the NOT gate 610 may be connected to an input terminal of the delay circuit 620 . The NOT gate 610 may perform a function of calculating and outputting the _{pulse width control signal V PWM} input to the control signal generator 510 by logically negating (NOT). I.e., NOT gate 610 may convert the high level of the pulse width control signal (V _PWM) to the low level, and converts the low level of the pulse width control signal (V _PWM) to the high level.

)를 일정 시간(T) 지연시키는 기능을 수행할 수 있다.The delay circuit 620 is connected between the NOT gate 610 and the AND gate 640, and the pulse width control signal (

) can be delayed for a certain time (T).

The comparator (or gate voltage sensing unit, 630 ) may be connected to the gate terminal of the SiC MOSFET 110 _{to sense the gate voltage (V G} ) of the SiC MOSFET 110 . An operational amplifier (OP AMP) may be used as the comparator 630 , but is not limited thereto.

The first input terminal of the AND gate 640 is connected to the output terminal of the delay circuit 620 , the second input terminal of the AND gate 640 is connected to the output terminal of the comparator 630 , and the AND gate 640 . The output terminal of may be connected to the first input terminal of the SR latch 650 .

)와 비교기(630)를 통과한 게이트 전압 신호(V_G)를 논리곱(AND) 연산하여 출력하는 기능을 수행할 수 있다. The AND gate 640 transmits the pulse width control signal (

) and the gate voltage signal V _G passing through the comparator 630 may perform an AND operation and output.

The first input terminal S of the SR latch 650 is connected to the output terminal of the AND gate 640 , and the second input terminal R of the SR latch 650 is connected to the output terminal of the PWM control unit 120 . and the first output terminal Q of the SR latch 650 may be connected to the switched capacitor unit 520 .

The SR latch 650 is a digital logic circuit capable of storing or retaining 1-bit information, and changes the output value when S=1, R=0 or S=0, R=1, and S=0, R=0 If so, you can keep the previous state as it is.

The SR latch 650 may drive the switched capacitor unit 520 to output _{a control signal V C2 for generating a negative voltage.} For example, as shown in FIG. 6B , when the pulse width control signal V _PWM is in an on state, the SR latch 650 is an off state control signal V _{C2 for charging the switched capacitor.} ) can be printed. Meanwhile, when the pulse width control signal V _PWM is in an off state, the SR latch 650 may output _{a control signal V C2 in an on state to generate a negative voltage.}

_{The on timing of the control signal V C2} output from the SR latch 650 is the _{time when V DS} is peaked after the off time (T ₀ ) of the pulse width control signal (V _PWM) (T ₂ ). This is to perform negative voltage driving with a small capacitor by applying the on-state control signal V _C2 to the switched capacitor unit 520 at a time when the driving current I _{G and sink decreases in size.} . _{Meanwhile, the off timing of the control signal V C2} output from the SR latch 650 coincides with the on timing of the pulse width control signal V _{PWM .}

On the other hand, in another embodiment, the on (on) timing of _{the control signal (V C2} ) output from the SR latch 650 is configured to coincide with the off (off) time (T _{0 ) of the pulse width control signal (V PWM)} Alternatively, it may be configured to coincide with an arbitrary time point (T _x ) after the corresponding off time point (T _{0 ).}

7 is a diagram illustrating a configuration of a switched capacitor unit according to an embodiment of the present invention.

Referring to FIG. 7 , the switched capacitor unit 520 according to the present invention includes a first switch 710 and a second switch 720 to which a first _{control signal V C1 is input, and a second control signal V C2} . Includes a capacitor 750 disposed between the third switch 730 and the fourth switch 740, the first and fourth switches 710 and 740, and the second and third switches 720 and 730 to which are input can do.

One terminal of the first switch 710 is connected to a voltage source (V _DD ) for driving a negative voltage, and the other terminal of the first switch 710 is connected to one terminal of the fourth switch 740 and the capacitor 750 . can

One terminal of the second switch 720 may be connected to a ground (ground), and the other terminal of the second switch 720 may be connected to one terminal of the third switch 730 and the capacitor 750 . One terminal of the fourth switch 740 may be connected to a ground (ground), and the other terminal of the fourth switch 740 may be connected to one terminal of the first switch 710 and the capacitor 750 .

One terminal of the third switch 730 is connected to the gate (G) terminal of the power switch 110 , and the other terminal of the third switch 730 is connected to one terminal of the second switch 720 and the capacitor 750 . can be connected

The first switch 710 and the second switch 720 may perform a switching operation according _{to the first control signal V C1} =V _{PWM output from the PWM control unit 120 .} That is, when the first control signal V _C1 =V _PWM is in an on state, the first switch 710 and the second switch 720 are closed, and the first control signal V _C1 = V _PWM ) When the off (off) state, the first switch 710 and the second switch 720 is opened (open).

The third switch 730 and the fourth switch 740 may perform a switching operation according _{to the second control signal V C2 output from the control signal generator 510 .} That is, when the second control signal V _C2 is in an on state, the third switch 730 and the fourth switch 740 are closed, and the second control signal V _C2 is turned off ( off), the third switch 730 and the fourth switch 740 are open.

The switched capacitor unit 520 may generate a negative voltage for performing a turn-off operation of the power switch 110 by using the switched capacitor.

For example, as shown in FIG. 8 , when the pulse width control signal V _PWM is in an on state, the first switch 710 and the second switch according to the first _{control signal V C1} =V _{PWM .} 720 is closed, and the third switch 730 and the fourth switch 740 are opened according to _{the second control signal V C2 . Accordingly, the voltage of V DD} is charged in the capacitor 750 during the P1 pass.

On the other hand, when the pulse width control signal (V _PWM ) is in an off state, the first switch 710 and the second switch 720 are opened according to the first _{control signal (V C1} =V _{PWM )} and the third switch 730 and the fourth switch 740 are closed according to the second control signal V _{C2 . Accordingly, the negative voltage (-V DD} ) charged in the capacitor 750 during the P2 pass is applied to the gate of the power switch 110 . Through this, it is possible to solve the problem that the SiC MOSFET is not completely turned off when the gate voltage (V _{GS ) is 0V due to interfacial defect characteristics.}

9A is a diagram illustrating a detailed configuration of a gate driving circuit according to an embodiment of the present invention, and FIG. 9B is a diagram illustrating waveforms of signals output from the gate driving circuit of FIG. 9A.

9A and 9B , during a turn-on operation, the gate driving circuit 130 may generate a first driving current I _{G, source} through the first driving circuit 132 . The first driving circuit 132 performs basic control in accordance with the pulse width control signal V _{PWM output from the PWM control unit 120 .}

Also, during the turn-on operation, the gate driving circuit 130 may charge the _{voltage V DD for driving the negative voltage using the switched capacitor.}

Meanwhile, during a turn-off operation, the gate driving circuit 130 may generate a second driving current I _{G, sink} through the second driving circuit 133 . The second driving circuit 133 performs basic control in accordance with the pulse width control signal V _{PWM output from the PWM control unit 120 .}

Also, during the turn-off operation, the gate driving circuit 130 may apply a negative voltage (-V _DD ) to the gate of the power switch 110 using the switched capacitor.

However, in the case of the initial sink current ( _{IG, sink} ) during the turn off operation, a large driving current is required depending on the capacity of the SiC MOSFET, which is the power switch, and when this is implemented as a switched capacitor, a relatively large capacitor A problem arises in that it must be attached to the outside of the driver IC.

In order to solve this problem, the gate driving circuit 130 according to the present invention drives the switched capacitor after a certain delay time (T _{2 ) rather than the off time of the pulse width control signal (V PWM ) to drive the negative voltage} can be authorized. That is, the gate driving circuit 130 applies the on-state control signal V _C2 to the switched capacitor unit 520 at a time point T _{2 when the size of the sink current I G and sink decreases.} , it is possible to perform negative voltage driving with a small capacitor.

As described above, the gate driving circuit for a SiC MOSFET according to the present invention senses the _{gate voltage (V G ) and controls the switched capacitor after the V DS} peak time to perform negative voltage driving with a low-capacitance capacitor. . In addition, the gate driving circuit for the SiC MOSFET can prevent the occurrence of additional switching noise by controlling the switched capacitor after _{the V DS peak point at which the switching noise is maximally generated.}

Various embodiments of the present invention have been described in detail above, but the scope of the present invention is not limited thereto, and various modifications and improvements by those skilled in the art using the basic concept of the present invention as defined in the following claims are also provided. is within the scope of the

100: power switch control circuit 110: power switch
120: PWM control unit 130: gate driving circuit
131: dead time generator 132: first driving circuit
133: second driving circuit 134: negative voltage generator

Claims (7)

a first driving circuit for generating a first driving current for driving a turn-on operation of a power switch according to an on signal of a pulse width control signal (V _{PWM) output from the PWM control unit;}
a second driving circuit for generating a second driving current for driving a turn-off operation of the power switch according to an off signal of the pulse width control signal (V _PWM); and
A negative voltage generator for generating a negative voltage for performing a turn-off operation of the power switch using a switched capacitor,
The negative voltage generator, a control signal for generating a control signal _{(V C2} ) for controlling the operation of the switched capacitor based on the _{gate voltage signal (V G} ) and the pulse width control signal (V _{PWM) of the power switch} A gate driving circuit comprising a generator. According to claim 1,
The negative voltage generator controls the switched capacitor based on the _{control signal V C2} received from the control signal generator and the pulse width control signal V _{PWM received from the PWM controller to turn off the power switch.} A gate driving circuit comprising a switched capacitor unit generating a negative voltage for performing an operation. 3. The method of claim 2,
The control signal generator, when the power switch is turned on, charges a specific voltage in the capacitor in a state in which the connection with the gate of the power switch is blocked by the switch,
In the turn-off operation of the power switch, after a specific point in time when the switching noise of the power switch occurs, a switch for blocking the gate connection between the charged capacitor and the power switch is controlled to be in an on state gate driving circuit. 3. The method of claim 2,
The control signal generator, when the power switch is turned off, outputs a control signal in an on state at a start time of an off signal among the pulse width control signals. 3. The method of claim 2,
The switched capacitor unit includes a first switch and a second switch to which a first control signal is input, a third switch and a fourth switch to which a second control signal is input, and between the first and fourth switches and the second and third switches. a capacitor disposed therein;
The first control signal corresponds to the pulse width control signal (V _PWM ) output from the PWM control unit, and the second control signal corresponds to the control signal (V _C2 ) output from the control signal generator, characterized in that gate driving circuit. 6. The method of claim 5,
When the pulse width control signal is on,
The switched capacitor unit closes the first switch and the second switch according to the first control signal, and opens the third switch and the fourth switch according to the second control signal. gate driving circuit. 6. The method of claim 5,
When the pulse width control signal is off (off) state,
The switched capacitor unit opens the first switch and the second switch according to the first control signal, and closes the third switch and the fourth switch according to the second control signal.

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