KR102026931B1 - Short circuit protection for power switch - Google Patents

Abstract

The present invention relates to a short protection circuit for a power switch. The short protection circuit includes a desaturation detection part which senses a voltage (V_DS) between the drain (D) end and the source (S) end of a power switch to detect whether the power switch is out of saturation; a gate voltage control part which reduces the gate driving voltage (V_G) of the power switch to a predetermined voltage when the desaturation state of the power switch is detected; and a driving current control part which outputs pulse width control signals that can gradually adjust a gate driving current for turning off the switching operation of the power switch when the desaturation state of the power switch is detected. It is possible to stably turn off the power switch.

Description

Short circuit protection circuit for power switch {SHORT CIRCUIT PROTECTION FOR POWER SWITCH}

The present invention relates to a short circuit protection circuit for a power switch, and more particularly, to a short circuit protection circuit for sensing the desaturation state of the power switch to safely turn off the operation of the switch.

In general, a power device is a semiconductor device that converts or controls power, and rectification diodes, power transistors, and triacs are used in various fields such as industry, information, communication, transportation, power, and home.

Typical power devices include metal oxide semiconductor field effect transistors (MOSFETs), insulated gate bipolar transistors (IGBTs), bipolar to junction transistors (BJTs), and power integrated circuits (ICs). MOSFETs with low furnace losses are drawing attention. The MOSFETs typically include silicon (Si) based MOSFETs and silicon carbide (SiC) based MOSFETs.

Compared to silicon-based power semiconductor devices, SiC MOSFETs have excellent device stability at high temperature and high voltage due to wider energy band width, higher breakdown voltage characteristics, faster saturation electron velocity, and excellent thermal conductivity. It is possible to improve the reliability of the existing electric / electronic system, increase the power conversion efficiency and lighten the system. Accordingly, SiC MOSFETs are spotlighted as next generation power semiconductor devices. For these SiC MOSFETs to be used in a variety of applications, device stability must be ensured. To do this, a short-circuit protection circuit is needed to safely protect the SiC MOSFET switch.

1 is a view showing a short circuit protection circuit of a MOSFET switch according to the prior art. As shown in FIG. 1, the conventional short-circuit protection circuit 10 indirectly senses the drain current amount of the power switch 20 using a desaturation circuit composed of a diode and a capacitor. When the power switch 20 is out of saturation, the diode of the short circuit protection circuit 10 is turned off, the capacitor is charged, and the output of the SR latch is at a low level. . When the SR latch output of the low level state is input to the NAND gate 30, the NAND gate 30 outputs a high level signal to the gate driving circuit 40 regardless of the PWM signal. Accordingly, the gate driving circuit 40 protects the switch 20 by forcibly turning off the operation of the power switch 20.

However, when the power switch 20 is switched from the turned on state to the turned off state, a spike voltage is generated between the drain D terminal and the source S terminal of the switch 20, and V _DS. The spike voltage becomes larger as dI _D / dt is larger.

If the power switch momentarily turns off while the power switch is out of saturation and the drain current I _D is excessively flowing, the V _DS spike voltage is generated larger, which causes the power switch to shut off. You are in danger of breaking out of your ability. Therefore, in order to prevent damage to the power switch in advance, it is necessary to sufficiently reduce the drain current before turning off the switch.

It is an object of the present invention to solve the above and other problems. Still another object is to provide a short circuit protection circuit for a power switch that can stably turn off a power switch through gate drive voltage control when detecting a desaturation state.

Still another object is to provide a short circuit protection circuit for a power switch that can stably turn off a power switch through gate drive current control when detecting a desaturation state.

According to an aspect of the present invention to achieve the above or another object, by sensing the voltage (V _DS ) between the drain (D) stage and the source (S) stage of the power switch to the power switch is out of saturation (saturation) state Desaturation detection unit for detecting the ground; A gate voltage controller configured to reduce the gate driving voltage V _G of the power switch to a predetermined voltage when detecting a desaturation state of the power switch; And a driving current control unit configured to output pulse width control signals that can gradually adjust a gate driving current for turning off the switching operation of the power switch when the desaturation state of the power switch is detected. to provide.

More preferably, the gate voltage controller includes a zener diode for reducing the gate driving voltage V _G to a predetermined voltage.

More preferably, the short-circuit protection circuit further comprises a delay circuit unit for delaying a control signal received from the desaturation detection unit for a predetermined time τ and then outputting the control signal to the driving current controller. The delay circuit unit may control the power switch to be turned off after reducing the drain current of the power switch for a predetermined time τ through a gate voltage controller.

More preferably, the driving current controller outputs a plurality of pulse width control signals to which the binary coding is applied to the gate driving circuit. The driving current control unit may control the gate driving current of the power switch to be gradually reduced by using pulse width control signals having a predetermined waveform.

More preferably, the short-circuit protection circuit further includes a gate driving circuit having a plurality of N-type transistors having different gate sizes to enable binary coding.

Referring to the effect of the short circuit protection circuit for the power switch according to the embodiments of the present invention.

According to at least one of the embodiments of the present invention, when the desaturation state is detected, the power switch is stably turned off through voltage control of the gate, thereby preventing the power switch from being destroyed through the V _DS spike voltage. The advantage is that you can.

Further, according to at least one of the embodiments of the present invention, when the desaturation state is detected, the power switch is stably turned off through the stepwise control of the gate driving current so that the power switch is destroyed through the V _DS spike voltage. There is an advantage that can be prevented in advance.

However, the effect that the short-circuit protection circuit for the power switch according to the embodiments of the present invention can achieve is not limited to those mentioned above, and other effects that are not mentioned in the following description in the technical field to which the present invention belongs. It will be clearly understood by those of ordinary skill.

1 shows a short circuit protection circuit of a MOSFET switch according to the prior art;
2 is a diagram showing the configuration of a power switch control circuit according to an embodiment of the present invention;
3 is a block diagram illustrating a short circuit protection circuit according to an exemplary embodiment of the present invention;
4 is a diagram showing a detailed configuration of a short circuit protection circuit according to an embodiment of the present invention;
FIG. 5 is a diagram illustrating a change in sink current according to waveforms of first and second pulse width control signals; FIG.
6 is a diagram showing waveforms of a plurality of control signals output from a short circuit protection circuit;

Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings, and the same or similar components are denoted by the same reference numerals regardless of the reference numerals, and redundant description thereof will be omitted. The suffixes "module" and "unit" for components used in the following description are given or used in consideration of ease of specification, and do not have distinct meanings or roles from each other. In addition, in describing the embodiments disclosed herein, when it is determined that the detailed description of the related known technology may obscure the gist of the embodiments disclosed herein, the detailed description thereof will be omitted. In addition, the accompanying drawings are intended to facilitate understanding of the embodiments disclosed herein, but are not limited to the technical spirit disclosed herein by the accompanying drawings, all changes included in the spirit and scope of the present invention. It should be understood to include equivalents and substitutes.

The present invention proposes a short-circuit protection circuit for a power switch capable of stably turning off the power switch by controlling the gate driving voltage when detecting a desaturation state. In addition, the present invention proposes a short-circuit protection circuit for a power switch capable of stably turning off the power switch through gate drive current control when detecting a desaturation state.

Hereinafter, various embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2 is a diagram illustrating a configuration of a power switch control circuit according to an embodiment of the present invention.

Referring to FIG. 2, the power switch control circuit 100 according to an embodiment of the present invention may include a power switch 110, a PWM controller 120, a gate driving circuit 130, and a short circuit protection circuit 140. Can be. The components shown in FIG. 2 are not essential to implementing the power switch control circuit 100, so that the power switch control circuit described herein may have more or fewer components than those listed above. Can be.

The power switch 110 is a kind of semiconductor power device, and may include a power MOSFET consisting of a gate G, a drain D, and a source S. The power MOSFET 110 has a property of high speed, high voltage, and high current driving.

The power MOSFET 110 includes an N-channel MOSFET that makes an N-type semiconductor between a drain (D) and a source (S) and a P-channel MOSFET that makes a P-type semiconductor between a drain (D) and a source (S). There is a kind. In addition, the power MOSFET 110 includes silicon (Si) based MOSFETs and silicon carbide (SiC) based MOSFETs.

MOSFET (110) for power is high level (high level) to which the gate drive voltage (or the gate voltage, V _G) is turned on (turn on) and low level (low level) gate drive voltage (V _G having a by Is turned off.

The PWM controller 120 may generate a pulse width control signal V _PWM for controlling the switching operation of the power switch 110.

For example, the PWM controller 120 may output a logic level signal having a low voltage (eg, 3V to 5V), or output a logic level signal having a high voltage (eg, 15V or more). When the PWM controller 120 outputs a low voltage logic level signal, the gate driving circuit 130 converts the low voltage logic level signal into a high voltage logic level signal for driving the power switch 110. shifter) and a pre-driver may be further included.

The gate driving circuit 130 may generate a driving voltage V _G and a driving current I _G for driving the switching operation of the power switch 110. For example, the gate driving circuit 130 increases the driving voltage V _G in synchronization with the rising edge of the pulse width control signal and decreases the driving voltage V _G in synchronization with the falling edge of the pulse width control signal. Can be.

The gate driving circuit 130 may include a dead time generator (not shown), a source driving circuit (not shown), and a sink driving circuit (not shown). In this case, the dead time generator is not necessarily a component of the gate driving circuit 130 and may be selectively employed.

The dead time generator may be configured to prevent a high level signal for turning on the switching operation of the power switch 110 and a low level signal for turning off the switching operation of the power switch 110 simultaneously. You can set the dead time. At this time, the dead time may be set to 100ns to 200ns, but is not necessarily limited thereto.

The source driving circuit may generate a first driving current (ie, source current, I _{G, source} ) for driving the power switch 110 during the turn on operation. The source driving circuit may include a level shifter, a pre-driver, a P-type transistor, and the like. Here, the P-type transistor may be a P-type MOSFET device or a P-type BJT device.

The sink driving circuit may generate a second driving current (ie, sink current, I _{G, sink} ) for driving the power switch 110 during the turn-off operation. The sink driving circuit may include a level shifter, a pre-driver, an N-type transistor, and the like. Here, the N-type transistor may be an N-type MOSFET device or an N-type BJT device.

On the other hand, the level shifter and the pre-driver installed in the source driving circuit and the sink driving circuit, respectively, may be configured to be omitted depending on the purpose and design specifications of the gate driving circuit 130.

The short circuit protection circuit 140 may perform a function of forcibly turning off the operation of the switch 110 by detecting a desaturation state when the power switch 110 is turned on. In this case, the short-circuit protection circuit 140 may detect whether the corresponding switch 110 is out of saturation by sensing the voltage V _DS between the drain D terminal and the source D terminal of the power switch 110.

The short circuit protection circuit 140 may stably turn off the power switch 110 by controlling a gate driving voltage using a zener diode when detecting a desaturation state.

In addition, the short circuit protection circuit 140 may stably turn off the power switch 110 through stepwise control of the gate driving current (ie, the sink current, I _sink ) when the desaturation state is detected.

As described above, the power switch control circuit 100 according to the present invention can safely turn off the operation of the switch 110 by detecting in real time whether the power switch 110 is out of saturation.

3 is a block diagram illustrating a short circuit protection circuit according to an exemplary embodiment of the present invention.

Referring to FIG. 3, the short circuit protection circuits 140 and 200 according to the present invention may include a desaturation detector 210, a gate voltage controller 220, a drive current controller 230, and a delay circuit unit 240. . The components shown in FIG. 3 are not essential to implementing the short circuit protection circuit 200, so that the short circuit protection circuit described herein may have more or fewer components than those listed above.

The desaturation detection unit 210 may detect whether the switch 110 enters a desaturation state when the power switch 110 is turned on. To this end, the desaturation detection unit 210 is connected to the drain (D) end of the power switch 110, the voltage (V _DS ) between the drain (D) end and the source (S) end of the power switch 110. You can sense it. The desaturation detector 210 may detect in real time whether the power switch 110 leaves the saturation state based on the sensed voltage V _DS .

When the desaturation detection unit 210 detects a desaturation state, the desaturation detection unit 210 may output a control signal for turning off the switching operation of the power switch 110 to the gate voltage control unit 220 and the delay circuit unit 240.

When the desaturation state is detected, the gate voltage controller 220 may reduce the drain current I _D flowing through the switch 110 by reducing the gate driving voltage V _G of the power switch 110.

The gate voltage controller 220 decreases the drain current I _D before the power switch 110 is turned off, so that the power switch 110 is connected between the drain D end and the source S end of the switch 110. It is possible to prevent the generation of V _DS spike voltage exceeding the breakdown voltage of).

The driving current controller 230 may output pulse width control signals capable of adjusting the gate driving current (ie, sink current) for turning off the switching operation of the power switch 110. In this case, binary coding may be applied to the pulse width control signals.

The driving current controller 230 minimizes the sink current in a predetermined period immediately before the gate voltage V _gs of the power switch 110 is changed to the threshold voltage V _th , thereby primarily changing the drain current dI. _D / dt), and secondly minimize the V _DS spike voltage of the power switch 110. That is, the driving current controller 230 applies a high sink current in the initial period of turn-off, and applies a low sink current near the threshold voltage V _th which affects the V _DS spike voltage.

The delay circuit unit 240 may delay the control signal received from the desaturation detection unit 210 for a predetermined time τ and then output the signal to the input terminal of the driving current controller 230. This is to reduce the drain current amount for a predetermined time τ through the gate driving voltage control, and then turn off the switching operation of the power switch 110.

As described above, the short circuit protection circuit 200 according to the present invention may stably turn off the power switch 110 through the gate driving voltage control when the desaturation state is detected. In addition, the short circuit protection circuit 140 may stably turn off the power switch 110 through stepwise control of the sink current I _sink when the desaturation state is detected.

4 is a diagram illustrating a detailed configuration of a short circuit protection circuit according to an exemplary embodiment of the present invention.

Referring to FIG. 4, the short circuit protection circuit 200 according to the present invention may include a desaturation detector 210, a gate voltage controller 220, a drive current controller 230, and a delay circuit unit 240.

The desaturation detection unit 210 may include an SR latch 211, a comparator 212, a P-type transistor 213, an N-type transistor 214, a capacitor 216, a diode 217, and a current source 218. Can be.

단은 지연 회로부(240) 및 게이트 전압 제어부(220)에 연결될 수 있다. 비교기(212)의 제1 입력 단(-)은 N형 트랜지스터(214)의 소스(S) 단과 커패시터(216)의 타 단에 연결될 수 있고, 제2 입력 단(+)은 커패시터(216)의 일 단과, P형 및 N형 트랜지스터(213, 214)의 드레인(D) 단과, 다이오드(217)의 애노드 단에 연결될 수 있다. 커패시터(216)의 일 단은 비교기(212)의 제2 입력 단(+)과 P형 및 N형 트랜지스터(213, 214)의 드레인(D) 단과 다이오드(217)의 애노드 단에 연결될 수 있고, 타 단은 비교기(212)의 제1 입력단(-)과 N형 트랜지스터(214)의 소스(S) 단에 연결될 수 있다. 다이오드(217)의 캐소드 단은 전력 스위치(110)의 드레인(D) 단에 연결될 수 있다. 전류원(218)은 P형 트랜지스터(218)의 소스(S) 단에 연결될 수 있다.The S (Set) end of the SR latch 211 may be connected to the output end of the comparator 212 and the

The stage may be connected to the delay circuit unit 240 and the gate voltage controller 220. The first input terminal (-) of the comparator 212 may be connected to the source S terminal of the N-type transistor 214 and the other end of the capacitor 216, and the second input terminal (+) may be connected to the capacitor 216. It may be connected to one end, a drain D end of the P-type and N-type transistors 213 and 214, and an anode end of the diode 217. One end of the capacitor 216 may be connected to the second input end (+) of the comparator 212, the drain (D) end of the P-type and N-type transistors 213 and 214, and the anode end of the diode 217. The other end may be connected to the first input terminal (-) of the comparator 212 and the source S terminal of the N-type transistor 214. The cathode end of the diode 217 may be connected to the drain D end of the power switch 110. The current source 218 may be connected to the source S terminal of the P-type transistor 218.

Desaturation detection unit 210 having such a configuration is connected to the drain (D) end of the power switch 110, the voltage (V _DS ) between the drain (D) end and the source (S) end of the power switch 110. Can sense. When the sensed voltage V _DS exceeds a predetermined threshold, the desaturation detector 210 may detect that the power switch 100 in the turned on state is out of saturation.

When the power switch 110 is out of saturation state, the cathode voltage of the diode 217 connected to the drain D terminal of the switch 110 becomes greater than the anode voltage. Accordingly, the diode 217 operates in an off state, and a current applied from the current source 218 passes through the P-type transistor 213 to charge the capacitor 216.

단을 통해 로우 레벨 신호를 출력하게 된다. 한편, 본 실시 예에서는, SR 래치(211)의

단을 통해 제어 신호를 출력하는 것을 예시하고 있으나 이를 제한하지는 않으며

단을 통해 제어 신호를 출력할 수 있음은 당업자에게 자명할 것이다. When the voltage of the capacitor 216 is charged, the comparator 212 outputs a low level signal because the comparator voltage 215 of the comparator and the charging voltage of the capacitor 216 are equal to each other. When the low level signal is input to the S (Set) end of the SR latch 211, the SR latch 211 is

A low level signal is output through the stage. On the other hand, in the present embodiment, the SR latch 211

It illustrates an example of outputting a control signal through a stage, but the present invention is not limited thereto.

It will be apparent to those skilled in the art that the control signal can be output through the stage.

The gate voltage controller 220 may include an inverter 221, a buffer gate 222, an N-type transistor 223, and a zener diode 224. Here, the buffer gate 222 may be configured to be omitted according to an embodiment.

단에 연결될 수 있고, 출력 단은 버퍼 게이트(222)의 입력 단에 연결될 수 있다. 버퍼 게이트(222)의 입력 단은 인버터(221)의 출력 단에 연결될 수 있고, 출력 단은 N형 트랜지스터(223)의 게이트(G) 단에 연결될 수 있다. N형 트랜지스터(223)의 게이트(G) 단은 버퍼 게이트(222)의 출력 단에 연결될 수 있고, 드레인(D) 단은 제너 다이오드(224)의 애노드 단에 연결될 수 있고, 소스(S) 단은 접지(ground)에 연결될 수 있다. 제어 다이오드(224)의 애노드 단은 N형 트랜지스터(223)의 드레인(D) 단에 연결될 수 있고, 캐소드 단은 전력 스위치(110)의 게이트(G) 단에 연결될 수 있다.The input terminal of the inverter 221 is connected to the SR latch 211

The output stage may be connected to the input terminal of the buffer gate 222. The input terminal of the buffer gate 222 may be connected to the output terminal of the inverter 221, and the output terminal may be connected to the gate G terminal of the N-type transistor 223. The gate (G) terminal of the N-type transistor 223 may be connected to the output terminal of the buffer gate 222, the drain (D) terminal may be connected to the anode terminal of the zener diode 224, and the source (S) terminal May be connected to ground. The anode terminal of the control diode 224 may be connected to the drain (D) terminal of the N-type transistor 223, the cathode terminal may be connected to the gate (G) terminal of the power switch 110.

단을 통해 로우 레벨 신호를 출력하게 되면, 인버터(221)는 입력 신호를 반전시켜 하이 레벨 신호를 출력하게 된다. 버퍼 게이트(222)는 인버터(221)로부터 입력된 하이 레벨 신호를 변경하지 않고, 해당 신호를 그대로 출력하게 된다. 하이 레벨 신호가 N형 트랜지스터(223)의 게이트(G) 단으로 입력되면, N형 트랜지스터(223)는 턴 온(turn on) 동작을 수행하게 된다. 상기 N형 트랜지스터(223)가 턴 온 상태로 스위칭되면, 제너 다이오드(224)는 애노드 단이 접지(ground)와 연결되어 동작하게 된다. 제너 다이오드(224)는 전력 스위치(110)의 게이트 구동전압을 미리 결정된 전압으로 낮추게 된다. 예를 들어, 12V의 제너 다이오드를 사용하게 되면, 25V로 구동하는 게이트 전압을 12V로 강제로 낮춰주게 된다.When detecting the desaturation state of the power switch 110, the SR latch 211

When the low level signal is output through the terminal, the inverter 221 inverts the input signal and outputs the high level signal. The buffer gate 222 outputs the signal as it is without changing the high level signal input from the inverter 221. When the high level signal is input to the gate G terminal of the N-type transistor 223, the N-type transistor 223 performs a turn on operation. When the N-type transistor 223 is switched on, the zener diode 224 operates with an anode terminal connected to ground. The zener diode 224 lowers the gate driving voltage of the power switch 110 to a predetermined voltage. For example, using a 12V Zener diode forces a gate voltage of 25V to 12V.

The gate voltage controller 220 reduces the gate driving voltage V _G of the switch 110 before the power switch 110 is turned off, and drain current I _D flowing through the switch 110. Can be reduced. Accordingly, the gate voltage controller 220 may prevent the V _DS spike voltage exceeding the breakdown voltage of the switch 110 from being generated between the drain D terminal and the source S terminal of the power switch 110. Can be.

Meanwhile, in the present exemplary embodiment, although the use of the zener diode to lower the gate driving voltage to a predetermined voltage is illustrated, the present invention is not limited thereto, and the gate voltage controller may be implemented using a circuit other than the zener diode.

단으로부터 수신된 로우 레벨 신호를 미리 결정된 시간(τ) 동안 지연시킨 다음 NAND 게이트(231)의 입력 단으로 출력할 수 있다. 가령, 도 6에 도시된 바와 같이, 전력 스위치(110)가 포화 상태를 벗어나는 것을 t₁ 시점에 감지하는 경우, SR 래치(211)는 t₁ 시점을 기산점으로 하여 로우 레벨 신호를 출력하게 된다. 지연 회로부(240)는 t₁ 시점으로부터 일정 시간(τ)이 경과한 t₂ 시점을 기산점으로 하여 로우 레벨 신호를 출력하게 된다. 이는 게이트 구동전압 제어를 통해 일정 시간(τ) 동안 드레인 전류량을 감소시킨 다음, 전력 스위치(110)의 스위칭 동작을 턴 오프시키기 위함이다.Delay circuitry 240 is connected to SR latch 211

The low level signal received from the terminal may be delayed for a predetermined time τ and then output to the input terminal of the NAND gate 231. For example, as illustrated in FIG. 6, when the power switch 110 detects that the power switch 110 is out of saturation at time t ₁ , the SR latch 211 outputs a low level signal using the time t _{1 as a base} point. Delay circuit section 240 to the time t ₂ has passed a predetermined time (τ) from time t ₁ to gisanjeom, and outputs a low-level signal. This is to reduce the drain current amount for a predetermined time τ through the gate driving voltage control, and then turn off the switching operation of the power switch 110.

The driving current controller 230 may include a NAND gate 231 and a sink current controller 232. An input terminal of the NAND gate 231 may be connected to a PWM controller (not shown) and a delay circuit unit 240, and an output terminal may be connected to the P-type transistor and the sink current controller 232 of the gate driving circuit 130. have. An input terminal of the sink current controller 232 may be connected to the NAND gate 231, and an output terminal may be connected to the first and second N-type transistors of the gate driving circuit 130.

Meanwhile, in the present embodiment, the gate driving circuit 130 may include one or more P-type transistors for generating the source current I _{G and source} and two or more N-type transistors for generating the sink current I _{G and sink} . Can include them. In this case, the gate driving circuit 130 may include N-type transistors having different gate sizes to enable binary coding. For example, as illustrated in the drawing, the size of the second N-type transistor X2 may be twice the size of the first N-type transistor X1. Due to the size ratio of the transistors, the magnitudes of the second sink currents I _{G and sink2} generated in the second N-type transistor X2 are equal to the first sink currents I _G, generated in the first N-type transistor X1 _{. It} may be twice the size of _sink1 ).

When the PWM signal output from the PWM controller and the low level signal output from the SR latch 211 are input to the NAND gate 231, the NAND gate 231 always outputs a high level signal regardless of the waveform of the PWM signal. do.

When the high level signal is input to the P-type transistor of the gate driving circuit 130, the P-type transistor performs a turn off operation. Meanwhile, when the high level signal is input to the sink current controller 232, the sink current controller 232 may output pulse width control signals capable of adjusting the sink current for turning off the switching operation of the power switch 110 in steps. Can be.

That is, the sink current controller 232 may generate first and second pulse width control signals V _PWM1 and V _PWM2 based on the high level signal received from the NAND gate 231. The sink current controller 232 outputs the first pulse width control signal V _PWM1 to the first N-type transistor X1 of the gate driving circuit 130, and outputs the second pulse width control signal V _PWM2 to the gate driving circuit. The second N-type transistor X2 of the furnace 130 may be output. In this case, binary coding may be applied to the first and second pulse width control signals.

For example, as shown in FIG. 5, the first and second pulse width control signals V _PWM1 and V _PWM2 are combined in four combinations ({low level signal (off), low level signal (off)) through binary coding. }, {High level signal (on), low level signal (off)}, {low level signal (off), high level signal (on)}, {high level signal (on), high level signal (on)}) It may be configured as. Accordingly, the gate driving circuit 130 may include four sink currents 0 and first sink currents having different magnitudes according to waveforms of the first and second pulse width control signals V _PWM1 and V _PWM2 . I _{G, sink1} ), the second sink current I _{G, sink2} , and the first sink current + second sink current I _{G, sink1} + I _{G, sink2} may be generated.

When the sink current controller 232 outputs the pulse width control signals V _PWM1 and V _PWM2 to which the predetermined binary coding is applied, the gate driving circuit 130 sinks the sink current I _G of the power switch 110. ) Can be adjusted step by step. For example, as shown in FIG. 6, the sink current control unit 232 has a waveform having a waveform of {H, L, H, H} based on a time point t ₂ after a predetermined time τ has elapsed from time t ₁ . The second pulse width control signal V _PWM2 having the waveform of one pulse width control signal V _PWM1 and {H, H, L, L} may be output. Accordingly, the gate driving circuit 130 may gradually reduce the sink current I _{G, sink} for turning off the switching operation of the power switch 110. That is, the gate driving circuit 130 may set the magnitudes of the sink currents I _{G and sink} as' the first sink current I _{G and sink1} + the second sink current I _{G and sink2} 'and' the second sink current ( I _{G, sink2} ) ', and the first sink current I _{G, sink1} may be decreased in this order.

As such, the sink current controller 232 may minimize the V _DS spike voltage of the power switch 110 by minimizing the sink current around the threshold voltage V _{th in which} the amount of change of the drain current dI _D / dt is large. have.

Meanwhile, in the present exemplary embodiment, two pulse width control signals are used, but the present invention is not limited thereto and three or more pulse width control signals may be used. Therefore, when the sink current control unit 232 outputs n pulse width control signals to which binary coding is applied, the gate driving circuit 130 according to the waveform of the pulse width control signals totals 2 ⁿ sink currents I _{G, sink} ).

As described above, when the desaturation state of the power switch is detected, the short circuit protection circuit 200 according to the present invention uses the at least one of the gate driving voltage control and the gate driving current control to switch the switch 110. Can be turned off stably.

Although various embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concept of the present invention as defined in the following claims are also provided. It belongs to the scope of rights.

100: power switch control circuit 110: power switch
120: PWM controller 130: gate driving circuit
140/200: short circuit protection circuit 210: desaturation detection unit
220: gate voltage controller 230: drive current controller
240: delay circuit

Claims (5)

A desaturation detector for sensing whether the power switch is out of a saturation state by sensing a voltage V _DS between a drain D end and a source S end of a power switch;
A gate voltage controller configured to reduce the gate driving voltage V _G of the power switch to a predetermined voltage when detecting a desaturation state of the power switch; And
And a driving current controller configured to generate and output pulse width control signals in which the gate driving current for turning off the switching operation of the power switch can be adjusted when the desaturation state of the power switch is detected,
The driving current controller outputs a plurality of pulse width control signals to which a binary coding is applied to a gate driving circuit, and controls the gate driving current of the power switch to be reduced step by step. Protection circuit. The method of claim 1,
The gate voltage controller includes a zener diode for reducing the gate driving voltage (V _G ) to a predetermined voltage. The method of claim 1,
And a delay circuit unit delaying the control signal received from the desaturation detection unit for a predetermined time τ and then outputting the control signal to the driving current controller.
And the delay circuit unit reduces the drain current of the power switch for a predetermined time (τ) through the gate voltage controller and then controls the power switch to be turned off. delete The method of claim 1,
And a gate driving circuit having a plurality of N-type transistors having different gate sizes to enable the binary coding.

Images