KR20210070591A - Short circuit protection for power switch - Google Patents

Abstract

The present invention relates to a short circuit protection circuit for a power switch, which comprises: a desaturation detecting unit for sensing voltage (VDS) between a drain (D) terminal and a source (S) terminal of a power switch to detect whether the power switch is out of a saturation state; a driving current control unit for controlling a gate driving current for turning off the power switch when a desaturation state of the power switch is detected; a delay circuit unit for delaying a control signal received from the desaturation detecting unit for a predetermined time (τ) when detecting the desaturation state, and then outputting the same to the driving current control unit; and a noise detection unit for initializing operations of the desaturation detecting unit and the delay circuit unit when a short circuit state is not maintained for the predetermined time (τ) in case of detecting the desaturation state. Accordingly, an unstable operation caused by noise can be prevented.

Description

Short circuit protection circuit for power switch {SHORT CIRCUIT PROTECTION FOR POWER SWITCH}

The present invention relates to a short-circuit protection circuit for a power switch, and more particularly, to a short-circuit protection circuit for a power switch that is robust against switching noise or external system noise.

In general, a power device is a semiconductor device that converts or controls power, and a rectifier diode, a power transistor, a triac, etc. are used in various fields such as industry, information, communication, transportation, power, and home.

Typical power devices include metal oxide semiconductor field effect transistors (MOSFETs), insulated gate bipolar transistors (IGBTs), Bipolar Junction Transistors (BJTs), and power integrated circuits (ICs). MOSFET devices with low loss to the furnace are attracting attention. Examples of the MOSFET device include a silicon (Si)-based MOSFET device and a silicon carbide (SiC)-based MOSFET device.

In order for these MOSFET devices to be applied to various applications, device stability must be secured. To this end, a short-circuit protection circuit is required to safely protect the MOSFET device.

1 is a view showing a short circuit protection circuit of a MOSFET switch according to the prior art. As shown in FIG. 1 , the conventional short circuit protection circuit 10 indirectly controls the amount of drain current of the power switch 20 using a desaturation circuit composed _{of a diode D 1} and a capacitor C _{1 .} sense When the power switch 20 is out of the saturation state, the diode D ₁ of the short-circuit protection circuit 10 is turned off, and the capacitor C ₁ is charged so that the output of the SR latch is low. It becomes a low level state. When the SR latch output in the low level state is input to the NAND gate 30 , the NAND gate 30 outputs a high level signal to the gate driving circuit 40 regardless of the PWM signal. Accordingly, the gate driving circuit 40 forcibly turns off the operation of the power switch 20 to protect the corresponding switch 20 .

As such, the conventional short circuit protection circuit 10 protects the corresponding power switch by using a desaturation detection method of detecting a short circuit by monitoring the _{drain voltage (V DS ) of the power switch.} However, the conventional desaturation detection method has a problem in that it is difficult to implement a stable system because there is a high probability that a malfunction of the power switch caused by switching noise or external system noise occurs.

SUMMARY OF THE INVENTION The present invention aims to solve the above and other problems. Another object of the present invention is to provide a short circuit protection circuit for a power switch that is strong against switching noise or external system noise.

Another object is to detect whether a short-circuit condition is maintained for a certain period of time when a desaturation state is detected, and when the short-circuit state is not maintained for a certain period of time, initiate a short-circuit protection operation to prevent the occurrence of damage caused by switching noise or external system noise. An object of the present invention is to provide a short circuit protection circuit for a power switch capable of preventing unstable operation caused.

According to an aspect of the present invention in order to achieve the above or other object, the voltage (V _DS ) between the drain (D) terminal and the source (S) terminal of the power switch is sensed so that the power switch leaves the saturation state. Desaturation detection unit for detecting the fat; a driving current controller configured to control a gate driving current for turning off the power switch when the desaturation state of the power switch is detected; a delay circuit unit for delaying the control signal received from the desaturation detection unit for a predetermined time τ when the desaturation state is detected and then outputting it to the driving current control unit; and a noise detection unit that initializes operations of the desaturation detection unit and the delay circuit unit when the short circuit state is not maintained for the predetermined time τ when the desaturation state is detected. .

More preferably, the desaturation detection unit is characterized in that it comprises an SR latch, a capacitor and a hysteresis comparator. In addition, the hysteresis comparator is determined output a high level signal if no greater than the terminal voltage the first reference voltage (V _ThH) (V _DESAT) is determined in advance of the capacitor, and the charging voltage (V _DESAT) of the capacitor is pre claim 2 It is characterized in that a low-level signal is output when it _becomes smaller than the reference voltage V ThL.

More preferably, the noise detector includes an inverter, an AND gate, and an OR gate. In addition, when the short-circuit state is not maintained for a predetermined time τ, the noise detector generates a reset signal and outputs the reset signal to the SR latch and delay circuit unit.

The effect of the short-circuit protection circuit for a power switch according to embodiments of the present invention will be described as follows.

According to at least one of the embodiments of the present invention, when the desaturation state of the power switch is detected, by detecting whether the short-circuit state is maintained for a predetermined time, and initializing the short-circuit protection operation when the short-circuit state is not maintained for a predetermined time, There is an advantage in that it is possible to effectively prevent a malfunction of the power switch caused by switching noise or external system noise.

However, the effects that can be achieved by the short-circuit protection circuit for power switches according to the embodiments of the present invention are not limited to those mentioned above, and other effects not mentioned are in the technical field to which the present invention belongs from the description below. It will be clearly understood by those of ordinary skill in the art.

1 is a view showing a short circuit protection circuit of a MOSFET switch according to the prior art;
2 is a diagram showing the configuration of a power switch system according to an embodiment of the present invention;
3 is a block diagram of a short circuit protection circuit according to an embodiment of the present invention;
4 is a view showing a detailed configuration of a short-circuit protection circuit according to an embodiment of the present invention;
FIG. 6 is a diagram referenced to explain the operation of a hysteresis comparator applicable to the desaturation detection unit of FIG. 4 ;
Fig. 7 is a diagram illustrating an operation waveform in a short-circuit protection circuit when a noise signal is generated;
Fig. 8 is a diagram illustrating an operation waveform in a short-circuit protection circuit when a short-circuit signal is generated;

Hereinafter, the embodiments disclosed in the present specification will be described in detail with reference to the accompanying drawings, but the same or similar components are assigned the same reference numerals regardless of reference numerals, and redundant description thereof will be omitted. The suffixes "module" and "part" for the components used in the following description are given or mixed in consideration of only the ease of writing the specification, and do not have a meaning or role distinct from each other by themselves. In addition, in describing the embodiments disclosed in the present specification, if it is determined that detailed descriptions of related known technologies may obscure the gist of the embodiments disclosed in the present specification, the detailed description thereof will be omitted. In addition, the accompanying drawings are only for easy understanding of the embodiments disclosed in the present specification, and the technical spirit disclosed herein is not limited by the accompanying drawings, and all changes included in the spirit and scope of the present invention , should be understood to include equivalents or substitutes.

The present invention proposes a short circuit protection circuit for a power switch that is robust against switching noise or external system noise. In addition, the present invention detects whether a short-circuit state is maintained for a predetermined time when the desaturation state is detected, and when the short-circuit state is not maintained for a predetermined period of time, initiates a short-circuit protection operation to protect against switching noise or external system noise. We propose a short-circuit protection circuit for power switch that can prevent unstable operation caused by

Hereinafter, various embodiments of the present invention will be described in detail with reference to the drawings.

2 is a diagram illustrating a configuration of a power switch system according to an embodiment of the present invention.

Referring to FIG. 2 , the power switch system 100 according to an embodiment of the present invention may include a power switch 110 and a power switch controller for controlling a switching operation of the power switch 110 . Here, the power switch control device may include a PWM control unit 120 , a gate driving circuit 130 , and a short circuit protection circuit 140 . The components shown in FIG. 2 are not essential for implementing the power switch system 100 , so the power switch system described herein may have more or fewer components than those listed above.

The power switch 110 is a kind of semiconductor power device, and includes a power MOSFET comprising a gate (G), a drain (D), and a source (S). The power MOSFET 110 has high speed, high voltage and high current driving characteristics.

The power MOSFET 110 includes two types of an N-channel MOSFET that makes an N-type semiconductor between the drain (D)-source (S) and a P-channel MOSFET that makes a P-type semiconductor between the drain (D) and the source (S). There are kinds. In addition, the power MOSFET 110 includes a silicon (Si)-based MOSFET, a silicon carbide (SiC)-based MOSFET, a gallium nitride (GaN)-based MOSFET, and the like.

When an N-type transistor (NMOS) is used as the power switch 110 , it is turned on by the _{gate driving voltage V GS having a high level, and a gate having a low level.} It is turned off by the driving voltage V _{GS .} Conversely, when a P-type transistor (PMOS) is used as the power switch 110 , it _{is turned on by the gate driving voltage V GS} having a low level, and is turned on by a high level. It is turned off by the gate driving voltage V _{GS .}

_{The PWM control unit 120 may generate a pulse width control signal V PWM} for controlling the switching operation of the power switch 110 based on a control signal of a controller (not shown). The pulse width control signal output from the PWM control unit 120 is a signal for controlling the turn-on time of the power switch 110 according to the pulse width to adjust the amount of current.

The logic level of the pulse width control signal output from the PWM controller 120 is generally the same as the output level of the controller. Accordingly, the PWM control unit 120 may output a pulse width control signal of a low voltage (eg, 3V to 5V) equal to the output level of the controller. When the PWM controller 120 outputs a low voltage signal (eg, a control signal of 3V), the gate driving circuit 130 converts the low voltage signal to a high voltage signal (eg, 20V or more) for driving the power switch 110 . ) may include a level shifter for step-up.

Meanwhile, in another embodiment, the PWM control unit 120 may output a pulse width control signal of a high voltage (eg, 20V or more) equal to the voltage of the gate driving circuit 130 . In this case, the level shifter does not need to be installed in the gate driving circuit 130 .

The gate driving circuit 130 may generate a driving voltage V _GS and a driving current I _G for driving the switching operation of the power switch 110 . _{For example, the gate driving circuit 130 increases the driving voltage V GS} when the pulse width control signal input from the PWM control unit 120 is at a high level, and the pulse width control signal input from the PWM control unit 120 . When is at the low level, the driving voltage V _GS may be reduced.

The gate driving circuit 130 may include a dead time generator (not shown), a first driving circuit (not shown), and a second driving circuit (not shown). In this case, the dead time generator is not a necessary component of the gate driving circuit 130 and may be selectively employed.

The dead time generator generates a dead time for preventing a phenomenon in which a high level signal for turning on the power switch 110 and a low level signal for turning off the power switch 110 are simultaneously turned on. Setting function can be performed. In this case, the dead time may be set to 200 ns to 300 ns, but is not necessarily limited thereto.

The first driving circuit, based on the pulse width control signal (V _PWM ) output from the PWM control unit 120, a gate driving current for driving the turn-on operation of the power switch 110 (hereinafter, for convenience of description, ' referred to as a 'source current'). To this end, the first driving circuit may include a level shifter, a pre-driver, and a P-type transistor.

The second driving circuit, based on the pulse width control signal (V _PWM ) output from the PWM control unit 120, a gate driving current for driving the turn-off operation of the power switch 110 (hereinafter, for convenience of description, ' referred to as a 'sink current'). To this end, the second driving circuit may include a level shifter, a pre-driver, and an N-type transistor.

Meanwhile, the level shifter and the predriver respectively installed in the first and second driving circuits may be configured to be omitted depending on the purpose of use and design specifications of the gate driving circuit 130 .

The short-circuit protection circuit 140 may perform a function of forcibly turning off the operation of the corresponding switch 110 by detecting a desaturation state during the turn-on operation of the power switch 110 . _{At this time, the short-circuit protection circuit 140 senses the voltage V DS} between the drain (D) terminal and the source (D) terminal of the power switch 110 to detect whether the corresponding switch 110 is out of the saturation state. .

The short circuit protection circuit 140 may stably turn off the power switch 110 by controlling the gate driving voltage using a Zener diode when a desaturation state is detected. In addition, the short-circuit protection circuit 140 stably turns the power switch 110 by controlling the _{gate driving current (ie, the sink current, I sink} ) after a predetermined time has elapsed when a desaturation state is detected. can be turned off

The short-circuit protection circuit 140 detects whether a short-circuit state is maintained for a predetermined time when the desaturation state is detected, and initiates a short-circuit protection operation when the short-circuit state is not maintained for a predetermined time to generate switching noise. Alternatively, unstable operation of the power switch caused by external system noise may be prevented in advance.

As described above, in the power switch system 100 according to the present invention, when the desaturation state of the power switch 110 is detected, the operation of the corresponding switch using a short circuit protection circuit capable of controlling the gate driving voltage and the driving current. can be safely turned off. In addition, when the power switch system 100 detects the desaturation state of the power switch 110 , it uses a short circuit protection circuit capable of detecting noise to prevent unstable operation of the power switch caused by switching noise or external system noise. can be prevented in

3 is a block diagram of a short circuit protection circuit according to an embodiment of the present invention.

Referring to FIG. 3 , the short circuit protection circuits 140 and 200 according to an embodiment of the present invention include a desaturation detection unit 210 , a noise detection unit 220 , a gate voltage control unit 230 , a delay circuit unit 240 , and a driving unit. A current control unit 250 may be included. The components shown in FIG. 3 are not essential for implementing the short-circuit protection circuit 200, so the short-circuit protection circuit described herein may have more or fewer components than those listed above.

The desaturation detection unit 210 may detect whether the corresponding switch 110 enters a desaturation state when the power switch 110 is turned on. To this end, the desaturation detection unit 210 is connected to the drain (D) terminal of the power switch 110, the voltage (V _DS ) between the drain (D) terminal and the source (S) terminal of the corresponding switch 110 . can sense In addition, the desaturation detection unit 210 may detect in real time whether the power switch 110 is out of a saturation state based on _{the sensed voltage V DS .}

The desaturation detection unit 210 generates a control signal for turning off the switching operation of the corresponding switch 110 when the desaturation state of the power switch 110 is detected, and transmits the generated control signal to the gate voltage control unit 230 . ) and the delay circuit unit 240 .

When detecting the desaturation state of the power switch 110 , the noise detector 220 may determine whether the short circuit state is maintained for a predetermined time. As a result of the check, when the short-circuit state of the power switch 110 is not maintained for a predetermined time, the noise detector 220 may determine that a noise signal, not a short-circuit signal, is input. In this case, the noise detection unit 220 may initialize the operations of the desaturation detection unit 210 and the delay circuit unit 240 to prevent the power switch 110 from being turned off due to switching noise or external system noise.

When detecting the desaturation state of the power switch 110 , the gate voltage control unit 230 _{adjusts the gate driving voltage (V G} ) of the corresponding switch 110 to a predetermined voltage to adjust the drain current flowing through the corresponding switch 110 ( I _D ) can be reduced.

_{The gate voltage control unit 230 reduces the drain current I D} before the power switch 110 is turned off, so that between the drain (D) terminal and the source (S) terminal of the power switch 110, the corresponding switch ( 110) can be prevented in advance from generating _{the V DS} spike voltage exceeding the withstand voltage.

The delay circuit unit 240 may delay the control signal received from the desaturation detection unit 210 for a predetermined time τ, and then output it to the input terminal of the driving current control unit 250 . This is to turn off the corresponding switch 110 after reducing the drain current of the power switch 110 for a predetermined time τ through the control of the driving voltage by the gate voltage controller 230 .

The driving current controller 250 may output pulse width control signals capable of stepwise adjusting the gate driving current (ie, sink current) for forcibly turning off the power switch 110 . In this case, binary coding may be applied to the pulse width control signals.

The driving current controller 250 minimizes the sink current in a predetermined period immediately before the _{gate voltage V gs} of the power switch 110 is changed to the threshold voltage V _{th , thereby primarily changing the drain current dI D} /dt), and secondarily, it is possible to minimize the _{V DS spike voltage of the power switch 110 .} That is, the driving current controller 230 applies a high sink current in the initial period of turn-off, and applies a low sink current near the threshold voltage V _{th that affects the V DS spike voltage.}

As described above, the short-circuit protection circuit 200 according to the present invention stably controls the power switch 110 through gate driving voltage and driving current control when the desaturation state of the power switch 110 is detected. can be turned off. In addition, the short-circuit protection circuit 140 detects switching noise or external system noise when a desaturation state is detected, thereby preventing a malfunction of the power switch caused by the noise in advance.

4 is a diagram illustrating a detailed configuration of a short circuit protection circuit according to an embodiment of the present invention.

Referring to FIG. 4 , the short circuit protection circuit 200 according to an embodiment of the present invention includes a desaturation detection unit 210 , a noise detection unit 220 , a gate voltage control unit 230 , a delay circuit unit 240 , and a driving current control unit. 250 may be included.

The desaturation detection unit 210 includes an SR latch 211 , a comparator 212 , a transistor 213 , first to third resistors 214 to 216 , a capacitor 217 , a diode 218 , and a current source 219 . may include, but are not necessarily limited to. Here, the comparator 212 , the transistor 213 , and the first to third resistors 214 to 216 may implement the operation of the hysteresis comparator.

단은 게이트 전압 제어부(230) 및 지연 회로부(240)의 일 단에 연결될 수 있다.The S(Set) terminal of the SR latch 211 may be connected to _{a first node N 1} where the output terminal of the comparator 212, the gate terminal of the transistor 213, and one end of the noise detector 220 meet, the SR latch The R (Reset) terminal of 211 may be connected to one end of the noise detection unit 220 and the delay circuit unit 240 . The Q terminal of the SR latch 211 may be connected to one end of the noise detection unit 220 , and the Q terminal of the SR latch 211 is

The terminal may be connected to one end of the gate voltage control unit 230 and the delay circuit unit 240 .

The first input terminal (-) of the comparator 212 may be connected to a fourth node N _{4 where one end of the first resistor 214, R 1} and one end of the second resistor 215, R _{2 meet, and} , the second input terminal (+) may be connected to _{a second node N 2} where one end of the capacitor 217, the anode end of the diode 218, and one end of the current source 219 meet. The output terminal of the comparator 212 may be connected to _{a first node N 1} where the S(Set) terminal of the SR latch 211, the gate terminal of the transistor 213, and one end of the noise detector 220 meet.

The gate (G) terminal of the transistor 213 may be connected to _{a first node N 1} where the S (Set) terminal of the SR latch 211, the output terminal of the comparator 212, and one end of the noise detector 220 meet, and , the drain (D) terminal may be connected to a fifth node (N ₅ ) where one end of the second resistor (215, R ₂ ) and one end of the third resistor (216, R ₃ ) meet, and the source (S) terminal may be connected to the third node N ₃ where one end of the third resistor 216, R ₃ and one end of the capacitor 217, C _{1 meet.} An N-type MOSFET device may be used as the transistor 213 , but is not limited thereto. Also, the third node N ₃ may be connected to the ground, but is not limited thereto.

The first resistor (214, R ₁ ) is a fourth node (N ₄ ) where the first input terminal (−) of the comparator 212 and one end of the second resistor (215, R ₂ ) meet and an external voltage source (V _{DD )} ) can be placed between The second resistor (215, R ₂ ) is the first input terminal (-) of the comparator 212 and one end of the first resistor (214, R ₁ ) meeting the fourth node (N ₄ ) and the transistor 213 It may be disposed between the drain terminal and the fifth node N ₅ where one end of the third resistors 216 and R _{3 meet.} The third resistors 216 and R ₃ are a third node N ₃ where the source terminal of the transistor 213 and one end of the capacitors 217 and C ₁ meet, and the drain terminal of the transistor 213 and one end of the second resistor. This meeting may be arranged between the fifth nodes (N _{5 ).}

One end of the capacitors 217 and C ₁ may be connected to _{the second node N 2} where the second input terminal (+) of the comparator 212, the anode terminal of the diode 218, and one end of the current source 219 meet. and the other end may be connected to a third node N ₃ where the source S terminal of the transistor 213 and one end of the third resistors 216 and R _{3 meet.}

The anode end of the diode 218 may be connected to _{a second node (N 2} ) where the second input terminal (+) of the comparator 212 and _{one end of the capacitors 217 and C 1} and one end of the current source 219 meet. and the cathode terminal may be connected to the drain (D) terminal of the power switch 110 . The current source 218 may be connected to _{a second node N 2} where the second input terminal (+) of the comparator 212 and one terminal of the capacitors 217 and C ₁ and the anode terminal of the diode 218 meet.

The desaturation detection unit 210 having such a configuration is connected to the drain (D) terminal of the power switch 110 , and the voltage V _{DS between the drain (D) terminal and the source (S) terminal of the power switch 110 .} ) can be sensed. When the sensed voltage V _DS exceeds a predetermined threshold voltage, the desaturation detection unit 210 may detect that the turned-on power switch 100 is out of the saturation state.

When the power switch 110 is out of the saturation state, the cathode voltage of the diode 218 connected to the drain (D) terminal of the corresponding switch 110 becomes greater than the anode voltage. Accordingly, the diode 218 is switched from the on state to the off state, and the current applied from the current source 219 charges the capacitor 217 .

단을 통해 로우 레벨 신호를 출력하게 된다.A voltage is continuously charged in the capacitor 217 , so that the charging voltage V _{DESAT of the capacitor 217 is a first reference voltage (V ThH} = V _ref + V _HYS ) set at the first input terminal (-) of the comparator 212 . ), the comparator 212 outputs a high level signal. When the high level signal is input to the S (Set) terminal of the SR latch 211, the SR latch 211 outputs a high level signal through the Q terminal,

A low level signal is output through the stage.

On the other hand, when the high level signal is output from the comparator 212 , the transistor 213 is switched from the turned-off state to the turn-on state, and accordingly, the voltage set at the first input terminal (-) of the comparator 212 is the first in the reference voltage _{(V ThH = V ref + V} HYS) the second reference voltage - is changed to _{(V ThL = V ref V HYS} ). Here, the first reference voltage V _ThH may be calculated as shown in Equation 1 below, and the second reference voltage V _ThL may be calculated as shown in Equation 2 below.

_{That is, different reference voltages (V ThH} , V _ThL ) are applied to the first input terminal (-) of the comparator 212 using the above-described resistance values of the transistor 213 and the first to third resistors 214 to 216 . can be set. This is to allow the noise detector 220 to detect switching noise or external system noise.

In general, the noise signal generated in the power switch system 100 is a kind of ripple signal, and has a characteristic of rapidly decreasing within a predetermined time from the corresponding time after the transient voltage is generated at a specific time. Therefore, when the first voltage is below the second reference voltage (V _ThL) within a predetermined time a second input (+) terminal as from a first voltage greater than the reference voltage (V _ThH) applying time point of the comparator 212 is applied, short It may be determined that a noise signal, not a signal, is input.

The noise signal is input to the desaturation detection unit 210 , and the charging voltage V _DESAT of the capacitor 217 is set to the first input terminal (−) of the comparator 212 , and the second reference voltage V _ThL = V _ref - When _{less than V HYS} ), the comparator 212 outputs a low level signal. When the low-level signal is input to the gate terminal of the transistor 213 , the transistor 213 is switched from a turned-on state to a turn-off state. Accordingly, the voltage set at the first input terminal (−) of the comparator 212 returns from the second reference voltage (V _ThL = V _ref - V _HYS ) to the first reference voltage (V _ThH = V _ref + V _HYS ). will do

Meanwhile, in another embodiment, the desaturation detection unit 210 may include the non-inverting hysteresis comparator 300 instead of omitting the comparator 212 , the transistor 213 , and the first to third resistors 214 to 216 . . For example, as shown in FIG. 5 , the non-inverting hysteresis comparator 300 has a first reference voltage value (V _I =) for outputting the high-level signal V _{OH from the comparator U 1 .} V _ThH ) and a second reference voltage value (V _I = V _ThL ) for outputting the low-level signal V _OL are different from each other, and a constant voltage difference ΔV exists between the two reference voltages. Here, the first reference voltage value (V _ThH ) for outputting the high level signal (V _OH ) may be determined through Equation 3 below, and the second reference voltage value ( _{V OL ) for outputting the low level signal (V OL )} V _ThL ) may be determined through Equation 4 below.

The noise detector 220 may include an inverter (or NOT gate, 221 ), an AND gate 222 , and an OR gate 223 , but is not limited thereto.

_{The input terminal of the inverter 221 may be connected to the first node N 1} where the output terminal of the comparator 212, the gate terminal of the transistor 213, and the S(Set) terminal of the SR latch 220 meet, and the output terminal is It may be connected to the input terminal of the AND gate 222 .

A first input terminal of the AND gate 222 may be connected to an output terminal of the inverter 221 , a second input terminal may be connected to an output terminal of the delay circuit unit 240 , and a third input terminal may be connected to the SR latch 220 . ) may be connected to the Q terminal, and the output terminal may be connected to the input terminal of the OR gate 223 .

A first input terminal of the OR gate 223 may be connected to a Power On Reset (POR), a second input terminal may be connected to an output terminal of the AND gate 222 , and the output terminal may be connected to the R of the SR latch 220 . The (Reset) terminal may be connected to one end of the delay circuit unit 240 .

The noise detection unit 220 having such a configuration may determine whether the short circuit state is maintained for a predetermined time when the desaturation state of the power switch 110 is detected. As a result of the check, if the short circuit state of the power switch 110 is not maintained for a predetermined time, the noise detection unit 220 determines that a noise signal, not a short circuit signal, is input, and the desaturation detection unit 210 and the delay circuit unit ( 240) may be initialized. Here, the predetermined time corresponds to the delay time set in the delay circuit unit 240 .

When the desaturation state of the power switch 110 is detected, if the short circuit state of the corresponding switch 110 is not maintained for a predetermined time (that is, when switching noise or external system noise occurs), the capacitor 217 the charging voltage (V _DESAT) is reduced to below the second reference voltage (V _ThL), whereby the comparator 212, and outputs a low-level signal.

단에서 출력된 신호를 일정 시간 동안 지연하여 생성된 하이 레벨 신호를 AND 게이트(222)의 제2 입력 단으로 출력한다. SR 래치(211)는 Q 단을 통해 하이 레벨 신호를 AND 게이트(222)의 제3 입력 단으로 출력한다.The inverter 221 inverts the low-level signal input from the comparator 212 to generate a high-level signal, and outputs the generated high-level signal to the first input terminal of the AND gate 222 . The delay circuit unit 240 of the SR latch 211

A high level signal generated by delaying the signal output from the terminal for a predetermined time is output to the second input terminal of the AND gate 222 . The SR latch 211 outputs a high level signal to the third input terminal of the AND gate 222 through the Q terminal.

When a high level signal is input through all input terminals of the AND gate 222 , the AND gate 222 performs an AND operation on the input signals to output a high level signal. When a POR signal (ie, a low-level signal) is inputted through the first input terminal of the OR gate 223 and a high-level signal is inputted from the AND gate 222 through the second input terminal, the OR The gate 223 outputs a high level signal (ie, a reset signal) to the R (Reset) terminal of the SR latch 211 and one terminal of the delay circuit unit 240 , respectively.

단을 통해 하이 레벨 신호를 출력하게 된다. 지연 회로부(240) 역시 자신의 상태가 초기화되어 SR 래치(211)로부터 바로 전에 수신된 로우 레벨 신호를 구동전류 제어부(250)로 출력하지 않게 된다. 따라서, 스위칭 노이즈 또는 외부 시스템 노이즈가 발생하더라도, 해당 노이즈에 의해 전력 스위치(110)가 턴 오프되는 현상을 미연에 방지할 수 있게 된다.Accordingly, the SR latch 211 has its state initialized and outputs a low level signal through the Q terminal,

A high level signal is output through the stage. The delay circuit unit 240 also does not output the low level signal immediately received from the SR latch 211 to the driving current control unit 250 because its state is initialized. Accordingly, even when switching noise or external system noise occurs, it is possible to prevent the power switch 110 from being turned off by the corresponding noise in advance.

The gate voltage controller 230 may include an inverter 231 , a buffer gate 232 , a transistor 233 , and a Zener diode 234 . Here, the buffer gate 232, as a current buffer, may be configured to be omitted according to an embodiment. In addition, as the transistor 233 , an N-type MOSFET device may be used, but is not limited thereto.

단에 연결될 수 있고, 출력 단은 버퍼 게이트(232)의 입력 단에 연결될 수 있다. 버퍼 게이트(232)의 입력 단은 인버터(231)의 출력 단에 연결될 수 있고, 출력 단은 트랜지스터(233)의 게이트(G) 단에 연결될 수 있다. 트랜지스터(233)의 게이트(G) 단은 버퍼 게이트(232)의 출력 단에 연결될 수 있고, 드레인(D) 단은 제너 다이오드(234)의 애노드 단에 연결될 수 있고, 소스(S) 단은 제3 노드(N₃)에 연결될 수 있다. 제너 다이오드(234)의 애노드 단은 트랜지스터(233)의 드레인(D) 단에 연결될 수 있고, 캐소드 단은 전력 스위치(110)의 게이트(G) 단에 연결될 수 있다.The input terminal of the inverter 231 is the SR latch 211

terminal, and the output terminal may be connected to the input terminal of the buffer gate 232 . An input terminal of the buffer gate 232 may be connected to an output terminal of the inverter 231 , and an output terminal may be connected to a gate (G) terminal of the transistor 233 . A gate (G) terminal of the transistor 233 may be connected to an output terminal of the buffer gate 232 , a drain (D) terminal may be connected to an anode terminal of the Zener diode 234 , and a source (S) terminal may be connected to the first terminal. It may be connected to 3 nodes (N _{3 ).} An anode terminal of the Zener diode 234 may be connected to a drain (D) terminal of the transistor 233 , and a cathode terminal may be connected to a gate (G) terminal of the power switch 110 .

단을 통해 로우 레벨 신호를 출력하게 되면, 인버터(231)는 입력 신호를 반전시켜 하이 레벨 신호를 출력하게 된다. 버퍼 게이트(232)는 인버터(231)로부터 입력된 하이 레벨 신호를 변경하지 않고, 전류량만 증가하여 해당 신호를 그대로 출력하게 된다. 하이 레벨 신호가 트랜지스터(233)의 게이트(G) 단으로 입력되면, 상기 트랜지스터(233)는 턴 오프(turn off) 상태에서 턴 온(turn on) 상태로 전환된다. 상기 트랜지스터(233)가 턴 온 상태로 전환되면, 제너 다이오드(234)는 애노드 단이 접지(ground)와 연결되어 동작하게 된다. 제너 다이오드(234)는 전력 스위치(110)의 게이트 구동전압을 미리 결정된 전압으로 낮추게 된다. 예를 들어, 12V의 제너 다이오드를 사용하게 되면, 25V로 구동하는 게이트 전압을 12V로 강제로 낮춰주게 된다.When the desaturation state of the power switch 110 is detected, the SR latch 211

When outputting the low level signal through the stage, the inverter 231 inverts the input signal to output the high level signal. The buffer gate 232 does not change the high level signal input from the inverter 231 , but only increases the amount of current to output the signal as it is. When a high level signal is input to the gate (G) terminal of the transistor 233 , the transistor 233 is switched from a turn off state to a turn on state. When the transistor 233 is turned on, the anode terminal of the Zener diode 234 is connected to ground to operate. The Zener diode 234 lowers the gate driving voltage of the power switch 110 to a predetermined voltage. For example, if a zener diode of 12V is used, the gate voltage driven by 25V is forcibly lowered to 12V.

_{The gate voltage control unit 230 reduces the gate driving voltage V G} of the corresponding switch 110 before the power switch 110 is switched to the turn-off state, thereby reducing the drain current I _D flowing through the corresponding switch 110 . can reduce Through this, the gate voltage control unit 230 prevents the occurrence of _{a V DS} spike voltage exceeding the withstand voltage of the corresponding switch 110 between the drain (D) terminal and the source (S) terminal of the power switch 110 in advance. can Meanwhile, in the present embodiment, the use of a Zener diode to lower the gate driving voltage to a predetermined voltage is exemplified, but this is not limited thereto, and a gate voltage controller may be implemented using a circuit other than the Zener diode.

단으로부터 수신된 로우 레벨 신호를 미리 결정된 시간(τ) 동안 지연시킨 다음 NAND 게이트(251)로 출력할 수 있다. 이는 게이트 구동전압 제어를 통해 일정 시간(τ) 동안 드레인 전류량을 감소시킨 다음, 전력 스위치(110)의 스위칭 동작을 턴 오프시키기 위함이다.When the delay circuit unit 240 detects the desaturation state of the power switch 110 , the SR latch 211

The low-level signal received from the stage may be delayed for a predetermined time τ, and then output to the NAND gate 251 . This is to reduce the amount of drain current for a predetermined time τ through the gate driving voltage control and then turn off the switching operation of the power switch 110 .

On the other hand, when a high level signal is received from the noise detection unit 220 before a predetermined time τ elapses from the time when the desaturation state is detected, the delay circuit unit 240 receives the low level signal received from the SR latch 211 . By initializing the signal, the corresponding signal is not output to the NAND gate 251 . Accordingly, it is possible to effectively prevent the power switch 110 from being turned off due to switching noise or external system noise.

The driving current controller 250 may include a NAND gate 251 and a sink current controller 232 . An input terminal of the NAND gate 251 may be connected to a PWM control unit (not shown) and a delay circuit unit 240 , and an output terminal may be connected to a P-type transistor of the gate driving circuit 130 and a sink current control unit 252 . have. An input terminal of the sink current controller 252 may be connected to the NAND gate 251 , and an output terminal may be connected to one or more N-type transistors constituting the gate driving circuit 130 .

When the PWM signal output from the PWM control unit and the low level signal output from the SR latch 211 are input to the NAND gate 251, the NAND gate 251 always outputs a high level signal regardless of the form of the PWM signal. do. When a high level signal is input to the P-type transistor of the gate driving circuit 130 , the P-type transistor performs a turn-off operation.

Meanwhile, when a high level signal is input to the sink current controller 252 , the sink current controller 252 may output pulse width control signals capable of stepwise adjusting the sink current for turning off the power switch 110 . In this case, binary coding may be applied to the plurality of pulse width control signals. For example, when the sink current controller 252 outputs pulse width control signals to which a predetermined binary coding is applied, the gate driving circuit 130 may stepwise adjust _{the sink current I G, sink of the power switch 110 .} there will be Accordingly, the sink current controller 252 minimizes the sink current around the _{threshold voltage V th} where the change amount of the drain current dI _D /dt is large _{, thereby minimizing the V DS} spike voltage of the power switch 110 . .

단을 통해 하이 레벨 신호를 출력하게 된다. 지연 회로부(240) 역시 SR 래치(211)로부터 수신된 로우 레벨 신호를 초기화하여 구동전류 제어부(250)로 출력하지 않게 된다. 따라서, 스위칭 노이즈 또는 외부 시스템 노이즈에 의해 전력 스위치(110)가 턴 오프되는 현상을 효과적으로 방지할 수 있게 된다.As such, the short circuit protection circuit 200 according to the present invention detects whether the short circuit state is maintained for a predetermined delay time when the desaturation state of the power switch is detected, and when the short circuit state is not maintained for a predetermined time, the short circuit protection circuit 200 By initializing the operation, it is possible to prevent malfunction of the power switch caused by switching noise or external system noise. For example, the second reference voltage in the, capacitor 217, charging voltage (V _DESAT) a first reference voltage (V _ThH = 9V) a predetermined delay time (delay time) from a point of time in excess of, as shown in Figure 6 (V _ThL = 6V) or less, the noise detection unit 220 determines the signal as a noise signal and outputs a high level signal (ie, a reset signal) to the SR latch 211 and the delay circuit unit 240 . do. Then, the SR latch 211 initializes its state and outputs a low level signal through the Q terminal,

A high level signal is output through the stage. The delay circuit unit 240 also initializes the low level signal received from the SR latch 211 and does not output it to the driving current control unit 250 . Accordingly, it is possible to effectively prevent the power switch 110 from being turned off due to switching noise or external system noise.

단을 통해 로우 레벨 신호를 출력하게 된다. 지연 회로부(240)는 SR 래치(211)로부터 수신된 로우 레벨 신호를 일정 시간 지연한 다음 구동전류 제어부(250)로 출력하게 된다. 상기 구동전류 제어부(250)는 게이트 구동회로(130)를 통해 싱크 전류를 제어하여 전력 스위치(110)를 안정적으로 턴 오프 시키게 된다.Meanwhile, the short circuit protection circuit 200 detects whether the short circuit state is maintained for a predetermined delay time when the desaturation state of the power switch is detected, and controls the gate driving voltage and the driving current when the short circuit state is maintained for a predetermined time. It is possible to turn off the power switch stably through For example, the expiration of the charging voltage (V _DESAT) a first reference voltage (V _ThH = 9V) a predetermined delay time (delay time) from a point of time in excess of the capacitor 217 as shown in Figure 7 following the When the voltage decreases below 2 reference voltage (V _ThL = 6V), the noise detection unit 220 determines the corresponding signal as a short-circuit signal and outputs a low-level signal to the SR latch 211 and the delay circuit unit 240 . Then, the SR latch 211 outputs a high level signal through the Q terminal while maintaining the current state,

A low level signal is output through the stage. The delay circuit unit 240 delays the low level signal received from the SR latch 211 for a predetermined time and then outputs it to the driving current control unit 250 . The driving current controller 250 controls the sink current through the gate driving circuit 130 to stably turn off the power switch 110 .

Various embodiments of the present invention have been described in detail above, but the scope of the present invention is not limited thereto, and various modifications and improvements by those skilled in the art using the basic concept of the present invention as defined in the following claims are also provided. is within the scope of the

100: power switch system 110: power switch
120: PWM control unit 130: gate driving circuit
140/200: short circuit protection circuit 210: desaturation detection unit
220: noise detection unit 230: gate voltage control unit
240: delay circuit unit 250: driving current control unit

Claims (5)

_{a desaturation detection unit sensing a voltage (V DS} ) between the drain (D) terminal and the source (S) terminal of the power switch to detect whether the power switch is out of a saturation state;
a driving current controller configured to control a gate driving current for turning off the power switch when the desaturation state of the power switch is detected;
a delay circuit unit for delaying the control signal received from the desaturation detection unit for a predetermined time τ when the desaturation state is detected and outputting the delay circuit unit to the driving current control unit; and
and a noise detection unit initializing operations of the desaturation detection unit and the delay circuit unit when the short circuit state is not maintained for the predetermined time τ when the desaturation state is detected. According to claim 1,
The desaturation detection unit short circuit protection circuit for a power switch, characterized in that it comprises an SR latch, a capacitor and a hysteresis comparator. 3. The method of claim 2,
The hysteresis comparator when the charge voltage (V _DESAT) of the capacitor is pre more greater than the predetermined first reference voltage (V _ThH) outputs a high level signal, and the charging voltage (V _DESAT) of the capacitor is determined in advance, the second A short circuit protection circuit for a power switch, characterized in that when it _becomes smaller than the reference voltage (V ThL ), a low-level signal is output. 3. The method of claim 2,
The noise detection unit short circuit protection circuit for a power switch, characterized in that it includes an inverter, an AND gate and an OR gate. 5. The method of claim 4,
The noise detection unit generates a reset signal and outputs the reset signal to the SR latch and delay circuit unit when the short circuit state is not maintained for the predetermined time τ.

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