CN112039506B

CN112039506B - Driving integrated circuit of SiC MOSFET switching device

Info

Publication number: CN112039506B
Application number: CN202010740504.2A
Authority: CN
Inventors: 张艺蒙; 周敏; 吕红亮; 汤晓燕; 宋庆文; 张玉明
Original assignee: Xidian University
Current assignee: Xidian University
Priority date: 2020-07-28
Filing date: 2020-07-28
Publication date: 2023-08-08
Anticipated expiration: 2040-07-28
Also published as: CN112039506A

Abstract

The invention relates to a drive integrated circuit of a SiC MOSFET switch device, comprising: the device comprises a voltage amplitude conversion module, an under-voltage protection module, a protection execution module, an output buffer module and a Miller platform improvement module. The driving integrated circuit improves a VGS platform of the power tube in the opening process, accelerates the falling speed of VDS, reduces loss, avoids the reduction of oscillation and overshoot by sacrificing the switching speed and increasing the switching loss, and simultaneously avoids current spikes; in addition, the driving circuit is designed as an integrated circuit, so that the circuit area is greatly reduced.

Description

Driving integrated circuit of SiC MOSFET switching device

Technical Field

The invention belongs to the technical field of integrated circuits, and particularly relates to a driving integrated circuit of a SiC MOSFET switching device.

Background

Currently, power electronics devices are mainly silicon-based devices. However, the narrow forbidden bandwidth of the silicon material makes it difficult to meet the requirements of the new generation power system in terms of blocking voltage, energy consumption, operating temperature, switching frequency and the like, and becomes a bottleneck for the development of the power electronic system. In order to solve this contradiction, research on third generation semiconductor materials is rapidly advancing, and among them, silicon carbide (SiC) materials are the most promising materials to replace silicon (Si) as the first choice materials for the fabrication of new generation power semiconductor devices. As a unipolar power device, a SiC MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) is an ideal high-voltage power switching device in the blocking voltage range of 300 to 4500V due to advantages of low on-resistance, high input impedance, high switching speed, and the like, and is very likely to replace a Si IGBT (Insulated Gate Bipolar Transistor ) device, and the overall efficiency and switching frequency of the system can be improved.

However, compared with the current state of the art of silicon carbide devices, the circuit application based on silicon carbide devices has not been popularized on a large scale, and in order to exert the potential and performance of SiC power devices to the maximum extent, the application circuit design of the SiC power devices needs to be modified and perfected according to the characteristics of the SiC power devices. The most direct and important part is a design method of a SiC MOSFET driving and protecting module, and the SiC MOSFET driving and protecting module directly controls the on and off of a SiC power device and directly influences the working performance and efficiency of the power device. Therefore, the driving and protection of the SiC MOSFET are researched and perfected, so that the SiC power device can be more rapidly and stably applied to a power electronic system, and the SiC power device has important significance in popularization.

In the application documents of Gao-tian, yang Yan and Cheng Ze et al (application publication No. CN108683327A, application No. 201810600993.4 and application date 2018.06.12), a silicon carbide MOSFET driving circuit is disclosed, a PWM (Pulse width modulation ) control circuit generates PWM pulse signals, after the PWM pulse signals pass through a driving signal amplifying circuit, a silicon carbide MOSFET switch is controlled through a resistor, a power supply output comprises +15V, 0V and-3V direct current voltages, and the +15V and-3V direct current voltages respectively supply power to the driving signal amplifying circuit, and the sources of the 0V and silicon carbide MOSFETs are connected; the silicon carbide MOSFET driving circuit can reduce crosstalk between upper and lower tubes of a bridge arm circuit in the power electronic converter by utilizing the driving negative voltage to turn off, so that bridge arm through is avoided, and the reliability of the silicon carbide MOSFET is improved; the diode can clamp the gate voltage to a safe range, so that the breakdown damage of the silicon carbide MOSFET gate is avoided; in the circuit, a discharge loop is formed by using the MOS tube M1, so that the turn-off speed of the silicon carbide MOSFET is increased, the switching speed of the silicon carbide MOSFET is increased, and the switching loss is reduced; the defects are that: the discrete components are utilized to build the circuit, so that the circuit area is relatively large; no corresponding solution is proposed for the miller effect during the silicon carbide MOSFET turn-on.

Zeng Zheng, shao Weihua, chen, etc. (Chinese motor engineering journal, 2018.4:1165-1176) discloses a method for regulating the switching behavior of a SiC MOSFET based on a gate driving loop, which is based on a plurality of degrees of freedom of regulation of the gate driving loop on the basis of parasitic parameters of the SiC MOSFET devices, establishes a circuit model of the switching process of the SiC MOSFET, analyzes the dynamic behavior of the switching process by using a mathematical model, and researches the effectiveness and the limitation of regulating the switching behavior by using gate resistance, parallel gate-source capacitance and driving voltage. The defects are that: these methods essentially trade off oscillations and overshoot reduction by sacrificing switching speed, increasing switching losses.

Accordingly, the existing silicon carbide MOSFET circuit has the following disadvantages: the circuit area is relatively large; the miller effect exists during the turn-on of the silicon carbide MOSFET; by sacrificing switching speed, increasing switching losses in exchange for oscillation and overshoot reduction.

Disclosure of Invention

In order to solve the above problems in the prior art, the present invention provides a driving integrated circuit of a SiC MOSFET switching device. The technical problems to be solved by the invention are realized by the following technical scheme:

The embodiment of the invention provides a driving integrated circuit of a SiC MOSFET switch device, which comprises: the device comprises a voltage amplitude conversion module, an under-voltage protection module, a protection execution module, an output buffer module and a Miller platform improvement module, wherein,

the input end of the voltage amplitude conversion module is used for inputting an external input square wave signal, the output end of the voltage amplitude conversion module is connected with the first input end of the protection execution module, the output end of the under-voltage protection module is connected with the second input end of the protection execution module, the output end of the protection execution module is connected with the input end of the output buffer module, the output end of the output buffer module is connected with the grid electrode of an external SiC MOSFET power tube, the first input end of the Miller platform improvement module is connected with the source electrode of the external SiC MOSFET power tube, the second input end of the Miller platform improvement module is connected with the drain electrode of the external SiC power tube, and the output end of the Miller platform improvement module is connected with the output end of the output buffer module;

the voltage amplitude conversion module is used for converting the amplitude of the square wave signal into the amplitude of the protection execution module;

the under-voltage protection module is used for outputting a first level or a second level according to the value of the power supply voltage;

The protection execution module is used for generating a first control signal to cut off the power supply and keep the cut-off state of the power supply when receiving the first level or generating a second control signal to restore the working state of the circuit when receiving the second level;

the output buffer module is used for outputting a third control signal consistent with the first control signal level according to the first control signal or outputting a fourth control signal consistent with the second control signal level according to the second control signal;

the miller platform improvement module is used for acting on the third control signal at the moment when the miller platform starts in the starting process of the external power tube so as to change the change trend of the miller platform.

In one embodiment of the present invention, the voltage amplitude conversion module includes: the bias current generating module, the first-stage hysteresis comparator, the second-stage hysteresis comparator, the reference voltage generating module, the first inverter module, the RC filter module and the output signal shaping module, wherein,

the bias current generating module, the first-stage hysteresis comparator, the second-stage hysteresis comparator, the reference voltage generating module, the first inverter module, the RC filter module and the output signal shaping module are connected in parallel between a power supply end and a grounding end;

The output end of the bias current generating module is connected with the first input end of the first-stage hysteresis comparator, the input end of the reference voltage generating module and the first input end of the second-stage hysteresis comparator, the in-phase input end of the first-stage hysteresis comparator is used for inputting the square wave signal, the reverse-phase input end of the first-stage hysteresis comparator is connected with the output end of the reference voltage generating module, the second input end of the second-stage hysteresis comparator is connected with the output end of the first-stage hysteresis comparator, the output end of the second-stage hysteresis comparator is connected with the input end of the first inverter module, the output end of the first inverter module is connected with the input end of the RC filter module, the output end of the RC filter module is connected with the input end of the output signal shaping module, and the output end of the output signal shaping module is connected with the first input end of the protection executing module.

In one embodiment of the invention, the bias current generating module comprises a first MOS tube and a first resistor, the reference voltage generating module comprises a second MOS tube, a first diode, a second resistor and a third resistor, the first-stage hysteresis comparator comprises a third MOS tube, a fourth MOS tube, a fifth MOS tube, a sixth MOS tube and a seventh MOS tube, the second-stage hysteresis comparator comprises an eighth MOS tube, a ninth MOS tube, a tenth MOS tube and an eleventh MOS tube, the first inverter module comprises a twelfth MOS tube M12 and a thirteenth MOS tube, the RC filtering module comprises a fourth resistor and a first capacitor, the output signal shaping module comprises a fourteenth MOS tube, a fifteenth MOS tube, a sixteenth MOS tube, a seventeenth MOS tube, an eighteenth MOS tube and a nineteenth MOS tube, wherein,

The source electrode of the first MOS tube, the source electrode of the second MOS tube, the source electrode of the third MOS tube, the source electrode of the tenth MOS tube, the source electrode of the eighth MOS tube, the source electrode of the twelfth MOS tube M, the source electrode of the fourteenth MOS tube, the source electrode of the sixteenth MOS tube and the source electrode of the eighteenth MOS tube are all connected with a power supply end; the source electrode of the sixth MOS tube, the source electrode of the seventh MOS tube, one end of the third resistor, the anode of the first diode, the source electrode of the ninth MOS tube, one end of the first resistor, the source electrode of the thirteenth MOS tube, one end of the first capacitor, the source electrode of the fifteenth MOS tube, the source electrode of the seventeenth MOS tube and the source electrode of the nineteenth MOS tube are all connected with a grounding end; the grid electrode of the first MOS tube is connected with the drain electrode of the first MOS tube and is connected with the other end of the first resistor, the grid electrode of the eighth MOS tube, the grid electrode of the eleventh MOS tube, the grid electrode of the second MOS tube and the grid electrode of the third MOS tube; the drain electrode of the second MOS tube is connected with one end of the second resistor and the cathode of the first diode, and the other end of the second resistor is connected with the other end of the third resistor and the grid electrode of the fifth MOS tube; the drain electrode of the third MOS tube is connected with the source electrode of the fourth MOS tube and the source electrode of the fifth MOS tube; the grid electrode of the fourth MOS tube inputs an externally input square wave signal, and the drain electrode of the fourth MOS tube is connected with the drain electrode of the sixth MOS tube, the grid electrode of the sixth MOS tube and the grid electrode of the seventh MOS tube; the drain electrode of the fifth MOS tube is connected with the drain electrode of the seventh MOS tube, the drain electrode of the eleventh MOS tube and the grid electrode of the ninth MOS tube; the drain electrode of the eighth MOS tube is connected with the grid electrode of the tenth MOS tube, the drain electrode of the ninth MOS tube, the grid electrode of the twelfth MOS tube and the grid electrode of the thirteenth MOS tube; the drain electrode of the tenth MOS tube is connected with the source electrode of the eleventh MOS tube; the drain electrode of the twelfth MOS tube is connected with the drain electrode of the thirteenth MOS tube and one end of the fourth resistor; the other end of the fourth resistor is connected with the other end of the first capacitor, the grid electrode of the fourteenth MOS tube and the grid electrode of the fifteenth MOS tube; the drain electrode of the fourteenth MOS tube is connected with the drain electrode of the fifteenth MOS tube, the grid electrode of the sixteenth MOS tube and the grid electrode of the seventeenth MOS tube; the drain electrode of the sixteenth MOS tube, the drain electrode of the seventeenth MOS tube, the grid electrode of the eighteenth MOS tube and the grid electrode of the nineteenth MOS tube are connected and connected with the second output end of the voltage amplitude conversion module; the drain electrode of the eighteenth MOS tube is connected with the drain electrode of the nineteenth MOS tube and is connected with the first output end of the voltage amplitude conversion module.

In one embodiment of the present invention, the under-voltage protection module includes: the reference voltage and bias current generating submodule, the feedback loop module, the power supply voltage detecting module, the current mirror structure, the two-stage comparator and the undervoltage signal output circuit, wherein,

the reference voltage and bias current generating sub-module, the power supply voltage detecting module, the current mirror structure, the two-stage comparator and the undervoltage signal output circuit are connected in parallel between the power supply end and the grounding end;

the reference voltage output end of the reference voltage and bias current generating sub-module is connected with the non-inverting input end of the two-stage comparator, and the bias current output end of the reference voltage and bias current generating sub-module is connected with the input end of the current mirror structure;

the reverse input end of the two-stage comparator is connected with the output end of the power supply voltage detection module, and the output end of the two-stage comparator is connected with the input end of the undervoltage signal output circuit;

the output end of the current mirror structure is connected with the first input end of the two-stage comparator;

the input end of the power supply voltage detection module is connected with the output end of the feedback loop module;

And the output end of the undervoltage signal output circuit is connected with the input end of the feedback loop module and the second input end of the protection execution module.

In one embodiment of the present invention, the reference voltage output terminal of the reference voltage and bias current generating sub-module outputs a reference voltage, and the bias current output terminal outputs a bias current; the current mirror structure comprises a twenty-third MOS tube, a twenty-first MOS tube and a twenty-second MOS tube, the two-stage comparator comprises a twenty-third MOS tube, a twenty-fourth MOS tube, a twenty-fifth MOS tube, a twenty-sixteen MOS tube, a twenty-seventeenth MOS tube, a twenty-eighth MOS tube and a twenty-ninth MOS tube, the undervoltage signal output circuit comprises a thirty-second MOS tube, a thirty-eleventh MOS tube (31), a thirty-second MOS tube and a thirty-third MOS tube, the power supply voltage detection module comprises a fifth resistor, a sixth resistor and a seventh resistor, the feedback loop module comprises a thirty-fourth MOS tube,

one end of the fifth resistor, the source electrode of the twenty-second MOS tube, the source electrode of the twenty-first MOS tube, the source electrode of the twenty-eighth MOS tube, the source electrode of the thirty-second MOS tube and the source electrode of the thirty-second MOS tube are connected with a power supply end; the source electrode of the thirty-fourth MOS tube, one end of the seventh resistor, the source electrode of the twenty-first MOS tube, the drain electrode of the twenty-first MOS tube, the source electrode of the twenty-first MOS tube and the source electrode of the thirty-first MOS tube are connected with a grounding end; the drain electrode of the twentieth MOS tube, the grid electrode of the twentieth MOS tube and the grid electrode of the twenty-first MOS tube are connected with input bias current; the drain electrode of the twenty-first MOS tube is connected with the drain electrode of the twenty-second MOS tube, the grid electrode of the twenty-seventh MOS tube and the grid electrode of the twenty-eighth MOS tube; the grid electrode of the twenty-third MOS tube is connected with the other end of the fifth resistor and one end of the sixth resistor, the source electrode of the twenty-third MOS tube is connected with the drain electrode of the twenty-seventh MOS tube and the source electrode of the twenty-fourth MOS tube, and the drain electrode of the twenty-third MOS tube is connected with the drain electrode of the twenty-fifth MOS tube, the grid electrode of the twenty-fifth MOS tube and the grid electrode of the twenty-sixteen MOS tube; the grid electrode of the twenty-fourth MOS tube inputs reference voltage, and the drain electrode of the twenty-fourth MOS tube is connected with the drain electrode of the twenty-sixth MOS tube (M26) and the grid electrode of the twenty-ninth MOS tube; the drain electrode of the twenty-eighth MOS tube is connected with the source electrode of the twenty-ninth MOS tube, the grid electrode of the thirty-first MOS tube and the grid electrode of the thirty-first MOS tube; the drain electrode of the thirty-eighth MOS tube is connected with the drain electrode of the thirty-eighth MOS tube, the grid electrode of the thirty-eighth MOS tube and the grid electrode of the thirty-eighth MOS tube; the drain electrode of the thirty-second MOS tube is connected with the drain electrode of the thirty-third MOS tube and the grid electrode of the thirty-fourth MOS tube and is connected with the output end of the under-voltage protection module.

In one embodiment of the present invention, the protection execution module includes a first logic nor gate, where the first logic nor gate includes a thirty-fifth MOS transistor, a thirty-sixteen MOS transistor, a thirty-seventh MOS transistor, and a thirty-eighth MOS transistor, where

The source electrode of the thirty-fifth MOS tube is connected with the power end, the grid electrode of the thirty-fifth MOS tube and the grid electrode of the thirty-seventh MOS tube are connected with the second output end of the voltage amplitude conversion module, the drain electrode of the thirty-fifth MOS tube is connected with the source electrode of the thirty-sixth MOS tube, the grid electrode of the thirty-eighth MOS tube is connected with the output end of the undervoltage protection module, the drain electrode of the thirty-sixth MOS tube and the drain electrode of the thirty-seventh MOS tube are connected with the drain electrode of the thirty-eighth MOS tube and are connected with the output end of the protection execution module, the output end of the first logical NOR gate is connected with the input end of the output buffer module, and the source electrode of the thirty-seventh MOS tube and the source electrode of the thirty-eighth MOS tube are connected with the ground end.

In one embodiment of the invention, the output buffer module comprises a first inverter chain, a second inverter chain and a second inverter module, wherein,

The input ends of the first inverter chain and the second inverter chain are connected with the output end of the protection execution module, the output end of the first inverter chain is connected with the first input end of the second inverter module, the output end of the second inverter chain is connected with the second input end of the inverter module, the second inverter module is connected between the power end and the grounding end, and the output end of the second inverter module is connected with the grid electrode of the external SiC MOSFET power tube.

In one embodiment of the present invention, the first inverter chain includes a first inverter, a second inverter, and a third inverter, the second inverter chain includes a fourth inverter, a fifth inverter, and a sixth inverter, the second inverter module includes a third nineteenth MOS transistor and a fortieth MOS transistor, wherein,

the input end of the first inverter and the input end of the fourth inverter are connected with the output end of the protection execution module, the output end of the first inverter is connected with the input end of the second inverter, the output end of the second inverter is connected with the input end of the third inverter, the output end of the third inverter is connected with the grid electrode of the nineteenth MOS tube, the output end of the fourth inverter is connected with the input end of the fifth inverter, the output end of the fifth inverter is connected with the input end of the sixth inverter, the output end of the sixth inverter is connected with the grid electrode of the fortieth MOS tube, the source electrode of the nineteenth MOS tube is connected with the power supply end, the drain electrode of the nineteenth MOS tube is connected with the drain electrode of the fortieth MOS tube and is connected with the output end of the output buffer module, and the source electrode of the fortieth MOS tube is connected with the ground.

In one embodiment of the present invention, the miller stage improvement module includes a voltage change rate detection circuit, an inverse proportional amplifier, a second logic nor gate, a seventh inverter, a bipolar switching tube, and a second capacitor, wherein,

the input end of the voltage change rate detection circuit is connected with the drain electrode of the external SiC MOSFET power tube, the first output end of the voltage change rate detection circuit is connected with the inverting input end of the inverse proportion amplifier, the second output end of the voltage change rate detection circuit is connected with the grounding end, the non-inverting input end of the inverse proportion amplifier is connected with the grounding end, the output end of the inverse proportion amplifier is connected with the first input end of the second logic NOR gate, the second input end of the second logic NOR gate is connected with the grounding end, the output end of the second logic NOR gate is connected with the input end of the seventh inverter, the output end of the seventh inverter is connected with the base electrode of the bipolar switch tube, the emitter electrode of the bipolar switch tube is connected with the output end of the output buffer module and the grid electrode of the external SiC MOSFET power tube, the collector electrode of the bipolar switch tube is connected with one end of the second capacitor, and the other end of the second capacitor is connected with the source electrode of the external SiC MOSFET power tube and the grounding end.

In one embodiment of the present invention, the voltage change rate detection circuit includes a third capacitor and a seventh resistor, the inverse proportion amplifier includes an operational amplifier, an eighth resistor, a ninth resistor, wherein,

one end of the third capacitor is connected with the drain electrode and the power supply end of the external power SiC MOSFT switch tube, and the other end of the third capacitor is connected with one end of the seventh resistor and one end of the eighth resistor; the other end of the seventh resistor, the non-inverting input end of the operational amplifier and the first input end of the second logical NOR gate are connected with a grounding end; the other end of the eighth resistor is connected with one end of the ninth resistor and the inverting input end of the operational amplifier; the output end of the operational amplifier is connected with the other end of the ninth resistor and the second input end of the second logical NOR gate, and the output end of the second logical NOR gate is connected with the input end of the seventh inverter.

Compared with the prior art, the invention has the beneficial effects that:

the drive integrated circuit disclosed by the invention has the advantages that the voltage amplitude conversion module is utilized to convert the amplitude of an external input square wave signal into the working voltage amplitude of the protection execution module, the under-voltage protection module is used for detecting the power supply voltage, the protection execution module is combined for cutting off or recovering a control signal, the whole drive circuit is protected, the output buffer module is used for enhancing the capability of outputting the drive current and ensuring that the output voltage amplitude reaches the switching voltage amplitude of an external SiC MOSFET power tube, the miller platform improvement module is used for improving the VGS platform of the power tube in the switching-on process, so that the VDS falling speed is accelerated, the loss is reduced, the exchange of oscillation and overshoot reduction by sacrificing the switching speed and increasing the switching loss is avoided, and meanwhile, the current peak is avoided; in addition, the driving circuit is designed as an integrated circuit, so that the circuit area is greatly reduced.

Drawings

Fig. 1 is a schematic block diagram of a driving integrated circuit of a SiC MOSFET switching device according to an embodiment of the present invention;

fig. 2 is a schematic diagram of a voltage amplitude conversion module according to an embodiment of the present invention;

FIG. 3 is a schematic diagram of an under-voltage protection module according to an embodiment of the present invention;

FIG. 4 is a schematic diagram of a protection execution module according to an embodiment of the present invention;

FIG. 5 is a schematic diagram of an output buffer module according to an embodiment of the present invention;

FIG. 6 is a schematic diagram of a Miller platform improvement module according to an embodiment of the invention;

FIG. 7 is a schematic diagram of a circuit waveform according to an embodiment of the present invention;

fig. 8 is a schematic diagram of another circuit waveform according to an embodiment of the present invention.

Detailed Description

The present invention will be described in further detail with reference to specific examples, but embodiments of the present invention are not limited thereto.

Example 1

Referring to fig. 1, fig. 1 is a schematic block diagram of a driving integrated circuit of a SiC MOSFET switching device according to an embodiment of the present invention. The drive integrated circuit of the SiC MOSFET switching device comprises: the device comprises a voltage amplitude conversion module, an under-voltage protection module, a protection execution module, an output buffer module and a Miller platform improvement module. Wherein,,

The input end of the voltage amplitude conversion module inputs external input square wave signals, the output end of the voltage amplitude conversion module is connected with the first input end of the protection execution module, the output end of the under-voltage protection module is connected with the second input end of the protection execution module, the output end of the protection execution module is connected with the input end of the output buffer module, the output end of the output buffer module is connected with the grid electrode of the external SiC MOSFET power tube, the first input end of the Miller platform improvement module is connected with the source electrode of the external SiC MOSFET power tube, the second input end of the Miller platform improvement module is connected with the drain electrode of the external SiC MOSFET power tube, and the output end of the Miller platform improvement module is connected with the output end of the output buffer module.

Specifically, the voltage amplitude conversion module is used for converting the amplitude of the square wave signal into the amplitude of the protection execution module. The under-voltage protection module is used for outputting a first level or a second level according to the value of the power supply voltage; specifically, the under-voltage protection module is configured to output a high level, i.e., a first level, to the protection execution module when the power supply voltage decreases to a certain limit value for some reason; when the power supply voltage rises to a certain value above the limit value, a low level, namely a second level, is output to the protection execution module. The protection execution module is used for generating a first control signal to cut off the power supply and keep the cut-off state of the power supply when receiving a first level output by the undervoltage protection module, namely a high level, or generating a second control signal to enable the circuit to recover the working state when receiving a second level output by the undervoltage protection module. The output buffer module is used for outputting a third control signal consistent with the first control signal level according to the first control signal or outputting a fourth control signal consistent with the second control signal level according to the second control signal; specifically, when the output of the protection execution module is at the first control signal, i.e., the high level, the output of the output buffer module is at the high level, and when the output of the protection execution module is at the second control signal, i.e., the low level, the output of the output buffer module is at the low level. The miller platform improvement module is used for acting on a third control signal at the moment when the miller platform starts in the starting process of the external power tube so as to change the change trend of the miller platform; specifically, the miller platform in the circuit is changed from a platform shape to a slowly rising state by the function of the miller platform improvement module, so that the miller effect is relieved.

Referring to fig. 2, fig. 2 is a schematic diagram of a voltage amplitude conversion module according to an embodiment of the invention. The voltage amplitude conversion module comprises: the bias current generation module, the first-stage hysteresis comparator, the second-stage hysteresis comparator, the reference voltage generation module, the first inverter module, the RC filter module and the output signal shaping module are connected in parallel between the power supply end and the ground end; the output end of the bias current generating module is connected with the first input end of the first-stage hysteresis comparator, the input end of the reference voltage generating module and the first input end of the second-stage hysteresis comparator, the in-phase input end of the first-stage hysteresis comparator inputs square wave signals, the inverting input end of the first-stage hysteresis comparator is connected with the output end of the reference voltage generating module, the second input end of the second-stage hysteresis comparator is connected with the output end of the first-stage hysteresis comparator, the output end of the second-stage hysteresis comparator is connected with the input end of the first inverter module, the output end of the first inverter module is connected with the input end of the RC filter module, the output end of the RC filter module is connected with the input end of the output signal shaping module, and the output end of the output signal shaping module is connected with the first input end of the protection executing module.

Specifically, the bias current generating module comprises a first MOS tube M1 and a first resistor R1, wherein the first MOS tube M1 is a bias MOS tube, and the first resistor R1 is a bias resistor. The reference voltage generating module comprises a second MOS tube M2, a first diode D1, a second resistor R2 and a third resistor R3, wherein the second MOS tube M2 is a mirror image MOS tube, the resistors R2-R3 are voltage dividing resistors, and the first diode D1 is a zener diode. The first-stage hysteresis comparator comprises a third MOS tube M3, a fourth MOS tube M4, a fifth MOS tube M5, a sixth MOS tube M6 and a seventh MOS tube M7, wherein the MOS tubes M3-M7 are first-stage MOS tubes, and the MOS tubes M2-M3 form a current mirror structure. The second-stage hysteresis comparator comprises an eighth MOS tube M8, a ninth MOS tube M9, a tenth MOS tube M10 and an eleventh MOS tube M11, wherein the MOS tubes M8-M9 are mirror image MOS tubes, and the MOS tubes M10-M11 are hysteresis MOS tubes. The first inverter module includes a twelfth MOS transistor M12 and a thirteenth MOS transistor M13. The RC filter module comprises a fourth resistor R4 and a first capacitor C1, wherein the fourth resistor R4 is a filter resistor, and the first capacitor C1 is a filter capacitor. The output signal shaping module comprises a fourteenth MOS tube M14, a fifteenth MOS tube M15, a sixteenth MOS tube M16, a seventeenth MOS tube M17, an eighteenth MOS tube M18 and a nineteenth MOS tube M19, wherein the MOS tubes M14-M15 are first-stage inverter MOS tubes, the MOS tubes M16-M17 are second-stage inverter MOS tubes, and the MOS tubes M18-M19 are third-stage inverter MOS tubes.

The source of the first MOS transistor M1, the source of the second MOS transistor M2, the source of the third MOS transistor M3, the source of the tenth MOS transistor M10, the source of the eighth MOS transistor M8, the source of the twelfth MOS transistor M12, the source of the fourteenth MOS transistor M14, the source of the sixteenth MOS transistor M16, and the source of the eighteenth MOS transistor M18 are all connected to the power supply VCC; the source electrode of the sixth MOS tube M6, the source electrode of the seventh MOS tube M7, one end of the third resistor R3, the anode of the first diode D1, the source electrode of the ninth MOS tube M9, one end of the first resistor R1, the source electrode of the thirteenth MOS tube M13, one end of the first capacitor C1, the source electrode of the fifteenth MOS tube M15, the source electrode of the seventeenth MOS tube M17 and the source electrode of the nineteenth MOS tube M19 are all connected with the grounding end; the grid electrode of the first MOS tube M1 is connected with the drain electrode of the first MOS tube M1, the other end of the first resistor R1, the grid electrode of the eighth MOS tube M8, the grid electrode of the eleventh MOS tube M11, the grid electrode of the second MOS tube M2 and the grid electrode of the third MOS tube M3; the drain electrode of the second MOS tube M2 is connected with one end of the second resistor R2 and the cathode of the first diode D1, and the other end of the second resistor R2 is connected with the other end of the third resistor R3 and the grid electrode of the fifth MOS tube M5; the drain electrode of the third MOS tube M3 is connected with the source electrode of the fourth MOS tube M4 and the source electrode of the fifth MOS tube M5; the grid electrode of the fourth MOS tube M4 inputs an externally input square wave signal, and the drain electrode of the fourth MOS tube M4 is connected with the drain electrode of the sixth MOS tube M6, the grid electrode of the sixth MOS tube M6 and the grid electrode of the seventh MOS tube M7; the drain electrode of the fifth MOS tube M5 is connected with the drain electrode of the seventh MOS tube M7, the drain electrode of the eleventh MOS tube M11 and the grid electrode of the ninth MOS tube M9; the drain electrode of the eighth MOS tube M8 is connected with the grid electrode of the tenth MOS tube M10, the drain electrode of the ninth MOS tube M9, the grid electrode of the twelfth MOS tube M12 and the grid electrode of the thirteenth MOS tube M13; the drain electrode of the tenth MOS tube M10 is connected with the source electrode of the eleventh MOS tube M11; the drain electrode of the twelfth MOS tube M12 is connected with the drain electrode of the thirteenth MOS tube M13 and one end of the fourth resistor R4; the other end of the fourth resistor R4 is connected with the other end of the first capacitor C1, the grid electrode of the fourteenth MOS tube M14 and the grid electrode of the fifteenth MOS tube M15; the drain electrode of the fourteenth MOS tube M14 is connected with the drain electrode of the fifteenth MOS tube M15, the grid electrode of the sixteenth MOS tube M16 and the grid electrode of the seventeenth MOS tube M17; the drain electrode of the sixteenth MOS tube M16, the drain electrode of the seventeenth MOS tube M17, the grid electrode of the eighteenth MOS tube M18 and the grid electrode of the nineteenth MOS tube M19 are connected and are the second output end OUT2 of the voltage amplitude conversion module; the drain electrode of the eighteenth MOS tube M18 is connected with the drain electrode of the nineteenth MOS tube M19 and is a first output end OUT1 of the voltage amplitude conversion module.

Referring to fig. 3, fig. 3 is a schematic diagram of an under-voltage protection module according to an embodiment of the invention. The undervoltage protection module includes: the device comprises a reference voltage and bias current generation submodule, a feedback loop module, a power supply voltage detection module, a current mirror structure, a two-stage comparator and an undervoltage signal output circuit.

The system comprises a reference voltage generation sub-module, a bias current generation sub-module, a feedback loop module, a power voltage detection module, a two-stage comparator and an undervoltage signal output circuit, which are connected in parallel between a power end and a grounding end; the reference voltage output end of the reference voltage and bias current generating sub-module is connected with the non-inverting input end of the two-stage comparator, and the bias current output end of the reference voltage and bias current generating sub-module is connected with the input end of the current mirror structure; the reverse input end of the two-stage comparator is connected with the output end of the power supply voltage detection module, and the output end of the two-stage comparator is connected with the input end of the undervoltage signal output circuit; the output end of the current mirror structure is connected with the first input end of the two-stage comparator; the input end of the power supply voltage detection module is connected with the output end of the feedback loop module; the output end of the undervoltage signal output circuit is connected with the input end of the feedback loop module and the second input end of the protection execution module.

Specifically, the reference voltage and bias current generating sub-module is used for outputting the reference voltage V _REF And bias current I _bias . The current mirror structure comprises a twenty-eighth MOS tube M20, a twenty-eighth MOS tube M21 and a twenty-eighth MOS tube M22, wherein the two-stage comparator comprises a twenty-seventh MOS tube M23, a twenty-seventh MOS tube M24, a twenty-fifth MOS tube M25, a twenty-seventh MOS tube M26, a twenty-seventh MOS tube M27, a twenty-eighth MOS tube M28 and a twenty-ninth MOS tube M29, wherein the MOS tubes M23-M27 are first-stage MOS tubes, and the MOS tubes M28-M29 are second-stage MOS tubes. The undervoltage signal output circuit comprises a thirty-first MOS tube M30, a thirty-first MOS tube M31, a thirty-second MOS tube M32 and a thirty-first MOS tube M33. The power supply voltage detection module comprises a fifth resistor R5, a sixth resistor R6 and a seventh resistor R7, wherein the resistors R5-R7 are detection resistors. The feedback loop module comprises a thirty-four MOS tube M34, and the thirty-four MOS tube M34 is a switch tube.

One end of the fifth resistor R5, the source of the twenty-second MOS transistor M22, the source of the twenty-seventh MOS transistor M27, the source of the twenty-eighth MOS transistor M28, the source of the thirty-second MOS transistor M30 and the source of the thirty-second MOS transistor M32 are connected with the power supply end VDD; the source electrode of the thirty-fourth MOS tube M34, one end of the seventh resistor R7, the source electrode of the twenty-first MOS tube M20, the source electrode of the twenty-first MOS tube M21, the source electrode of the twenty-fifth MOS tube M25, the source electrode of the twenty-sixth MOS tube M26, the drain electrode of the twenty-ninth MOS tube M29, the source electrode of the thirty-first MOS tube M31 and the source electrode of the thirty-third MOS tube M33 are connected with a grounding end; the drain electrode of the twenty-first MOS transistor M20, the grid electrode of the twenty-first MOS transistor M20 and the grid electrode of the twenty-first MOS transistor M21 are connected and input with bias current I _bias The method comprises the steps of carrying out a first treatment on the surface of the The drain electrode of the twenty-first MOS tube M21 is connected with the drain electrode of the twenty-second MOS tube M22, the grid electrode of the twenty-seventh MOS tube M27 and the grid electrode of the twenty-eighth MOS tube M28; a grid electrode of the twenty-third MOS tube M23 is connected with the other end of the fifth resistor R5 and one end of the sixth resistor R6, the thThe source electrode of the twenty-third MOS tube M23 is connected with the drain electrode of the twenty-seventh MOS tube M27 and the source electrode of the twenty-fourth MOS tube M24, and the drain electrode of the twenty-third MOS tube M23 is connected with the drain electrode of the twenty-fifth MOS tube M25, the grid electrode of the twenty-fifth MOS tube M25 and the grid electrode of the twenty-sixth MOS tube M26; the grid electrode of the twenty-fourth MOS transistor M24 inputs reference voltage V _REF The drain electrode of the twenty-fourth MOS tube M24 is connected with the drain electrode of the twenty-sixth MOS tube M26 and the grid electrode of the twenty-ninth MOS tube M29; the drain electrode of the twenty-eighth MOS tube M28 is connected with the source electrode of the twenty-ninth MOS tube M29, the grid electrode of the thirty-eighth MOS tube M30 and the grid electrode of the thirty-first MOS tube M31; the drain electrode of the thirty-first MOS tube M31, the grid electrode of the thirty-second MOS tube M32 and the grid electrode of the thirty-third MOS tube M33 are connected with the drain electrode of the thirty-first MOS tube M30; the drain electrode of the thirty-second MOS tube M32 is connected with the drain electrode of the thirty-third MOS tube M33 and the grid electrode of the thirty-fourth MOS tube M34, and the drain electrode is connected with the output end UV of the undervoltage protection module.

Referring to fig. 4, fig. 4 is a schematic diagram of a protection execution module according to an embodiment of the invention. The protection execution module comprises a first logical nor Gate1.

Specifically, the first logical nor Gate1 includes a thirty-fifth MOS transistor M35, a thirty-sixteen MOS transistor M36, a thirty-seventeenth MOS transistor M37, and a thirty-eighth MOS transistor M38.

The source electrode of the thirty-fifth MOS transistor M35 is connected to the power supply terminal, the gate electrode of the thirty-fifth MOS transistor M35 and the gate electrode of the thirty-seventh MOS transistor M37 are connected to the second output terminal OUT2 of the voltage amplitude conversion module, the drain electrode of the thirty-fifth MOS transistor M35 is connected to the source electrode of the thirty-sixth MOS transistor M36, the gate electrode of the thirty-sixth MOS transistor M36 and the gate electrode of the thirty-eighth MOS transistor M38 are connected to the output terminal UV of the undervoltage protection module, the drain electrode of the thirty-sixth MOS transistor M36 and the drain electrode of the thirty-seventh MOS transistor M37 are connected to the drain electrode of the thirty-eighth MOS transistor M38 and to the output terminal OUT3 of the protection execution module, and the output terminal OUT3 of the first logical nor gate is connected to the input terminal of the output buffer module. The source electrode of the thirty-seventh MOS transistor M37 and the source electrode of the thirty-eighth MOS transistor M38 are connected with the grounding end.

Referring to fig. 5, fig. 5 is a schematic diagram of an output buffer module according to an embodiment of the invention. The output buffer module comprises a first inverter chain, a second inverter chain and a second inverter module, wherein the input ends of the first inverter chain and the second inverter chain are connected with the output end of the protection execution module, the output end of the first inverter chain is connected with the first input end of the second inverter module, the output end of the second inverter chain is connected with the second input end of the inverter module, the second inverter module is connected between the power end VCC and the grounding end, and the output end of the second inverter module is connected with the grid electrode of the external SiC MOSFET power tube.

Specifically, the first inverter chain includes a first inverter INV1, a second inverter INV2 and a third inverter INV3, the second inverter chain includes a fourth inverter INV4, a fifth inverter INV5 and a sixth inverter INV6, and the second inverter module includes a third nineteenth MOS transistor M39 and a fortieth MOS transistor M40, wherein the MOS transistors M39-M40 are switching transistors.

Wherein, the input end of the first inverter INV1 and the input end of the fourth inverter INV4 are connected with the output end OUT3 of the protection execution module, the output end of the first inverter INV1 is connected with the input end of the second inverter INV2, the output end of the second inverter INV2 is connected with the input end of the third inverter INV3, the output end of the third inverter INV3 is connected with the grid electrode of the thirty-ninth MOS tube M39, the output end of the fourth inverter INV4 is connected with the input end of the fifth inverter INV5, the output end of the fifth inverter INV5 is connected with the input end of the sixth inverter INV6, the output end of the sixth inverter INV6 is connected with the grid electrode of the fortieth MOS tube M40, the source electrode of the thirty-ninth MOS tube M39 is connected with the power supply end VCC, the drain electrode of the thirty-ninth MOS tube M40 and is used as the output end V of the output buffer module _G The source electrode of the forty MOS transistor M40 is connected with the grounding end.

Referring to fig. 6, fig. 6 is a schematic diagram of a miller platform improvement module according to an embodiment of the invention. The miller platform improvement module comprises a voltage change rate detection circuit, an inverse proportion amplifier, a second logic NOR Gate2, a seventh inverter INV7, a bipolar switching tube Q1 and a second capacitor C2, wherein the bipolar switching tube Q1 is an NPN transistor, and compared with an MOS switching tube and a PNP switching tube, the NPN transistor is easier to drive.

The input end of the voltage change rate detection circuit is connected with the drain electrode of the external SiC MOSFET power tube, the first output end of the voltage change rate detection circuit is connected with the inverting input end of the inverse proportion amplifier, the second output end of the voltage change rate detection circuit is connected with the grounding end, the non-inverting input end of the inverse proportion amplifier is connected with the grounding end, the output end of the inverse proportion amplifier is connected with the first input end of the second logic NOR Gate valve 2, the second input end of the second logic NOR Gate valve 2 is connected with the grounding end, the output end of the second logic NOR Gate valve 2 is connected with the input end of the seventh inverter INV7, the output end of the seventh inverter INV7 is connected with the base electrode of the bipolar switch tube Q1, the emitter electrode of the bipolar switch tube Q1 is connected with the output end of the output buffer module and the grid electrode of the external SiC MOSFET power tube, the collector electrode of the bipolar switch tube Q1 is connected with one end of the second capacitor C2, and the other end of the second capacitor C2 is connected with the source electrode of the external SiC MOSFET power tube and the grounding end.

Specifically, the voltage change rate detection circuit includes a third capacitor C3 and a seventh resistor R7, where the third capacitor C3 is a detection capacitor and the seventh resistor R7 is a detection resistor. The inverse proportion amplifier includes an operational amplifier OP1, an eighth resistor R8, and a ninth resistor R9.

One end of the third capacitor C3 is connected with the drain electrode and the power supply end VDD of the external power SiC MOSFT switch tube, and the other end of the third capacitor C3 is connected with one end of the seventh resistor R7 and one end of the eighth resistor R8; the other end of the seventh resistor R7, the non-inverting input end of the operational amplifier OP1 and the first input end of the second logic NOR Gate2 are connected with the grounding end; the other end of the eighth resistor R8 is connected with one end of the ninth resistor R9 and the reverse input end of the operational amplifier OP 1; the output end of the operational amplifier OP1 is connected with the other end of the ninth resistor R9 and the second input end of the second logical NOR Gate2, the output end of the second logical NOR Gate2 is connected with the input end of the seventh inverter INV7, the output end of the seventh inverter INV7 is connected with the base electrode of the bipolar switching tube Q1, and the emitter electrode of the bipolar switching tube Q1 is connected with the output end V of the output buffer module _G And the grid electrode of the external SiC MOSFET power tube, the collector electrode of the bipolar switching tube Q1 is connected with one end of the second capacitor C2, and the other end of the second capacitor C2 is connected with the source electrode and the grounding end of the external SiC MOSFET power tube.

Referring to fig. 7, fig. 7 is a schematic circuit waveform diagram according to an embodiment of the invention. When the square wave signal VIN is input externally, the amplitude of the input voltage is converted into the voltage amplitude required by the normal operation of the protection execution module through the voltage amplitude conversion module, and the logic of the voltage amplitude is subjected to inversion processing to obtain OUT2. When the power supply voltage is in the normal working voltage range, the undervoltage protection module outputs a low level, and when the power supply voltage is lower than the normal working voltage range due to loss and the like, the undervoltage protection module outputs a high level, so that UV is obtained. After judging the protection signal, the protection execution module determines whether to send an input control signal to the output buffer module, when the undervoltage signal is at a low level, the output of the protection execution module is at a high level when the input is at a high level, and the output of the protection execution module is at a low level when the input is at a low level; when the undervoltage signal is at a high level, the output of the protection execution module is kept at a low level no matter the input signal is at a high level or a low level; thus, vnor was obtained. When the output of the protection execution module is at a high level, the output of the output buffer module is at a high level, and when the output of the protection execution module is at a low level, the output of the output buffer module is at a low level, so that VG is obtained.

Referring to fig. 8, fig. 8 is a schematic diagram of another circuit waveform according to an embodiment of the invention. In fig. 8, the solid line shows waveforms of the gate-source voltage VGS, the drain-source voltage VDS, and the drain current Id of the external SiC MOSFET power tube when the miller effect occurs, and the broken line shows the influence of the miller stage improvement module on the waveforms VGS, VDS, and Id. t is t ₂ -t ₄ The time period is a Miller platform, VGS is kept unchanged, id is kept unchanged, and VDS is lowered; the function of adding the miller stage improvement module only during the miller stage occurrence period, i.e., at t ₂ -t ₄ The goal is to make VGS rise slowly, id rise slowly, VDS fall quickly, so that the maintenance time of Miller platform is shortened, i.e. from t ₂ -t ₄ Becomes t ₂ -t ₄ ’。

The driving integrated circuit of the embodiment utilizes the voltage amplitude conversion module to convert the amplitude of an external input square wave signal to the working voltage amplitude of the protection execution module, the under-voltage protection module detects the power supply voltage, the protection execution module is combined to cut off or recover the control signal, the whole driving circuit is protected, the output buffer module enhances the capability of outputting driving current, the output voltage amplitude is ensured to reach the switching voltage amplitude of an external SiC MOSFET power tube, the Miller platform improvement module improves the VGS platform of the power tube in the opening process, the VDS falling speed is accelerated, the loss is reduced, the reduction of oscillation and overshoot by sacrificing the switching speed and increasing the switching loss is avoided, and meanwhile, the current peak is avoided; in addition, the driving circuit is designed as an integrated circuit, so that the circuit area is greatly reduced.

The foregoing is a further detailed description of the invention in connection with the preferred embodiments, and it is not intended that the invention be limited to the specific embodiments described. It will be apparent to those skilled in the art that several simple deductions or substitutions may be made without departing from the spirit of the invention, and these should be considered to be within the scope of the invention.

Claims

1. A drive integrated circuit of a SiC MOSFET switching device, comprising: the device comprises a voltage amplitude conversion module, an under-voltage protection module, a protection execution module, an output buffer module and a Miller platform improvement module, wherein,

the miller platform improvement module is used for acting on the third control signal at the moment when the miller platform starts in the starting process of the external power tube so as to change the change trend of the miller platform;

the miller platform improvement module comprises a voltage change rate detection circuit, an inverse proportion amplifier, a second logic NOR Gate (Gate 2), a seventh inverter (INV 7), a bipolar switch tube (Q1) and a second capacitor (C2), wherein the input end of the voltage change rate detection circuit is connected with the drain electrode of the external SiC MOSFET power tube, the first output end of the voltage change rate detection circuit is connected with the inverting input end of the inverse proportion amplifier, the second output end of the voltage change rate detection circuit is connected with the grounding end, the non-inverting input end of the inverse proportion amplifier is connected with the grounding end, the output end of the inverse proportion amplifier is connected with the first input end of the second logic NOR Gate (Gate 2), the second input end of the second logic NOR Gate (Gate 2) is connected with the grounding end, the output end of the second logic NOR Gate (Gate 2) is connected with the input end of the seventh inverter (INV 7), the output end of the seventh inverter (INV 7) is connected with the output end of the bipolar MOSFET power tube (Q1) and the bipolar power tube (C2), and the other end of the bipolar MOSFET power tube (C2) is connected with the output end of the bipolar MOSFET power tube (Q1).

2. The SiC MOSFET switching device driver integrated circuit of claim 1, wherein the voltage amplitude conversion module comprises: the bias current generating module, the first-stage hysteresis comparator, the second-stage hysteresis comparator, the reference voltage generating module, the first inverter module, the RC filter module and the output signal shaping module, wherein,

3. The driving integrated circuit of the SiC MOSFET switching device according to claim 2, wherein the bias current generating module includes a first MOS transistor (M1) and a first resistor (R1), the reference voltage generating module includes a second MOS transistor (M2), a first diode (D1), a second resistor (R2) and a third resistor (R3), the first-stage hysteresis comparator includes a third MOS transistor (M3), a fourth MOS transistor (M4), a fifth MOS transistor (M5), a sixth MOS transistor (M6) and a seventh MOS transistor (M7), the second-stage hysteresis comparator includes an eighth MOS transistor (M8), a ninth MOS transistor (M9), a tenth MOS transistor (M10) and an eleventh MOS transistor (M11), the first inverter module includes a twelfth MOS transistor (M12) and a thirteenth MOS transistor (M13), the RC filter module includes a fourth resistor (R4) and a first capacitor (C1), the output signal shaping module includes a fourteenth MOS transistor (M14), a fifteenth MOS transistor (M15), a seventeenth MOS transistor (M16) and a seventeenth MOS transistor (M11),

the source electrode of the first MOS tube (M1), the source electrode of the second MOS tube (M2), the source electrode of the third MOS tube (M3), the source electrode of the tenth MOS tube (M10), the source electrode of the eighth MOS tube (M8), the source electrode of the twelfth MOS tube (M12), the source electrode of the fourteenth MOS tube (M14), the source electrode of the sixteenth MOS tube (M16) and the source electrode of the eighteenth MOS tube (M18) are all connected with a power supply end (VCC); the source electrode of the sixth MOS tube (M6), the source electrode of the seventh MOS tube (M7), one end of the third resistor (R3), the positive electrode of the first diode (D1), the source electrode of the ninth MOS tube (M9), one end of the first resistor (R1), the source electrode of the thirteenth MOS tube (M13), one end of the first capacitor (C1), the source electrode of the fifteenth MOS tube (M15), the source electrode of the seventeenth MOS tube (M17) and the source electrode of the nineteenth MOS tube (M19) are all connected with a grounding end; the grid electrode of the first MOS tube (M1) is connected with the drain electrode of the first MOS tube and is connected with the other end of the first resistor (R1), the grid electrode of the eighth MOS tube (M8), the grid electrode of the eleventh MOS tube (M11), the grid electrode of the second MOS tube (M2) and the grid electrode of the third MOS tube (M3); the drain electrode of the second MOS tube (M2) is connected with one end of the second resistor (R2) and the negative electrode of the first diode (D1), and the other end of the second resistor (R2) is connected with the other end of the third resistor (R3) and the grid electrode of the fifth MOS tube (M5); the drain electrode of the third MOS tube (M3) is connected with the source electrode of the fourth MOS tube (M4) and the source electrode of the fifth MOS tube (M5); the grid electrode of the fourth MOS tube (M4) inputs an externally input square wave signal, and the drain electrode of the fourth MOS tube (M4) is connected with the drain electrode of the sixth MOS tube (M6), the grid electrode of the sixth MOS tube (M6) and the grid electrode of the seventh MOS tube (M7); the drain electrode of the fifth MOS tube (M5) is connected with the drain electrode of the seventh MOS tube (M7), the drain electrode of the eleventh MOS tube (M11) and the grid electrode of the ninth MOS tube (M9); the drain electrode of the eighth MOS tube (M8) is connected with the grid electrode of the tenth MOS tube (M10), the drain electrode of the ninth MOS tube (M9), the grid electrode of the twelfth MOS tube (M12) and the grid electrode of the thirteenth MOS tube (M13); the drain electrode of the tenth MOS tube (M10) is connected with the source electrode of the eleventh MOS tube (M11); the drain electrode of the twelfth MOS tube (M12) is connected with the drain electrode of the thirteenth MOS tube (M13) and one end of the fourth resistor (R4); the other end of the fourth resistor (R4) is connected with the other end of the first capacitor (C1), the grid electrode of the fourteenth MOS tube (M14) and the grid electrode of the fifteenth MOS tube (M15); the drain electrode of the fourteenth MOS tube (M14) is connected with the drain electrode of the fifteenth MOS tube (M15), the grid electrode of the sixteenth MOS tube (M16) and the grid electrode of the seventeenth MOS tube (M17); the drain electrode of the sixteenth MOS tube (M16), the drain electrode of the seventeenth MOS tube (M17), the grid electrode of the eighteenth MOS tube (M18) and the grid electrode of the nineteenth MOS tube (M19) are connected and connected with the second output end (OUT 2) of the voltage amplitude conversion module; the drain electrode of the eighteenth MOS tube (M18) is connected with the drain electrode of the nineteenth MOS tube (M19) and is connected with the first output end (OUT 1) of the voltage amplitude conversion module.

4. The drive integrated circuit of a SiC MOSFET switching device of claim 1, wherein the under-voltage protection module comprises: the reference voltage and bias current generating submodule, the feedback loop module, the power supply voltage detecting module, the current mirror structure, the two-stage comparator and the undervoltage signal output circuit, wherein,

the reference voltage and bias current generating sub-module, the power supply voltage detecting module, the current mirror structure, the two-stage comparator and the undervoltage signal output circuit are connected in parallel between a power supply end and a grounding end;

5. The SiC MOSFET switching device driver integrated circuit of claim 4, wherein the reference voltage output of the reference voltage and bias current generating sub-module outputs a reference voltage (V _REF ) The bias current output end outputs bias current (I _bias ) The method comprises the steps of carrying out a first treatment on the surface of the The current mirror structure comprises a twenty-third MOS tube (M20), a twenty-first MOS tube (M21) and a twenty-second MOS tube (M22), the two-stage comparator comprises a twenty-third MOS tube (M23), a twenty-fourth MOS tube (M24), a twenty-fifth MOS tube (M25), a twenty-second MOS tube (M26), a twenty-first MOS tube (M27), a twenty-first MOS tube (M28) and a twenty-first MOS tube (M29), the undervoltage signal output circuit comprises a thirty-first MOS tube (M30), a thirty-first MOS tube (31), a thirty-first MOS tube (M32) and a thirty-first MOS tube (M33), the power supply voltage detection module comprises a fifth resistor (R5), a sixth resistor (R6) and a seventh resistor (R7), the feedback loop module comprises a thirty-fourth MOS tube (M34),

one end of the fifth resistor (R5), the source electrode of the second twelve MOS transistor (M22), the source electrode of the second seventeenth MOS transistor (M27), the source electrode of the second eighteenth MOS transistor (M28), the source electrode of the thirty-second MOS transistor (M30) and the source electrode of the third twelve MOS transistor (M32) are connected with a power supply end (VDD); a source electrode of the thirty-fourth MOS transistor (M34), one end of the seventh resistor (R7), the twentieth The source electrode of the MOS tube (M20), the source electrode of the twenty-first MOS tube (M21), the source electrode of the twenty-fifth MOS tube (M25), the source electrode of the twenty-first MOS tube (M26), the drain electrode of the twenty-ninth MOS tube (M29), the source electrode of the thirty-first MOS tube (M31) and the source electrode of the thirty-first MOS tube (M33) are connected with a grounding end; the drain electrode of the twentieth MOS tube (M20), the grid electrode of the twentieth MOS tube (M20) and the grid electrode of the twenty-first MOS tube (M21) are connected with an input bias current (I) _bias ) The method comprises the steps of carrying out a first treatment on the surface of the The drain electrode of the twenty-first MOS tube (M21) is connected with the drain electrode of the twenty-second MOS tube (M22), the grid electrode of the twenty-seventh MOS tube (M27) and the grid electrode of the twenty-eighth MOS tube (M28); the grid electrode of the twenty-third MOS tube (M23) is connected with the other end of the fifth resistor (R5) and one end of the sixth resistor (R6), the source electrode of the twenty-third MOS tube (M23) is connected with the drain electrode of the twenty-seventh MOS tube (M27) and the source electrode of the twenty-fourth MOS tube (M24), and the drain electrode of the twenty-third MOS tube (M23) is connected with the drain electrode of the twenty-fifth MOS tube (M25), the grid electrode of the twenty-fifth MOS tube (M25) and the grid electrode of the twenty-sixth MOS tube (M26); the grid electrode of the twenty-four MOS tube (M24) inputs a reference voltage (V) _REF ) The drain electrode of the twenty-fourth MOS tube (M24) is connected with the drain electrode of the twenty-sixth MOS tube (M26) and the grid electrode of the twenty-ninth MOS tube (M29); the drain electrode of the twenty-eighth MOS tube (M28) is connected with the source electrode of the twenty-ninth MOS tube (M29), the grid electrode of the thirty-eighth MOS tube (M30) and the grid electrode of the thirty-eleventh MOS tube (M31); the drain electrode of the thirty-third MOS tube (M30) is connected with the drain electrode of the thirty-first MOS tube (M31), the grid electrode of the thirty-second MOS tube (M32) and the grid electrode of the thirty-third MOS tube (M33); the drain electrode of the thirty-second MOS tube (M32) is connected with the drain electrode of the thirty-third MOS tube (M33) and the grid electrode of the thirty-fourth MOS tube (M34) and is connected with the output end (UV) of the under-voltage protection module.

6. The SiC MOSFET switching device driver integrated circuit of claim 1, wherein the protection execution module comprises a first logic nor Gate (Gate 1), the first logic nor Gate (Gate 1) comprising a thirty-five MOS transistor (M35), a thirty-sixteen MOS transistor (M36), a thirty-seventeen MOS transistor (M37), and a thirty-eight MOS transistor (M38), wherein

The source electrode of thirty-five MOS pipe (M35) is connected with a power end, the grid electrode of thirty-five MOS pipe (M35) the grid electrode of thirty-seven MOS pipe (M37) is connected with the second output end (OUT 2) of the voltage amplitude conversion module, the drain electrode of thirty-five MOS pipe (M35) is connected with the source electrode of thirty-six MOS pipe (M36), the grid electrode of thirty-six MOS pipe (M36) the grid electrode of thirty-eight MOS pipe (M38) is connected with the output end (UV) of the undervoltage protection module, the drain electrode of thirty-six MOS pipe (M36) the drain electrode of thirty-seven MOS pipe (M37) is connected with the drain electrode of thirty-eight MOS pipe (M38) and is connected with the output end (OUT 3) of the protection execution module, the output end (OUT 3) of the first logic NOR gate is connected with the input end of the output buffer module, the source electrode of thirty-seven MOS pipe (M37) and the source electrode of thirty-eight MOS pipe (M38) are connected with the ground.

7. The drive integrated circuit of the SiC MOSFET switching device as recited in claim 1 wherein the output buffer module includes a first inverter chain, a second inverter chain, and a second inverter module, wherein,

the input ends of the first inverter chain and the second inverter chain are connected with the output end of the protection execution module, the output end of the first inverter chain is connected with the first input end of the second inverter module, the output end of the second inverter chain is connected with the second input end of the inverter module, the second inverter module is connected between a power supply end (VCC) and a grounding end, and the output end of the second inverter module is connected with the grid electrode of the external SiC MOSFET power tube.

8. The SiC MOSFET switching device driving integrated circuit of claim 7, wherein the first inverter chain includes a first inverter (INV 1), a second inverter (INV 2), and a third inverter (INV 3), the second inverter chain includes a fourth inverter (INV 4), a fifth inverter (INV 5), and a sixth inverter (INV 6), the second inverter module includes a third nineteenth MOS transistor (M39), and a fortieth MOS transistor (M40), wherein,

The input end of the first inverter (INV 1) and the input end of the fourth inverter (INV 4) are connected with the output end (OUT 3) of the protection execution module, the output end of the first inverter (INV 1) is connected with the input end of the second inverter (INV 2), the output end of the second inverter (INV 2) is connected with the input end of the third inverter (INV 3), the output end of the third inverter (INV 3) is connected with the grid electrode of the third nineteenth MOS transistor (M39), the output end of the fourth inverter (INV 4) is connected with the input end of the fifth inverter (INV 5), the output end of the fifth inverter (INV 5) is connected with the input end of the sixth inverter (INV 6), the output end of the sixth inverter (INV 6) is connected with the grid electrode of the fortieth MOS transistor (M40), the source electrode of the third nineteenth MOS transistor (M39) is connected with the power supply end (VCC), the output end of the third inverter (INV 4) is connected with the drain electrode of the fortieth MOS transistor (M40).

9. The SiC MOSFET switching device driving integrated circuit of claim 1, wherein the voltage change rate detection circuit includes a third capacitor (C3) and a seventh resistor (R7), the inverse ratio amplifier includes an operational amplifier (OP 1), an eighth resistor (R8), a ninth resistor (R9), wherein,

One end of the third capacitor (C3) is connected with the drain electrode and the power supply end (VDD) of the external power SiC MOSFT switching tube, and the other end of the third capacitor (C3) is connected with one end of the seventh resistor (R7) and one end of the eighth resistor (R8); the other end of the seventh resistor (R7), the non-inverting input end of the operational amplifier (OP 1) and the first input end of the second logic NOR Gate (Gate 2) are connected with a grounding end; the other end of the eighth resistor (R8) is connected with one end of the ninth resistor (R9) and the inverting input end of the operational amplifier (OP 1); the output end of the operational amplifier (OP 1) is connected with the other end of the ninth resistor (R9) and the second input end of the second logical NOR Gate (Gate 2), and the output end of the second logical NOR Gate (Gate 2) is connected with the input end of the seventh inverter (INV 7).