CN113630121B

CN113630121B - Sample-hold and knee point detection circuit

Info

Publication number: CN113630121B
Application number: CN202110953925.8A
Authority: CN
Inventors: 周泽坤; 艾雪; 何金阳; 王卓; 张波
Original assignee: University of Electronic Science and Technology of China
Current assignee: University of Electronic Science and Technology of China
Priority date: 2021-08-19
Filing date: 2021-08-19
Publication date: 2023-07-04
Anticipated expiration: 2041-08-19
Also published as: CN113630121A

Abstract

The invention belongs to the technical field of power management, and particularly relates to a sampling hold and knee point detection circuit. The buffer and the comparator of the circuit of the invention multiplex a folding type common-source common-gate structure, thereby omitting extra operational amplifier and reducing the power consumption and the cost of the circuit. In the feedbackWhen the voltage reaches the knee point, the voltage waveform can drop sharply, and the buffer has time delay, and a voltage difference is formed between the two voltages to enable the comparator to turn over, so that the knee point signal is detected, and then the sampling switch is opened to sample the capacitor C _delay The stored charge is shared to the holding capacitor C _hold After a narrow pulse time, the comparator is turned off, and the sampling switch is turned off, so that the sampling work is completed, and the knee point voltage value is obtained.

Description

Sample-hold and knee point detection circuit

Technical Field

The invention belongs to the technical field of power management, and particularly relates to a sampling hold and knee point detection circuit.

Background

In recent years, with the development of electronic devices, electronic devices are pursuing power supplies having higher power density, higher efficiency, and smaller volume. The primary power supply types in the early days, linear regulated power supplies were unable to meet these increasing demands, and switching power supplies have therefore become the dominant trend. The traditional flyback converter adopts an optocoupler and TL431 to sample output voltage information, however, the optocoupler and TL431 occupy large volume, no method is available for realizing internal integration, miniaturization is not facilitated, the optocoupler is greatly influenced by temperature and irradiation, and the sampling precision can be influenced by environment. Therefore, primary-side feedback flyback converters are favored in the market due to their simpler peripheral structural design, smaller volume and lower cost.

Since the accuracy of the sampling determines the accuracy of the output voltage, one of the key points of the primary feedback flyback converter design is the design of the sample-hold and knee-point detection circuits. Specifically, as shown in fig. 1, when the secondary side is turned on and the primary side is turned off, the output voltage information is flyback to the primary side through the primary side winding and is reflected in the drain voltage V of the power tube _SW Then the VIN clamping circuit is used for feeding back the voltage V _FB Clamp to VIN to cause feedback resistor R _FB The voltage at two ends only contains flyback voltage information and passes through the reference resistor R _REF Generating a feedback reference voltage V _RREF Feedback referenceVoltage V _RREF And the output voltage information is transmitted to a sampling hold and knee point detection circuit, and the system adjusts the duty ratio through the output voltage information obtained by sampling, so that constant voltage output is realized. Therefore, the accurate detection of the output voltage can ensure that the output voltage of the system has higher precision. At the knee point, the parasitic impedance of the secondary side produces a voltage drop that is not to V due to the zero secondary side inductor current _SW Influence at this time V _SW The information of the output voltage can be described more precisely.

In the existing knee point detection and sample hold scheme, multiple paths of circuits are used for sequentially sampling to obtain multiple sampling values, the voltage of the last sampling point is subtracted by a fixed voltage value and is compared with the current sampling voltage value to obtain a true sampling value, and the truest sampling value is sent to a sampling method of a subsequent module. Digital assistance using analog-to-digital converters ADC and digital-to-analog converters DAC is also often used for accurate knee point detection, but is often prohibitively expensive. Still other schemes adopt a delay circuit consisting of resistance and capacitance to delay the voltage and V _FB The knee point is obtained by comparing through the additional comparator, and the method adopts the additional comparison circuit, so that the power consumption is relatively large.

Disclosure of Invention

The invention mainly designs and realizes a sampling hold and knee point detection circuit, and a buffer and a comparator of the circuit multiplex a folding type common-source common-gate structure, thereby omitting extra operational amplifier and reducing the power consumption and the cost of the circuit. When the feedback voltage reaches the knee point, the voltage waveform can drop sharply, and the buffer itself has time delay, and the voltage difference is formed between the two voltages to enable the comparator to turn over, so that the knee point signal is obtained by detection, and then the sampling switch is opened to sample the capacitor C _delay The stored charge is shared to the holding capacitor C _hold After a narrow pulse time, the comparator is turned off, and the sampling switch is turned off, so that the sampling work is completed, and the knee point voltage value is obtained.

In order to achieve the above purpose, the technical scheme of the invention is as follows:

a sample-hold and knee point detection circuit is used for detecting knee point voltage of a primary side feedback flyback converter when secondary side inductance current is zero, and comprises a buffer, a comparator, a first NMOS tube, a second NMOS tube, a third NMOS tube, a first resistor, a first capacitor, a second capacitor and a voltage source;

the non-inverting input end of the buffer is connected with the feedback voltage, the inverting input end of the buffer is connected with the output end of the buffer, the output end of the buffer is grounded after sequentially passing through the first resistor and the first capacitor, an enabling signal of the buffer is defined as a first enabling signal, and the output of the buffer is defined as a delay voltage;

the non-inverting input end of the comparator is connected with the delay voltage, the inverting input end of the comparator is connected with the positive end of the voltage source, the negative end of the voltage source is connected with the feedback voltage, the enabling signal of the comparator is defined as a second enabling signal, the output voltage is defined as a judging voltage, and the voltage source generates a fixed offset voltage;

the drain electrode of the first NMOS tube is connected with a delay voltage, and the grid electrode of the first NMOS tube is connected with a third enabling signal;

the source electrode and the drain electrode of the second NMOS tube are connected with the source electrode of the first NMOS tube, the grid electrode of the second NMOS tube is connected with the reverse signal of the first enabling signal, the connection point of the source electrode of the first NMOS tube and the source electrode of the second NMOS tube is grounded after passing through the second capacitor, and the output of the connection point of the source electrode of the first NMOS tube, the source electrode of the second NMOS tube and the second capacitor is defined as knee point voltage holding voltage;

the drain electrode of the third NMOS tube is connected with the connection point of the first resistor, the first capacitor and the drain electrode of the first NMOS tube, the grid electrode of the third NMOS tube is connected with a pulse signal, and the source electrode of the third NMOS tube is grounded; when the primary side is conducted, the pulse signal is in a high level, the third NMOS tube is turned on, and when the secondary side is conducted, the pulse signal is in a low level, and the third NMOS tube is turned off;

when the secondary side is conducted and the feedback voltage rises, the first enabling signal controls the buffer to be started, and the second enabling signal controls the comparator to be turned off, so that the delay voltage always follows the feedback voltage, and the voltage value of the first capacitor is updated; when the feedback voltage enters a platform period, a second enabling signal controls a comparator to be started, when a knee point arrives, the comparator turns over, the judgment voltage turns over from low potential to high potential, a third enabling signal correspondingly turns high, a first NMOS tube is started for sampling, the charge of a first capacitor is shared to the second capacitor, and a buffer is controlled by the first enabling signal to be turned off, so that the delay voltage keeps the knee point voltage; after a narrow pulse time, the third enable signal turns low, the first NMOS tube is turned off, the second NMOS tube is turned on, meanwhile, the second enable signal controls the comparator to be turned off, and the first enable signal controls the buffer to be turned on.

Further, the comparator comprises a first PMOS tube, a second PMOS tube, a third PMOS tube, a fourth PMOS tube, a fifth PMOS tube, a fourth NMOS tube, a fifth NMOS tube, a sixth NMOS tube, a seventh PMOS tube, an eighth PMOS tube, a second resistor, a third resistor, a fourth resistor, a tenth NMOS tube and a twelfth NMOS tube; the buffer comprises a first PMOS tube, a second PMOS tube, a third PMOS tube, a fourth PMOS tube, a sixth PMOS tube, a fourth NMOS tube, a fifth NMOS tube, a seventh PMOS tube, an eighth PMOS tube, a seventh NMOS tube, an eighth NMOS tube, a ninth NMOS tube, a second resistor, a third resistor, a fourth resistor and an eleventh NMOS tube;

the sources of the first PMOS tube, the second PMOS tube, the third PMOS tube, the fourth PMOS tube, the fifth PMOS tube and the sixth PMOS tube are all connected with a power supply; grid-drain interconnection of the first PMOS tube, and drain electrode of the first PMOS tube is connected with a current source; the grid electrodes of the second PMOS tube, the third PMOS tube, the fourth PMOS tube, the fifth PMOS tube and the sixth PMOS tube are connected with the drain electrode of the first PMOS tube; the first PMOS tube, the second PMOS tube, the third PMOS tube, the fourth PMOS tube, the fifth PMOS tube and the sixth PMOS tube form a current mirror for providing bias current for the circuit, and the mirror ratio is 1:8:4:4:4:1;

the source electrode of the seventh PMOS tube is connected with the drain electrode of the second PMOS tube, the grid electrode of the seventh PMOS tube is connected with the feedback voltage through the fourth resistor, and the drain electrode of the seventh PMOS tube is grounded through the second resistor;

the drain electrode of the second NMOS tube is connected with feedback voltage through a fourth resistor, the grid electrode and the source electrode of the second NMOS tube are connected with each other, and the source electrode of the second NMOS tube is grounded;

the source electrode of the eighth PMOS tube is connected with the drain electrode of the second PMOS tube, the grid electrode of the eighth PMOS tube is connected with the source electrode of the seventh NMOS tube, and the drain electrode of the eighth PMOS tube is grounded after passing through the third resistor;

the grid electrode and the drain electrode of the fourth NMOS tube are connected with the drain electrode of the third PMOS tube, and the source electrode of the fourth NMOS tube is grounded after passing through the second resistor; the drain electrode of the fifth NMOS tube is connected with the drain electrode of the fourth PMOS tube, the grid electrode of the fifth NMOS tube is connected with the drain electrode of the third PMOS tube, and the source electrode of the fifth NMOS tube is grounded after passing through the third resistor;

the drain electrode of the sixth NMOS tube is connected with the drain electrode of the fifth PMOS tube, the grid electrode of the sixth NMOS tube is connected with the drain electrode of the fourth PMOS tube, and the source electrode of the sixth NMOS tube is grounded;

the drain electrode of the tenth NMOS tube is connected with the drain electrode of the fifth PMOS tube, the grid electrode of the tenth NMOS tube is connected with a second enabling signal, and the source electrode of the tenth NMOS tube is grounded;

the connection point of the drain electrode of the fifth PMOS tube, the drain electrode of the sixth NMOS tube and the drain electrode of the tenth NMOS tube is the output end of the comparator;

the drain electrode of the seventh NMOS tube is connected with a power supply, and the grid electrode of the seventh NMOS tube is connected with the drain electrode of the fourth PMOS tube; the grid electrode and the drain electrode of the eighth NMOS tube are connected with the drain electrode of the sixth PMOS tube, and the source electrode of the eighth NMOS tube is grounded; the drain electrode of the ninth NMOS tube is connected with the source electrode of the seventh NMOS tube, the grid electrode of the ninth NMOS tube is connected with the drain electrode of the sixth PMOS tube, and the source electrode of the ninth NMOS tube is grounded;

the drain electrode of the eleventh NMOS tube is connected with the drain electrode of the sixth PMOS tube, the grid electrode of the eleventh NMOS tube is connected with the first enabling signal, and the source electrode of the eleventh NMOS tube is grounded;

the connection point of the source electrode of the seventh NMOS tube, the grid electrode of the eighth PMOS tube and the drain electrode of the ninth NMOS tube is the output end of the buffer.

The beneficial effects of the invention are as follows: accurate knee point voltage value can be obtained, and meanwhile, the power consumption and the cost of the circuit are reduced.

Drawings

Fig. 1 is a schematic diagram of a primary-side feedback flyback converter.

Fig. 2 is a waveform diagram of the feedback reference VRREF voltage and inductor current.

Fig. 3 is a block diagram of a sample-hold and knee point detection scheme proposed by the present invention.

Fig. 4 is a timing diagram of sample-and-hold and knee detection schemes proposed by the present invention.

Fig. 5 is a circuit diagram of sample-and-hold and knee point detection according to the present invention.

Detailed Description

The technical scheme of the invention is described in detail below with reference to the accompanying drawings:

the schematic diagram of the primary side flyback converter provided by the invention is shown in fig. 1. Feedback reference V _RREF The waveforms of the voltage and inductor current are shown in FIG. 2, where I _PRI For primary inductor current, I _SEC Is the secondary inductor current. In the toff time period of secondary side opening, t0-t1 is influenced by leakage inductance and parasitic capacitance of the power tube, V _SW Ringing occurs to make V _RREF Ringing also occurs and the system typically chooses to mask this period of time in order to avoid false triggers. After ringing, in t1-t2, the parasitic impedance of the secondary side and the reduction of the secondary side current influence V _SW There is a tendency to drop down to V during this time _SW Can be expressed as

V _SW (t)＝VIN+N _PS (V _out +V _F +I _SEC (t)R _s )

Wherein VIN is input voltage, N _PS For turn ratio of primary and secondary transformers, V _F R is the conduction voltage drop of the secondary side diode _S Is the secondary equivalent impedance.

At time t2, the secondary current drops to 0 and reaches the knee point, at which time V _SW No secondary parasitic resistance information is included. After the knee point, V _RREF High frequency resonance occurs and voltage ripple varies drastically. According to the characteristics of knee points, a sample-hold and knee point detection scheme proposed by the present invention is shown in fig. 3. The scheme mainly comprises the following steps: buffer A1, comparator A2, first order low pass filter resistor R _delay And capacitor C _delay Holding capacitor C _hold Sampling switch MN1, dummy switch MN2, and reset switch tube MN3.

The control time sequence of the sampling hold and knee point detection scheme provided by the invention is shown in figure 4, when the secondary side is conducted, the MN3 tube is turned off, and the feedback parameter is fed backTest voltage V _RREF Rapidly rise and at the same time due to the action of the buffer V _buffer The voltage will follow V _RREF The voltage rises from zero. t0-t1, namely when the secondary side is just conducted, a large amount of charges are stored in the parasitic capacitance of the power tube, resonance is formed between the parasitic capacitance of the power tube and the primary side inductance, and in order to avoid false triggering of the comparator A2 in the period of time, EN_LEB is not enabled, so that only the buffer A1 works and the buffer A2 does not work at the moment. t1-t2, V _RREF Entering the platform phase, EN_LEB is enabled, the comparator A2 starts to work, and the buffer A1 is always started to open V _buffer The voltage always following V _RREF Voltage, update capacitance C _delay Is a voltage value of (a). At time t2, the secondary side inductance current drops to 0, the knee point arrives, V _RREF The voltage drops rapidly, which is limited by the pull-down slew rate and buffer delay, V _buffer Unable to follow in time, V _buffer And V is equal to _RREF The voltage difference exists between the two voltages to enable the comparator A2 to overturn, and knee to overturn from low potential to high potential, V _SES Potential turning-up, sampling switch opening, C _delay Is shared to C _hold The EN_hold signal turns off the pull-down current of buffer A1 such that V _buffer Maintaining knee point voltage, ensuring accurate knee point voltage and V _buffer And V is equal to _RREF So that the comparator does not malfunction. After a small narrow pulse time, V _SES The potential is turned down, the sampling switch MN1 is turned off, the virtual switch MN2 is turned on, clock feedthrough is compensated, the EN_LEB potential is turned up, the comparator A2 is turned off, resonance after the knee point is ensured not to cause the comparator to be triggered by mistake, the EN_hold potential is turned down, and the A1 starts to work normally. When the primary side is conducted, i.e. the PWM signal is at high potential, the MN3 tube is opened to make C _delay The voltage of the upper plate is reset to zero.

The sample-and-hold and knee point detection circuit is shown in fig. 5. In the figure, MP1, MP2, MP3, MP4, MP5, and MP6 tube form a current mirror providing bias current to the circuit with a mirror ratio of 1:8:4:4:4:1. The circuit is mainly divided into four parts, the first part is of a common-source common-gate structure, the mirror ratio of the current mirrors MP2, MP3, MP4, MN4 and MN5 is 1:1, and the input pair transistors MP7 and MP are input8, load resistors R1 and R2, a current limiting resistor R3 and a GGNMOS tube MN12 for protecting electrostatic discharge (ESD); the second part is MP5 and MN6, and a switch tube MN10, and the second part and the first part are combined to form a comparator A2; the third part consists of current mirrors MP6, MN8 and MN9, wherein the mirror image ratio of MN8 to MN9 is 1:1, a source follower MN7 and a switch tube MN11, and the third part and the first part are combined to form a buffer A1; the fourth part is composed of a first-order low-pass filter (resistor R _delay And capacitor C _delay ) Holding capacitor C _hold Sampling switch MN1, virtual switch MN2 and reset switch tube MN3. The invention adopts a structure that the comparator and the buffer share a folding common-source common-gate, thereby omitting extra operational amplifier and reducing the power consumption and the cost of the circuit.

The sample-and-hold and knee point detection circuits are described in detail below. The first part is a cascode structure of the comparator and the buffer multiplex, which aims to provide larger gain for the buffer and the comparator. Due to V _RREF Introduced from the outside of the chip, in order to avoid the damage of larger current and static electricity to the input tube MP7, R3 is adopted to limit the current, GGNMOS tube MN12 is adopted to carry out static electricity discharge, and meanwhile, parasitic capacitance of R3 and MN12 forms a first-order low-pass filter which can be used for V _RREF Simple filtering is performed. The folding type common-source common-gate structure ensures that the structure has larger output resistance while ensuring the input common-mode range, thereby ensuring that the structure has larger gain.

Input common mode range is

8I _BIAS R ₁ -|V _THP |≤ICMR≤V _DD -V _ov -|V _THP |

Wherein I is _BIAS As reference current, V _THP Vov is the threshold voltage of the PMOS transistor, and Vov is the overdrive voltage.

The gain of the multiplexing cascode structure is

A _V1 ＝g _m,MP7 {r _o,MP4 ||[g _m,MN5 r _o,MN5 (R ₂ ||r _o,MP8 )]}

Wherein g _m,MP7 ，g _m,MN5 R is the transconductance of MP7 and MN5 _o,MP4 ，r _o,MN5 ，r _o,MP8 On-resistances of MP4, MN5, and MP8, respectively.

To ensure accuracy of the sampled voltage, it is first necessary to ensure buffer output accuracy. When the precision requirement is 0.5%, the open loop gain of the buffer is required to be more than 200 times. The open loop gain of the buffer can be expressed as

Wherein g _m,MN7 Transconductance of MN7, r _o,MN9 Is the on-resistance of MN 9.

Knee point detection needs to be performed at V _RREF When the voltage drops, V _buffer Does not quickly follow V _RREF The negative slew rate of the buffer needs to be small, which can be expressed as

The negative slew rate is related to the pull-down current, and to ensure a smaller pull-down current, the ratio of MP1 to MP6 to MN8 to MN9 current mirrors is 1 to 1.

The comparator multiplexing the folded cascade structure with the buffer can obtain larger open loop gain without extra operational amplifier, and can be expressed as

A _V3 ＝A _V1 ×g _m,MN6 (r _o,MP5 ||r _o,MN6 )

＝g _m,MP7 {r _o,MP4 ||[g _m,MN5 r _o,MN5 (R ₂ ||r _o,MP8 )]}×g _m,MN6 (r _o,MP5 ||r _o,MN6 )

The time delay of the comparator turning consists of a small signal time delay and a large signal time delay. The small signal delay depends on the-3 dB bandwidth of the open loop state, while the large signal delay is determined by the slew rate. When the knee point arrives, V _RREF Rapidly drops and thus large signal delays dominate. Forward switching speed of comparatorThe rate can be expressed as

Wherein C is _knee The parasitic capacitance of the output node of the comparator mainly comprises the gate-drain capacitance of MP5 and MN 6.

To ensure accuracy of sampling, R needs to be utilized _delay And C _delay To eliminate the effect of comparator delay, i.e. to ensure

Wherein V is _turn The flip level of the later control logic is triggered for knee, typically VDD/2.

At the same time when the knee point is reached, V _SES C, controlling the sampling switch to be turned on _delay And C _hold The capacitor performs charge sharing. According to the principle of conservation of charge, V after the end of sample and hold _hold The method comprises the following steps:

it can be seen that when C _delay The larger C _hold The smaller the V _hold The smaller the error from the knee voltage, the more often it is necessary to let C _delay The capacitance value of (C) _hold Ten times and more the capacitance.

Claims

1. The sampling hold and knee point detection circuit is used for detecting knee point voltage of a primary side feedback flyback converter when secondary side inductance current is zero and is characterized by comprising a buffer, a comparator, a first NMOS tube, a second NMOS tube, a third NMOS tube, a first resistor, a first capacitor, a second capacitor and a voltage source;

when the secondary side is conducted and the feedback voltage rises, the first enabling signal controls the buffer to be started, and the second enabling signal controls the comparator to be turned off, so that the delay voltage always follows the feedback voltage, and the voltage value of the first capacitor is updated; when the feedback voltage enters a platform period, a second enabling signal controls a comparator to be started, when a knee point arrives, the comparator turns over, the judgment voltage turns over from low potential to high potential, a third enabling signal correspondingly turns high, a first NMOS tube is started for sampling, the charge of a first capacitor is shared to the second capacitor, and a buffer is controlled by the first enabling signal to be turned off, so that the delay voltage keeps the knee point voltage; after a narrow pulse time, the third enabling signal is turned down, the first NMOS tube is turned off, the second NMOS tube is turned on, meanwhile, the second enabling signal controls the comparator to be turned off, and the first enabling signal controls the buffer to be turned on;

the comparator comprises a first PMOS tube, a second PMOS tube, a third PMOS tube, a fourth PMOS tube, a fifth PMOS tube, a fourth NMOS tube, a fifth NMOS tube, a sixth NMOS tube, a seventh PMOS tube, an eighth PMOS tube, a second resistor, a third resistor, a fourth resistor, a tenth NMOS tube and a twelfth NMOS tube; the buffer comprises a first PMOS tube, a second PMOS tube, a third PMOS tube, a fourth PMOS tube, a sixth PMOS tube, a fourth NMOS tube, a fifth NMOS tube, a seventh PMOS tube, an eighth PMOS tube, a seventh NMOS tube, an eighth NMOS tube, a ninth NMOS tube, a second resistor, a third resistor, a fourth resistor and an eleventh NMOS tube;