JPH05283676A - Semiconductor device - Google Patents

Abstract

PURPOSE:To provide a low loss power device for high-frequency application by remarkably improving trade-off between on-voltage reduction and switching time shortening that is difficult for conventional power device such as an MCT or IGBT. CONSTITUTION:A semiconductor device is provided with a first MOS 13n which supplies electronic current from an emitter electrode 7 to an n<->-type base layer 3 and a second mode switching MOS 14 which drains hole current from a p-type base layer 4 to the emitter electrode 7. When the device is turned on, low on- voltage is allowed under the thyristor condition and when the device is turned off, the second MOS 14 is conducted so as to change from the thyristor condition to the transistor condition and the turn-off time is shortened.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a structure of a MOS type semiconductor device used as a power device or the like, and more particularly to a double gate type semiconductor device having two gate electrodes.

[0002]

2. Description of the Related Art In recent years, the performance of power semiconductor devices has dramatically improved. For example, with regard to bipolar transistors, high performance, high breakdown voltage, and large current can be achieved.
Intelligent modules with various protection functions have also appeared. In addition, as IGBTs (conductivity modulation type transistors), ones capable of high-speed response have also appeared. These power devices are used in battery-driven miniaturized electric products that are easy to carry, as well as in electric vehicles that are being considered for environmental protection, and play a role in saving power. ing.
And to meet the ever-increasing demand for electricity,
Further power saving loss is also required for these power semiconductor devices.

For example, an MCT (MOS gate control thyristor) has been developed for the purpose of reducing the on-voltage by a thyristor structure and high speed and low driving power by a MOS gate device. This MCT is a device having a configuration and an equivalent circuit as shown in FIGS. 24 and 25, and is a paper published by VAK Temple ("MO
S controlled thyristors "IEEE International Electr
on Device Meeting Digest 1984) etc. MC
The T60 has an ON-FET 62a and an OFF-FET 62b controlled by a single gate electrode 61, and makes the ON-FET 62a conductive and OF.
When the F-FET 62b is cut off, an npnp thyristor composed of the n ⁺ cathode layer 64 provided with the cathode electrode 63, the p ⁻ base layer 65, the n base layer 66, and the p ⁺ anode layer 67 provided with the anode electrode 68 is formed. Turns on. When the OFF-FET 62b is turned on and the ON-FET 62a is cut off, the n base layer 66 and the anode electrode 68 are short-circuited, and the pnp transistor constituted by the p ⁻ base layer 65, the n base layer 66, and the p ⁺ anode layer 67. Since 69 is off, the device is turned off. In this way, MCT
Since 60 turns on the device by MOS, the response speed is fast, and the thyristor turns on.
The on-voltage is also very low, about 1V. However, as shown in FIG. 26, in the thyristor state, the carrier density of holes and electrons existing in the anode layer 67 and the base layers 65 and 66 is high. Therefore, due to such a very high carrier density, the turn-off time is as long as 2 to 3 μsec, and the loss during this time becomes a problem. Especially in high frequency applications, the power loss will be greatly increased.

On the other hand, in the IGBT shown in FIG. 27,
A typical waveform at the time of turn-off is as shown in FIG. As can be seen in FIG. 28, the waveform at turn-off is
There are a first phase 91 and a second phase 92. The first phase 91 shows a phenomenon in which the channel due to the gate 87 disappears and the supply of the electron current from the emitter electrode 88 to the n ⁻ base layer 82 is stopped, so that the current instantaneously decreases by that amount. In the second phase 92, the carriers remaining in the n ⁻ base layer 82 are changed to the p ⁺ collector layers 81, n.
^- pn constituted by a base layer 82, p base layer 83
It shows a phenomenon that the current flows due to the action of the p-transistor and decreases due to recombination disappearance due to the carrier lifetime τ. Therefore,
In order to shorten the turn-off time of the IGBT, the injection level of the hole current may be reduced or the carrier life τ may be shortened. Therefore, a technique of forming an n ⁺ layer between the p ⁺ collector layer 81 and the n ⁻ base layer 82 to control the injection level of the hole current (IEEE, IEDM Technical Digest, 4.3).
(1983) pp. 79-82), or a technique for controlling the concentration of the collector layer 81 has been proposed. As a technique for reducing the carrier life τ, a technique that applies a lifetime control process such as electron beam irradiation or heavy metal diffusion (IEEE, Trans. Electron Devices, ED-31
(1984) pp.1790-1795) has been proposed. With this kind of technology, the fall time at turn-off is ~ 2
It is possible to reduce the time to 00 ns, and the device can be used for high frequencies. In addition, this IGB
Regarding the technology related to T, the paper ("New IGBT Modules with Improved Power Loss at
High Frequency PWM Mode "Electronica '90 Munchen)
Familiar with.

As described above, the IGBT has the advantage that the turn-off time is short, while the concentration of the p base layer 83 is increased in order to prevent the parasitic thyristor from operating and the latch-up state. Since the on-voltage is as high as about 2 V due to the fact that it cannot be performed, it is a device in which it is difficult to reduce the on-loss. In the IGBT, as shown in FIG. 27, the emitter current is I
_{When E} = I _h + I _MOS and the gain of the pnp transistor composed of the p base region 83, the n ⁻ drift region 82, and the p ⁺ collector region 81 is α _PNP , I _h = (α _PNP / (1-α _PNP )) × I _MOS , and therefore, I _E = (1 / (1−α _PNP )) × I _MOS . I _h (hole current) changes depending on the value of α _PNP , that is, the current of the IGBT changes. I _MOS is an electron current.

[0006]

One of the most important key technologies for solving the problems such as high performance, miniaturization and cost reduction in power electronics is to reduce the loss of power devices. For that purpose, it is necessary to develop a power device that has a short turn-off time and a low on-voltage. However, for example, in the above MCT, in order to shorten the turn-off time, the same measure as that of the IGBT, that is,
If the lifetime is reduced and the n ⁺ buffer layer is adopted, the on-voltage rises as in the IGBT. Therefore, the advantage of MCT that the on-voltage is low is not utilized. Furthermore, in order to shorten the turn-off time, MC
It is necessary to pull out the carriers accumulated in T at once.
However, for this purpose, it is necessary to add a MOS gate for current extraction, and an increase in drive power for current extraction also poses a problem. Furthermore, in order to extract a large current in a short time, it is necessary to achieve a low on resistance of the MOS gate. As described above, at present, it is possible to achieve high performance by making use of the characteristics of a device having a low on-voltage and a device having a short turn-off time, but it can be said that it is difficult to realize a device having both characteristics.

In view of the above problems, the present invention has a feature that the MCT has a low on-voltage and I
The objective is to realize a new power device that takes advantage of the short turn-off time of the GBT.

[0008]

In order to solve the above problems, in the present invention, a new device has been developed which is in a thyristor state when turned on and is in a transistor state when turned off like IGBT. That is, the semiconductor device according to the present invention is a semiconductor device having a thyristor structure including a first conductivity type collector region, a second conductivity type base region, a first conductivity type base region, and a second conductivity type emitter region. First MISF capable of injecting majority carriers into the second conductivity type base region
ET and a second MISFET capable of opening / closing independently of the first MISFET and capable of extracting majority carriers from the first conductivity type base region. In this semiconductor device, the second MI
In addition to the SFET, a third MISFET may be provided which shares the gate electrode of the first MISFET and can extract the majority carriers from the first conductivity type base region. As a semiconductor built-in structure for realizing such an equivalent circuit structure, a first conductivity type emitter is provided separately from the second conductivity type emitter region to which an emitter potential is applied together in the first conductivity type base region. Form an area. Specifically, the first conductivity type emitter region is formed in the second conductivity type emitter region. The second gate electrode of the second MISFET is formed on the surfaces of the first conductivity type emitter region and the second conductivity type emitter region and the first conductivity type base region through the gate insulating film, and the second conductivity type is formed. The emitter region of the mold is the channel region. Further, the common first gate electrode of the first MISFET and the third MISFET is the first emitter region to the second conductivity type emitter region, the first conductivity type base region, and the second conductivity type base region. Is formed on the surface of the substrate through a gate insulating film, and the first conductivity type base region serves as the channel region of the first MISFET and the second conductivity type emitter region serves as the channel region of the third MISFET. In such a case, the dose amount of the first conductivity type base region is set to 2 × 10 ¹³ cm ⁻² or more and 1 × 10 ¹⁴ cm ⁻² or less, and the dose amount of the second conductivity type emitter region is set to the first conductivity type. It is preferably set to 1 × 10 ¹⁴ cm ⁻² or less at the dose amount of the base region or more.

The first-conductivity-type base region may be composed of a first-conductivity-type high-concentration well and a first-conductivity-type peripheral region shallower than the well. In this case, when a well of the first conductivity type high concentration is formed by surface diffusion, it is preferable that the dose amount be 1 × 10 ¹³ cm ⁻² or more and 5 × 10 ¹⁵ cm ⁻² or less. When a well of high conductivity of the first conductivity type is formed as an embedded type, the dose amount is 1 × 1.
It is preferably 0 ¹² cm ⁻² or more and 3 × 10 ¹⁴ cm ⁻² or less. Further, when a well of high concentration of the first conductivity type is formed as a buried type, the edge of the diffusion window of the well of the high concentration of the first conductivity type is located at a second position from the inner edge of the emitter region of the first conductivity type. It is set so as to be located on the second gate electrode side of the MISFET.

The second-conductivity-type emitter region may also be composed of a second-conductivity-type high-concentration well and a second-conductivity-type peripheral portion shallower than the well. In such a case, the surface concentration of the well of the second conductivity type is 5 × 10 ¹⁷ cm ⁻³ or more and 5 × 10 ²⁰ or less.
It is preferable to set it to be cm ⁻³ or less. The diffusion depth of the second-conductivity-type high-concentration well is preferably not less than the diffusion depth of the second-conductivity-type peripheral portion and not more than 1.9 μm. Furthermore,
The gate length of the first gate electrode is 20 μm or more and 30 μm
The gate length of the second gate electrode is 1 μm or more and 8 μm or less, and the first conductivity type emitter region and the second
The contact length of the emitter electrode that is in conductive contact with the conductive type emitter region is preferably 1 μm or more and 6 μm or less.

A second conductive type shallow counter-doping region may be formed on the surface of the first conductive type base region related to the first MISFET. Furthermore, the second MISF
A high concentration doping region of the first conductivity type may be formed on the surface of the first conductivity type base region related to ET.

[0012]

In the above semiconductor device, the first MISFE
When T is turned on, majority carriers are injected from the second-conductivity-type emitter region into the second-conductivity-type base region, and in response to this, a small number of minor-carriers are transferred from the first-conductivity-type collector region to the second-conductivity-type base region. Carriers are injected. Therefore, the transistor including the first conductivity type collector region, the second conductivity type base region, and the first conductivity type base region is turned on. As a result, majority carriers are injected into the first-conductivity-type base region, and at the same time, a transistor including the second-conductivity-type base region, the first-conductivity-type base region, and the second-conductivity-type emitter region is formed. It turns on. Therefore, the thyristor including the first conductivity type collector region, the second conductivity type base region, the first conductivity type base region, and the second conductivity type emitter region is turned on. Therefore, the ON voltage can be lowered.

On the other hand, when the second MISFET for mode switching is turned on while the first MISFET is on, the majority carriers in the base region of the first conductivity type pass through the second MISFET and pass the first conductivity type. Of the second conductivity type base region, the first conductivity type base region, and the second conductivity type emitter region are turned off. Therefore, the thyristor state changes to a transistor state similar to that of the IGBT, and the carrier density in the device decreases. Therefore, it is possible to shorten the turn-off time when the first MISFET is turned off thereafter and the semiconductor device is turned off.

In the case where the third MISFET is provided, the third MISFET is turned on and the third MISFET is turned on.
When the MISFET of is turned on, the action of extracting majority carriers in the emitter region of the first conductivity type is enhanced,
The turn-off time can be further shortened. First
The first gate electrode of the second MISFET from the first emitter layer formed in the emitter region of the second conductivity type to the second
By installing the conductive type emitter region, the first conductive type base region, and the second conductive type base region,
When turned on, majority carriers can be injected from the second conductivity type emitter region to the second conductivity type base region. On the other hand, when off, minority carriers can be extracted from the first conductivity type base region to the first emitter layer, and the turn-off time can be further shortened. Third MISFET
Since the gate electrode of the first MISFET and the gate electrode of the first MISFET are common, the third MIS is generated when the first MISFET is off.
The FET is turned on. Separately, by forming the first conductivity type base region with the first conductivity type high-concentration well and the first conductivity type peripheral region shallower than the well, the ON voltage can be controlled to be low and the controllable current can be increased. be able to. If the second-conductivity-type emitter region is composed of the second-conductivity-type high-concentration well and the shallower second-conductivity-type peripheral portion, a larger controllable current can be obtained with a lower on-voltage. The channel length of the first MISFET is reduced by the second conductive type shallow counter-doping region formed on the surface of the first conductive type base region, and the turn-off characteristic and the on-voltage can be improved. And again, the gate electrode of the second MISFET is
By arranging from the second emitter layer formed in the second conductivity type emitter region to the second conductivity type emitter region and the first conductivity type base region, the first conductivity type base region to the second conductivity type Majority carriers can flow out to the emitter layer. Further, by forming a high-concentration doping region of the first conductivity type on the surface of the first conductivity type base region where the gate electrode of the second MISFET is installed, the resistance in the outflow of majority carriers is reduced, and the transistor state is improved. The ON resistance of the second MISFET can be reduced.

[0015]

Embodiments of the present invention will be described below with reference to the drawings.

[Embodiment 1] FIG. 1 is a cross-sectional view taken along the line AA 'in the plan view of this embodiment shown in FIG. 2, showing a double gate of a first gate and a second gate. The structure (cell structure) of the provided semiconductor device is shown. In the semiconductor device of this example, a p ⁺ type substrate having a collector electrode 1 provided on the back surface is used as a collector layer 2, and an n ⁻ type base layer 3 is formed on the collector layer 2 by epitaxial growth or the like. .. Then, on the surface of the n ⁻ type base layer 3, a p type base layer 4 which is a well-like p or p ⁺ type diffusion layer is formed. Further, n-type emitter layers 5a and 5b are formed on the inner surface of the p-type base layer 4 by two n-type wells. Two p ⁺ -type emitter layers 6a and 6b are formed on the inner surface of each n-type emitter layer 5a and 5b. These two p ⁺ type emitter layers 6
An emitter electrode 7 is connected to a, 6b and the n-type emitter layers 5a, 5b. Further, from the p ⁺ type emitter layer 6a to the surface of the n type emitter layer 5a or 5b, the p type base layer 4 and the n ⁻ type base layer 3,
A first gate electrode (common gate electrode) 11 constituting the first MOSFET 13n and the third MOSFET 13p is provided via the gate oxide film 8. On the other hand, p ⁺
A second gate electrode 12 forming a second MOS 14 is provided through the gate oxide film 8 from the emitter layer 6b of the n-type to the surface of the emitter layer 5a or 5b of the n-type and the base layer 4 of the p-type. Has been done. First gate electrode 11 and second
The gate electrode 12 is formed separately from the gate electrode 12 of FIG.
That is, for example, as shown in FIG. 2, the first gate electrode 11
And the second gate electrode 12 are formed in a comb shape.

Since the two n-type emitter layers 5a and 5b have the same structure, the description will be given below with reference to the n-type emitter layer 5a. First, the gate electrode 1
The MOS 13 constituted by 1 has an n-type emitter layer 5
a, p-type base layer 4 and the n ^- first and MOS13n the configured n-channel type by the type of base layer 3, p ⁺
-Type emitter layer 6a, n-type emitter layer 5a, and p-type base layer 4
OS 13p. On the other hand, the second MOS 14 constituted by the gate electrode 12 is a p-channel type MO
It is an SFET.

FIG. 3 shows an equivalent circuit of this device. In this device, the n-type emitter layer 5a, the p-type base layer 4 and the n ⁻ -type base layer 3 form an npn-type transistor Qnpn. Further, a p-type base layer 4, an n ⁻ -type base layer 3 and a p ⁺ -type collector layer 2
A pnp-type transistor Qpnp is constituted by. Therefore, these transistors Qnpn and Qp
The thyristor 15 is composed of np. Note that, in the equivalent circuit shown in FIG. 3, the collector 1 and the emitter 7 are shown as being divided into two thyristors, but they are shown separately for convenience, and both are the same.

These transistors Qnpn and Qpnp
On the other hand, the first MOS 13n includes the transistor Qnpn
And the base of the transistor Qpnp and the emitter electrode 7 are connected. Also, the third
The MOS 13p is configured to connect the base of the transistor Qnpn and the emitter electrode 7 via the p ⁺ type emitter layer 6a. On the other hand, the second MOS 14 is configured to connect the base of the transistor Qnpn and the emitter electrode 7 via the p ⁺ type emitter layer 6b.

In this device having such a structure, when both the first gate electrode 11 and the second gate electrode 12 are set to a high potential, the first MOSFET 13n is turned on,
Second MOSFET 14 and third MOSFET 13p
Remains off. That is, the surface of the n-type emitter layer 5a immediately below the gate electrode 11 becomes an n ⁺ -type storage layer, and the surface of the p-type base layer 4 becomes an n-type inversion layer. The emitter layer 5a, the n ⁺ type accumulation layer on the surface thereof, the n type inversion layer on the surface of the p type base layer 4, and the n ⁻ type base layer 3 are connected. Therefore, electrons are injected from the emitter electrode 7 into the n ⁻ type base layer 3 which is the drift region, and correspondingly, holes are injected from the p ⁺ type collector layer 2. This means that the pnp type transistor Qpnp is turned on. Further, the hole current of the transistor Qpnp is changed by the n-type emitter layer 5a, the p-type base layer 4 and the n-type emitter layer 5a.
^- constituted by the type of the base layer 3 transistor Qnp
Since the base current is n, the transistor Qnpn is turned on. That is, the p ⁺ type collector layer 2, n ⁻
The thyristor 15 composed of the p-type base layer 3, the p-type base layer 4, and the n-type emitter layer 5a is turned on, high-concentration carriers exist in the device, and the device has low resistance. As described above, in the present device, by setting the gate electrodes 11 and 12 to a high potential, only the first MOSFET 13n is turned on, and n
^- it is injected majority carriers (electrons) for the type of the base layer 3, a thyristor state similar to the MCT described above in response to this. Therefore, this example is a power device with a low on-voltage. Here, the first MOSFET 13n serves as a MOSFET for turning on the thyristor.

When the first gate electrode 11 is kept at a high potential and the gate electrode 12 of the second MOS 14 is set to a negative potential from the on state of the thyristor, the second MOS 14 is turned on. That is, the surface of the n-type emitter layer 5a immediately below the gate electrode 12 is inverted to p-type. Then, the p-type base layer 4, the p-type inverted surfaces of the n-type emitter layer 5a, and the p ⁺ -type emitter layer 6b are short-circuited. Therefore, the hole current injected from the p ⁺ type collector layer 2 is
It flows out from the p-type base layer 4 to the emitter electrode 7 through the p ⁺ -type emitter layer 6b. Therefore, the transistor Qnpn composed of the n-type emitter layer 5a, the p-type base layer 4, and the n ⁻ -type base layer 3 is turned off. As a result, the thyristor operation disappears and the p-type base layer 4, n ⁻
Only the transistor Qpnp composed of the p-type base layer 3 and the p ⁺ -type collector layer 2 is in the operating state. This state is the same as the operating state of the IGBT described above, and therefore the carrier density existing in the device is reduced. Therefore, after this, the first
When the gate electrode 11 is turned off with a negative potential, the time required for sweeping out carriers can be shortened, and the turn-off time can be shortened. Here, the second MOSFET 14
Has a role of a MOSFET for mode switching that extracts (extracts) majority carriers (holes) from the p-type base layer 4 and shifts from the thyristor operation mode to the operation mode of only the transistor Qpnp. Furthermore, the second
If the gate electrode 11 becomes a negative potential while the gate electrode 12 of the MOS 14 is kept at a negative potential, the first MOSFET 13n
Turns off and the third MOS 13p turns on. That is,
The injection of majority carriers (electrons) into the n ⁻ type base layer 3 is stopped, and in addition to the action of extracting the majority carriers (holes) from the p type base 4 by the second MOS 14, it is formed on the surface of the n type emitter layer 5a. The p-type base layer 4 and the p ⁺ -type emitter layer 6a are connected to each other through the formed inversion layer, so that the majority carriers (holes) of the p-type base 4 are extracted. Therefore, holes remaining in the p-type base layer 4 are rapidly extracted to the emitter electrode 7 by the second MOSFET 14 and the third MOSFET 13p, so that the turn-off time can be further shortened. Here, the third MOSFET 13p extracts holes in the peripheral portion of the p-type base 4, and the second MOS 14 extracts holes in the central portion of the p-type base 4.

FIG. 4 shows gate control potentials applied to the first gate electrode 11 and the second gate electrode 12. As described above, first, when the gate electrodes 11 and 12 are set to a high potential, the device is turned on and exhibits a low on-voltage of about 1.5 V under the thyristor state. And
When a negative potential is applied to the gate electrode 12 with the gate potential 11 kept at a high potential, the state becomes a transistor. If a negative potential is applied to the gate electrode 11 while keeping the gate electrode 12 at a negative potential in this state, the device turns off in a short turn-off time of ˜1.0 μsec. Further, the transition from the thyristor state to the transistor state is completed in 0.5 second or less. In this way, in this device, it is turned on at a low on-voltage like MCT and turned off at a short turn-off time like IGBT. Therefore, FIG.
As shown in, by repeating the thyristor state and the transistor state, it is possible to realize a power device with less switching loss even in high frequency applications.

Next, current flow and carrier density in the thyristor state and the transistor state will be described. FIGS. 5A and 5B show current flow charts in the thyristor state and the transistor state. In the thyristor state (a), the p-type base layer 4, n ⁻
It can be seen that the hole current and the electron current flow integrally from the inside of the base layer 3 of the mold to the emitter electrode 7, and the thyristor mode is achieved. On the other hand, (b)
In the transistor state shown in, the p-type base layer 4
A hole current flows inside, and flows out to the emitter electrode 7 through the MOS 14. Then, it is understood that the electron current flows from the inside of the n ⁻ type base layer 3 to the emitter electrode 7 through the MOS 13n, similarly to the IGBT.

FIG. 6 shows carrier densities in the thyristor state and the transistor state. This figure shows
The results of simulating the density 21 of holes and the density 22 of electrons from the surface of the semiconductor device of this example in which the emitter electrode is installed to the back surface of the semiconductor device in which the collector electrode is installed are shown. In the figure, the vertical axis represents the hole or electron carrier density, and the horizontal axis represents the distance from the surface of the semiconductor device. First, FIG. 6A shows the carrier density in the thyristor state, and the density of both carriers is 10 ¹⁶ to 10 ¹⁷ / cm from the surface of the device to the p-type base layer 4 and the n ⁻ -type base layer 3. ^A large value of ³ is shown. In the p ⁺ -type collector layer 2, which is the back surface of the semiconductor device, the density of holes, which are majority carriers, is 2
1 is increased and the electron density 22 is decreased. On the other hand, in the transistor state shown in FIG.
Near the boundary between the n ^- type base layer 4 and the n ^- type base layer 3
It can be seen that the carrier density has decreased to about 0 ¹⁴ .
As described above, by shifting from the thyristor state to the transistor state, the carrier density inside the device is reduced, so that the turn-off time can be shortened. Therefore, the turn-off time of this device can be shortened similarly to the IGBT.

Next, FIG. 7 shows the result of simulating the on-voltage in this device. Collector current I
When the collector-emitter voltage V _{CE at} which c reaches 200 A / cm ² is the ON voltage Von, Von is ˜1.0 V in the thyristor state, and Von is ˜1.8 V in the transistor state. As described above, by setting the thyristor state when the device is turned on, the on-voltage can be suppressed to be low.

FIG. 8 collectively shows changes in the gate voltages of the gates 11 and 12 relating to the ON operation and the OFF operation of the device, the collector current Ic and the collector-emitter voltage V _CE of the device. .. The operation of the device in each operation is omitted because it has been described in detail above. Indicates voltage. Then, by setting the gate 12 to a negative potential, the thyristor operation shifts to the transistor operation, and the shift is completed in about 0.5 μsec or less.
After that, it is possible to turn off with a short fall time of about 0.3 μsec.

As described above, the device of this example is a completely new device that realizes a thyristor state corresponding to MCT and a transistor state corresponding to IGBT by using the two independent gate electrodes 11 and 12. MCT, IGB
As technologies for improving the performance of devices such as T, there have been high speed and low driving power by MOS gate devices, low on-voltage by thyristor structure, and high performance by combining various device structures. No device has been found that significantly improves the tradeoff between reduction and switching time. However, this device was invented based on a new concept of controlling one device to a suitable state of turning on and off, and has a high performance with a low on-voltage of a thyristor and a short switching time of an IGBT. Power devices can be realized.

By the way, in the element having such a structure, the p-type base layer 4 and the n-type emitter layers 5a and 5b (5) are formed.
It is very important to optimize the distribution of each impurity.
That is, in the thyristor state, the first MOSFET 1
The amount of electrons injected from the n-type emitter layer 5 to the p-type base 4 by turning on 3n greatly depends on the amount of impurities in the p-type base 4 and the n-type emitter layer 5. That is, the electron injection amount increases exponentially by increasing the impurity amount of the n-type emitter layer 5, and the electron inflow amount is greatly suppressed by increasing the impurity amount of the p-type base 4.
Therefore, the n-type emitter layer 5 has a high impurity concentration,
The p-type base 4 can reduce the ON voltage of the thyristor by reducing the amount of impurities. On the other hand, in the transistor state, as shown in FIG. 5B, the hole current flows through the lower portion of the n-type emitter layer 5, so that p
When the impurity concentration of the type base layer 4 is low, the bipolar transistor Qnpn including the n type emitter layer 5, the p type base 4 and the n ⁻ type base 3 is turned on due to the voltage drop due to the parasitic resistance of the p type base layer 4, and the thyristor is turned on. A latch-up phenomenon occurs that shifts to the state. Therefore, when the impurity concentration of the p-type base layer 4 is increased, the latch-up phenomenon in the transistor state can be suppressed. Therefore, the concentrations of the p-type base layer 4 and the n-type emitter layer 5 must be set to optimum values so that the on-voltage in the thyristor state is kept low and the latch-up phenomenon in the transistor state does not occur.

Here, the p-type collector layer 2 having a resistivity of 0.01 Ω · cm and the resistivity of 0.1 Ω · c formed thereon.
m ⁺ 20 μm thick n ⁺ -type buffer layer and epitaxially grown on it 40 Ω · cm thick and 60 μ thick
Using a semiconductor substrate including the n-type layer 4 of m, the device characteristics of the p-type base 4 were evaluated by device simulation. FIG. 9 shows a surface concentration of 1 × 10 ¹⁷ c
m ⁻³ , the on-voltage of the thyristor and the latch-up current of the transistor (controllable current until the latch-up phenomenon occurs) with respect to the dose amount of the p-type base 4 when the n-type emitter layer 5 having a diffusion depth of 1 μm is formed. It is a graph which shows a relationship. The diffusion depth of the p-type base 4 is 8μ.
m. As is clear from this figure, when the dose amount of the p-type base 4 is reduced, the value of the on-voltage V _ON is reduced, but the latch-up current I _L is also reduced, and the latch-up phenomenon easily occurs. Since the latch-up current I _L of the power device needs to be at least 300 Acm ⁻² , the lower limit of the dose amount of the p-type base 4 is 2 × 10.
^{It is 13} cm ^-2 . If the dose amount is larger than this, a sufficient latch-up current can be secured, and a device with a large current capacity can be realized. When the dose amount is large, the on-state voltage V of the thyristor
_ON rises. IGBT on-state voltage is about 1.7V
Considering that, the ON voltage of the device of this example is 1.
When planned to be 5 V, the upper limit of the dose amount of the p-type base 4 is 1 × 10 ¹⁴ cm ^-2 . If the dose amount of the p-type base 4 is 1 × 10 ¹⁴ cm ⁻² , the first MOSFET 13
The threshold voltage of n exceeds 10V and the gate control voltage becomes high, which is not preferable. Therefore, if the dose amount of the p-type base 4 is 2 × 10 ¹³ cm ^-2 or more, it is 1 × 10 ¹⁴ cm.
^By setting it to ^-2 or less, it is possible to realize a device with a large on-current capacity (sufficient latch-up resistance) and a low on-voltage.

FIG. 10 shows a dose amount of 1.25 × 10 ¹³ cm ^-2.
6 is a graph showing the relationship between the dose of the n-type emitter layer 5 and the on-voltage of the thyristor and the latch-up current of the transistor (controllable current until the latch-up phenomenon occurs) when the p-type base 4 of FIG. As is clear from this figure, the ON voltage V _ON becomes high when the dose amount of the n-type emitter layer 5 is small, and the latch-up current I _L becomes small when the dose amount is large. _Turn on voltage V _ON to 1.
When the voltage is 5 V, the dose amount is larger than that of the p-type base layer 4 and needs to be 1.25 × 10 ¹³ cm ⁻² or more, and when the latch-up current I _L is 300 Acm ⁻² , the dose amount is 1 ×. It is required to be 10 ¹⁴ cm ^-2 or less.

If the dose is too large, the second MOS
The threshold voltage of the FET 14 and the third MOSFET 13p exceeds 10V, and the gate control voltage increases, which is not preferable. Therefore, it is necessary to set the dose amount of the n-type emitter layer 5 to 1 × 10 ¹⁴ cm ⁻² or less, which is larger than that of the p-type base layer 4.

[Second Embodiment] FIG. 11 shows a second embodiment of the present invention.
2 shows a configuration of a semiconductor device having a double gate including a first gate and a second gate according to FIG. The configuration and operation of the semiconductor device of the present example are substantially the same as those of the semiconductor device of the first embodiment, and common parts are denoted by the same reference numerals and description thereof is omitted. Also in the semiconductor device of this example, the p ⁺ type substrate having the collector electrode 1 on the back surface is used as the collector layer 2 and the n ⁻ type base layer 3 is formed on the p ⁺ type substrate. A p-type base layer 4 is formed on the surface of the layer 3. An n ⁺ type buffer layer may be interposed between the collector layer 2 and the base layer 3. In the device of this example, the base layer 4 is formed around a slightly deep p ⁺ type well 4a and a p type peripheral layer (channel portion) 4b which is shallower around the well. And
On the inner surface of the p-type base layer 4, n-type emitter layers 5a and 5b and p ⁺ -type emitter layers 6a and 6b are formed as in the first embodiment. The first gate electrode 11 is composed of the first MOSFET 13n and the third MOSFET
ET13p, and the second gate electrode 12 constitutes a second MOS 14. In the device of this example, a counter doping layer 9 doped with n ⁺ type is formed on the surface of the n ⁻ type base layer 3 constituting the MOS 13n in order to shorten the channel length. Then, the MOS1 constituted by the gate electrode 12
On the surface of the p-type base layer 4 below the gate electrode 12, a high-concentration doping layer 10 having p ⁺ -type doping is formed.

In the present device having such a structure, when the first gate electrode 11 and the second gate electrode 12 are set to a high potential, the emitter electrode 7 is connected to the n-type emitter layer 5a,
It is connected to the n ⁺ type accumulation layer on the surface, the n type inversion layer on the surface of the p type base layer 4, the counter doping layer 9, and the n ⁻ type base layer 3. Therefore, when the thyristor 15 is turned on, the counter doping layer 9 can shorten the channel length of the n-channel formed at the time of turning on. That is, since the operation speed of the first MOSFET 13n is improved, the turn-on and turn-off characteristics of this device are improved.

From the thyristor-on state, the second MO
When the gate electrode 12 of S14 is set to a negative potential, the surface of the n-type emitter layer 5a immediately below the gate electrode 12 is inverted to p-type, and the p-type base layer 4 and the p ⁺ -type high-concentration doping layer 1 are formed.
The surface of the 0, n-type emitter layer 5a inverted to p-type, and the p ⁺ -type emitter layer 6b are short-circuited. As a result, the thyristor operation disappears, and a transistor state in which only the transistor Qpnp including the p-type base layer 4, the n ⁻ -type base layer 3 and the p ⁺ -type collector layer 2 which are the same as the operation state of the IGBT is activated. Further, in the device of this example, since the p ⁺ -type high-concentration doping layer 10 is formed, a large hole current can be passed when the thyristor state is changed to the transistor state. That is, the second
Since the hole extracting ability of the MOSFET 14 is improved, the transition time from the thyristor state to the transistor state is shortened.

The reason for forming the p ⁺ type well 4a is as follows. That is, by providing the p ⁺ type well 4a, the latch-up current value during transistor operation can be increased, and the controllable current can be increased. However,
If the dose amount is too large, the on-voltage of the thyristor rises, so the dose amount needs to be optimized.
Here, the dose amount is examined for the case where the p ⁺ type well 4a is formed by diffusion from the surface and the case where the p ⁺ type well 4a is formed for the buried type. First, the case of diffusing from the surface to form the p ⁺ type well 4a will be examined. FIG. 12 shows the latch-up current of a transistor with respect to the dose amount of a p ⁺ -type well formed by surface diffusion when a p-type peripheral layer (channel portion) having a diffusion depth of 6 μm is formed (up to the occurrence of the latch-up phenomenon. It is a graph which shows the relationship of controllable current. The diffusion depth X _j of the p ⁺ type well is used as a parameter, and the star mark in the figure indicates the value when the p ⁺ type well is not formed. As is clear from this figure, the latch-up current I _L also rises as the dose amount increases, regardless of the value of the diffusion depth X _j . Since the latch-up current I _L when the p ⁺ type well is not formed is about 300 Acm ^−2, it is 1 × 10 ¹³ c.
A sufficient latch-up resistance can be obtained with a dose amount of m ^-2 or more. On the other hand, FIG. 13 is a graph showing the relationship between the on-voltage of the thyristor and the dose amount of the p ⁺ -type well formed by surface diffusion when the p-type peripheral layer (channel portion) having a diffusion depth of 6 μm is formed. is there. At X _j = 8 μm, the on-voltage V _ON rises as the dose increases, but since the rate of change is small, it does not pose a problem. Therefore, the upper limit of the dose may be determined from the productivity such as the ion implantation time, and the realistic upper limit is 5
× 10 ¹⁵ cm ^-2 is desirable. Therefore, the dose amount of the p ⁺ type well is preferably 1 × 10 ¹³ cm ⁻² or more and 5 × 10 ¹⁵ cm ⁻² or less.

Next, the case where the p ⁺ type well 4a is formed as a buried type will be examined. FIG. 14 is a graph showing the relationship between the dose of a p ⁺ type well formed as a buried type and the on-voltage of the thyristor and the latch-up current of the transistor (controllable current until the latch-up phenomenon occurs). As is clear from this figure, the latch-up current I _L rises as the dose amount increases. When the dose amount is 1 × 10 ¹² cm ^-2 , the latch-up current I _L is about 350 Acm ^-2 , and a sufficient latch-up resistance is obtained. The on-voltage V _ON also rises due to the increase in the dose amount, and the on-voltage V _ON at the dose amount 3 × 10 ¹⁴ cm ^-2.
_ON is about 1.5v. Therefore, when the p ⁺ type well 4a is formed as an embedded type, the dose amount is preferably set to 1 × 10 ¹² cm ⁻² or more and 3 × 10 ¹⁴ cm ⁻² or less.

Here, the optimum position of the diffusion window when the p ⁺ type well 4a is formed as a buried type will be determined. First, as shown in FIG. 15, the central point of the first gate electrode 11 is the origin and the central point of the second gate electrode 12 is 25 μm. The edge of the diffusion window is X. FIG. 16 is a graph showing the relationship between the thyristor ON voltage and the transistor latch-up current (controllable current until the latch-up phenomenon occurs) with respect to the edge position X of the diffusion window. The latch-up current I _L becomes higher as the edge position X of the diffusion window becomes closer to the gate electrode 11, but the ON voltage V _ON also rises accordingly. ON voltage V _ON is 1.5V
Then, X = 16 μm, and the edge position of the diffusion window is p
It is on the inner edge of the ⁺ type emitter layer 6a. Therefore, 1.
In order to obtain a large controllable current while keeping the ON voltage of 5 V or less, the edge of the diffusion window needs to be located closer to the gate electrode 12 than the inner edge of the p ⁺ -type emitter layer 6a.

[Embodiment 3] FIG. 17 shows a structure of a semiconductor device having a double gate of a first gate and a second gate according to Embodiment 3 of the present invention. The configuration and operation of the semiconductor device of the present example are substantially the same as those of the semiconductor device of the second embodiment, and common parts are denoted by the same reference numerals and description thereof is omitted. A p-type base layer 4 is formed on the surface of the n-type base layer 3. The base layer 4 is composed of a deep p ⁺ type well layer 4a formed by diffusion or burying, and a p type peripheral layer (channel portion) 4b around the deep well layer 4a, which is shallower than the well layer 4a. Then, on the inner surface of the p-type base layer 4, n-type emitter layers 5a and 5b and p ⁺ -type emitter layers 6a and 6b are formed as in the second embodiment. The first gate electrode 11 is the first
And the second MOSFET 13n and the third MOSFET 13p, and the second gate electrode 12 is the second MOS1.
Make up 4. In this example, the n-type emitter layers 5a and 5b are deep n ⁺ -type well layers 5a and 5b, and an n-type peripheral layer 5a that is shallower around the well layers 5a and 5b.
b and 5bb. By forming the n-type emitter layers 5a and 5b having such a structure, it is possible to obtain a high latch-up current and a low on-voltage as described below.

As in the first and second embodiments, the n-type emitter layers 5a and 5b are the second MOSFET 14 and the third MO.
Since the channel region of the SFET 13p is formed, M
In order to lower the threshold voltage of OS and obtain a high latch-up current, it is necessary to lower the concentration of the n-type emitter layers 5a and 5b to some extent, while to reduce the on-voltage during thyristor operation, n-type is required. It is necessary to increase the concentration of the emitter layers 5a and 5b to a certain extent. In Example 1, the concentrations of the n-type emitter layers 5a and 5b were set to optimum values so as to satisfy both of these characteristics. However, as in this example, the deep n ⁺ type well layers 5a and 5b and the shallow n type peripheral layers 5ab and 5bb can always satisfy both characteristics. That is, the deep n ⁺ type well layers 5a and 5b
The ON voltage during thyristor operation can be lowered by the thyristor operation, and the shallow n-type peripheral layers 5ab and 5bb reduce the surface concentration, so that a high latch-up current can be obtained. Further, in order to obtain a good ohmic contact with the emitter electrode 7, the presence of the n ⁺ type well layers 5a and 5b is significant.

[0040] Figure 18 is latch-up current (latch-up phenomenon of the ON voltage and the transistor of the thyristor to the surface concentration of the n ⁺ -type well layer occur in the case of forming the well layer of n ⁺ -type diffusion depth 1.5μm FIG. 4 is a graph showing a relationship of (controllable current up to). As is clear from this figure, in order to keep the latch-up current I _L large and reduce the on-voltage V _ON (1.5 V or less), n ⁺
The surface concentration of the well layer of the mold must be 5 × 10 ¹⁷ cm ⁻³ or more. The upper limit of the surface concentration is difficult and is not necessary in order to ^attain a high concentration of 5 × 10 ²⁰ cm ⁻³ or more as compared with the current semiconductor process technology. Therefore, it is desirable that the surface concentration of the n ⁺ type well layer be 5 × 10 ¹⁷ cm ⁻³ or more and 5 × 10 ²⁰ cm ⁻³ or less.

FIG. 19 shows the surface concentration of the n ⁺ type well layer as 1.
× 10 ¹⁹ cm ⁻³ and the diffusion depth of the n-type peripheral portion is 0.6.
FIG. 7 is a graph showing the relationship between the on-voltage of the thyristor and the latch-up current of the transistor (controllable current until the latch-up phenomenon occurs) with respect to the diffusion depth of the n ⁺ type well layer fixed to μm. As you can see from this figure,
When the diffusion depth of the n ⁺ type well layer approaches the diffusion depth of the n type peripheral portion (channel portion), the ON voltage V _{ON of the} thyristor is turned on.
Rises. The diffusion depth of the n ⁺ type well layer is 1.5.
The latch-up current I _L decreases substantially linearly when the thickness is more than μm. If the latch-up current I _L needs to be at least about 300 Acm ⁻² , the diffusion depth of the n ⁺ type well layer must be greater than the diffusion depth of the n type peripheral portion (channel portion) and not more than 1.9 μm. There is.

Next, as shown in FIG. 20, optimum values of the gate length L _{g1 of} the first gate electrode 11, the gate length L _{g2 of} the second gate electrode 12 and the contact length L _E of the emitter electrode 7 are obtained. .. FIG. 21 is a graph showing the relationship between the gate length L _{g1 and the} gate-up voltage L _g1 in the case of a transistor and the on-voltage of the transistor when the gate length L _g2 is 4 μm. As is clear from this figure, L _g1 / 2 is 10
Since the on-voltage V _{ON of the} transistor is about 7 V when μm, the on-voltage is too high for practical use with a gate length shorter than this. On the other hand, when the gate length L _g1 increases, the on-voltage decreases and the latch-up current also decreases. If the latch-up current I _L requires about 300 Acm ^-2 , L
_g1 / 2 must be 15 μm or less. Therefore, the first
Gate electrode 11 has a gate length L _g1 of 20 μm or more and 30
It is desirable to set to less than μm. The transistor does not turn on when the thickness is 8 μm or less.

FIG. 22 is a graph showing the relationship between the gate length L _g2 when the gate length L _g1 is 15 μm and the latch-up current in the transistor and the on-voltage in the thyristor. In such a case, the p-type base 4b
Has a surface concentration of 3 × 10 ¹⁷ and a diffusion depth of 8 μm.
The type emitter layer 5ab has a surface concentration of 5 × 10 ¹⁷ and a diffusion depth of 1
μm. Furthermore, the counter doping layer as shown in Example 2 is formed. As is clear from this figure, when L _g2 / 2 is 4 μm or less, the latch-up current I _L
Is over 300 Acm ^-2 . On the other hand, when L _g2 is reduced, the on-voltage V _ON is reduced, so that the lower limit of the gate length does not matter. However, since sub-micron size fine processing is disadvantageous in terms of cost, etc., 1 μm is an appropriate lower limit. Therefore, the gate L _g2 of the second gate electrode 12 is preferably 1 μm or more and 8 μm or less.

FIG. 23 is a graph showing the relationship between the contact length L _E of the emitter electrode 7 and the latch-up current in the transistor and the on-voltage in the thyristor. The surface concentration of the p-type base 4b is 2.7 × 10 ¹⁶ here.
And the diffusion depth is 6 μm, the surface concentration of the n-type emitter layer 5ab is 1.0 × 10 ¹⁷ cm ⁻² , the diffusion depth is 1.0 μm, and the surface concentration of the n ⁺ type well layer 5a is 1.0 × 10 ¹⁹ cm ^−2. And the diffusion depth is 1.5 μm. As is clear from this figure, as the contact length L _E increases, the latch-up current I _L decreases. Since the latch-up current I _L is about 300 Acm ⁻² when L _E is 6 μm, it is desirable to set the upper limit value to 6 μm. Although the lower limit is not limited, submicron size fine processing is disadvantageous in terms of cost and the like, so 1 μm is appropriate as a tentative lower limit. Therefore, the contact length L _E of the emitter electrode 7 is preferably 1 μm or more and 6 μm or less.

Although the present embodiment and the first embodiment are described based on a vertical device in which the emitter electrode and the collector electrode are installed on the front surface and the back surface of the device, the emitter electrode and the collector electrode are on the same surface. Needless to say, this can be realized even in the installed horizontal device. Further, a substrate having a conductivity type opposite to that of the semiconductor substrate in the above embodiment may be used. Further, the configurations of the base layers, the emitter layers, etc. are not limited to those in the above embodiment, and various configurations can be adopted. It goes without saying that various configurations can be adopted for the first and second MOSs as well.

[0046]

As described above, the semiconductor device according to the present invention is a two-terminal control power device using the first MISFET and the second MISFET for mode switching which can be opened and closed independently of the first MISFET. Therefore, a low ON voltage similar to that of a thyristor is turned on when turned on, and a thyristor operation is switched to a transistor operation when turned off.
The same short turn-off time as T can be realized. Therefore, it is possible to greatly improve the trade-off between the switching time and the on-state voltage, which was not possible with the conventional power semiconductor devices such as MCT, IGBT and GTO. For example, a turn-off time of 1 μsec or less, a fall time of 0.3 μsec or less, and an on-voltage of 1.0 V / 300 A / cm ² can be sufficiently realized. Therefore, with this device, medium, high current, and
It is possible to significantly improve the performance of power devices used in middle and high breakdown voltage devices and circuits. In addition, the frequency band is ~ 1
Since it is possible to cover up to the 00 kHz level, it is possible to significantly reduce the loss even in high frequency applications. As described above, by adopting the semiconductor device according to the present invention, it is possible to realize low loss and downsizing of various devices which have been recently demanded particularly from the viewpoint of power saving.

[Brief description of drawings]

FIG. 1 is a sectional view showing a configuration of a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a plan view showing the configuration of the semiconductor device according to the first embodiment.

FIG. 3 is a circuit diagram showing an equivalent circuit of the semiconductor device according to the first embodiment.

FIG. 4 is an explanatory diagram showing an operating state of the semiconductor device according to the first embodiment.

5A is a sectional view showing a current flow in a thyristor state in the semiconductor device according to the first embodiment, and FIG. 5B is a sectional view showing a current flow in a transistor state in the semiconductor device according to the first embodiment. It is a figure.

FIG. 6A is a graph showing a state of carrier density in a thyristor state in the semiconductor device according to the first embodiment;
FIG. 6B is a graph showing a carrier density state in a transistor state in the semiconductor device according to the first embodiment.

FIG. 7 is a graph showing an on-voltage of the semiconductor device according to the first embodiment.

FIG. 8 is a graph showing switching characteristics of the semiconductor device according to the first embodiment.

FIG. 9 is a graph showing a relationship between an ON voltage of a thyristor and a latch-up current of a transistor with respect to a dose amount of a p-type base in the semiconductor device according to the first embodiment.

FIG. 10 is a graph showing a relationship between the ON voltage of the thyristor and the latch-up current of the transistor with respect to the dose amount of the n-type emitter layer in the semiconductor device according to the first embodiment.

FIG. 11 is a sectional view showing a configuration of a semiconductor device according to a second embodiment of the invention.

FIG. 12 is a graph showing a relationship between a dose amount of a p ⁺ type well formed by surface diffusion and a latch-up current of a transistor in the semiconductor device according to the second embodiment.

FIG. 13 is a graph showing the relationship between the ON voltage of the thyristor and the dose amount of the p ⁺ type well formed by surface diffusion in the semiconductor device according to the second embodiment.

FIG. 14 is a graph showing a relationship between a dose amount of a p ⁺ type well formed as a buried type and a turn-on voltage of a thyristor and a latch-up current of a transistor in the semiconductor device according to the second embodiment.

FIG. 15 is a cross-sectional view showing a relative relationship between an edge position X of a diffusion window of a p ⁺ type well formed as a buried type and a P gate electrode in the semiconductor device according to the second embodiment.

FIG. 16 is a graph showing the relationship between the on-voltage of the thyristor and the latch-up current of the transistor with respect to the edge position X of the diffusion window in the semiconductor device according to the second embodiment.

FIG. 17 is a sectional view showing a configuration of a semiconductor device according to a third embodiment of the present invention.

FIG. 18 is a graph showing the relationship between the surface concentration of the n ⁺ type well layer and the on-voltage of the thyristor and the latch-up current of the transistor in the semiconductor device according to the third embodiment.

FIG. 19 is a graph showing the relationship between the on-voltage of the thyristor and the latch-up current of the transistor with respect to the diffusion depth of the n ⁺ type well layer in the semiconductor device according to the third embodiment.

FIG. 20 is a cross-sectional view showing the gate length L _g1 of the first gate electrode, the gate length L _g2 of the second gate electrode, and the contact length L _E of the emitter electrode in the semiconductor device according to the third embodiment. Find the optimum value of.

FIG. 21 is a graph showing a relationship between a gate-up length L _g1 and a latch-up current in a transistor and an on-voltage in a transistor in the semiconductor device according to the third embodiment.

FIG. 22 is a graph showing the relationship between the gate length L _g2 and the latch-up current in the transistor and the on-voltage in the thyristor with respect to the gate length L _g2 in the semiconductor device according to the third embodiment.

FIG. 23 is a graph showing the relationship between the contact length L _E of the emitter electrode and the latch-up current in the transistor and the on-voltage in the thyristor in the semiconductor device according to the third embodiment.

FIG. 24 is a cross-sectional view showing an example of the structure of an MCT.

FIG. 25 is a circuit diagram showing an equivalent circuit of the MCT.

FIG. 26 is a graph showing a carrier density of the MCT.

FIG. 27 is a cross-sectional view showing an example of the structure of an IGBT.

FIG. 28 is a waveform diagram showing a turn-off waveform of the same IGBT.

[Explanation of symbols]

1 ... a collector electrode 2, ... p ⁺ -type collector layer 3, ... n ^- -type base layer 4 ... p-type base layer 5, ... n-type emitter layer 6 ... p ⁺ Type emitter layer 7 ... Emitter electrode 8 ... Gate oxide film 9 ... N ⁺ type counter-doping layer 10 ... P ⁺ type high-concentration doping layer 11 ... First gate electrode 12・ ・ ・ Second gate electrode 13 ・ ・ ・ First MOS 14 ・ ・ ・ Second MOS 15 ・ ・ ・ Thyristor 21 ・ ・ ・ Density of holes 22 ・ ・ ・ Density of electrons 60 ・ ・ ・ MCT 61・ ・ ・ Gate electrode 62 ・ ・ ・ MOS 63 ・ ・ ・ Cathode electrode 64 ・ ・ ・ n ⁺ type cathode layer 65 ・ ・ ・ p ⁻ type base layer 66 ・ ・ ・ n type base layer 67 ・ ・ ・ p ⁺ -type anode layer 68 ... anode electrode 81 ... p ⁺ -type Substrate 82 ... n ^- -type base layer 83 ... p-type channel layer 84, ... n ⁺ -type emitter layer 85 ... p ⁺ -type well 86 ... gate oxide film 87 ...・ Gate electrode 88 ・ ・ ・ Emitter electrode 89 ・ ・ ・ Collector electrode

Claims (19)

[Claims] 1. A semiconductor device having a thyristor structure composed of a collector region of a first conductivity type, a base region of a second conductivity type, a base region of a first conductivity type and an emitter region of a second conductivity type. A first MISFET capable of injecting the majority carriers into the base region;
2. A semiconductor device comprising: a second MISFET which can be opened and closed independently of the second MISFET and which can extract majority carriers from the first conductivity type base region. 2. The second MISF according to claim 1.
In addition to ET, a semiconductor device having a third MISFET capable of extracting majority carriers from the first conductivity type base region and having a common gate electrode of the first MISFET. 3. The second electric field structure according to claim 2, wherein an emitter potential is applied together in the first conductivity type base region.
A semiconductor device comprising a conductive type emitter region and a first conductive type emitter region. 4. The semiconductor device according to claim 3, wherein the first conductive type emitter region is formed in the second conductive type emitter region. 5. The second MISF according to claim 4,
The second gate electrode of ET is formed on the surfaces of the first conductivity type emitter region and the second conductivity type emitter region and the first conductivity type base region via a gate insulating film. Characteristic semiconductor device. 6. The common first gate electrode of the first MISFET and the third MISFET according to claim 4 or 5, wherein the common first gate electrode extends from the first emitter region to the second conductivity type emitter region. A semiconductor device formed on the surfaces of the first conductivity type base region and the second conductivity type base region via a gate insulating film. 7. The dose amount of the first conductivity type base region according to claim 6, wherein the dose amount is 2 × 10 ¹³ cm ⁻² or more and 1 × 10.
¹⁴ cm ⁻² or less, and the dose amount of the second conductivity type emitter region is equal to or more than the dose amount of the first conductivity type base region.
A semiconductor device having a ^{density of} × 10 ¹⁴ cm ^-2 or less. 8. The semiconductor device according to claim 6 or 7, wherein the first-conductivity-type base region has a first-conductivity-type high-concentration well and a first-conductivity-type peripheral region shallower than the well. .. 9. The dose amount of the first conductivity type high concentration well formed by surface diffusion according to claim 8, wherein the dose amount is 1 ×.
A semiconductor device having a size of 10 ¹³ cm ^-2 or more and 5 × 10 ¹⁵ cm ^-2 or less. 10. The dose amount of the high-concentration well of the first conductivity type formed as the buried type according to claim 8,
A semiconductor device having a ^{density of not} less than × 10 ¹² cm ^{-2 and not} more than 3 × 10 ¹⁴ cm ^-2 . 11. A second gate electrode of the second MISFET according to claim 10, wherein an edge of a diffusion window of the first-conductivity-type high-concentration well is located inside an inner edge of the first-conductivity-type emitter region. A semiconductor device characterized by being located on the side. 12. A semiconductor device according to claim 6, wherein the second conductive type emitter region has a second conductive type high concentration well and a second conductive type peripheral portion shallower than the well. .. 13. The surface concentration of the second-conductivity-type high-concentration well according to claim 12, which is 5 × 10 ¹⁷ cm ⁻³ or more.
A semiconductor device characterized by having a ^{density of} 10 ²⁰ cm ^-3 or less. 14. The diffusion depth of the second-conductivity-type high-concentration well according to claim 12 or 13, which is greater than or equal to the diffusion depth of the second-conductivity-type peripheral portion and not greater than 1.9 μm. Semiconductor device. 15. The gate length of the first gate electrode according to claim 12, wherein the first gate electrode has a gate length of 20 μm.
A semiconductor device having a thickness of at least m and at most 30 μm. 16. The gate length of the second gate electrode according to claim 12, wherein the second gate electrode has a gate length of 1 μm.
A semiconductor device having a thickness of 8 μm or less. 17. The contact length of an emitter electrode conductively contacting the first conductive type emitter region and the second conductive type emitter region according to claim 12, wherein the contact length is 1 μm or more and 6 μm or less. There is a semiconductor device. 18. The shallow counter-doping region of the second conductivity type according to claim 6, wherein a surface of the base region of the first conductivity type of the first MISFET is formed. A semiconductor device characterized by: 19. The high-concentration doping region of the first conductivity type according to claim 6, wherein a surface of the first conductivity type base region of the second MISFET is formed. A semiconductor device characterized by the above.