WO2015180150A1 - 多机变频器产生同步信号方法和多机变频器 - Google Patents

多机变频器产生同步信号方法和多机变频器 Download PDF

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Publication number
WO2015180150A1
WO2015180150A1 PCT/CN2014/078966 CN2014078966W WO2015180150A1 WO 2015180150 A1 WO2015180150 A1 WO 2015180150A1 CN 2014078966 W CN2014078966 W CN 2014078966W WO 2015180150 A1 WO2015180150 A1 WO 2015180150A1
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Prior art keywords
unit
execution
clock
control unit
main control
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PCT/CN2014/078966
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English (en)
French (fr)
Inventor
柯冬生
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深圳市英威腾电气股份有限公司
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Application filed by 深圳市英威腾电气股份有限公司 filed Critical 深圳市英威腾电气股份有限公司
Priority to CN201480019850.4A priority Critical patent/CN105612465A/zh
Priority to PCT/CN2014/078966 priority patent/WO2015180150A1/zh
Publication of WO2015180150A1 publication Critical patent/WO2015180150A1/zh

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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B19/00—Programme-control systems
    • G05B19/02—Programme-control systems electric
    • G05B19/04—Programme control other than numerical control, i.e. in sequence controllers or logic controllers
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J3/00—Circuit arrangements for ac mains or ac distribution networks
    • H02J3/38—Arrangements for parallely feeding a single network by two or more generators, converters or transformers
    • H02J3/40—Synchronising a generator for connection to a network or to another generator

Definitions

  • the invention mainly relates to the field of power electronics technology, and particularly relates to a method for generating a synchronization signal by a multi-machine frequency converter and a multi-machine frequency converter. Background technique
  • the single-unit inverters use a control unit to directly control an inverter unit.
  • the control unit generally does not control the rectifier unit.
  • the specific structure can be as shown in Figure 1-a.
  • the single-machine inverter should be operated synchronously (ie, the speed/torque of the load motor of at least two single-machine inverters is the same or the output of the corresponding or at least two single-machine inverters is connected in parallel with the load motor or asynchronous to realize the factory macro)
  • At least two single-machine inverters form a multi-machine system of the inverter, and each inverter is based on the RS485 bus communication mode.
  • the structure of the 485 bus communication mode is shown in Figure 1-b.
  • the console transmits the system running frequency to each inverter through the 485 bus.
  • Each inverter transmits the status feedback information to the console through the bus.
  • the system gives the shutdown signal and the torque signal sent by the main inverter to the slave inverter through a separate signal line connection.
  • the embodiment of the invention provides a method for generating a synchronization signal of a multi-machine frequency converter and a multi-machine frequency converter, in order to improve the synchronous running performance of the frequency converter.
  • a multi-machine frequency converter generates a synchronization signal
  • the multi-machine frequency converter includes a main control unit and M1 controllable execution units to be synchronized, the M1 execution units share a common DC bus, and the M1 is greater than 1.
  • the main control unit initializes related parameters of the M1 execution units, and after the initialization of the parameter initialization package parameters is completed, the main control unit sends initialization data to the M1 execution orders. And configuring a related register for synchronously transmitting data, activating a synchronous clock unit of the execution unit, and causing the execution unit to generate a synchronization signal.
  • the distributed clock initialization includes a transmission delay calculation, a system clock offset compensation, a static clock compensation, and a dynamic clock compensation, and each execution unit uses a phase-locked loop technology to make its own system clock consistent with a selected reference clock. .
  • the distributed clock initialization specifically includes: the main control unit periodically sends a reference clock to each execution unit; and calculates a time compensation value corresponding to each execution unit, corresponding thereto After the time compensation value, time offset compensation is performed on the local system clock by using the received time compensation value, and the currently received reference clock and the time offset compensation are performed based on the phase locked loop.
  • the local system clock is step locked.
  • the time compensation value corresponding to the execution unit is obtained by using a time offset value and a delay value, where the time deviation value is a deviation between a local system clock of the execution unit and a reference clock, and the delay value is The transmission delay value between the execution unit and the main control unit.
  • the method further includes:
  • the main control unit reads the data of the M1 execution units and determines whether the synchronization is successful. If the main control unit reads the data of the M1 execution units and determines whether the synchronization is successful, the main control unit includes: The main control unit reads the system clock deviation register of each execution unit to determine whether the synchronization is successful, and the system clock deviation register of the execution unit records the current time deviation of the local system clock and the reference clock in the distributed clock initialization.
  • the reference clock is a system clock of the main control unit, or is a system clock of any one of the M1 execution units.
  • the M1 controllable execution units to be synchronized include a Mil controllable rectification unit that needs to be synchronized, and M12 inverter units that need to be synchronized, where the Mil and M12 are integers greater than 1, the different or different .
  • the multi-machine frequency converter includes an uncontrolled rectification unit, and the M1 controllable functions that need to be synchronized
  • the row unit includes Mil controllable rectification units that need to be synchronized, and then the rectified reference clock of the Mil controllable rectification units that need to be synchronized is the system clock of the uncontrolled rectification unit.
  • a multi-machine frequency converter includes a main control unit and M1 controllable execution units to be synchronized, the M1 execution units have a common DC mother, and the M1 is an integer greater than 1;
  • a method of generating a synchronization signal in a multi-machine frequency converter is a method of generating a synchronization signal by a multi-machine frequency converter according to any one of claims 1 to 9.
  • Figure 1-a is a schematic diagram of a stand-alone frequency converter provided by the prior art
  • Figure 1-b is a parallel diagram of a plurality of single-machine frequency converters provided by the prior art
  • FIG. 2-a is a schematic diagram of a multi-machine frequency converter according to an embodiment of the present invention.
  • FIG. 2 is a schematic diagram of another multi-machine frequency converter according to an embodiment of the present invention.
  • 2-c is a schematic diagram of another multi-machine frequency converter according to an embodiment of the present invention.
  • FIG. 3 is a schematic diagram of another multi-machine frequency converter according to an embodiment of the present invention.
  • FIG. 4 is a schematic flow chart of a method for generating a synchronization signal by a multi-machine frequency converter according to an embodiment of the present invention
  • FIG. 5 - a is a schematic diagram of another multi-machine frequency converter according to an embodiment of the present invention.
  • Figure 5 - b is a schematic diagram of another multi-machine frequency converter according to an embodiment of the present invention.
  • FIG. 5 - c is a schematic diagram of another multi-machine frequency converter according to an embodiment of the present invention. detailed description
  • the embodiment of the invention provides a method for generating a synchronization signal of a multi-machine frequency converter and a multi-machine frequency converter, in order to improve the synchronous running performance of the frequency converter.
  • the present invention provides a method for generating a synchronization signal by a multi-machine frequency converter.
  • the multi-machine frequency converter includes a main control unit and M1 controllable execution units to be synchronized, and the M1 execution units have a common DC bus.
  • the M1 is an integer greater than one.
  • the main control unit can read the number of execution units and the networking situation of the communication unit connected to the main control unit before initializing the related parameters of the M1 synchronization execution units.
  • the execution unit communicatively coupled to the main control unit is an execution unit capable of communicating with the main control unit.
  • the N1 execution units shown in FIG. 2-a are execution units communicatively coupled to the main control unit.
  • M1 execution units to be synchronized are some or all execution units communicatively connected with the main control unit.
  • the main control unit sends initialization data to the M1 execution units, activates a synchronous clock unit of the execution unit, and causes the execution unit to generate a synchronization signal.
  • the multi-machine frequency converter includes a main control unit, at least one rectifying unit, and at least two inverter units, and the inverter unit outputs a load-bearing motor; from the viewpoint of whether the rectifying unit and the inverter unit are controllable, the multi-machine
  • the frequency converter includes a main control unit and has M1 controllable execution units that need to be synchronized, and the M1 is an integer greater than one.
  • the execution unit is a rectification unit or an inverter unit
  • the switching device that implements power conversion in the controllable execution unit is a controllable device, such as an IGBT, a MOSFET, etc., and accordingly, the power conversion is implemented in the uncontrollable execution unit.
  • the switching device is an uncontrollable device such as a diode.
  • the controllable execution unit that needs to be synchronized includes a controllable rectification unit that is operated by a plurality of parallel machines to achieve power expansion, and/or a plurality of controllable inverter units that need to perform parallel operation, such as at least two inverses
  • the variable load motor implements the factory macro.
  • some or all of the rectifying units in the multi-machine frequency converter may be controllable rectifying units that can be controlled by the main control unit, or may be uncontrollable rectifying units that are not controlled by the main control unit, but in a multi-machine frequency converter
  • the rectifier unit must be operated synchronously.
  • the structure of the multi-machine inverter will be exemplified below with reference to the accompanying drawings.
  • FIG. 2-a is a schematic structural diagram of a multi-machine frequency converter according to an embodiment of the present invention.
  • a multi-machine frequency converter provided by an embodiment of the present invention may include:
  • the main control unit 201 and the N1 execution units 202 connected in series through the communication port, the N1 execution unit common DC bus 210.
  • the first communication port P1 of the main control unit 201 is connected to the second communication port P0 of the first execution unit among the N1 execution units 202.
  • the first execution unit is an execution unit at one end edge position among the above-mentioned N1 execution units connected in series through the communication port (wherein, in the example architecture of FIG. 2-a, one end edge position of the N1 execution units after the series connection is remaining The first execution unit of the second communication port P0, and the other end edge position is the second execution unit of the remaining first communication port P1).
  • the execution unit 202 is a rectification unit or an inverter unit, wherein the N1 execution units 202 include a total of Nil rectification units and N12 inverter units, and the Nil is a positive integer, and the N12 is greater than 1. A positive integer.
  • each execution unit 202 in FIG. 2-a includes two communication ports (communication port P0 and communication port P1).
  • the functions of the two communication ports may be the same or similar, and in some scenarios, the two communication The ports are interchangeable.
  • the communication port P0 and the communication port P1 of each of the execution units in the intermediate position in the N1 execution units 202 are connected to the other execution units 202, respectively, to realize the concatenation of the N1 execution units 202.
  • the main control unit 201 can send a command word, a data word (for example, a data word including a pulse width modulation (PWM), such as a voltage angle and a voltage modulation ratio) and/or a state through the first communication port P1. Words, etc.
  • the first execution unit can receive the command word, data word and/or status word from the main control unit 201 through its second communication port P0, and the first execution unit can be forwarded through its first communication port P1 (for The transparently transmitted data can be directly forwarded, and the data to be processed can be forwarded after processing) the received command word, data reception command word, data word and/or status word from the main control unit 201.
  • PWM pulse width modulation
  • the "forwarding" in the embodiments of the present invention may be that the received data is directly forwarded without modification, or may be forwarded after the received data is correspondingly repaired, for example, for the received command.
  • the transparently transceivable content of the word, data word and/or status word can be directly forwarded without modification, and the content of the received command word, data word and/or status word cannot be transparently transmitted. It is forwarded after modification.
  • the N1 execution units 202 may generate a synchronization signal according to information such as a reference clock and a time compensation value sent by the main control unit; and may also be based on a command word and a data word from the main control unit 201 (eg, including a voltage angle and a voltage modulation ratio, etc.) The data word of the PWM wave key data) and/or the status word are correspondingly operated.
  • the N1 execution units 202 can enter a state of power-on startup or hibernation according to a command word from the main control unit 201.
  • the N1 execution units 202 may generate synchronized pulse width modulated waves according to data words from the main control unit 201 including PWM voltage key data such as voltage angle and voltage modulation ratio; and use the generated pulse width wave to drive the motor to operate.
  • the main control unit 201 further includes a second communication port P0, and the main control unit 201 can transmit a command word, a data word, and/or a status word or the like through the second communication port P0.
  • the second communication port P0 of the main control unit 201 may also be connected to the first communication port P1 of the second execution unit of the N1 execution units 202.
  • the main control unit 201 can send a command word, a data word, and/or a status word to each execution unit 202 through the second communication port P0 and/or the first communication port P1, which is equivalent to providing two
  • the communication channel for transmitting information and the introduction of the communication loop enable the communication channel between the units to have a redundant backup function, and the anti-fault and fault tolerance capabilities are enhanced, which is beneficial to further improve the stability and reliability of the system operation.
  • the multi-machine frequency converter may further include N2 execution units 203 connected in series through a communication port, wherein the N2 execution units 203 share a common DC bus 210.
  • the second communication port P0 of the main control unit 201 is connected to the first communication port P1 of the third execution unit among the N2 execution units 203 connected in series through the communication port, wherein the N2 is a positive integer, and the N2 is
  • the execution unit includes a rectification unit and/or an inverter unit, wherein the third execution unit is an execution unit at one end edge position among the N2 execution units 203 connected in series through the communication port.
  • main control unit 201 includes two communication ports, both of which are connected to the communication port of the execution unit, and the main difference from the architecture shown in FIG. 2-b is that the main control unit A communication loop is not formed between the 201 and the execution unit.
  • the main control unit 201 can also include more communication ports, and each communication port of the main control unit 201 can be connected to the communication port of the execution unit in the manner shown in Figure 2-c.
  • the rectifying unit and the inverter unit may be staggered with each other.
  • the rectifying unit and the inverting unit may not be staggered with each other.
  • the communication port of the execution unit and the control unit may be a fiber optic communication port or an Ethernet communication port or a level signal communication port or a differential communication interface or other type of communication port.
  • FIG. 3 is a schematic structural diagram of another multi-machine frequency converter according to another embodiment of the present invention.
  • the multi-machine inverter includes:
  • the N3 execution units and the N4 execution units share a common DC bus 310.
  • the first communication port P1 of the main control unit 301 is connected to the second communication port P0 of the sixth execution unit of the N3 execution units connected in series through the communication port, and the second communication port P0 and the pass of the main control unit are The first communication port P1 of the seventh execution unit of the above-described N4 execution units connected in series with the communication port is connected.
  • the N3 execution units and the N4 execution units include XI rectification units and X2 inverter units, wherein the XI is a positive integer, the X2 is a positive integer greater than 1, and the sixth execution unit passes An execution unit at one end edge position among the above-mentioned N3 execution units connected in series with the communication port, wherein the seventh execution unit is an execution unit at one end edge position among the N4 execution units connected in series through the communication port.
  • N3 and N4 are positive integers, and the sum of N3 and N4 is greater than or equal to 3.
  • the N3 execution units and the N4 execution units located on both sides of the main control unit 301 are included in the architecture shown in FIG. 3 of the embodiment.
  • XI rectifying units and X2 inverter units that is, at least one inverter unit can be respectively disposed on both sides of the main control unit 301, and in the architecture shown in FIG. 2-a, one side of the main control unit 301 is At least two inverter units and at least one rectifier unit are deployed (N1 execution units 202 include a total of Nil rectifier units and N12 inverter units).
  • the main control unit 301 can send a command word, a data word, and/or a status word to the N3 execution units 302 and the N4 execution units 303 through the first communication port P1 and the second communication port P0, respectively, and specifically send and forward.
  • the process is similar to the previous part and will not be described here.
  • the rectifying unit and the inverter unit can be staggered with each other.
  • the rectifying unit and the inverting unit may not be staggered with each other.
  • the communication port of the execution unit and the control unit may be a fiber optic communication port or an Ethernet communication port or a level signal communication port or a differential communication interface or other type of communication port.
  • the communication port of the main control unit includes but is not limited to the first communication port P1 and the second communication port P0, and may further include more communication ports, the main control list
  • Each communication port of the element can be connected to at least one execution unit connected in series through the communication port; of course, in order to improve the stability of the system and implement redundant control, the two communication ports of the main control unit can be connected in series with the communication port respectively.
  • the execution units are connected in series to form a communication loop, as in the embodiment shown in Figure 2-b.
  • the networking of the system is caused by the number of communication ports of the main control unit used and the number and arrangement of the execution units connected to each communication port (mainly the order of arrangement between the controllable rectification unit and the inverter unit). The situation is different.
  • the initialization of the parameters described in the step of initializing the related parameters of the M1 execution units mainly includes performing unit address initialization, FMMU (Fieldbus Memory Management Unit), initial setting, and SM (synchronization management). Unit, Synchronous Management) Configuration initialization and distributed clock initialization, etc.
  • the execution unit address initialization is that the main control unit allocates addresses for each execution unit to facilitate later access and related operations;
  • the FMMU configuration initialization is that the main control unit clears the FMMU address;
  • the SM configuration initialization is that the main control unit clears the SM address.
  • Distributed clock initialization is the M1 execution units that need to synchronize to make their own local system clock consistent with the reference clock of the network.
  • Distributed clock initialization includes transmission delay calculation, system clock offset compensation, static clock compensation, and steps in which each execution unit uses its phase-locked loop technology to align its own system clock with the reference clock.
  • the transmission delay is calculated as a time taken to calculate data from the main control unit to each execution unit;
  • the system clock offset is an offset between a local system clock of each execution unit and a system clock of the main control unit;
  • the system clock The offset compensation adjusts the respective system time of the respective execution units to be consistent with the system time of the main control unit;
  • the static clock compensation includes a compensation transmission delay, and the dynamic clock compensation includes compensation for network jitter and crystal vibration, Ml execution units are clock synchronized at any time.
  • the reference clock is a system clock of the main control unit, or is a system clock of any one of the M1 execution units.
  • the distributed clock initialization is specifically: the main control unit periodically sends a reference clock to each execution unit; calculates a time compensation value corresponding to each of the inverter units, and sends the time compensation value to each The time compensation value corresponding thereto is transmitted.
  • the main control unit can periodically transmit the reference clock signal through the communication port, and the M1 execution units can The reference clock signal coming to the autonomous control unit is received through the communication port.
  • the period in which the main control unit periodically sends the reference clock signal may be a fixed period or a variable period, and the specific period of time may be set according to specific needs, and the period may be, for example, 100 microseconds, 500 microseconds, 1 millisecond, 5 milliseconds, 50 milliseconds or 100 milliseconds or other duration.
  • the time compensation value is obtained based on a time deviation value and a delay value, where the time deviation value is a deviation between a local system clock of the inverter unit and a reference clock, and the delay value is data from the main control unit to each execution. The time it takes for the unit.
  • time offset compensation is performed on the local system clock by using the received time compensation value, and the current reception is understandable based on the phase locked loop, a step of periodically transmitting a reference clock signal by the main control unit, and the foregoing
  • the main control unit sends the first time compensation value to the first inverting unit, so that the first After receiving the first time compensation value, the inverting unit performs time offset compensation on the first local system clock of the first inverting unit, and based on the phase locked loop, the currently received reference clock sent by the main control unit
  • the signal is step locked with the first local system clock after time offset compensation.
  • the main control unit may send the second time compensation value to the second inverting unit, so that the second inverting unit may receive the second local unit of the second inverting unit after receiving the second time compensation value.
  • the system clock performs time offset compensation, and the system reference clock signal sent by the currently received main control unit is step-locked with the second local system clock after time offset compensation based on the phase locked loop.
  • the first time compensation value may be obtained based on the first time deviation value and the first time delay value, where the first time deviation value is a deviation between the first local system clock and the system reference clock,
  • the first delay value is a transmission delay value between the foregoing main control unit and the first inverting unit.
  • the first time compensation value may be equal to the first time deviation value minus or plus the first delay value.
  • the first time compensation value may be obtained based on the first time offset value, the first delay value, and the first dynamic clock compensation value, where the first dynamic clock compensation value may be based on the transmission Determining the jitter and/or the crystal jitter of the first inverter unit, for example, the first time compensation value may be equal to the first time deviation value minus or adding the first delay value, plus or minus The first dynamic clock compensation value.
  • the second time compensation value is calculated in the same manner as the first time compensation value, and is not described here.
  • the step further comprises: the main control unit reading the data of the M1 execution units and determining whether the synchronization is successful; if the synchronization is successful, the parameter initialization is completed until the synchronization is successful. Through this step, it can be effectively judged whether the synchronization is successful.
  • the master unit can determine whether the synchronization is successful by reading the system clock deviation register of each execution unit, and the system clock deviation register of the execution unit records the current time offset of the local system clock and the reference clock in the distributed clock initialization.
  • a certain threshold for example, 10 microseconds or other values
  • the main control unit sends the initialization data to the M1 execution units.
  • the initialization data is data for fault protection and the like, and is configured to synchronously transmit the synchronization unit of the data, and activate the execution.
  • a synchronous clock unit of the unit causes the execution unit to generate a synchronization signal.
  • the above configuration is for synchronously transmitting related registers of data, and the above related registers include FMMUs and SMs for synchronously transmitting data, mainly because the main control unit allocates addresses for FMMUs and SMs.
  • the above-mentioned synchronous clock unit of the execution unit mainly activates the synchronous clock unit to generate a synchronization signal.
  • the multi-machine frequency converter comprises Mil controllable rectification units requiring synchronization and M12 inverter units requiring synchronization, and the Mil and M12 are integers greater than one. Since synchronization is not required between the rectifier unit and the inverter unit in the multi-machine inverter, only the synchronization of the Mil controlled rectifier units is required. Synchronization with the M12 inverter units may be the same, or the rectified reference clock synchronized by the controllable rectification unit may be the same as or different from the inverter reference clock synchronized with the inverter unit.
  • the rectified reference clock is the same as the inverter reference clock, and the Mil controllable rectifications may be used.
  • the rectified reference clock and the inverting reference clock may be different or the same.
  • the rectifying unit of the multi-machine frequency converter comprises Mil controllable rectifying units and non-controlled rectifying units that need to be synchronized
  • the rectified reference clock of the Mil controllable rectifying units that need to be synchronized may be a system clock that does not control the rectifying unit.
  • the "synchronization" in the embodiment of the present invention may mean that the interval time is less than a threshold value, for example, "synchronous zero-crossing point", which may refer to a zero-crossing point at the same time, and may also mean that the interval between zero-crossing points is less than Wide value.
  • the synchronous loading of the comparison value may refer to loading the comparison value at the same time, or may mean that the interval between loading the comparison value is less than the threshold value. Other cases and so on.
  • the local system clocks of the Mil rectifying units lock the same rectified reference clock signal, so that the synchronizing performance of the synchronizing signals generated by the Mil rectifying units is stronger, which is advantageous for the correction signal based on the synchronization signal in each rectifying unit.
  • the PWM wave crosses the zero point at the same time, which is beneficial to realize the synchronization of the PWM wave zero-crossing point corresponding to the Mill rectifying units to a certain extent, which is beneficial to enhance the PWM wave synchronization performance of multiple rectifying units, and realize the parallel running performance of multiple rectifying units. It is enhanced, which is beneficial to synchronously operating a large number of rectifying units, and outputting more power, thereby facilitating realization of large current and large capacity.
  • an embodiment of the present invention further provides a multi-machine frequency converter 800.
  • the specific structure may be as shown in FIG. 5-a to FIG. 5-c, wherein the multi-machine frequency converter 800
  • the main control unit 801 and the M1 execution units 802, the M1 execution units 802 share a common DC bus 803; the M1 execution units 802 include a total of Mill rectification units and M12 inverter units, and the M12 is greater than 1 An integer, the Mil is a positive integer.
  • the method for generating a synchronization signal in the multi-machine frequency converter 800 can be a method for generating a synchronization signal in any of the multi-machine frequency converters provided in the foregoing embodiments.
  • the descriptions of the various embodiments are different, and the parts that are not detailed in an embodiment can be referred to the related descriptions of other embodiments.
  • the specific working process of the foregoing device may refer to the corresponding process in the foregoing method embodiments, and details are not described herein.
  • the disclosed apparatus and method can be implemented in other ways.
  • the device embodiments described above are merely illustrative.
  • the division of the foregoing units is only a logical function division. In actual implementation, there may be another division manner, for example, multiple units or components may be combined or may be Integration into another system, or some features can be ignored, or not executed.
  • the mutual coupling or direct connection or communication connection shown or discussed may be an indirect coupling or communication connection through some port, device or unit, and may be in electrical or other form.
  • the units described above as separate components may or may not be physically separate, and the components displayed as units may or may not be physical units, i.e., may be located in one place, or may be distributed over multiple network units. Some or all of the units may be selected according to actual needs to achieve the objectives of the solution of the embodiment.
  • each functional unit in each embodiment of the present invention may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.
  • the above integrated unit can be implemented in the form of hardware or in the form of a software functional unit.
  • the above integrated units can be stored in a computer readable storage medium if they are implemented in the form of software functional units and sold or used as separate products.
  • the technical solution of the present invention which is essential or contributes to the prior art, or all or part of the technical solution, may be embodied in the form of a software product stored in a storage medium.
  • a number of instructions are included to cause a computer device (which may be a personal computer, server, frequency converter, processor or network device, etc.) to perform all or part of the steps of the above-described methods of various embodiments of the present invention.
  • the foregoing storage medium may include, for example, a USB flash drive, a removable hard disk, a read-only memory (ROM), a magnetic disk, an optical disk, or a random access memory (RAM). Medium.

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  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Automation & Control Theory (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Inverter Devices (AREA)

Abstract

一种多机变频器产生同步信号的方法和多机变频器。一种多机变频器产生同步信号的方法，所述多机变频器包括主控单元和M1个需同步的可控执行单元，所述M1个执行单元共直流母线，所述M1为大于1的整数；所述主控单元初始化所述M1个执行单元的相关参数，所述参数初始化包括使各自的系统时钟与选定的参考时钟同步的分布式时钟初始化；参数初始化完成后，所述主控单元将初始化数据发送给所述M1个执行单元，配置用于同步传输数据的相关寄存器，激活执行单元的同步时钟单元，使所述执行单元产生同步信号。本发明实施例提供的方案有利于提高多机变频器同步运行性能。

Description

多机变频器产生同步信号方法和多机变频器 技术领域
本发明主要涉及电力电子技术领域，具体涉及多机变频器产生同步信号的 方法和多机变频器。 背景技术
当前， 市场上大多数变频器为单机变频器，单机变频器都釆用的是一个控 制单元直接控制一个逆变单元，控制单元一般不控制整流单元， 具体结构可如 图 1-a所示。
单机变频器要做并机同步运行（即至少两个单机变频器的负载电机的速度 /转矩相同或相应或至少两个单机变频器的输出并联后带负载电机或非同步来 实现工厂宏）时， 至少两个单机变频器组成变频器多机系统， 各变频器之间基 于 RS485总线通信方式。 485总线通信方式的结构如图 1-b所示， 控制台通过 485总线将系统运行频率传送至各变频器， 各变频器将状态反馈信息通过总线 传送至控制台。此外，控制台给出的系统起停机信号及主变频器发送给从变频 器的转矩信号均是通过单独信号线连接来实现。
研究和实践过程中发明人发现，由于现有技术中多个单机变频器相连以实 现并机同步运行时多个单机变频器工作时仍然相对独立，多个单机变频器相连 以并机同步运行的同步性能较差。 发明内容
本发明实施例提供多机变频器产生同步信号的方法和多机变频器，以期提 高变频器同步运行性能。
一种多机变频器产生同步信号的方法， 所述多机变频器包括主控单元和 Ml个需同步的可控执行单元， 所述 Ml个执行单元共直流母线， 所述 Ml为大 于 1的整数；
所述主控单元初始化所述 Ml个执行单元的相关参数， 所述参数初始化包 参数初始化完成后， 所述主控单元将初始化数据发送给所述 Ml个执行单 元， 配置用于同步传输数据的相关寄存器， 激活执行单元的同步时钟单元， 使 所述执行单元产生同步信号。
可选的， 所述分布式时钟初始化包括传输延时计算、 系统时钟偏移补偿、 静态时钟补偿和动态时钟补偿，各个执行单元使用锁相环技术使自身的系统时 钟与选定的参考时钟一致。
可选的， 所述分布式时钟初始化具体包括： 所述主控单元周期性地向所述 每个执行单元发送参考时钟； 计算出与所述每个执行单元对应的时间补偿值， 与之对应的所述时间补偿值之后，利用接收到的所述时间补偿值对本地系统时 钟进行时间偏移补偿，基于锁相环将当前接收到的所述参考时钟与进行时间偏 移补偿之后的所述本地系统时钟进行步调锁定。
可选的， 所述执行单元对应的时间补偿值基于时间偏差值和时延值得到， 所述时间偏差值为所述执行单元的本地系统时钟与参考时钟的偏差，所述时延 值为该执行单元与所述主控单元之间的传输时延值。
可选的， 所述分布式时钟初始化后还包括：
所述主控单元读取所述 Ml个执行单元的数据并判断同步是否成功； 如果 可选的， 所述主控单元读取所述 Ml个执行单元的数据并判断同步是否成 功， 具体包括： 主控单元读取各个执行单元的系统时钟偏差寄存器来判断同步 是否成功，所述执行单元的系统时钟偏差寄存器记录分布式时钟初始化中本地 系统时钟与参考时钟的当前时间偏差。
可选的， 所述参考时钟为所述主控单元的系统时钟， 或为所述 Ml个执行 单元中任一执行单元的系统时钟。
可选的， 所述 Ml个需同步的可控执行单元包括 Mil个需要同步的可控整 流单元和需要同步的 M12个逆变单元， 所述 Mil和 M12为大于 1的整数， 所述 或不同。
可选的， 所述多机变频器包括不控整流单元， 所述 Ml个需同步的可控执 行单元包括 Mil个需要同步的可控整流单元， 则 Mil个需要同步的可控整流单 元的整流参考时钟为不控整流单元的系统时钟。
一种多机变频器， 所述多机变频器包括主控单元和 Ml个需同步的可控执 行单元， 所述 Ml个执行单元共直流母， 所述 Ml为大于 1的整数； 其中， 所述 多机变频器中产生同步信号方法为如权利要求 1至 9任意一项所述的多机变频 器产生同步信号的方法。
可以看出， 在本发明一些实施例中， 由于 Ml个执行单元的本地系统时钟 步调锁定相同的参考时钟， 这使得 Ml个执行单元所产生的同步信号的同步性 能更强，有利于使得每个执行单元中基于同步信号校正的脉冲宽度调制波同时 过零点， 进而有利于在一定程度上实现 Ml个执行单元对应的 PWM波过零点同 步， 进而有利于增强多个执行单元的 PWM波的同步性能， 使得多个执行单元 并机同步运行性能得到增强。 附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施 例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地， 下面描述 中的附图仅仅是本发明的一些实施例， 对于本领域普通技术人员来讲，在不付 出创造性劳动性的前提下， 还可以根据这些附图获得其它的附图。
图 1-a是现有技术提供的一种单机变频器的示意图；
图 1-b是现有技术提供的一种多个单机变频器的并机示意图；
图 2-a是本发明实施例提供的一种多机变频器的示意图；
图 2-b是本发明实施例提供的另一种多机变频器的示意图；
图 2-c是本发明实施例提供的另一种多机变频器的示意图；
图 3是本发明实施例提供的另一种多机变频器的示意图；
图 4是本发明实施例提供的一种多机变频器产生同步信号的方法的流程示 意图；
图 5 - a是本发明实施例提供的另一种多机变频器的示意图；
图 5 - b是本发明实施例提供的另一种多机变频器的示意图；
图 5 - c是本发明实施例提供的另一种多机变频器的示意图。 具体实施方式
本发明实施例提供多机变频器产生同步信号的方法和多机变频器，以期提 高变频器同步运行性能。
为使得本发明的发明目的、 特征、 优点能够更加的明显和易懂， 下面将结 合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、 完整地描 述， 显然， 下面所描述的实施例仅仅是本发明一部分实施例， 而非全部的实施 例。基于本发明中的实施例， 本领域普通技术人员在没有做出创造性劳动前提 下所获得的所有其它实施例， 都属于本发明保护的范围。
本发明的说明书和权利要求书及上述附图中的术语 "第一"、 "第二"、 "第 三" "第四" 等是用于区别不同的对象， 而不是用于描述特定顺序。 此外， 术 语 "包括" 和 "具有" 以及它们任何变形， 意图在于覆盖不排他的包含。 例如 包含了一系列步骤或单元的过程、 方法、 系统、 产品或设备没有限定于已列出 的步骤或单元， 而是可选地还包括没有列出的步骤或单元， 或可选地还包括对 于这些过程、 方法、 产品或设备固有的其它步骤或单元。
参见图 4， 本发明提供了一种多机变频器产生同步信号的方法， 所述多机 变频器包括主控单元和 Ml个需同步的可控执行单元， 所述 Ml个执行单元共直 流母线， 所述 Ml为大于 1的整数。
401、 初始化所述 Ml个需同步的执行单元的相关参数。
其中， 在初始化所述 Ml个需同步的执行单元的相关参数之前， 主控单元 可读取与主控单元通信连接的执行单元的个数和组网情况。其中， 与主控单元 通信连接的执行单元是能够与主控单元进行通信的执行单元， 例如图 2-a中示 出的 N1个执行单元均为与主控单元通信连接的执行单元。 其中， Ml个需同步 的执行单元为与主控单元通信连接的部分或全部执行单元。
402、 参数初始化完成后， 所述主控单元将初始化数据发送给所述 Ml个执 行单元， 激活执行单元的同步时钟单元， 使所述执行单元产生同步信号。
由于 Ml个执行单元的本地系统时钟步调锁定相同的参考时钟， 这使得 Ml 个执行单元所产生的同步信号的同步性能更强，有利于使得每个执行单元中基 于同步信号校正的脉冲宽度调制 （PWM， Pulse Width Modulation ) 波同时过 零点， 进而有利于在一定程度上实现 Ml个执行单元对应的 PWM波过零点同 步， 进而有利于增强多个执行单元的 PWM波的同步性能， 使得多个执行单元 并机同步运行性能得到增强。
其中， 所述多机变频器包括主控单元、至少一个整流单元和至少两个逆变 单元， 所述逆变单元输出接负载电机； 从整流单元和逆变单元是否可控来看， 多机变频器包括主控单元和有 Ml个需要同步的可控执行单元， 所述 Ml为大于 1的整数。 具体地， 所述执行单元为整流单元或逆变单元， 可控执行单元中实 现电力变换的开关器件为可控器件， 如 IGBT、 MOSFET等开关管， 相应地， 不可控执行单元中实现电力变换的开关器件为不可控器件，如二极管等。 所述 需要同步的可控执行单元包括通过多个并机同步运行以实现功率扩展的可控 整流单元， 和 /或需要做并机同步运行的多个可控逆变单元， 如至少两个逆变 负载电机实现工厂宏。其中， 所述多机变频器中部分或全部整流单元可以是可 受主控单元控制的可控整流单元，或者也可以是不受主控单元控制的不可控整 流单元，但是多机变频器中的整流单元必须同步运行， 下面结合附图对多机变 频器的结构进行举例说明。
首先请参见图 2-a， 图 2-a是本发明的一个实施例提供的一种多机变频器的 结构示意图。 其中， 如图 2-a所示， 本发明一个实施例提供的一种多机变频器 可包括：
主控单元 201、 通过通信端口串联的 N1个执行单元 202， 上述 N1个执行单 元共直流母线 210。
其中， 主控单元 201的第一通信端口 P1和上述 N1个执行单元 202之中的第 一执行单元的第二通信端口 P0连接。其中，第一执行单元为通过通信端口串联 的上述 N1个执行单元之中处于一端边缘位置的执行单元（其中， 图 2-a举例架 构中， 串联后的 N1个执行单元的一端边缘位置是剩余第二通信端口 P0的第一 执行单元， 另一端边缘位置是剩余第一通信端口 P1的第二执行单元 )。
上述执行单元 202为整流单元或逆变单元， 其中， N1个执行单元 202共包 括 Nil个整流单元和 N12个逆变单元， 上述 Nil为正整数， 上述 N12为大于 1的 正整数。
其中， 图 2-a中以每个执行单元 202均包括两个通信端口 （通信端口 P0和通 信端口 Pl )， 当然， 两个通信端口的功能可以相同或相近， 在一些场景下这两 个通信端口可以互换。 串联后的 N1个执行单元 202中处于中间位置的每个执行 单元的通信端口 P0和通信端口 P1分别连接其它执行单元 202， 以实现 N1个执行 单元 202的串联。
其中， 主控单元 201可以通过第一通信端口 P1发送命令字、 数据字 （例如 包含电压角度和电压调制比等脉冲宽度调制 （PWM， Pulse Width Modulation ) 波关键数据的数据字）和 /或状态字等。 而第一执行单元则可通过其第二通信 端口 P0接收来自主控单元 201的命令字、 数据字和 /或状态字等， 第一执行单元 则可通过其第一通信端口 P1转发 (对于可透传的数据可直接转发，对于需处理 的数据则可在进行处理之后转发）接收到的来自主控单元 201的命令字、 数据 接收命令字、 数据字和 /或状态字等。
需要说明的是， 本发明各实施例中的 "转发"， 可能是将接收到的数据不 做修改而直接转发，也可能是将接收到的数据进行相应修之后转发， 例如对于 接收到的命令字、 数据字和 /或状态字中可透传的内容， 则可不做修改而直接 转发， 而对于接收到的命令字、 数据字和 /或状态字中不可透传的内容， 则可 在对其进行修改之后转发。
其中， N1个执行单元 202可根据主控单元发送的参考时钟及时间补偿值等 信息产生同步信号； 还可根据来自主控单元 201的命令字、 数据字 （例如包含 电压角度和电压调制比等 PWM波关键数据的数据字）和 /或状态字等进行对应 的操作。 例如， N1个执行单元 202可以根据来自主控单元 201命令字进入上电 启动或休眠等状态。 又例如， N1个执行单元 202可以根据来自主控单元 201的 包含电压角度和电压调制比等 PWM波关键数据的数据字， 产生同步的脉冲宽 度调制波； 利用产生的脉冲宽度波驱动电机工作。
在图 2-a的基础上， 主控单元 201还包括第二通信端口 P0， 主控单元 201可 以通过第二通信端口 P0发送命令字、 数据字和 /或状态字等。 在本发明的一些实施例中， 如图 2-b所示， 主控单元 201的第二通信端口 P0 还可与上述 N1个执行单元 202中的第二执行单元的第一通信端口 P1连接从而 形成通信环路设计结构，主控单元 201可以通过第二通信端口 P0和 /或第一通信 端口 P1向各执行单元 202发送命令字、 数据字和 /或状态字等， 相当于提供了两 条传递信息的通信通道，引入通信环路可以使得各单元之间的通信通道具有冗 余备份功能，抗故障和容错能力得到增强，有利于进一步提升系统运行的稳定 可靠性。
在本发明的另一些实施例中， 如图 2-c所示， 上述多机变频器还可包括通 过通信端口串联的 N2个执行单元 203， 其中， 上述 N2个执行单元 203共直流母 线 210。
其中， 上述主控单元 201的第二通信端口 P0与通过通信端口串联的上述 N2 个执行单元 203之中的第三执行单元的第一通信端口 P1连接， 其中， 上述 N2为 正整数， 上述 N2个执行单元包括整流单元和 /或逆变单元， 其中， 第三执行单 元为通过通信端口串联的上述 N2个执行单元 203中处于一端边缘位置的执行 单元。
其中， 图 2-c举例示出上述主控单元 201包括两个通信端口， 这两个通信端 口都与执行单元的通信端口连接， 与图 2-b所示架构的主要区别在于， 主控单 元 201与执行单元之间未形成通信环路。 当然， 主控单元 201也可包括更多通信 端口， 主控单元 201的每个通信端口均可按照图 2-c所示方式与执行单元的通信 端口连接。
可以理解， 在通过通信端口串联的 N1个执行单元中， 整流单元和逆变单 元可以相互交错排列， 当然整流单元和逆变单元也可以不相互交错排列。
在本发明的一些实施例中，执行单元和控制单元的通信端口可以为光纤通 信端口或以太网通信端口或电平信号通信端口或差分通信接口或者其它类型 的通信端口。
请参见图 3，图 3是本发明另一个实施例提供的另一种多机变频器的结构示 意图。 该多机变频器包括：
主控单元 301、 通过通信端口串联的 N3个执行单元 302和通过通信端口串 联的 N4个执行单元 303。
其中， 上述 N3个执行单元和上述 N4个执行单元共直流母线 310。
其中， 上述主控单元 301的第一通信端口 P1和通过通信端口串联的上述 N3 个执行单元中的第六执行单元的第二通信端口 P0连接，上述主控单元的第二通 信端口 P0和通过通信端口串联的上述 N4个执行单元中的第七执行单元的第一 通信端口 P1连接。
其中， 上述 N3个执行单元和上述 N4个执行单元中共包括 XI个整流单元和 X2个逆变单元， 其中， 上述 XI为正整数， 上述 X2为大于 1的正整数， 上述第 六执行单元为通过通信端口串联的上述 N3个执行单元中处于一端边缘位置的 执行单元， 其中， 第七执行单元为通过通信端口串联的上述 N4个执行单元中 处于一端边缘位置的执行单元。 其中， 上述 N3和 N4为正整数， 上述 N3与 N4 之和大于或等于 3。
其中， 与前述实施例中举例的图 2-a所示架构相比， 本实施例图 3所示架构 中，位于主控单元 301两侧的上述 N3个执行单元和上述 N4个执行单元中共包括 XI个整流单元和 X2个逆变单元， 也就是说， 主控单元 301两侧可以分别部署至 少 1个逆变单元， 而图 2-a所示架构中， 主控单元 301的其中一侧就部署了至少 两个逆变单元和至少一个整流单元（ N1个执行单元 202共包括 Nil个整流单元 和 N12个逆变单元）。
其中， 主控单元 301可以通过第一通信端口 P1和第二通信端口 P0分别发送 命令字、 数据字和 /或状态字等至 N3个执行单元 302和 N4个执行单元 303， 具体 发送和转发等过程与前述部分相似， 在此不再赘述。
可以理解， 在通过通信端口串联的 N3个执行单元中， 整流单元和逆变单 元可以相互交错排列， 当然整流单元和逆变单元也可以不相互交错排列。
在本发明的一些实施例中，执行单元和控制单元的通信端口可以为光纤通 信端口或以太网通信端口或电平信号通信端口或差分通信接口或者其它类型 的通信端口。
上述为多机变频器的几种组成形式，所述主控单元的通信端口包括但不仅 限于第一通信端口 P1和第二通信端口 P0，还可以包括更多的通信端口，主控单 元的每个通信端口都可以连接至少 1个通过通信端口串联的执行单元； 当然为 了提高系统的稳定性实现冗余控制，主控单元的两个通信端口可与分别与通过 通信端口串联的多个执行单元串联形成通信环路， 如图 2-b所示的实施例。 由 于使用的主控单元的通信端口数量和每个通信端口所连接的执行单元的连接 数量及排列方式（主要指可控整流单元和逆变单元之间的排列顺序）不同， 导 致系统的组网情况也不同。
上述初始化所述 Ml个执行单元的相关参数步骤中所述的参数初始化， 主 要包括执行单元地址初始化、 FMMU (现场总线内存管理单元， Fieldbus Memory Management Unit ) 酉己置初始 4匕， SM (同步管理单元， Synchronous Management ) 配置初始化和分布式时钟初始化等。
具体地，执行单元地址初始化是主控单元为各个执行单元分配地址，便于 后期的访问和相关操作； FMMU配置初始化是主控单元将 FMMU地址清零； SM配置初始化是主控单元将 SM地址清零； 分布式时钟初始化是需要同步的 Ml个执行单元的使自身的本地系统时钟与该网络的参考时钟一致。
分布式时钟初始化包括传输延时计算、 系统时钟偏移补偿、静态时钟补偿 和各个执行单元使用锁相环技术使自身的系统时钟与该所述参考时钟一致等 步骤。 所述传输延时计算为计算数据从主控单元到各个执行单元所花费的时 间；所述系统时钟偏移为各个执行单元本地系统时钟与主控单元的系统时钟的 偏移；所述系统时钟偏移补偿为所述各个执行单元调整各自的系统时间以与主 控单元的系统时间保持一致； 所述静态时钟补偿包括补偿传输延时， 所述动态 时钟补偿包括补偿网络抖动及晶振抖动， 使 Ml个执行单元在任何时间的时钟 同步。
具体地， 上述参考时钟为主控单元的系统时钟， 或为所述 Ml个执行单元 中任一执行单元的系统时钟。
分布式时钟初始化具体为，所述主控单元周期性地向所述每个执行单元发 送参考时钟； 计算出与所述每个逆变单元对应的时间补偿值， 并向所述每个执 行单元发送与之对应的所述时间补偿值。
主控单元可通过通信端口周期性地发送参考时钟信号， Ml个执行单元可 通过通信端口接收到来自主控单元的参考时钟信号。上述主控单元周期性地发 送参考时钟信号的周期可为固定周期或可变周期，而具体的周期时长可根据具 体需要进行设定， 周期例如可为 100微秒、 500微秒、 1毫秒、 5毫秒、 50毫秒或 100毫秒或其他时长。
上述时间补偿值基于时间偏差值和时延值得到，所述时间偏差值为所述逆 变单元的本地系统时钟与参考时钟的偏差，所述时延值为数据从主控单元到每 个执行单元所花费的时间。
所述每个执行单元接收到与之对应的所述时间补偿值之后，利用接收到的 所述时间补偿值对本地系统时钟进行时间偏移补偿，基于锁相环将当前接收到 可以理解地， 上述主控单元周期性地发送参考时钟信号的步骤、 以及上述
的时间顺序。
举例来说， H没上述 Ml个执行单元之中包括第一逆变单元和第二逆变单 元， 则主控单元向上述第一逆变单元发送上述第一时间补偿值， 以使得上述第 一逆变单元在接收到上述第一时间补偿值之后，对上述第一逆变单元的第一本 地系统时钟进行时间偏移补偿，基于锁相环将当前接收到的上述主控单元发送 的参考时钟信号与进行时间偏移补偿后的第一本地系统时钟进行步调锁定。主 控单元可向上述第二逆变单元发送上述第二时间补偿值，以使得上述第二逆变 单元在接收到上述第二时间补偿值之后，可对上述第二逆变单元的第二本地系 统时钟进行时间偏移补偿，基于锁相环将当前接收到的上述主控单元发送的系 统参考时钟信号与进行时间偏移补偿之后的第二本地系统时钟进行步调锁定。
具体举例来说，上述第一时间补偿值可基于第一时间偏差值和第一时延值 得到， 其中， 上述第一时间偏差值为上述第一本地系统时钟与上述系统参考时 钟的偏差，上述第一时延值为上述主控单元和上述第一逆变单元之间的传输时 延值。举例来说， 上述第一时间补偿值可等于上述第一时间偏差值减去或加上 第一时延值。 或者， 上述第一时间补偿值可以基于上述第一时间偏差值、 第一 时延值和第一动态时钟补偿值得到， 其中， 上述第一动态时钟补偿值可基于传 输抖动和 /或上述第一逆变单元的晶振抖动等确定， 例如， 上述第一时间补偿 值可等于上述第一时间偏差值减去或加上第一时延值，再加上或减去第一动态 时钟补偿值。
上述第二时间补偿值的计算方式与第一时间补偿值的方式相同，在此不再 赘述。
优选地， 分布式时钟初始化后还包括步骤： 所述主控单元读取所述 Ml个 执行单元的数据并判断同步是否成功； 如果同步成功， 则说明参数初始化已完 直至同步成功。 通过该步骤可以有效地判断同步是否成功。
具体地，主控单元可以通过读取各个执行单元的系统时钟偏差寄存器来判 断同步是否成功，所述执行单元的系统时钟偏差寄存器记录分布式时钟初始化 中本地系统时钟与参考时钟的当前时间偏差。当某执行单元的偏差寄存器中记 录的当前时间偏差大于设定的某个阔值（例如 10微妙或其它值）时， 该执行单 补偿，再基于锁相环将当前接收到的参考时钟信号与进行动态补偿之后的本地 时钟之间的步调。
参数初始化完成后， 所述主控单元将初始化数据发送给所述 Ml个执行单 元， 具体的， 所述初始化数据为故障保护等方面的数据， 配置用于同步传输数 据的同步单元， 并激活执行单元的同步时钟单元，使所述执行单元产生同步信 号。
上述配置用于同步传输数据的相关寄存器，上述相关寄存器包括用于同步 传输数据的 FMMU和 SM， 主要是主控单元为 FMMU和 SM分配地址。
上述激活执行单元的同步时钟单元， 主要为使能同步时钟单元， 以使其产 生同步信号。
优选地， 多机变频器包括 Mil个需要同步的可控整流单元和需要同步的 M12个逆变单元， 所述 Mil和 M12为大于 1的整数。 由于多机变频器中整流单 元和逆变单元之间并不需要同步， 因此仅需要实现 Mil个可控整流单元的同步 和 M12个逆变单元的同步即可，所述可控整流单元同步的整流参考时钟与所述 逆变单元同步的逆变参考时钟可以相同或不同。 例如， 若 Mil个可控整流单元 与所述 M12个逆变单元串联后与主控单元 201的一个通信端口相连， 则整流参 考时钟与逆变参考时钟相同， 可以为所述 Mil个可控整流单元和 M12个逆变单 元中任一执行单元的系统时钟； 若 M12个逆变单元串联后与主控单元 201的一 个通信端口相连， 而 Mil个可控整流单元串联后与主控单元 201的另一个通信 端口相连， 则整流参考时钟与逆变参考时钟可以不同或相同。
优选地， 多机变频器的整流单元包括 Mil个需要同步的可控整流单元和不 控整流单元，则 Mil个需要同步的可控整流单元的整流参考时钟可以为不控整 流单元的系统时钟。
其中， 本发明实施例所述的 "同步"， 可以是指同时， 也可以是指间隔时 间小于阔值， 例如 "同步过零点"， 可以指同时过零点， 也可指过零点的间隔 时间小于阔值。 又例如， 同步装载比较值， 可以指同时装载比较值， 也可指装 载比较值的间隔时间小于阔值。 其它情况以此类推。
由上可知， Mil个整流单元的本地系统时钟步调锁定相同的整流参考时钟 信号， 使得 Mil个整流单元所产生的同步信号的同步性能更强， 有利于使得每 个整流单元中基于同步信号校正的 PWM波同时过零点， 进而有利于在一定程 度上实现 Mil个整流单元对应的 PWM波过零点同步， 进而有利于增强多个整 流单元的 PWM波同步性能， 使多个整流单元并机同步运行性能得到增强， 进 而有利于同步运行数量较多的整流单元，输出更大功率， 进而有利于实现大电 流大容量。
参见图 5-a〜图 5-c， 本发明实施例还提供一种多机变频器 800， 具体结构可 如图 5-a〜图 5-c所示， 其中， 所述多机变频器 800包括主控单元 801和 Ml个执行 单元 802， 所述 Ml个执行单元 802共直流母线 803; Ml个执行单元 802共包括 Mil个整流单元和 M12个逆变单元， 所述 M12为大于 1的正整数， 所述 Mil为正 整数。
其中， 多机变频器 800中产生同步信号方法可如上述实施例提供的任意一 种多机变频器中产生同步信号方法。 在上述实施例中， 对各个实施例的描述都各有侧重， 某个实施例中没 有详述的部分， 可以参见其他实施例的相关描述。
所属领域的技术人员可以清楚地了解到， 为描述的方便和简洁， 上述描述 的装置的具体工作过程， 可以参考前述方法实施例中的对应过程，在此不再赘 述。 在本申请所提供的几个实施例中， 应该理解到， 所揭露的装置和方法， 可 以通过其它的方式实现。 例如， 以上所描述的装置实施例仅仅是示意性的， 例 如， 上述单元的划分， 仅仅为一种逻辑功能划分， 实际实现时可以有另外的划 分方式， 例如多个单元或组件可以结合或者可以集成到另一个系统， 或一些特 征可以忽略， 或不执行。 另一点， 所显示或讨论的相互之间的耦合或直接輛合 或通信连接可以是通过一些端口， 装置或单元的间接耦合或通信连接， 可以是 电性或其它的形式。上述作为分离部件说明的单元可以是或者也可以不是物理 上分开的，作为单元显示的部件可以是或者也可以不是物理单元， 即可以位于 一个地方， 或者也可以分布到多个网络单元上。可以才艮据实际的需要选择其中 的部分或者全部单元来实现本实施例方案的目的。 另外，在本发明各个实施例 中的各功能单元可以集成在一个处理单元中， 也可以是各个单元单独物理存 在，也可以两个或两个以上单元集成在一个单元中。上述集成的单元既可以釆 用硬件的形式实现，也可以釆用软件功能单元的形式实现。上述集成的单元如 果以软件功能单元的形式实现并作为独立的产品销售或使用时，可以存储在一 个计算机可读取存储介质中。
基于这样的理解，本发明的技术方案本质上或者说对现有技术做出贡献的 部分或者该技术方案的全部或部分可以以软件产品的形式体现出来，该计算机 软件产品存储在一个存储介质中， 包括若干指令用以使得一台计算机设备（可 以是个人计算机， 服务器， 变频器、 处理器或者网络设备等）执行本发明各个 实施例上述方法的全部或部分步骤。 而前述的存储介质例如可包括： U盘、 移 动硬盘、 只读存储器（ROM， Read-Only Memory )、 磁碟、 光盘或者随机存取 存储器 （RAM, Random Access Memory )等各种可存储程序代码的介质。 以 上上述， 以上实施例仅用以说明本发明的技术方案， 而非对其限制； 尽管参照 前述实施例对本发明进行了详细的说明， 本领域的普通技术人员应当理解： 其 依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特 征进行等同替换； 而这些修改或者替换， 并不使相应技术方案的本质脱离本发 明各实施例技术方案的精神和范围。

Claims

权 利 要 求
1、 一种多机变频器产生同步信号的方法， 其特征在于， 所述多机变频器 包括主控单元和 Ml个需同步的可控执行单元， 所述 Ml个执行单元共直流母 线， 所述 Ml为大于 1的整数；
所述主控单元初始化所述 Ml个执行单元的相关参数， 所述参数初始化包 参数初始化完成后， 所述主控单元将初始化数据发送给所述 Ml个执行单 元， 配置用于同步传输数据的相关寄存器， 激活执行单元的同步时钟单元， 使 所述执行单元产生同步信号。
2、根据权利要求 1所述的方法， 其特征在于， 所述分布式时钟初始化包括 传输延时计算、 系统时钟偏移补偿、 静态时钟补偿和动态时钟补偿， 各个执行 单元使用锁相环技术使自身的系统时钟与选定的参考时钟一致。
3、根据权利要求 2所述的方法， 其特征在于， 所述分布式时钟初始化具体 包括： 所述主控单元周期性地向所述每个执行单元发送参考时钟； 计算出与所 述每个执行单元对应的时间补偿值，并向每个执行单元发送与之对应的所述时 间补偿值； 所述每个执行单元接收到与之对应的所述时间补偿值之后， 利用接 收到的所述时间补偿值对本地系统时钟进行时间偏移补偿，基于锁相环将当前 调锁定。
4、 根据权利要求 3所述的方法， 其特征在于，
所述执行单元对应的时间补偿值基于时间偏差值和时延值得到，所述时间 偏差值为所述执行单元的本地系统时钟与参考时钟的偏差，所述时延值为该执 行单元与所述主控单元之间的传输时延值。
5、 根据权利要求 2至 4任一项所述的方法， 其特征在于， 所述分布式时钟 初始化后还包括：
所述主控单元读取所述 Ml个执行单元的数据并判断同步是否成功； 如果
6、 根据权利要求 5所述的方法， 其特征在于， 所述主控单元读取所述 Ml 个执行单元的数据并判断同步是否成功， 具体包括： 主控单元读取各个执行单 元的系统时钟偏差寄存器来判断同步是否成功，所述执行单元的系统时钟偏差 寄存器记录分布式时钟初始化中本地系统时钟与参考时钟的当前时间偏差。
7、 根据权利要求 2至 4中任一项所述的方法， 其特征在于， 所述参考时钟 为所述主控单元的系统时钟， 或为所述 Ml个执行单元中任一执行单元的系统 时钟。
8、 根据权利要求 2至 4中任一项所述的方法， 其特征在于， 所述 Ml个需同 步的可控执行单元包括 Mil个需要同步的可控整流单元和需要同步的 M12个 逆变单元， 所述 Mil和 M12为大于 1的整数， 所述可控整流单元同步的整流参
9、 根据权利要求 2至 4中任一项所述的方法， 其特征在于， 所述多机变频 器包括不控整流单元， 所述 Ml个需同步的可控执行单元包括 Mil个需要同步 的可控整流单元，则 Mil个需要同步的可控整流单元的整流参考时钟为不控整 流单元的系统时钟。
10、 一种多机变频器， 其特征在于， 所述多机变频器包括主控单元和 Ml 个需同步的可控执行单元， 所述 Ml个执行单元共直流母， 所述 Ml为大于 1的 整数； 其中， 所述多机变频器中产生同步信号方法为如权利要求 1至 9任意一项 所述的多机变频器产生同步信号的方法。
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