WO2016184018A1 - 时钟输出方法及装置 - Google Patents

时钟输出方法及装置 Download PDF

Info

Publication number
WO2016184018A1
WO2016184018A1 PCT/CN2015/092033 CN2015092033W WO2016184018A1 WO 2016184018 A1 WO2016184018 A1 WO 2016184018A1 CN 2015092033 W CN2015092033 W CN 2015092033W WO 2016184018 A1 WO2016184018 A1 WO 2016184018A1
Authority
WO
WIPO (PCT)
Prior art keywords
dpll
clock
state
output
frequency
Prior art date
Application number
PCT/CN2015/092033
Other languages
English (en)
French (fr)
Inventor
何波
Original Assignee
中兴通讯股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 中兴通讯股份有限公司 filed Critical 中兴通讯股份有限公司
Publication of WO2016184018A1 publication Critical patent/WO2016184018A1/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop

Definitions

  • the present invention relates to the field of communications, and in particular to a clock output method and apparatus.
  • Loop Timing In communication device applications, many interfaces require that the sender can follow the frequency of the receiver, which is called Loop Timing.
  • the traditional Synchronous Optical Network (SONET)/Synchronous Digital Hierarchy (SDH) transmission network, the optical transport network (Optical Transport Network, OTN for short) and the metropolitan area network Synchronous Ethernet networks in packet networks have the need for frequency synchronization between ports.
  • SONET Synchronous Optical Network
  • SDH Synchronous Digital Hierarchy
  • OTN optical Transport Network
  • the port frequency synchronization implementation scheme in the related art generally adopts two types: an external clock mode and a line clock mode.
  • FIG. 1 is a schematic diagram of port frequency synchronization in an external clock mode in the related art. It can be seen from FIG. 1 that when the port frequency synchronization mode of the external clock mode is adopted, the network device needs to obtain clock information from the clock source of the Building Integrated Timing System (BITS), and the distribution of the synchronous clock is The most reliable way, but the need to add expensive BITS equipment in the central office.
  • BITS Building Integrated Timing System
  • FIG. 2 is a schematic diagram of port frequency synchronization in the line clock mode in the related art.
  • the first-level network device uses the external BITS clock source to transmit the synchronous clock information from the transmitting port Tx to the first The receiving port Rx of the secondary network device.
  • the second-level network device Rx recovers the synchronous clock information from the receiving side, and the synchronized clock information is sent to the external narrow-band phase-locked loop (Phase-Locked Loop) by the clock recovered by the clock data recovery (Clock Data Recovery, CDR for short).
  • PLL after PLL processing, provides a high-quality reference clock to the Physical Layer Protocol (PHY) module in the Tx direction.
  • PHY Physical Layer Protocol
  • An external phase-locked loop solution requires an external phase-locked loop to handle the recovered clock.
  • the interface board requires a large number of external phase-locked loops. This brings additional cost, greater power consumption, and high complexity of printed circuit board (PCB) design.
  • PCB printed circuit board
  • the solution in the related art may have the problems of high equipment cost and complicated PCB design.
  • the invention provides a clock output method and device, so as to at least solve the problems of high equipment cost and complicated PCB design existing in the related art.
  • a clock output method comprising: a digital phase-locked loop DPLL receiving an output recovered clock, wherein the DPLL is configured using a logic resource of a chip; the DPLL is according to the DPLL The status output clock at the location.
  • the recovery clock of the DPLL receiving output includes: the DPLL receives a recovery clock outputted by a serializer Serdes transmitting side; and the DPLL outputs a clock according to a state in which the DPLL is located: the DPLL is configured according to The state in which the DPLL is in outputs a clock to the serializer Serdes receiving side.
  • the method further includes: configuring, by the DPLL, parameters of the DPLL internal component according to a requirement of a reference clock of the Serdes transmitting side, where
  • the internal components of the DPLL include at least one of the following: a phase detector, a filter, and a frequency phase controller.
  • the outputting, by the DPLL, the clock according to a state in which the DPLL is located includes: determining, by the DPLL, a state in which the DPLL is located, where the state includes one of: a freely oscillating state, a holding state, and a locked state.
  • the DPLL outputs a clock according to the determined state.
  • the DPLL outputting the clock according to the determined state includes: when the state in which the DPLL is in a freely oscillating state, the DPLL sends one to the Serdes sending side according to the configured parameters of the DPLL internal component. a free clock, wherein a frequency of the free clock is uncorrelated with a frequency of the recovered clock; when the state in which the DPLL is in a hold state, the DPLL is configured according to parameters of the configured internal components of the DPLL
  • the Serdes transmitting end transmits a fixed frequency clock, wherein the fixed frequency is a frequency of a clock locked in front of the DPLL; when the state of the DPLL is in a locked state, the DPLL is configured according to the DPLL
  • the recovered component clock is processed by parameters of the internal component; the DPLL sends the processed recovered clock to the Serdes transmitting side.
  • a clock output device for use in a digital phase locked loop DPLL, comprising: a receiving module configured to receive an output recovered clock, wherein the DPLL is a chip using An output module configured to output a clock according to a state in which the DPLL is located.
  • the receiving module includes: a recovery clock that receives a serial side Serdes transmitting side output; the output module includes: receiving a side output clock to the serializer Serdes according to a state in which the DPLL is in.
  • the apparatus further includes: a configuration module configured to configure parameters of the DPLL internal component according to a requirement of a reference clock of the Serdes transmitting side, wherein the DPLL internal component includes at least one of the following: phase discrimination , filter, frequency phase controller.
  • the output module includes: a determining unit, configured to determine a state in which the DPLL is located, where the state includes one of: a freely oscillating state, a hold state, a locked state; and an output unit configured to be Determined state output clock.
  • the output unit includes: when the state of the DPLL is in a freely oscillating state, the DPLL sends a free clock to the Serdes sending side according to the configured parameters of the DPLL internal component, where The frequency of the free clock is not related to the frequency of the recovered clock; when the state of the DPLL is in a hold state, the DPLL sends a signal to the Serdes sender according to the configured parameters of the DPLL internal component.
  • Fixed frequency a clock, wherein the fixed frequency is a frequency of a clock locked in front of the DPLL; and when the state in which the DPLL is in a locked state, the DPLL is configured according to parameters of the DPLL internal component configured The clock is processed; the DPLL sends the processed recovered clock to the Serdes transmitting side.
  • the output recovery clock is received by the digital phase-locked loop DPLL, wherein the DPLL is configured using the logic resources of the chip; the DPLL outputs a clock according to the state of the DPLL, and the related art exists.
  • the problem of high equipment cost and complicated PCB design has the effect of reducing equipment cost and PCB design complexity.
  • FIG. 1 is a schematic diagram of port frequency synchronization in an external clock mode in the related art
  • FIG. 2 is a schematic diagram of port frequency synchronization in a line clock mode in the related art
  • FIG. 3 is a flow chart of a clock output method according to an embodiment of the present invention.
  • FIG. 4 is a block diagram showing the structure of a clock output device according to an embodiment of the present invention.
  • FIG. 5 is a block diagram showing a preferred structure of a clock output device according to an embodiment of the present invention.
  • FIG. 6 is a block diagram showing the structure of an output module 44 in a clock output device according to an embodiment of the present invention.
  • FIG. 7 is a schematic diagram of an implementation apparatus for implementing port frequency synchronization of a communication device by using a single chip according to an embodiment of the invention
  • FIG. 8 is a flow chart of a method for implementing port frequency synchronization of a communication device by a single chip according to an embodiment of the invention.
  • FIG. 3 is a flowchart of a clock output method according to an embodiment of the present invention. As shown in FIG. 3, the process includes the following steps:
  • Step S302 the digital phase locked loop DPLL receives the output recovery clock, wherein the DPLL is configured using the logic resources of the chip;
  • step S304 the DPLL outputs a clock according to the state in which the DPLL is located.
  • the digital phase locked loop (DPLL) is used to receive the recovered clock and the output clock, and the DPLL is a digital phase locked loop configured by using the logic resources of the chip, and does not need to occupy the internal and external dedicated of the chip.
  • Phase-locked loop resources therefore, in the high-density multi-port communication device interface board design, the DPLL can be fully matched according to the number of physical ports, and the equipment cost and the design complexity of the PCB are greatly reduced, thereby solving the related art.
  • the problem of high equipment cost and complicated PCB design has the effect of reducing equipment cost and PCB design complexity.
  • the recovery clock of the DPLL receiving output includes: the DPLL receiving the recovered clock outputted by the serializer Serdes transmitting side; the DPLL outputting the clock according to the state of the DPLL includes: the DPLL is according to the DPLL The state outputs a clock to the serializer Serdes receiving side.
  • the Serdes transmitting side may first obtain the recovered clock, and the obtaining manner may be multiple. The following is an example: serializer clock data recovery in the Serdes receiving side The Serdes CDR recovers the clock signal from the high speed serial code stream, which is the recovered clock.
  • the DPLL before the DPLL outputs a clock according to the state of the DPLL, the DPLL further includes: configuring, by the DPLL, parameters of a DPLL internal component according to a requirement of a reference clock of a Serdes transmitting side, where the DPLL internal component includes At least one of the following: phase detector, filter, frequency phase controller.
  • the operation of configuring the parameters of the internal components of the DPLL according to the requirements of the reference clock of the sender side of the Serdes and the operation of recovering the clock of the digital phase-locked loop DPLL receiving output may be various, and the DPLL may be configured first.
  • the parameters of the internal components of the DPLL are then received to recover the clock; the recovered clock can also be received first, and then the parameters of the internal components of the DPLL can be configured; of course, the parameters for recovering the clock and configuring the internal components of the DPLL can also be received.
  • the purpose of configuring the above parameters of the DPLL is to output a high quality clock.
  • the outputting of the clock by the DPLL according to the state of the DPLL includes: determining, by the DPLL, a state in which the DPLL is located, wherein the state in which the DPLL is located includes one of: a freely oscillating state, a holding state, Locked state; the DPLL outputs a clock based on the determined state. This ensures that the output meets the high quality clock frequency required by the transport network protocol for port clock jitter specifications.
  • the DPLL outputting the clock according to the determined state includes: when the state of the DPLL is in a freely oscillating state, the DPLL sends a free clock to the Serdes sending side according to the configured parameters of the DPLL internal component.
  • the frequency of the free clock is irrelevant to the frequency of the recovered clock; when the state of the DPLL is in the hold state, the DPLL sends a fixed frequency clock to the Serdes transmitting end according to the configured parameters of the internal components of the DPLL, wherein The fixed frequency is the frequency of the clock locked in front of the DPLL; when the state of the DPLL is in the locked state, the DPLL processes the recovered clock according to the parameters of the configured internal components of the DPLL; the DPLL sends the processed recovered clock to the Serdes Send side.
  • the method according to the above embodiment can be implemented by means of software plus a necessary general hardware platform, and of course, by hardware, but in many cases, the former is A better implementation.
  • the technical solution of the present invention which is essential or contributes to the prior art, may be embodied in the form of a software product stored in a storage medium (such as ROM/RAM, disk, CD-ROM, including a number of instructions to make a terminal device (can be a mobile phone, a computer, The server, or network device, etc.) performs the methods described in various embodiments of the present invention.
  • a clock output device is also provided, which is used to implement the above-mentioned embodiments and preferred embodiments, and has not been described again.
  • the term "module” may implement a combination of software and/or hardware of a predetermined function.
  • the apparatus described in the following embodiments is preferably implemented in software, hardware, or a combination of software and hardware, is also possible and contemplated.
  • FIG. 4 is a block diagram showing the structure of a clock output device according to an embodiment of the present invention.
  • the device can be applied to a digital phase locked loop DPLL. As shown in FIG. 4, the device includes a receiving module 42 and an output module 44. Be explained.
  • the receiving module 42 is configured to receive an output recovery clock, wherein the DPLL is configured using a logic resource of the chip; the output module 44 is coupled to the receiving module 42 and configured to output a clock according to a state in which the DPLL is located.
  • the receiving module 42 includes: a recovery clock that receives the output of the serializer Serdes transmitting side; and the output module 44 includes: receiving the output clock to the serializer Serdes according to the state of the DPLL.
  • FIG. 5 is a block diagram showing a preferred structure of a clock output apparatus according to an embodiment of the present invention. As shown in FIG. 5, the apparatus includes a configuration module 52 in addition to all the modules shown in FIG. 4, which will be described below.
  • the configuration module 52 is connected to the output module 44 and configured to configure parameters of the internal components of the DPLL according to the requirements of the reference clock of the Serdes transmitting side, wherein the DPLL internal components include at least one of the following: a phase detector, a filter, and a frequency phase. Controller.
  • FIG. 6 is a block diagram showing the structure of an output module 44 in a clock output device according to an embodiment of the present invention. As shown in FIG. 6, the output module 44 includes a determining unit 62 and an output unit 64, which will be described below.
  • the determining unit 62 is configured to determine a state in which the DPLL is located, wherein the state comprises one of: a freely oscillating state, a holding state, and a locked state; the output unit 64 is connected to the determining unit 62, and configured to output according to the determined state clock.
  • the output unit 64 includes: when the state of the DPLL is in a freely oscillating state, the DPLL sends a free clock to the Serdes transmitting side according to the configured parameters of the DPLL internal component, wherein the free clock
  • the frequency of the clock is not related to the frequency of the recovered clock
  • the DPLL sends a fixed frequency clock to the Serdes transmitter according to the parameters of the configured internal components of the DPLL, wherein the fixed frequency is DPLL.
  • the frequency of the previously locked clock when the state of the DPLL is locked, the DPLL processes the recovered clock according to the parameters of the configured internal components of the DPLL; the DPLL sends the processed recovered clock to the Serdes transmitting side.
  • an apparatus and a method for realizing the frequency synchronization of the communication device port by using a single chip are also proposed in the embodiment of the present invention, and the DPLL is implemented by using the internal logic of the chip.
  • the line recovers the clock, and after configuring the relevant parameters of the DPLL, it can output a high-quality reference clock to the transmitting end, thereby achieving frequency synchronization of each port on the communication device.
  • FIG. 7 is a schematic diagram of an apparatus for implementing port frequency synchronization of a communication device according to an embodiment of the present invention, as shown in FIG. 7 As shown, the device includes the following modules:
  • the Serdes receiving module 72, the Serdes transmitting module 74, and the DPLL module 76 (same as the receiving module 42, the output module 44, and the configuration module 52 described above) will be described below.
  • the Serdes receiving module 72 and the Serdes transmitting module 74 are receiving and transmitting processing modules of the high speed serial interface.
  • the DPLL module 76 is arranged to implement port frequency synchronization. The relationship between the Serdes receiving module 72, the Serdes transmitting module 74, and the DPLL module 76 is as follows.
  • the Serdes receiving module 72 is interconnected with the receiving side of the optical module. In addition to basic serial data reception, serial-to-parallel conversion and decoding, the Serdes CDR module output recovery clock is mainly sent to the DPLL module 76 for processing.
  • the DPLL module 76 mainly implements locking of the CDR recovery clock, and generates a corresponding high quality clock to the Serdes transmission module 74 according to the configuration parameters.
  • the DPLL control module in the DPLL module 76 needs to implement the three states of free oscillation, hold and lock according to the DPLL lock state, ensuring that the output meets the high quality clock frequency required by the transmission network protocol for the port clock jitter specification.
  • each physical port should be equipped with a separate DPLL. Since the DPLL is completely implemented by the logic unit and does not occupy the dedicated phase-locked loop resources inside and outside the chip, in the design of the interface board of the high-density multi-port communication device, the DPLL can be fully configured according to the number of physical ports to realize the clock frequency of the port level. Synchronize. According to the solution provided in this embodiment, hardware performance, power consumption, and design difficulty of the board can be saved while improving the performance of the communication device product.
  • FIG. 8 is a flowchart of a method for implementing port frequency synchronization of a communication device by using a single chip according to an embodiment of the present invention. As shown in FIG. 8, the method includes the following steps:
  • Step S802 The receiving side of the chip Serdes determines whether a valid high-speed serial signal is received, and if yes, executes S804, otherwise, continues to wait;
  • Step S804 The Serdes CDR locking operation recovers the clock information from the high-speed serial code stream outputted by the Serdes receiving side.
  • the CDR state machine enters the locked state, it indicates that the recovery clock of the CDR output is stable and can be provided to the lower-level module.
  • the CDR lock signal triggers the S806 operation;
  • Step S806 The Serdes receiving module 72 determines that the CDR lock and the Serdes receiving state are normal, and outputs a stable recovery clock to the DPLL module 76 corresponding to the port;
  • Step S808 The DPLL module 76 configures corresponding parameters, and configures internal components of the DPLL, such as a phase detector, a filter, and a frequency phase control, according to the requirements of the system for the reference clock of the transmitting side, and waits for the result of the step S810 after the parameters are configured;
  • Step S810 After determining the DPLL lock state, the steps S812, S814 and S816 are performed, in the initial power-on locking process, step S812 is performed; in the lock state, step S816 is performed; in the unlock state, step S814 is performed;
  • Step S812 DPLL free oscillation state, at this time, the DPLL module 76 outputs a free clock, and the free clock frequency is not related to the input clock (same recovery clock as described above);
  • Step S814 The DPLL maintains the state. At this time, during the relocking process of the DPLL, the DPLL module 76 maintains the clock locked at the front to output a fixed frequency clock;
  • Step S816 DPLL lock state, when the DPLL is in the process of locking, the frequency of the clock output by the DPLL module 76 follows the frequency of the input recovered clock;
  • Step S818 The output clock of the DPLL module 76 is sent to the Serdes transmission side phase locked loop, which is multiplied by the phase locked loop to the clock frequency required by the system.
  • the external clock mode scheme requires an expensive BITS device; the line clock mode uses an external phase-locked loop to implement clock recovery, which brings cost, power consumption, and design complexity. Degree and other issues. Due to the complexity of the design, the clock recovery scheme using an external phase-locked loop can not achieve the port-level frequency synchronization.
  • the method and the device in the embodiment of the present invention use the DPLL built by the internal logic resources of the chip to implement the port clock frequency recovery, which can improve the performance of the communication device product, save the hardware cost, and reduce the board. Design difficulty. With the trend of increasing the physical port density of the communication products and increasing the pressure of cost optimization, the port frequency synchronization method provided by this patent is used to design the interface board, which is beneficial to reducing cost and power consumption, and improving the flexibility of the board design.
  • each of the above modules may be implemented by software or hardware.
  • the foregoing may be implemented by, but not limited to, the foregoing modules are all located in the same processor; or, the modules are located in multiple In the processor.
  • Embodiments of the present invention also provide a storage medium.
  • the foregoing storage medium may be configured to store program code for performing the following steps:
  • the digital phase-locked loop DPLL receives the recovered clock of the output, wherein the DPLL is configured using the logic resources of the chip;
  • the above DPLL outputs a clock according to the state in which the DPLL is located.
  • the foregoing storage medium may include, but is not limited to, a USB flash drive, a Read-Only Memory (ROM), and a Random Access Memory (RAM).
  • ROM Read-Only Memory
  • RAM Random Access Memory
  • modules or steps of the present invention described above can be implemented by a general-purpose computing device that can be centralized on a single computing device or distributed across a network of multiple computing devices. Alternatively, they may be implemented by program code executable by the computing device such that they may be stored in the storage device by the computing device and, in some cases, may be different from the order herein.
  • the steps shown or described are performed, or they are separately fabricated into individual integrated circuit modules, or a plurality of modules or steps thereof are fabricated as a single integrated circuit module.
  • the invention is not limited to any specific combination of hardware and software.
  • the clock output method and apparatus provided by the embodiments of the present invention have the following beneficial effects: solving the problems of high equipment cost and complicated PCB design in the related art, thereby reducing equipment cost and PCB design complexity. Effect.

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)

Abstract

本发明提供了一种时钟输出方法及装置，其中，该方法包括：数字锁相环（DPLL）接收输出的恢复时钟，其中，该DPLL是使用芯片的逻辑资源配置的；上述DPLL根据DPLL所处的状态输出时钟。通过本发明，解决了相关技术中存在的设备成本高、印刷电路板（PCB）设计复杂的问题，进而达到了降低设备成本和PCB设计复杂度的效果。

Description

时钟输出方法及装置 技术领域
本发明涉及通信领域，具体而言，涉及一种时钟输出方法及装置。
背景技术
在通信设备应用中，很多接口要求实现发送端能够跟随接收端的频率，称之为定时环回功能(Loop Timing)。例如传统的同步光纤网络(Synchronous Optiical Network，简称为SONET)/同步数字体系(Synchronous Digital Hierarchy，简称为SDH)传输网络，骨干网和城域网中光传送网络(Optical Transport Network，简称为OTN)，分组网络中的同步以太网(Synchronous Ethernet networks)等都有端口间频率同步的需求。在通信设备端口频率同步的系统设计中，相关技术中的端口频率同步实现方案一般采用外部时钟模式和线路时钟模式两种。
图1是相关技术中的外部时钟模式下的端口频率同步示意图。由图1可知，当采用外部时钟模式的端口频率同步方式时，网络设备需要从外部大楼综合定时系统(Building Integrated Timing System，简称为BITS)时钟源中获取时钟信息，这种同步时钟的分发是最可靠的方式，但是在中心机房需要增加昂贵的BITS设备。
图2是相关技术中的线路时钟模式下的端口频率同步示意图，由图2可知，采用线路时钟模式时，第一级网络设备使用外部BITS时钟源，将同步时钟信息从发射端口Tx传递到第二级网络设备的接收端口Rx。第二级网络设备Rx从接收侧恢复出同步时钟信息，同步时钟信息通过时钟数据恢复(Clock Data Recovery，简称为CDR)恢复出来的时钟送到外部窄带锁相环(Phase-Locked Loop，简称为PLL)，经过PLL处理后提供高质量参考时钟给Tx方向物理层协议(Physical Layer Protocol，简称为PHY)模块。采用外部锁相环的方案每个端口都需要一个外部的锁相环来处理恢复时钟，当设计高密度多通道接口板时，该接口板会需要增加很多外部锁相环。这会带来额外的成本，更大的功耗，印刷电路板(Printed Circuit Board，简称为PCB)设计复杂度高等问题。
因此，当需要实现端口频率同步时，采用相关技术中的方案会存在着设备成本高、PCB设计复杂的问题。
针对相关技术中存在的设备成本高、PCB设计复杂的问题，目前尚未提出有效的解决方案。
发明内容
本发明提供了一种时钟输出方法及装置，以至少解决相关技术中存在的设备成本高、PCB设计复杂的问题。
根据本发明的一个方面，提供了一种时钟输出方法，包括：数字锁相环DPLL接收输出的恢复时钟，其中，所述DPLL是使用芯片的逻辑资源配置的；所述DPLL根据所述DPLL所处的状态输出时钟。
可选地，所述DPLL接收输出的所述恢复时钟包括：所述DPLL接收串行器Serdes发送侧输出的恢复时钟；所述DPLL根据所述DPLL所处的状态输出时钟包括：所述DPLL根据所述DPLL处于的状态向串行器Serdes接收侧输出时钟。
可选地，所述DPLL在根据所述DPLL所处的状态输出时钟之前，还包括：所述DPLL按照所述Serdes发送侧的参考时钟的要求配置所述DPLL内部组件的参数，其中，所述DPLL内部组件包括以下至少之一：鉴相器、滤波器、频率相位控制器。
可选地，所述DPLL根据所述DPLL所处的状态输出时钟包括：所述DPLL确定所述DPLL所处的状态，其中，所述状态包括以下之一：自由震荡状态、保持状态、锁定状态；所述DPLL根据确定的状态输出时钟。
可选地，所述DPLL根据确定的状态输出时钟包括：当所述DPLL所处的状态为自由震荡状态时，所述DPLL根据配置的所述DPLL内部组件的参数向所述Serdes发送侧发送一个自由时钟，其中，所述自由时钟的频率与所述恢复时钟的频率不相关；当所述DPLL所处的状态为保持状态时，所述DPLL根据配置的所述DPLL内部组件的参数向所述Serdes发送端发送一个固定频率的时钟，其中，所述固定频率为所述DPLL前面锁定过的时钟的频率；当所述DPLL所处的状态为锁定状态时，所述DPLL根据配置的所述DPLL内部组件的参数对所述恢复时钟进行处理；所述DPLL将处理后的恢复时钟发送给所述Serdes发送侧。
根据本发明的另一方面，提供了一种时钟输出装置，所述装置应用于数字锁相环DPLL中，包括：接收模块，设置为接收输出的恢复时钟，其中，所述DPLL是使用芯片的逻辑资源配置的；输出模块，设置为根据所述DPLL所处的状态输出时钟。
可选地，所述接收模块包括：接收串行器Serdes发送侧输出的恢复时钟；所述输出模块包括：根据所述DPLL处于的状态向串行器Serdes接收侧输出时钟。
可选地，所述装置还包括：配置模块，设置为按照所述Serdes发送侧的参考时钟的要求配置所述DPLL内部组件的参数，其中，所述DPLL内部组件包括以下至少之一：鉴相器、滤波器、频率相位控制器。
可选地，所述输出模块包括：确定单元，设置为确定所述DPLL所处的状态，其中，所述状态包括以下之一：自由震荡状态、保持状态、锁定状态；输出单元，设置为根据确定的状态输出时钟。
可选地，所述输出单元包括：当所述DPLL所处的状态为自由震荡状态时，所述DPLL根据配置的所述DPLL内部组件的参数向所述Serdes发送侧发送一个自由时钟，其中，所述自由时钟的频率与所述恢复时钟的频率不相关；当所述DPLL所处的状态为保持状态时，所述DPLL根据配置的所述DPLL内部组件的参数向所述Serdes发送端发送一个固定频率的时 钟，其中，所述固定频率为所述DPLL前面锁定过的时钟的频率；当所述DPLL所处的状态为锁定状态时，所述DPLL根据配置的所述DPLL内部组件的参数对所述恢复时钟进行处理；所述DPLL将处理后的恢复时钟发送给所述Serdes发送侧。
通过本发明，采用数字锁相环DPLL接收输出的恢复时钟，其中，所述DPLL是使用芯片的逻辑资源配置的；所述DPLL根据所述DPLL所处的状态输出时钟，解决了相关技术中存在的设备成本高、PCB设计复杂的问题，进而达到了降低设备成本和PCB设计复杂度的效果。
附图说明
此处所说明的附图用来提供对本发明的进一步理解，构成本申请的一部分，本发明的示意性实施例及其说明用于解释本发明，并不构成对本发明的不当限定。在附图中：
图1是相关技术中的外部时钟模式下的端口频率同步示意图；
图2是相关技术中的线路时钟模式下的端口频率同步示意图；
图3是根据本发明实施例的时钟输出方法的流程图；
图4是根据本发明实施例的时钟输出装置的结构框图；
图5是根据本发明实施例的时钟输出装置的优选结构框图；
图6是根据本发明实施例的时钟输出装置中输出模块44的结构框图；
图7是根据本发明实施例的单芯片实现通信设备端口频率同步的实现装置示意图；
图8是根据本发明实施例的单芯片实现通信设备端口频率同步的方法流程图。
具体实施方式
下文中将参考附图并结合实施例来详细说明本发明。需要说明的是，在不冲突的情况下，本申请中的实施例及实施例中的特征可以相互组合。
需要说明的是，本发明的说明书和权利要求书及上述附图中的术语“第一”、“第二”等是用于区别类似的对象，而不必用于描述特定的顺序或先后次序。
在本实施例中提供了一种时钟输出方法，图3是根据本发明实施例的时钟输出方法的流程图，如图3所示，该流程包括如下步骤：
步骤S302，数字锁相环DPLL接收输出的恢复时钟，其中，该DPLL是使用芯片的逻辑资源配置的；
步骤S304，上述DPLL根据DPLL所处的状态输出时钟。
通过上述步骤，利用数字锁相环(Digital Phase Locked Loop，简称为DPLL)接收恢复时钟以及输出时钟，并且，该DPLL是利用芯片的逻辑资源配置的数字锁相环，无需占用芯片内部和外部专用锁相环资源，因此，在高密度多端口通信设备接口板设计中，可以完全按照物理端口数量满配DPLL，并且极大的降低了设备成本以及PCB的设计复杂度，从而解决了相关技术中存在的设备成本高、PCB设计复杂的问题，进而达到了降低设备成本和PCB设计复杂度的效果。
在一个可选的实施例中，上述DPLL接收输出的恢复时钟包括：该DPLL接收串行器Serdes发送侧输出的恢复时钟；上述DPLL根据DPLL所处的状态输出时钟包括：该DPLL根据DPLL处于的状态向串行器Serdes接收侧输出时钟。其中，DPLL在接收Serdes发送侧输出的恢复时钟之前，Serdes发送侧可以首先获取恢复时钟，其获取方式可以为多种，下面以一种示例进行说明：Serdes接收侧中的串行器时钟数据恢复Serdes CDR从高速串行码流中恢复时钟信号，即获取恢复时钟。
在一个可选的实施例中，上述DPLL在根据DPLL所处的状态输出时钟之前，还包括：该DPLL按照Serdes发送侧的参考时钟的要求配置DPLL内部组件的参数，其中，该DPLL内部组件包括以下至少之一：鉴相器、滤波器、频率相位控制器。需要说明的是，DPLL按照Serdes发送侧的参考时钟的要求配置DPLL内部组件的参数的操作和上述的数字锁相环DPLL接收输出的恢复时钟的操作的先后顺序可以为多种，DPLL可以先配置DPLL内部组件的参数，然后再接收恢复时钟；也可以先接收恢复时钟，再配置DPLL内部组件的参数；当然，也可以同时接收恢复时钟和配置DPLL内部组件的参数。其中，该DPLL配置上述参数的目的在于输出高质量的时钟。
在一个可选的实施例中，上述DPLL根据DPLL所处的状态输出时钟包括：该DPLL确定DPLL所处的状态，其中，该DPLL所处的状态包括以下之一：自由震荡状态、保持状态、锁定状态；该DPLL根据确定的状态输出时钟。从而确保输出符合传输网络协议对端口时钟抖动指标要求的高质量的时钟频率。
在一个可选的实施例中，上述DPLL根据确定的状态输出时钟包括：当该DPLL所处的状态为自由震荡状态时，DPLL根据配置的DPLL内部组件的参数向Serdes发送侧发送一个自由时钟，其中，该自由时钟的频率与恢复时钟的频率不相关；当该DPLL所处的状态为保持状态时，DPLL根据配置的DPLL内部组件的参数向Serdes发送端发送一个固定频率的时钟，其中，该固定频率为DPLL前面锁定过的时钟的频率；当该DPLL所处的状态为锁定状态时，DPLL根据配置的DPLL内部组件的参数对恢复时钟进行处理；该DPLL将处理后的恢复时钟发送给Serdes发送侧。
通过以上的实施方式的描述，本领域的技术人员可以清楚地了解到根据上述实施例的方法可借助软件加必需的通用硬件平台的方式来实现，当然也可以通过硬件，但很多情况下前者是更佳的实施方式。基于这样的理解，本发明的技术方案本质上或者说对现有技术做出贡献的部分可以以软件产品的形式体现出来，该计算机软件产品存储在一个存储介质(如ROM/RAM、磁碟、光盘)中，包括若干指令用以使得一台终端设备(可以是手机，计算机， 服务器，或者网络设备等)执行本发明各个实施例所述的方法。
在本实施例中还提供了一种时钟输出装置，该装置用于实现上述实施例及优选实施方式，已经进行过说明的不再赘述。如以下所使用的，术语“模块”可以实现预定功能的软件和/或硬件的组合。尽管以下实施例所描述的装置较佳地以软件来实现，但是硬件，或者软件和硬件的组合的实现也是可能并被构想的。
图4是根据本发明实施例的时钟输出装置的结构框图，该装置可以应用于数字锁相环DPLL中，如图4所示，该装置包括接收模块42和输出模块44，下面对该装置进行说明。
接收模块42，设置为接收输出的恢复时钟，其中，该DPLL是使用芯片的逻辑资源配置的；输出模块44，连接至上述接收模块42，设置为根据DPLL所处的状态输出时钟。
在一个可选的实施例中，上述接收模块42包括：接收串行器Serdes发送侧输出的恢复时钟；上述输出模块44包括：根据DPLL处于的状态向串行器Serdes接收侧输出时钟。
图5是根据本发明实施例的时钟输出装置的优选结构框图，如图5所示，该装置除包括图4所示的所有模块外，还包括配置模块52，下面对该装置进行说明。
配置模块52，连接至上述输出模块44，设置为按照Serdes发送侧的参考时钟的要求配置DPLL内部组件的参数，其中，该DPLL内部组件包括以下至少之一：鉴相器、滤波器、频率相位控制器。
图6是根据本发明实施例的时钟输出装置中输出模块44的结构框图，如图6所示，该输出模块44包括确定单元62和输出单元64，下面对该输出模块44进行说明。
确定单元62，设置为确定DPLL所处的状态，其中，该状态包括以下之一：自由震荡状态、保持状态、锁定状态；输出单元64，连接至上述确定单元62，设置为根据确定的状态输出时钟。
在一个可选的实施例中，上述输出单元64包括：当DPLL所处的状态为自由震荡状态时，该DPLL根据配置的DPLL内部组件的参数向Serdes发送侧发送一个自由时钟，其中，该自由时钟的频率与恢复时钟的频率不相关；当DPLL所处的状态为保持状态时，该DPLL根据配置的DPLL内部组件的参数向Serdes发送端发送一个固定频率的时钟，其中，该固定频率为DPLL前面锁定过的时钟的频率；当DPLL所处的状态为锁定状态时，该DPLL根据配置的DPLL内部组件的参数对恢复时钟进行处理；DPLL将处理后的恢复时钟发送给Serdes发送侧。
为解决上述两种相关技术中的端口频率同步方案存在的问题，本发明实施例中还提出了一种利用单芯片实现通信设备端口频率同步的装置和方法，利用芯片内部逻辑实现的DPLL来处理线路恢复时钟，并且，在配置了DPLL的相关参数后，能够输出高质量的参考时钟给发送端，从而实现通信设备上各端口的频率同步。下面对该装置及方法进行说明。
图7是根据本发明实施例的单芯片实现通信设备端口频率同步的实现装置示意图，如图7 所示，该装置包括以下模块：
Serdes接收模块72、Serdes发送模块74和DPLL模块76(同上述的接收模块42、输出模块44和配置模块52)，下面对该装置进行说明。
Serdes接收模块72和Serdes发送模块74是高速串行接口的接收和发送处理模块。DPLL模块76设置为实现端口频率同步。其中，Serdes接收模块72、Serdes发送模块74和DPLL模块76之间的关系如下。
Serdes接收模块72跟光模块接收侧互联，除了实现基本的串行数据接收、串并转换和解码以外，主要利用Serdes CDR模块输出恢复时钟送给DPLL模块76进行处理。
DPLL模块76主要实现对CDR恢复时钟的锁定，并根据配置参数，生成相应高质量时钟给Serdes发送模块74。DPLL模块76中的DPLL控制模块需要根据DPLL锁定状态实现自由振荡、保持和锁定三种状态的切换，确保输出符合传输网络协议对端口时钟抖动指标要求的高质量时钟频率。
在系统设计中，每个物理端口都应配有独立的DPLL。由于DPLL完全是由逻辑单元实现，不占用芯片内部和外部专用锁相环资源，因此在高密度多端口通信设备接口板设计中，可以完全按照物理端口数量满配置DPLL，实现端口级别的时钟频率同步。按照该实施例中提供的解决方案，可以在提升通信设备产品性能的同时，节约硬件成本、功耗和降低单板的设计难度。
图8是根据本发明实施例的单芯片实现通信设备端口频率同步的方法流程图，如图8所示，该方法包括如下步骤，：
步骤S802：芯片Serdes接收侧判断是否接收到有效的高速串行信号，如收到则执行S804，否则，继续等待；
步骤S804：Serdes CDR锁定操作，从Serdes接收侧输出的高速串行码流中恢复时钟信息，当CDR状态机进入锁定状态，表明此时CDR输出的恢复时钟已经稳定，可以提供给下级模块使用，CDR锁定信号触发S806操作；
步骤S806：Serdes接收模块72判断CDR锁定和Serdes接收状态等正常后，输出稳定的恢复时钟给该端口对应的DPLL模块76；
步骤S808：DPLL模块76配置相应参数，按照系统对发送侧参考时钟的要求配置DPLL内部组件，例如鉴相器、滤波器和频率相位控制等参数，参数配置好后等待S810步骤的结果；
步骤S810：判断DPLL锁定状态后，执行S812、S814和S816三个步骤，在初始化上电锁定过程中，执行步骤S812；在锁定状态下，执行步骤S816；在失锁状态下，执行步骤S814；
步骤S812：DPLL自由振荡状态，此时DPLL模块76输出一个自由时钟，自由时钟频率跟输入时钟(同上述的恢复时钟)不相关；
步骤S814：DPLL保持状态，此时DPLL在重新锁定过程中，DPLL模块76保持前面锁定的频率输出固定频率的时钟；
步骤S816：DPLL锁定状态，此时DPLL在锁定过程中，DPLL模块76输出的时钟的频率跟随输入的恢复时钟的频率；
步骤S818：DPLL模块76输出时钟送给Serdes发送侧锁相环，由锁相环倍频至系统所需要时钟频率。
综上可知，相关技术中的实现通信设备端口频率同步的方法中，外部时钟模式方案需要昂贵的BITS设备；线路时钟模式使用外部锁相环来实现时钟恢复会带来成本、功耗和设计复杂度等问题。由于设计的复杂度等问题，使用外部锁相环实现时钟恢复的方案往往无法做到端口级别的频率同步，只能降低性能实现单板级别的时钟恢复。采用本发明实施例中的方法和装置，与相关技术相比，使用芯片内部逻辑资源搭建的DPLL来实现端口时钟频率恢复，可以在提升通信设备产品性能的同时，节约硬件成本和降低单板的设计难度。随着通信产品物理端口密度提高和成本优化压力增大的趋势下，使用本专利提供的端口频率同步方法来设计接口单板，有利于降低成本和降低功耗，提高单板设计灵活性。
需要说明的是，上述各个模块是可以通过软件或硬件来实现的，对于后者，可以通过以下方式实现，但不限于此：上述模块均位于同一处理器中；或者，上述模块分别位于多个处理器中。
本发明的实施例还提供了一种存储介质。可选地，在本实施例中，上述存储介质可以被设置为存储用于执行以下步骤的程序代码：
S1，数字锁相环DPLL接收输出的恢复时钟，其中，该DPLL是使用芯片的逻辑资源配置的；
S2，上述DPLL根据DPLL所处的状态输出时钟。
可选地，在本实施例中，上述存储介质可以包括但不限于：U盘、只读存储器(Read-Only Memory，简称为ROM)、随机存取存储器(Random Access Memory，简称为RAM)、移动硬盘、磁碟或者光盘等各种可以存储程序代码的介质。
可选地，本实施例中的具体示例可以参考上述实施例及可选实施方式中所描述的示例，本实施例在此不再赘述。
显然，本领域的技术人员应该明白，上述的本发明的各模块或各步骤可以用通用的计算装置来实现，它们可以集中在单个的计算装置上，或者分布在多个计算装置所组成的网络上，可选地，它们可以用计算装置可执行的程序代码来实现，从而，可以将它们存储在存储装置中由计算装置来执行，并且在某些情况下，可以以不同于此处的顺序执行所示出或描述的步骤，或者将它们分别制作成各个集成电路模块，或者将它们中的多个模块或步骤制作成单个集成电路模块来实现。这样，本发明不限制于任何特定的硬件和软件结合。
以上所述仅为本发明的优选实施例而已，并不用于限制本发明，对于本领域的技术人员来说，本发明可以有各种更改和变化。凡在本发明的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本发明的保护范围之内。
工业实用性
如上所述，本发明实施例提供的一种时钟输出方法及装置具有以下有益效果：解决了相关技术中存在的设备成本高、PCB设计复杂的问题，进而达到了降低设备成本和PCB设计复杂度的效果。

Claims (10)

  1. 一种时钟输出方法，包括：
    数字锁相环DPLL接收输出的恢复时钟，其中，所述DPLL是使用芯片的逻辑资源配置的；
    所述DPLL根据所述DPLL所处的状态输出时钟。
  2. 根据权利要求1所述的方法，其中，
    所述DPLL接收输出的所述恢复时钟包括：所述DPLL接收串行器Serdes发送侧输出的恢复时钟；
    所述DPLL根据所述DPLL所处的状态输出时钟包括：所述DPLL根据所述DPLL处于的状态向串行器Serdes接收侧输出时钟。
  3. 根据权利要求2所述的方法，其中，所述DPLL在根据所述DPLL所处的状态输出时钟之前，还包括：
    所述DPLL按照所述Serdes发送侧的参考时钟的要求配置所述DPLL内部组件的参数，其中，所述DPLL内部组件包括以下至少之一：鉴相器、滤波器、频率相位控制器。
  4. 根据权利要求3所述的方法，其中，所述DPLL根据所述DPLL所处的状态输出时钟包括：
    所述DPLL确定所述DPLL所处的状态，其中，所述状态包括以下之一：自由震荡状态、保持状态、锁定状态；
    所述DPLL根据确定的状态输出时钟。
  5. 根据权利要求4所述的方法，其中，所述DPLL根据确定的状态输出时钟包括：
    当所述DPLL所处的状态为自由震荡状态时，所述DPLL根据配置的所述DPLL内部组件的参数向所述Serdes发送侧发送一个自由时钟，其中，所述自由时钟的频率与所述恢复时钟的频率不相关；
    当所述DPLL所处的状态为保持状态时，所述DPLL根据配置的所述DPLL内部组件的参数向所述Serdes发送端发送一个固定频率的时钟，其中，所述固定频率为所述DPLL前面锁定过的时钟的频率；
    当所述DPLL所处的状态为锁定状态时，所述DPLL根据配置的所述DPLL内部组件的参数对所述恢复时钟进行处理；所述DPLL将处理后的恢复时钟发送给所述Serdes发送侧。
  6. 一种时钟输出装置，应用于数字锁相环DPLL中，包括：
    接收模块，设置为接收输出的恢复时钟，其中，所述DPLL是使用芯片的逻辑资源 配置的；
    输出模块，设置为根据所述DPLL所处的状态输出时钟。
  7. 根据权利要求6所述的装置，其中，
    所述接收模块包括：接收串行器Serdes发送侧输出的恢复时钟；
    所述输出模块包括：根据所述DPLL处于的状态向串行器Serdes接收侧输出时钟。
  8. 根据权利要求7所述的装置，其中，还包括：
    配置模块，设置为按照所述Serdes发送侧的参考时钟的要求配置所述DPLL内部组件的参数，其中，所述DPLL内部组件包括以下至少之一：鉴相器、滤波器、频率相位控制器。
  9. 根据权利要求8所述的装置，其中，所述输出模块包括：
    确定单元，设置为确定所述DPLL所处的状态，其中，所述状态包括以下之一：自由震荡状态、保持状态、锁定状态；
    输出单元，设置为根据确定的状态输出时钟。
  10. 根据权利要求9所述的装置，其中，所述输出单元包括：
    当所述DPLL所处的状态为自由震荡状态时，所述DPLL根据配置的所述DPLL内部组件的参数向所述Serdes发送侧发送一个自由时钟，其中，所述自由时钟的频率与所述恢复时钟的频率不相关；
    当所述DPLL所处的状态为保持状态时，所述DPLL根据配置的所述DPLL内部组件的参数向所述Serdes发送端发送一个固定频率的时钟，其中，所述固定频率为所述DPLL前面锁定过的时钟的频率；
    当所述DPLL所处的状态为锁定状态时，所述DPLL根据配置的所述DPLL内部组件的参数对所述恢复时钟进行处理；所述DPLL将处理后的恢复时钟发送给所述Serdes发送侧。
PCT/CN2015/092033 2015-05-19 2015-10-15 时钟输出方法及装置 WO2016184018A1 (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201510257408.1 2015-05-19
CN201510257408.1A CN106301748A (zh) 2015-05-19 2015-05-19 时钟输出方法及装置

Publications (1)

Publication Number Publication Date
WO2016184018A1 true WO2016184018A1 (zh) 2016-11-24

Family

ID=57319258

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2015/092033 WO2016184018A1 (zh) 2015-05-19 2015-10-15 时钟输出方法及装置

Country Status (2)

Country Link
CN (1) CN106301748A (zh)
WO (1) WO2016184018A1 (zh)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116846530B (zh) * 2023-06-29 2024-03-19 北京邮电大学 基于全网时钟频率同步的光交换网络、数据发送及接收方法

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1325186A (zh) * 2000-08-31 2001-12-05 深圳市中兴通讯股份有限公司 一种能抑制时钟低频漂移的数字锁相环方法
EP1351418A2 (en) * 2002-04-02 2003-10-08 Northrop Grumman Space Technology & Missions Systems Corp. Radio frequency integrated circuit for loopback self-test
CN2831617Y (zh) * 2005-08-22 2006-10-25 中兴通讯股份有限公司 一种数字锁相环装置
CN1867119A (zh) * 2005-12-02 2006-11-22 华为技术有限公司 一种射频远端模块中时钟恢复方法和装置

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6924678B2 (en) * 2003-10-21 2005-08-02 Altera Corporation Programmable phase-locked loop circuitry for programmable logic device

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1325186A (zh) * 2000-08-31 2001-12-05 深圳市中兴通讯股份有限公司 一种能抑制时钟低频漂移的数字锁相环方法
EP1351418A2 (en) * 2002-04-02 2003-10-08 Northrop Grumman Space Technology & Missions Systems Corp. Radio frequency integrated circuit for loopback self-test
CN2831617Y (zh) * 2005-08-22 2006-10-25 中兴通讯股份有限公司 一种数字锁相环装置
CN1867119A (zh) * 2005-12-02 2006-11-22 华为技术有限公司 一种射频远端模块中时钟恢复方法和装置

Also Published As

Publication number Publication date
CN106301748A (zh) 2017-01-04

Similar Documents

Publication Publication Date Title
EP1388975B1 (en) System and method for data transition control in a multirate communication system
WO2019153810A1 (zh) 传输信号的方法、驱动器及系统
USRE48130E1 (en) Method for switching master/slave timing in a 1000Base-T link without traffic disruption
US6266799B1 (en) Multi-phase data/clock recovery circuitry and methods for implementing same
US9215092B2 (en) Clock selection for synchronous Ethernet
US9791887B2 (en) Synchronization of a data signal
US9054823B2 (en) Synchronous network device
CN107528585A (zh) 具有电超负载保护电路的锁相回路
CN104052561A (zh) 同步网络应用内的传输参考信号清理
CN113406993A (zh) 基于恢复时钟的fpga芯片时钟域同步方法及相关设备
KR20150038213A (ko) 복수의 통신 채널들 사이의 직렬 통신 포트를 공유하기 위한 시스템들 및 방법들
US11888586B2 (en) Low latency network device and method for treating received serial data
US8995596B1 (en) Techniques for calibrating a clock signal
US8675798B1 (en) Systems, circuits, and methods for phase inversion
JP6077097B2 (ja) 多重シリアルメディア独立インターフェース
WO2016184018A1 (zh) 时钟输出方法及装置
US9166769B2 (en) Data transmission method and data restoration method
JP5704988B2 (ja) 通信装置
WO2017059822A1 (zh) 一种芯片间的通信方法、系统及计算机存储介质
CN105227288B (zh) Gmii数据发送方法和装置
US9008128B2 (en) Low-cost port synchronization method in multiport Ethernet devices
KR101396912B1 (ko) ＳｅｒＤｅｓ 네트워크에서의 직렬 링크 동기화 방법
WO2018196833A1 (zh) 报文发送方法和报文接收方法及装置
WO2012048561A1 (zh) 时隙交叉多通道对齐的方法及系统
US8111794B2 (en) Data synchronizer for synchronizing data and communication interface including the same

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 15892396

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 15892396

Country of ref document: EP

Kind code of ref document: A1