WO2017059822A1 - 一种芯片间的通信方法、系统及计算机存储介质 - Google Patents

一种芯片间的通信方法、系统及计算机存储介质 Download PDF

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Publication number
WO2017059822A1
WO2017059822A1 PCT/CN2016/101661 CN2016101661W WO2017059822A1 WO 2017059822 A1 WO2017059822 A1 WO 2017059822A1 CN 2016101661 W CN2016101661 W CN 2016101661W WO 2017059822 A1 WO2017059822 A1 WO 2017059822A1
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port
mac
clock
chip
sending
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PCT/CN2016/101661
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English (en)
French (fr)
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李刚
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深圳市中兴微电子技术有限公司
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter

Definitions

  • the present invention relates to communication technologies, and in particular, to a method and system for communication between chips and a computer storage medium.
  • the mainstream communication method that is well known is: when the media access control (MAC) transmits the data in the memory, the parallel data is converted into a physical interface transceiver (PHY) to The serial data is then sent through the network port; after the data arrives at the peer end, it is received by the network port of the opposite end, and then the data is converted by the PHY through the network port, and then the data is sent by the MAC to the corresponding memory to complete two Data transfer between devices.
  • the advantage of this method is that the cost of the line is greatly reduced by reducing the number of communication cables between the devices in the case of long-distance transmission.
  • MAC+PHY+PHY+MAC mode the implementation of the MAC+PHY+PHY+MAC mode follows the inherent thinking mode, removes the network port on the original basis, and directly uses the board level between the PHYs of the two chips. Compared with the original scheme, this method not only ensures the communication performance between the chips, but also solves the problem that the network port is poorly contacted due to multiple insertions and removals.
  • inter-chip communication does not require PHY to implement data serial-to-parallel conversion, ie, Using the serial-to-parallel conversion function of the PHY, the extra PHY+PHY line between the chips will make the circuit structure between the chips more complicated. 2. If the PHY and a series of circuits around him have a problem, it will directly affect the MAC. The link between the links greatly increases the probability of circuit failure.
  • embodiments of the present invention are expected to provide a method, system, and computer storage medium for communication between chips, simplifying hardware structure, reducing cost, and improving communication reliability.
  • An embodiment of the present invention provides an inter-chip communication system, where the communication system includes: a first chip and a second chip; the first chip includes a first media access controller (MAC), and the second chip Including a second MAC;
  • the communication system includes: a first chip and a second chip; the first chip includes a first media access controller (MAC), and the second chip Including a second MAC;
  • MAC media access controller
  • the first MAC sending port is connected to the second MAC receiving port, and the first MAC receiving port is connected to the second MAC sending port; wherein the first MAC sending port, the first MAC receiving port, the second MAC sending port, and the second The MAC receiving port is a port in the same MAC interface mode;
  • the first MAC sending port is configured to use a sending working clock of the first MAC, and send the first data to the second MAC receiving port;
  • the second MAC receiving port is configured to receive the first data by using a sending MAC address of the first MAC
  • the second MAC sending port is configured to use a sending working clock of the second MAC, and send the second data to the first MAC receiving port;
  • the first MAC receiving port is configured to receive the second data by using a transmit clock of the second MAC.
  • the same MAC interface mode includes one of the following interface modes: a media independent interface (MII) interface mode, a simplified media independent interface (RMII) interface mode, and a serial media independent interface (SMII) interface mode.
  • MII media independent interface
  • RMII media independent interface
  • SMII serial media independent interface
  • GMII Gigabit Media Independent Interface
  • RGMII simplified Gigabit Media Independent Interface
  • SGMII Serial Gigabit Media Independent Interface
  • the first working clock port of the first MAC and the second working clock port of the second MAC are connected to the same clock source.
  • the first chip further includes a first clock output port;
  • the first working clock port and the second working clock port are connected to the same clock source through the first clock output port.
  • the first working clock port and the second working clock port are connected to the same clock source; the same clock source is located at the same When the outside of the first chip and the second chip are described;
  • the first working clock port and the second working clock port are directly connected to the same clock source.
  • the first working clock port and the second working clock port are connected to the same clock source; the same clock source is located at the same
  • the first chip further includes a first clock output port, and the second chip further includes a second clock input port;
  • the first working clock port is connected to the same clock source
  • the second working clock port sequentially connects the same clock source through the second clock input port and the first clock output port.
  • the first working clock port and the second working clock port are connected to the same clock source; the same clock source is located at the same When the first chip and the second chip are external, the first chip further includes a first clock input port, and the second chip further includes a second clock input port;
  • the first working clock port is connected to the same clock source through a first clock input port;
  • the second working clock port is connected to the same clock source through a second clock input port.
  • the first working clock port and the second working clock port are Connected to different clock sources;
  • the first chip further includes a first clock source and a first clock output port, and the second chip further includes a second clock source and a second clock output port;
  • the receiving clock input port of the first working clock port is connected to the second clock source through a second clock output port, and the other port of the first working clock port is connected to the first clock source;
  • the receiving clock input port of the second working clock port is connected to the first clock source through a first clock output port; the other port of the second working clock port is connected to the second clock source.
  • the physical layer PHY configuration clock MDC port is suspended, and the remaining ports are connected to 0.
  • the embodiment of the invention further provides a communication method for applying the above-mentioned communication system between chips, the method comprising:
  • the first MAC sending port uses the sending working clock of the first MAC, and sends the first data to the second MAC receiving port;
  • the second MAC receiving port receives the first data by using a sending AND clock of the first MAC
  • the second MAC sending port uses the sending working clock of the second MAC to send the second data to the first MAC receiving port;
  • the first MAC receiving port receives the second data by using a transmit clock of the second MAC.
  • the embodiment of the invention further provides a computer storage medium, wherein the computer storage medium stores computer executable instructions, and the computer executable instructions are used to execute the inter-chip communication method according to the embodiment of the invention.
  • Embodiments of the present invention provide an inter-chip communication method, system, and computer storage medium, which directly interconnect a transceiver port of a MAC on two chips in the same MAC interface mode, and between MACs on two chips.
  • the data transmission uses the respective associated clocks, so that the MAC between the two chips can accurately perform data interaction.
  • the two MACs are directly interconnected, simplifying the connection between the first chip and the second chip.
  • the interconnect structure the data does not need to go through some complicated intermediate processing (such as PHY processing), directly through the MAC transmission; the hardware structure saves the two PHY and PHY related circuits, saving the hardware cost of this part, due to the reduction These circuits reduce the influence of the intermediate circuit and the electromagnetic environment on the data signal, reduce the data error probability, and improve the reliability and stability of the data transmission.
  • some complicated intermediate processing such as PHY processing
  • the circuit uses fewer basic circuit components, the power consumption of the original inter-chip interconnect circuit is also saved, thereby reducing the power consumption of the entire device; since the two MACs are directly interconnected, the PHY is no longer operated on the software. It also simplifies the software implementation process, and only needs to configure two MACs according to the same duplex mode and speed mode;
  • the data communication between the two chips is not limited by the bottleneck limit of 100 Mbps (currently most devices use 100 Mbps) without any increase in cost, and data transmission can be realized more efficiently. Use this model to save costs The effect is more obvious.
  • FIG. 1 is a structural block diagram of an inter-chip communication system according to Embodiment 1 of the present invention.
  • FIG. 2 is a structural block diagram of a communication system between chips in an MII interface mode according to Embodiment 2 of the present invention
  • FIG. 3 is a structural block diagram of a communication system between chips in an RMII interface mode according to Embodiment 2 of the present invention.
  • FIG. 4 is a structural block diagram of a communication system between chips in a GMII interface mode according to Embodiment 2 of the present invention.
  • FIG. 5 is a structural block diagram of a communication system between chips in an RGMII interface mode according to Embodiment 2 of the present invention.
  • FIG. 6 is a structural block diagram of a communication system between chips in an SMII interface mode according to Embodiment 2 of the present invention.
  • FIG. 7 is a structural block diagram of a communication system between chips in an SGMII interface mode according to Embodiment 2 of the present invention.
  • FIG. 8 is a schematic flowchart of a method for communication between chips according to Embodiment 3 of the present invention.
  • An embodiment of the present invention provides an inter-chip communication system.
  • the communication system includes: a first chip and a second chip; the first chip includes a first MAC 1, and the second chip Includes the second MAC 2.
  • the MAC interconnection between the first chip and the second chip is:
  • the first MAC sending port 10 is connected to the second MAC receiving port 21, and the first MAC receiving port 11 is connected to the second MAC sending port 20; wherein the first MAC sending port 10, A MAC receiving port 11, a second MAC sending port 20, and a second MAC receiving port 21 are ports in the same MAC interface mode.
  • the first MAC sending port 10, the first MAC receiving port 11, the second MAC sending port 20, and the second MAC receiving port 21 are ports in the same MAC interface mode; and the ports are correspondingly connected, so The first MAC sending port 10 can send data to the second MAC receiving port 21, and the second MAC sending port 20 can also send data to the first MAC receiving port 11, that is, the first MAC 1 and the second. Direct communication between MAC 2 is possible.
  • the first working clock port 12 of the first MAC and the second working clock port 22 of the second MAC are connected to the clock source 3; as an implementation manner, the clock source 3 is The same clock source, that is, the first working clock port 12 and the second working clock port 22 are connected to the same clock source, so that the clocks used for receiving and transmitting the first MAC and the second MAC are common sources. It ensures that the data between the two MACs can be transmitted correctly.
  • the clock source 3 can also be a different clock source, that is, the first working clock port 12 is connected to a clock source, and the second working clock port 22 is connected to another clock source.
  • the same clock source may be located on the first chip or on the second chip, or may be located outside the first chip and the second chip as shown in FIG. 1 .
  • This embodiment of the present invention does not limit this.
  • the first MAC sending port 10 is configured to use the sending working clock of the first MAC to send the first data to the second MAC receiving port 21; the second MAC receiving port 21 is configured to adopt the first MAC Transmitting the associated clock to receive the first data;
  • the second MAC sending port 20 is configured to use a sending working clock of the second MAC, and send the second data to the second MAC receiving port 11; the first MAC receiving port 11, The second data is received by using a transmit path clock of the second MAC.
  • the MAC between the two chips can accurately perform data interaction, and the first MAC and the second MAC are directly interconnected, thereby simplifying the interconnection structure between the first chip and the second chip.
  • the data is transmitted directly through the MAC without some complicated intermediate processing; the first MAC and the second MAC are directly interconnected, and the two PHY and PHY related circuits are saved, which saves the hardware cost of this part, due to the reduction of the middle
  • the link circuit reduces the influence of the intermediate circuit and the electromagnetic environment on the data signal, reduces the data error probability, and improves the reliability and stability of the data transmission.
  • the circuit uses fewer basic circuit components, the power consumption of the original inter-chip interconnect circuit is also saved, thereby reducing the power consumption of the entire device; since the first MAC and the second MAC are directly interconnected, the software is no longer correct.
  • the operation of the PHY also simplifies the software implementation process, and only needs to configure the MACs at both ends according to the same duplex mode and speed mode;
  • the data communication between the two chips is not limited by the bottleneck limit of 100 Mbps (currently most devices use 100 Mbps) without any increase in cost, and data transmission can be realized more efficiently. This mode is more effective in terms of cost savings.
  • An embodiment of the present invention provides an inter-chip communication system.
  • the communication system includes: a first chip and a second chip; the first chip includes a first MAC 1, and the second chip Includes the second MAC 2.
  • the MAC is interconnected between the first chip and the second chip, and the interconnected port is in the same MAC interface mode: Media Independent Interface (MII) interface mode.
  • MII Media Independent Interface
  • the first MAC sending port includes: a data sending port TXD[3:0] label 1021 of the first MAC 1, a data sending enable port TX_EN label 1022, and a data sending error prompting port TX_ER label. 1023.
  • the second MAC receiving port includes: The data receiving port RXD[3:0] number 2121 of the second MAC 2, the data reception valid indication port RX_DV port 2122, and the data reception error prompting port RX_ER number 2123.
  • the first MAC sending port is connected to the second MAC receiving port, as shown in FIG. 2, the port 1021 is connected to the port 2121, the port 1022 is connected to the port 2122, and the port 1023 is connected to the port 2123.
  • the first MAC receiving port includes a data receiving port RXD[3:0] number 1121 of the first MAC 1, a data receiving valid indication port RX_DV port 1122, and a data receiving error prompting port RX_ER number 1123.
  • the second MAC sending port includes: a data sending port TXD[3:0] number 2021 of the second MAC 2, a data sending enable port TX_EN number 2022, and a data sending error prompting port TX_ER number 2023.
  • the first MAC receiving port is connected to the second MAC sending port, as shown in FIG. 2, the port 1121 is connected to the port 2021, the port 1122 is connected to the port 2022, and the port 1123 is connected to the port 2023.
  • the first chip when the same clock source 3 is located in the first chip, the first chip further includes a first clock output port; the first working clock port is a receiving clock port 1221 of the first MAC and is sent.
  • the clock port 1222 and the second working clock port, that is, the receiving clock port 2221 and the transmitting clock port 2222 of the second MAC are both connected to the same clock source 3 through the first clock output port 3121.
  • the same clock source 3 in FIG. 2 is a phase locked loop (PLL) that can generate a 25 MHz/2.5 MHz clock. If the transmission speed is 100 Mbps, the generated clock is 25 MHz, if the transmission is performed. At a speed of 10 Mbps, the resulting clock is 2.5 MHz.
  • PLL phase locked loop
  • the same clock source 3 is located on the first chip.
  • the same clock source may also be located on the second chip.
  • a working clock port that is, a receiving clock port 1221 (rx_clk_i) and a transmitting clock port 1222 (tx_clk_i) of the first MAC, and a receiving clock port 2221 (rx_clk_i) and a transmitting clock port 2222 of the second working clock port, that is, the second MAC ( Tx_clk_i) passes through the first chip
  • the first clock output port is connected to the same clock source.
  • the same clock source may also be located outside the first chip and the second chip. At this time, the first working clock port and the second working clock port are also directly connected to the same Clock source.
  • the first MAC may send data to the second MAC through a connection between the port 1021 and the port 2121; through the connection between the port 2021 and the port 1121, the second MAC may Transmitting data to the first MAC; each of the other interconnected ports provides various indications and an operating clock to ensure accurate data transmission between the first MAC and the second MAC.
  • the functions of the ports in the MII interface mode are the same as those in the prior art, and are not described here.
  • the two MAC jobs can only be full-duplex communication and require software to configure them to the same speed mode.
  • MII interface mode only the port shown in FIG. 2 is used, and no other port is used. Therefore, among the ports where the first MAC and the second MAC are not connected, the PHY configuration clock MDC port is suspended, and the remaining ports are connected to 0.
  • An embodiment of the present invention provides an inter-chip communication system.
  • the communication system includes: a first chip and a second chip; the first chip includes a first MAC 1, and the second chip Includes the second MAC 2.
  • the MAC connection between the first chip and the second chip is the same MAC interface mode: the simplified media independent interface (RMII) interface mode.
  • RMII media independent interface
  • the first MAC 1 sending port includes: a data sending port TXD[1:0] number 1031 of the first MAC 1, a data sending enable port TX_EN number 1032, and the second MAC receiving.
  • the port includes: a data receiving port RXD[1:0] label 2131 of the second MAC 2, and a data receiving valid indication port RX_DV port 2132.
  • the first MAC sending port is connected to the second MAC receiving port, as shown in FIG. 3, the port 1031 is connected to the port 2131, and the port 1032 is connected to the port 2132.
  • the first MAC receiving port includes a data receiving port RXD[1:0] label 1131 of the first MAC 1, a data receiving valid indication port RX_DV port 1132, and the second MAC sending port includes The data transmission port TXD[1:0] of the second MAC 2 is labeled 2031, and the data transmission enable port TX_EN is numbered 2032.
  • the first MAC receiving port is connected to the second MAC sending port, as shown in FIG. 3, the port 1131 is connected to the port 2031, and the port 1132 is connected to the port 2032.
  • the first chip when the same clock source 3 is located in the first chip, the first chip further includes a first clock output port Chip1_rmii_clk_o numbered 3131, and the second chip further includes a second clock input port Chip2_rmii_clk_i
  • the label is 3231.
  • the first working clock port that is, the receiving clock port 1231 (rx_clk_i) of the first MAC and the transmitting clock port 1232 (tx_clk_i) directly connect the same clock source to the 2/20 frequency after the first chip, and the RMII clock is connected.
  • the port 1233 (rmii_clk_i) directly connects to the same clock source inside the first chip, and the same clock source sequentially passes through the first clock output port 3131 and the second clock input port 3231, and then performs a 2/20 frequency division connection.
  • a receiving clock port 2231 (rx_clk_i), a transmitting clock port 2232 (tx_clk_i), and a RMII clock port 2233 (rmii_clk_i) in the second working clock port sequentially pass through the second clock input port 3231 and the first clock output port.
  • 3131 connects the same clock source 3.
  • the same clock source 3 in FIG. 3 is a PLL that can generate a 50 MHz clock.
  • the same clock source 3 may be located on the first chip.
  • the same clock source may also be located on the second chip.
  • a first clock input port is required on the first chip
  • a second clock output port is required on the second chip
  • the second working clock port is directly connected to the same clock source in the second chip.
  • the first working clock port needs to connect the same clock source through the first clock input port on the first chip and the second clock output port on the second chip in sequence.
  • the same clock source may also be located outside the first chip and the second chip.
  • the first chip further includes a first clock input port
  • the second chip further includes A second clock input port is included; the first working clock port is connected to the same clock source through a first clock input port; and the second working clock port is connected to the same clock source through a second clock input port.
  • the first MAC may send data to the second MAC through a connection between the port 1031 and the port 2131; through the connection between the port 2031 and the port 1131, the second MAC may Transmitting data to the first MAC; each of the other interconnected ports provides various indications and an operating clock to ensure accurate data transmission between the first MAC and the second MAC.
  • the functions of the ports in the RMII interface mode are the same as those in the prior art, and are not described here.
  • the two MAC jobs can only be full-duplex communication and require software to configure them to the same speed mode.
  • the RMII interface mode only the port shown in FIG. 3 is used, and no other port is used. Therefore, among the ports where the first MAC and the second MAC are not connected, the MDC port is suspended, and the remaining ports are connected to 0.
  • An embodiment of the present invention further provides an inter-chip communication system.
  • the communication system includes: a first chip and a second chip; the first chip includes a first MAC 1, and the second The chip includes a second MAC 2.
  • the MAC is interconnected between the first chip and the second chip, and the interconnected ports are in the same MAC interface mode: Gigabit Media Independent Interface (GMII) interface mode.
  • GMII Gigabit Media Independent Interface
  • the first MAC sending port includes: a data sending port TXD[7:0] label 1041 of the first MAC 1, a data sending enable port TX_EN label 1042, and a data sending error prompting port TX_ER label. 1043.
  • the second MAC receiving port includes: a data receiving port RXD[7:0] number 2141 of the second MAC 2, a data receiving valid indication port RX_DV port 2142, and a data receiving error prompting port RX_ER number 2143.
  • First MAC The sending port is connected to the second MAC receiving port, as shown in FIG. 4, the port 1041 is connected to the port 2141, the port 1042 is connected to the port 2142, and the port 1043 is connected to the port 2143.
  • the first MAC receiving port includes a data receiving port RXD[7:0] of the first MAC 1 and a data receiving valid indication port RX_DV port 1142, and a data receiving error prompting port RX_ER number 1143.
  • the second MAC sending port includes: a data sending port TXD[7:0] number 2041 of the second MAC 2, a data sending enable port TX_EN label 2042, and a data sending error prompting port TX_ER number 2043.
  • the first MAC receiving port is connected to the second MAC sending port, as shown in FIG. 4, the port 1141 is connected to the port 2041, the port 1142 is connected to the port 2042, and the port 1143 is connected to the port 2043.
  • the first chip further includes a first clock source 3 and a first clock output port GTX_CLK_O numbered 3141
  • the second chip further includes a second clock source 4 and a second clock output port GTX_CLK_O number. It is 3241.
  • the receiving clock port 1241 (rx_clk_i) of the first MAC in the first working clock port is connected to the second clock source 4 through the second clock output port 3241, and the other ports in the first working clock port are sending clocks.
  • the port 1242 (tx_clk_i) is directly connected to the first clock source 3 in the first chip, and the second working clock port, that is, the receiving clock port 2241 (rx_clk_i) of the second MAC is connected through the first clock output port 3141.
  • a clock source 3, the other of the second working clock ports, that is, the transmit clock port 2242 (tx_clk_i) is directly connected to the second clock source 4 inside the second chip.
  • first clock source 3 and the second clock source 4 in FIG. 4 are respectively PLLs that can generate a 125 MHz clock.
  • the first MAC may send data to the second MAC through a connection between the port 1041 and the port 2141; through the connection between the port 2041 and the port 1141, the second MAC may Transmitting data to the first MAC; each of the interconnected ports provides various indications and an operating clock to ensure accurate between the first MAC and the second MAC Data transmission.
  • the functions of the ports in the GMII interface mode are the same as those in the prior art, and are not described here.
  • the two MAC operations can only be full-duplex communication, and software is required to configure it to a speed mode of 1000 Mbps.
  • the GMII interface mode only the port shown in FIG. 4 is used, and no other port is used. Therefore, among the ports that are not connected to the first MAC and the second MAC, the MDC port is suspended, and the remaining ports are connected to 0.
  • the embodiment of the present invention further provides an inter-chip communication system.
  • the communication system includes: a first chip and a second chip; the first chip includes a first MAC 1, and the second The chip includes a second MAC 2.
  • the MAC is interconnected between the first chip and the second chip, and the interconnected ports are in the same MAC interface mode: the simplified Gigabit Media Independent Interface (RGMII) interface mode is simplified.
  • RGMII Gigabit Media Independent Interface
  • the first MAC 1 sending port includes: a data sending port TXD[3:0] label 1051 of the first MAC 1, a data sending enable port TX_EN label 1052, and the second MAC receiving.
  • the port includes: a data receiving port RXD[3:0] number 2151 of the second MAC 2, and a data receiving valid indication port RX_DV port 2152.
  • the first MAC sending port is connected to the second MAC receiving port, as shown in FIG. 5, the port 1051 is connected to the port 2151, and the port 1052 is connected to the port 2152.
  • the first MAC receiving port includes a data receiving port RXD[3:0] label 1151 of the first MAC 1, a data receiving valid indication port RX_DV port 1152, and the second MAC sending port includes The data transmission port TXD[3:0] of the second MAC 2 is numbered 2051, and the data transmission enable port TX_EN is numbered 2052.
  • the first MAC receiving port is connected to the second MAC sending port, as shown in FIG. 5, the port 1151 is connected to the port 2051, and the port 1152 is connected to the port 2052.
  • the first chip further includes a first clock source 3 and a first clock output port GTX_CLK_O numbered 3151
  • the second chip further includes a second clock source 4 and a second time.
  • the clock output port GTX_CLK_O is numbered 3251.
  • the receiving clock port 1251 (rx_clk_i) of the first MAC in the first working clock port divides the second clock source 4 by 1/5/50 in the second chip through the second clock output port 3251 And the post-delay connection, the transmit clock port 1252 (tx_clk_i) in the first working clock port directly connects the first clock source 3 to 1/5/50 frequency division and delay after the first chip.
  • the receiving reverse clock input port 1253 (tx_clk_180_i) and the sending reverse clock input port 1254 (rx_clk_180_i) in the first working clock port directly make the first clock source 3 1/5/50 inside the first chip.
  • the receiving clock port 2251 (rx_clk_i) in the second working clock port passes the first clock source 3 inside the first chip through the first clock output port 3151 Performing a 1/5/50 frequency division and a post-delay connection, the transmission clock port 2252 (tx_clk_i) in the second working clock port directly makes the second clock source 4 1/5 inside the second chip.
  • the input port 2253 (tx_clk_180_i) and the transmit reverse clock input port 2254 (rx_clk_180_i) directly divide the second clock source 4 into 1/5/50 frequency division, delay, and reverse connection in the second chip. .
  • first clock source 3 and the second clock source 4 in FIG. 5 are respectively PLLs that can generate a 125 MHz clock.
  • the first MAC may send data to the second MAC through a connection between the port 1051 and the port 2151; through the connection between the port 2051 and the port 1151, the second MAC may Transmitting data to the first MAC; each of the other interconnected ports provides various indications and an operating clock to ensure accurate data transmission between the first MAC and the second MAC.
  • the functions of the ports in the RGMII interface mode are the same as those in the prior art, and are not described here.
  • the two MAC operations can only be full-duplex communication, and software is required to configure it to a speed mode of 1000 Mbps.
  • RGMII interface mode only use the graph
  • the port shown in FIG. 5 does not use other ports. Therefore, among the ports in which the first MAC and the second MAC are not connected, the MDC port is suspended, and the remaining ports are connected to 0.
  • the embodiment of the present invention further provides an inter-chip communication system.
  • the communication system includes: a first chip and a second chip; the first chip includes a first MAC 1, and the second The chip includes a second MAC 2.
  • the MAC interconnection between the first chip and the second chip is the same MAC interface mode: Serial Media Independent Interface (SMII) interface mode.
  • SII Serial Media Independent Interface
  • the first MAC sending port includes: a data sending port TXD number 1061 of the first MAC 1, a data sending enable port TX_EN number 1062, and the second MAC receiving port includes: The data reception port RXD number 2161 of the second MAC 2, the data reception valid indication port RX_DV port 2162.
  • the first MAC sending port is connected to the second MAC receiving port, as shown in FIG. 6.
  • the port 1061 is connected to the port 2161, and the port 1062 is connected to the port 2162.
  • the first MAC receiving port includes a data receiving port RXD label 1161 of the first MAC 1, a data receiving valid indication port RX_DV port 1162, and the second MAC sending port includes: the second The data transmission port TXD number 2061 of the MAC 2, and the data transmission enable port TX_EN number 2062.
  • the first MAC receiving port is connected to the second MAC sending port, as shown in FIG. 6.
  • the port 1161 is connected to the port 2061, and the port 1162 is connected to the port 2062.
  • the first chip further includes a first clock source 3 and a first clock output port SMII_CLK_O labeled as 3161
  • the second chip further includes a second clock source 4 and a second clock output port SMII_CLK_O.
  • the number is 3261.
  • the receiving clock port 1261 (rx_clk_125_i) of the first MAC in the first working clock port is connected to the second clock source 4 through the second clock output port 3261, and the transmitting clock port 1262 in the first working clock port ( Tx_clk_125_i) directly in the first chip
  • the first clock source 3 is connected to the first clock source 3, and the working clock input port 1263 (tx_clk_i) and the working clock input port 1264 (rx_clk_i) in the first working clock port directly connect the first clock source 3 inside the first chip.
  • the receiving clock port 2261 (rx_clk_125_i) in the second working clock port is connected to the first clock source 3 through the first clock output port 3161, and the second working clock port is
  • the transmit clock port 2262 (tx_clk_125_i) directly connects the second clock source 4 inside the second chip, the working clock input port 2263 (tx_clk_i) and the working clock input port 2264 (rx_clk_i) in the second working clock port.
  • the second clock source 4 is directly connected to the second chip after being divided by 5/50.
  • first clock source 3 and the second clock source 4 in FIG. 6 are respectively PLLs that can generate a 125 MHz clock.
  • the first MAC may send data to the second MAC through a connection between the port 1061 and the port 2161; through the connection between the port 2061 and the port 1161, the second MAC may Transmitting data to the first MAC; each of the other interconnected ports provides various indications and an operating clock to ensure accurate data transmission between the first MAC and the second MAC.
  • the functions of the ports in the SMII interface mode are the same as those in the prior art, and are not described here.
  • the two MAC jobs can only be full-duplex communication and require software to configure them to the same speed mode.
  • the SMII interface mode only the port shown in FIG. 6 is used, and no other port is used. Therefore, among the ports that are not connected to the first MAC and the second MAC, the MDC port is suspended, and the remaining ports are connected to 0.
  • An embodiment of the present invention further provides an inter-chip communication system.
  • the communication system includes: a first chip and a second chip; the first chip includes a first MAC 1, and the second The chip includes a second MAC 2.
  • the MAC is interconnected between the first chip and the second chip, and the interconnected ports are in the same MAC interface mode: Serial Gigabit Media Independent Interface (SGMII) interface mode.
  • SGMII Serial Gigabit Media Independent Interface
  • the first MAC sending port includes: a data sending port TXD[7:0] number 1071 of the first MAC 1, a data sending enable port TX_EN number 1072, and a data sending error prompting port TX_ER label. 1073.
  • the second MAC receiving port includes: a data receiving port RXD[7:0] number 2171 of the second MAC 2, a data receiving valid indication port RX_DV port 2172, and a data receiving error prompting port RX_ER number 2173.
  • the first MAC sending port is connected to the second MAC receiving port, as shown in FIG. 7.
  • the port 1071 is connected to the port 2171
  • the port 1072 is connected to the port 2172
  • the port 1073 is connected to the port 2173.
  • the first MAC receiving port includes a data receiving port RXD[7:0] number 1171 of the first MAC 1, a data receiving valid indication port RX_DV port 1172, and a data receiving error prompting port RX_ER number 1173.
  • the second MAC sending port includes: a data sending port TXD[7:0] number 2071 of the second MAC 2, a data sending enable port TX_EN number 2072, and a data sending error prompting port TX_ER number 2073.
  • the first MAC receiving port is connected to the second MAC sending port, as shown in FIG. 7.
  • the port 1171 is connected to the port 2071
  • the port 1172 is connected to the port 2072
  • the port 1173 is connected to the port 2073.
  • the first chip further includes a first clock source 3 and a first clock output port sgmii_clk_o labeled as 3171
  • the second chip further includes a second clock source 4 and a second clock output port sgmii_clk_O.
  • the label is 3271.
  • the receiving clock port (rx_clk_125_i) 1271 of the first MAC in the first working clock port is connected to the second clock source 4 through the second clock output port 3271, and the other ports in the first working clock port are sending clocks.
  • the port (tx_clk_125_i) 1272, the working clock input port (tx_clk_i) 1273, the working clock input port (rx_clk_i) 1274, and the sending reverse clock input port (tx_clk_125_180_i) 1275 are directly connected to the first clock source 3 inside the first chip; After the first clock source 3 is inverted, the reverse clock input port 1275 is connected, and the first clock source 3 is divided by 1/5/50 (1000 Mbps is 1 frequency division; 100 Mbps is 5 frequency division; 10 Mbps; It is divided by 50) connected to the working clock input port 1273 and the working clock input port 1274, respectively.
  • the receiving clock port 2271 of the second MAC in the second working clock port is connected to the first clock source 3 through the first clock output port 3171, and the other port in the second working clock port is the sending clock port 2272.
  • the working clock input port (tx_clk_i) 2273, the working clock input port (rx_clk_i) 2274, and the sending reverse clock input port (tx_clk_125_180_i) 2275 are directly connected to the second clock source 4 inside the second chip; wherein the second clock After the source 4 is inverted, the connection sends a reverse clock input port 2275, and the second clock source 4 is divided by 1/5/50 (1000 Mbps is 1 frequency division; 100 Mbps is 5 frequency division; 10 Mbps is 50 frequency division)
  • a working clock input port 2273 and a working clock input port 2274 are connected.
  • first clock source 3 and the second clock source 4 in FIG. 7 are respectively PLLs that can generate a 125 MHz clock.
  • the first MAC may send data to the second MAC through a connection between the port 1071 and the port 2171; through the connection between the port 2071 and the port 1171, the second MAC may Transmitting data to the first MAC; each of the other interconnected ports provides various indications and an operating clock to ensure accurate data transmission between the first MAC and the second MAC.
  • the functions of the ports in the SGMII interface mode are the same as those in the prior art, and are not described here.
  • the two MAC operations can only be full-duplex communication, and software is required to configure it to a speed mode of 1000 Mbps.
  • the SGMII interface mode only the port shown in FIG. 7 is used, and no other port is used. Therefore, among the ports that are not connected to the first MAC and the second MAC, the MDC port is suspended, and the remaining ports are connected to 0.
  • the embodiment of the present invention further provides an inter-chip communication method.
  • the method in this embodiment is a method for applying the communication system described in Embodiment 1 and Embodiment 2, as shown in FIG.
  • the processing flow includes the following steps:
  • Step 801 The first MAC sending port adopts a sending working clock of the first MAC, to the first The second MAC receiving port sends the first data.
  • Step 802 The second MAC receiving port receives the first data by using a sending AND clock of the first MAC.
  • Step 803 The second MAC sending port uses the sending working clock of the second MAC to send the second data to the first MAC receiving port.
  • Step 804 The first MAC receiving port receives the second data by using a transmit clock of the second MAC.
  • steps 801-802 and steps 803-804 there is no order between steps 801-802 and steps 803-804, which can be performed simultaneously.
  • embodiments of the present invention can be provided as a method, system, or computer program product. Accordingly, the present invention can take the form of a hardware embodiment, a software embodiment, or a combination of software and hardware. Moreover, the invention can take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage and optical storage, etc.) including computer usable program code.
  • the computer program instructions can also be stored in a computer readable memory that can direct a computer or other programmable data processing device to operate in a particular manner, such that the instructions stored in the computer readable memory produce an article of manufacture comprising the instruction device.
  • the device is implemented in a flow chart A function specified in a block or blocks of a process or multiple processes and/or block diagrams.
  • These computer program instructions can also be loaded onto a computer or other programmable data processing device such that a series of operational steps are performed on a computer or other programmable device to produce computer-implemented processing for execution on a computer or other programmable device.
  • the instructions provide steps for implementing the functions specified in one or more of the flow or in a block or blocks of a flow diagram.
  • the technical solution of the embodiment of the present invention directly interconnects the transceiver ports of the MACs on the two chips in the same MAC interface mode, and the data transmission between the MACs on the two chips uses respective associated clocks, so that the two chips
  • the inter-MAC can accurately perform data interaction.
  • two MACs are directly interconnected, which simplifies the interconnection structure between the first chip and the second chip, and the data does not need to undergo some complicated intermediate processing (such as PHY processing), directly through the MAC transmission;
  • this hardware structure saves the two PHY and PHY related circuits, saving the hardware cost of this part, reducing the intermediate circuit and electromagnetic environment by reducing these circuits
  • the impact on the data signal reduces the probability of data errors and improves the reliability and stability of data transmission.

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Abstract

本发明实施例公开了一种芯片间的通信系统，所述通信系统包括：第一芯片中的第一MAC，第二芯片中的第二MAC；第一MAC发送端口对应连接第二MAC接收端口，第一MAC接收端口对应连接第二MAC发送端口；第一MAC发送端口、第一MAC接收端口、第二MAC发送端口、第二MAC接收端口为同一MAC接口模式；第一MAC发送端口采用第一MAC的发送工作时钟向第二MAC接收端口发送数据，第二MAC发送端口采用第二MAC的发送工作时钟向第一MAC接收端口发送数据。本发明实施例还公开了一种芯片间的通信方法及计算机存储介质。

Description

一种芯片间的通信方法、系统及计算机存储介质 技术领域
本发明涉及通信技术，尤其涉及一种芯片间的通信方法、系统及计算机存储介质。
背景技术
随着信息化的高速发展，人们的生活和网络息息相关，作为网络通信的基本元素的设备都为大家所熟悉，如：光猫、路由器、交换机、机顶盒以及集线器等。目前大家所熟知的主流的通信方法为：当媒体接入控制器(MAC，Media Access Control)将内存中的数据发送出来以后，通过物理接口收发器(PHY，Physical interface transceiver)将并行数据转换为串行数据，然后通过网口发出；数据到达对端后，被对端的网口接收，然后通过PHY的将网口接收数据转换并行后，再由MAC将数据送给对应的内存，完成两个设备之间的数据传输。这种方法的优点在于，在远距离传输的情况下通过减少设备之间通讯电缆的数量极大的节省了线路成本。
随着网络普及这种用法的缺点慢慢的显露出来，在家庭中小设备较多，这种用法会使得设备之间的连线较多给人们带来不便，更重要的是由于网口经常插拔而导致各种接触不良问题。为了解决这些问题，现有技术中通过一种高效而可靠互联方式，将多个设备做成芯片互联并集成在一个设备中，实现芯片间的数据交互。例如：将原来相互独立的光猫和交换机设备集成到一个设备同时具有光猫+交换机的功能，这样不但减少的设备的数量和网线，而且还提高了数据传输的可靠性。类似的应用还有光猫+机顶盒、光猫+路由器等。
目前集成在网络设备的各个芯片间的通信多采用 MAC+PHY+PHY+MAC方式，所述MAC+PHY+PHY+MAC方式的实现沿用了固有思维方式，在原有的基础之上去掉了网口，直接将两个芯片的PHY之间用板级走线连接，这种方式与原来的方案相比，不仅保证芯片间的通信性能，而且解决了网口由于多次插拔造成接触不良的问题。
虽然MAC+PHY+PHY+MAC应用比较广泛，但还是有几个不足之处：1、对于板级芯片间通信而言，芯片间的通信不需要使用PHY实现数据的串并转换，即不需要使用PHY的串并转换功能，所以芯片间多出的PHY+PHY线路，会使芯片间的电路结构比较复杂；2、如果PHY和他周围的一系列电路一旦出了问题就会直接影响MAC之间的链路，大大增加了电路故障概率。
发明内容
有鉴于此，本发明实施例期望提供一种芯片间的通信方法、系统及计算机存储介质，简化硬件结构，降低成本，提高通信可靠性。
为达到上述目的，本发明实施例的技术方案是这样实现的：
本发明实施例提供了一种芯片间的通信系统，所述通信系统包括：第一芯片和第二芯片；所述第一芯片包括第一媒体接入控制器(MAC)，所述第二芯片包括第二MAC；
第一MAC发送端口对应连接第二MAC接收端口，第一MAC接收端口对应连接第二MAC发送端口；其中，所述第一MAC发送端口、第一MAC接收端口、第二MAC发送端口、第二MAC接收端口为同一MAC接口模式下的端口；
所述第一MAC发送端口，配置为采用第一MAC的发送工作时钟，向所述第二MAC接收端口发送第一数据；
所述第二MAC接收端口，配置为采用第一MAC的发送随路时钟，接收所述第一数据；
所述第二MAC发送端口，配置为采用第二MAC的发送工作时钟，向所述第一MAC接收端口发送第二数据；
所述第一MAC接收端口，配置为采用第二MAC的发送随路时钟，接收所述第二数据。
作为一种实施方式，所述同一MAC接口模式包括以下接口模式中的一种：媒体独立接口(MII)接口模式，简化媒体独立接口(RMII)接口模式、串行媒体独立接口(SMII)接口模式、千兆媒体独立接口(GMII)接口模式、简化千兆媒体独立接口(RGMII)接口模式、串行千兆媒体独立接口(SGMII)接口模式。
作为一种实施方式，在所述同一MAC接口模式为MII接口模式的情况下，所述第一MAC的第一工作时钟端口以及所述第二MAC的第二工作时钟端口连接在同一时钟源上；所述同一时钟源位于所述第一芯片时，所述第一芯片上还包括第一时钟输出口；
所述第一工作时钟端口以及所述第二工作时钟端口都通过所述第一时钟输出口连接所述同一时钟源。
作为一种实施方式，在所述同一MAC接口模式为MII接口模式的情况下，所述第一工作时钟端口以及所述第二工作时钟端口连接在同一时钟源上；所述同一时钟源位于所述第一芯片和第二芯片的外部时；
所述第一工作时钟端口与所述第二工作时钟端口直接连接所述同一时钟源。
作为一种实施方式，在所述同一MAC接口模式为RMII接口模式的情况下，所述第一工作时钟端口以及所述第二工作时钟端口连接在同一时钟源上；所述同一时钟源位于所述第一芯片时，所述第一芯片上还包括第一时钟输出口，所述第二芯片上还包括第二时钟输入口；
所述第一工作时钟端口连接所述同一时钟源；
所述第二工作时钟端口依次通过所述第二时钟输入口和所述第一时钟输出口连接所述同一时钟源。
作为一种实施方式，在所述同一MAC接口模式为RMII接口模式的情况下，所述第一工作时钟端口以及所述第二工作时钟端口连接在同一时钟源上；所述同一时钟源位于所述第一芯片和第二芯片的外部时，所述第一芯片上还包括第一时钟输入口，所述第二芯片上还包括第二时钟输入口；
所述第一工作时钟端口通过第一时钟输入口连接所述同一时钟源；
所述第二工作时钟端口通过第二时钟输入口连接所述同一时钟源。
作为一种实施方式，在所述同一MAC接口模式为所述SMII接口模式、GMII接口模式、RGMII接口模式或SGMII接口模式的情况下，所述第一工作时钟端口以及所述第二工作时钟端口连接在不同时钟源上；所述第一芯片上还包括第一时钟源和第一时钟输出口，所述第二芯片上还包括第二时钟源和第二时钟输出口；
所述第一工作时钟端口中的接收时钟输入端口通过第二时钟输出口连接所述第二时钟源，所述第一工作时钟端口中的其他端口连接所述第一时钟源；
所述第二工作时钟端口中的接收时钟输入端口通过第一时钟输出口连接所述第一时钟源；所述第二工作时钟端口中的其他端口连接所述第二时钟源。
作为一种实施方式，所述第一MAC和所述第二MAC未连接的端口中，物理层PHY配置时钟MDC端口悬空，剩余端口接0。
本发明实施例还提供了一种应用上述的芯片间的通信系统的通信方法，所述方法包括：
第一MAC发送端口采用第一MAC的发送工作时钟，向第二MAC接收端口发送第一数据；
第二MAC接收端口采用第一MAC的发送随路时钟接收所述第一数据；
第二MAC发送端口采用第二MAC的发送工作时钟，向第一MAC接收端口发送第二数据；
所述第一MAC接收端口采用第二MAC的发送随路时钟，接收所述第二数据。
本发明实施例还提供了一种计算机存储介质，所述计算机存储介质中存储有计算机可执行指令，所述计算机可执行指令用于执行本发明实施例所述的芯片间的通信方法。
本发明实施例提供了一种芯片间的通信方法、系统及计算机存储介质，通过将两个芯片上的MAC在同一MAC接口模式下的收发端口直接互联，且两个芯片上的MAC之间的数据传输采用各自的随路时钟，使得两个芯片间的MAC可以准确地进行数据交互，本发明实施例提供的通信系统中，两个MAC直接互联，简化了第一芯片和第二芯片之间的互联结构，数据无需经过一些复杂的中间处理(如PHY的处理)，直接通过MAC进行传输；该硬件结构省掉了两个PHY以及PHY的相关电路，节省了这部分的硬件成本，由于减少了这些电路，就减小了中间电路和电磁环境对数据信号的影响，降低了数据出错概率，提高了数据传输的可靠性和稳定性。
另外，由于电路使用基本电路原件少了，因此也省掉了原来片间互联电路的功耗，从而降低了整个设备功耗；由于两个MAC直接互联，使得软件上不再对PHY进行操作，也简化了软件实现过程，只需要按照相同的双工模式和速度模式来配置两个MAC即可；
最后，如果使用1000Mbps的模式互联通信，在不增加任何成本的情况下，使得两芯片之间数据通信不受100Mbps速率(当前大多数设备使用的是100Mbps)瓶颈限制，可以更高效实现数据传输。用此模式在节省成本 方面效果更加明显。
附图说明
图1为本发明实施例1提供的一种芯片间的通信系统的结构框图；
图2为本发明实施例2提供的一种MII接口模式下的芯片间的通信系统的结构框图；
图3为本发明实施例2提供的一种RMII接口模式下的芯片间的通信系统的结构框图；
图4为本发明实施例2提供的一种GMII接口模式下的芯片间的通信系统的结构框图；
图5为本发明实施例2提供的一种RGMII接口模式下的芯片间的通信系统的结构框图；
图6为本发明实施例2提供的一种SMII接口模式下的芯片间的通信系统的结构框图；
图7为本发明实施例2提供的一种SGMII接口模式下的芯片间的通信系统的结构框图；
图8为本发明实施例3提供的一种芯片间的通信方法流程示意图。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述。
实施例1
本发明实施例提供了一种芯片间的通信系统，如图1所示，所述通信系统包括：第一芯片和第二芯片；所述第一芯片包括第一MAC 1，所述第二芯片包括第二MAC 2。
本实施例提供的通信系统中，第一芯片和第二芯片间的MAC互联，即： 所述第一MAC发送端口10对应连接所述第二MAC接收端口21，所述第一MAC接收端口11对应连接所述第二MAC发送端口20；其中，所述第一MAC发送端口10、第一MAC接收端口11、第二MAC发送端口20、第二MAC接收端口21为同一MAC接口模式下的端口。
由于所述第一MAC发送端口10、第一MAC接收端口11、第二MAC发送端口20、第二MAC接收端口21为同一MAC接口模式下的端口；并且各端口之间对应连接，故所述第一MAC发送端口10就可以向所述第二MAC接收端口21发送数据，所述第二MAC发送端口20也可以向所述第一MAC接收端口11发送数据，即第一MAC 1和第二MAC 2之间就可以进行直接通信。
如图1所示，所述第一MAC的第一工作时钟端口12以及所述第二MAC的第二工作时钟端口22连接在时钟源3上；作为一种实施方式，所述时钟源3为同一时钟源，即所述第一工作时钟端口12和所述第二工作时钟端口22连接在同一时钟源上，这样所述第一MAC和第二MAC接收和发送时用到的时钟是共源的，保证了两个MAC之间的数据能够被正确地传输。当然，所述时钟源3也可以为不同时钟源，即所述第一工作时钟端口12连接在一时钟源上，所述第二工作时钟端口22连接在另一时钟源上。
在这里需要说明的是，所述同一时钟源可以位于所述第一芯片上，也可以位于第二芯片上，还可以如图1所示，位于所述第一芯片和第二芯片的外部，本发明实施例对此并不做限定。
所述第一MAC发送端口10，配置为采用第一MAC的发送工作时钟，向所述第二MAC接收端口21发送第一数据；所述第二MAC接收端口21，配置为采用第一MAC的发送随路时钟，接收所述第一数据；
所述第二MAC发送端口20，配置为采用第二MAC的发送工作时钟，向所述第二MAC接收端口11发送第二数据；所述第一MAC接收端口11， 配置为采用第二MAC的发送随路时钟，接收所述第二数据。
应用本实施例提供的芯片间的通信系统，两个芯片间的MAC可以准确地进行数据交互，通过第一MAC和第二MAC直接互联，简化了第一芯片和第二芯片之间的互联结构，数据无需经过一些复杂的中间处理，直接通过MAC进行传输；第一MAC和第二MAC直接互联，省掉了两个PHY以及PHY的相关电路，节省了这部分的硬件成本，由于减少了中间环节电路，就减小了中间电路和电磁环境对数据信号的影响，降低了数据出错概率，提高了数据传输的可靠性和稳定性。
另外，由于电路使用基本电路原件少了，因此也省掉了原来片间互联电路的功耗，从而降低了整个设备功耗；由于第一MAC和第二MAC直接互联，使得软件上不再对PHY进行操作，也简化了软件实现过程，只需要按照相同的双工模式和速度模式来配置两端的MAC即可；
最后，如果使用1000Mbps的模式互联通信，在不增加任何成本的情况下，使得两芯片之间数据通信不受100Mbps速率(当前大多数设备使用的是100Mbps)瓶颈限制，可以更高效实现数据传输。用此模式在节省成本方面效果更加明显。
实施例2
本发明实施例提供了一种芯片间的通信系统，如图2所示，所述通信系统包括：第一芯片和第二芯片；所述第一芯片包括第一MAC 1，所述第二芯片包括第二MAC 2。如图2所示的通信系统中，第一芯片和第二芯片间的MAC互联，互联的端口为同一MAC接口模式：媒体独立接口(MII，Media Independent Interface)接口模式。
如图2所示，所述第一MAC发送端口包括：所述第一MAC 1的数据发送端口TXD[3:0]标号1021、数据发送使能端口TX_EN标号1022、数据发送错误提示端口TX_ER标号1023，所述第二MAC接收端口包括：所述 第二MAC 2的数据接收端口RXD[3:0]标号2121、数据接收有效指示端口RX_DV端口2122、数据接收出错提示端口RX_ER标号2123。第一MAC发送端口与第二MAC接收端口对应连接即如图2所示，端口1021连接端口2121，端口1022连接端口2122，端口1023连接端口2123。
如图2所示，所述第一MAC接收端口包括所述第一MAC 1的数据接收端口RXD[3:0]标号1121、数据接收有效指示端口RX_DV端口1122、数据接收出错提示端口RX_ER标号1123，所述第二MAC发送端口包括：所述第二MAC 2的数据发送端口TXD[3:0]标号2021、数据发送使能端口TX_EN标号2022、数据发送错误提示端口TX_ER标号2023。第一MAC接收端口与第二MAC发送端口对应连接即如图2所示，端口1121连接端口2021，端口1122连接端口2022，端口1123连接端口2023。
如图2所示，同一时钟源3位于所述第一芯片时，所述第一芯片上还包括第一时钟输出口；所述第一工作时钟端口即第一MAC的接收时钟端口1221和发送时钟端口1222以及所述第二工作时钟端口即第二MAC的接收时钟端口2221和发送时钟端口2222都通过所述第一时钟输出口3121连接所述同一时钟源3。
在这里需要说明的是，图2中的同一时钟源3是可以产生25MHz/2.5MHz时钟的锁相环(PLL，Phase Locked Loop)，若传输速度为100Mbps时，产生的时钟为25MHz，若传输速度为10Mbps时，产生的时钟为2.5MHz。
如图2所示，所述同一时钟源3位于所述第一芯片上，可选的，所述同一时钟源也可以位于第二芯片上，此时，可以参考图2所示，所述第一工作时钟端口即第一MAC的接收时钟端口1221(rx_clk_i)和发送时钟端口1222(tx_clk_i)以及所述第二工作时钟端口即第二MAC的接收时钟端口2221(rx_clk_i)和发送时钟端口2222(tx_clk_i)都通过所述第一芯片 上的第一时钟输出口连接该同一时钟源。
作为一种实施方式，所述同一时钟源也可以位于所述第一芯片和第二芯片的外部，此时，所述第一工作时钟端口以及所述第二工作时钟端口也直接连接所述同一时钟源。
参考图2所示的通信系统，通过端口1021与端口2121之间的连接，所述第一MAC可以向所述第二MAC发送数据；通过端口2021与端口1121之间的连接，第二MAC可以向所述第一MAC发送数据；其他互联的各端口提供各种指示以及工作时钟，保证第一MAC和第二MAC之间能够准确地进行数据传输。MII接口模式下各端口的功能与现有技术中相同，在此不再一一赘述。
图2所示的通信系统中，两个MAC工作只能是全双工通信，并且需要软件将其配置成相同的速度模式。在MII接口模式下，只使用图2所示的端口，不使用其他端口，故所述第一MAC和所述第二MAC未连接的端口中，PHY配置时钟MDC端口悬空，剩余端口接0。
本发明实施例提供了一种芯片间的通信系统，如图3所示，所述通信系统包括：第一芯片和第二芯片；所述第一芯片包括第一MAC 1，所述第二芯片包括第二MAC 2。如图3所示的通信系统中，第一芯片和第二芯片间的MAC互联，互联的端口为同一MAC接口模式：简化媒体独立接口(RMII，Reduced Media Independent Interface)接口模式。
如图3所示，所述第一MAC 1发送端口包括：所述第一MAC 1的数据发送端口TXD[1:0]标号1031、数据发送使能端口TX_EN标号1032，所述第二MAC接收端口包括：所述第二MAC 2的数据接收端口RXD[1:0]标号2131、数据接收有效指示端口RX_DV端口2132。第一MAC发送端口与第二MAC接收端口对应连接即如图3所示，端口1031连接端口2131，端口1032连接端口2132。
如图3所示，所述第一MAC接收端口包括所述第一MAC 1的数据接收端口RXD[1:0]标号1131、数据接收有效指示端口RX_DV端口1132，所述第二MAC发送端口包括：所述第二MAC 2的数据发送端口TXD[1:0]标号2031、数据发送使能端口TX_EN标号2032。第一MAC接收端口与第二MAC发送端口对应连接即如图3所示，端口1131连接端口2031，端口1132连接端口2032。
如图3所示，同一时钟源3位于所述第一芯片时，所述第一芯片上还包括第一时钟输出口Chip1_rmii_clk_o标号为3131，所述第二芯片上还包括第二时钟输入口Chip2_rmii_clk_i标号为3231。
所述第一工作时钟端口即第一MAC的接收时钟端口1231(rx_clk_i)、发送时钟端口1232(tx_clk_i)直接在第一芯片内部将所述同一时钟源做2/20分频后连接、RMII时钟端口1233(rmii_clk_i)直接在第一芯片内部连接所述同一时钟源，所述同一时钟源依次通过所述第一时钟输出口3131和所述第二时钟输入口3231后做2/20分频连接所述第二工作时钟端口中的接收时钟端口2231(rx_clk_i)、发送时钟端口2232(tx_clk_i)；RMII时钟端口2233(rmii_clk_i)依次通过所述第二时钟输入口3231和所述第一时钟输出口3131连接所述同一时钟源3。
在这里需要说明的是，图3中的同一时钟源3是可以产生50MHz时钟的PLL。
如图3所示，所述同一时钟源3可位于所述第一芯片上，作为另一种实施方式，所述同一时钟源也可以位于第二芯片上，此时，可以参考图3所示，第一芯片上需要有一个第一时钟输入口，所述第二芯片上需要有一个第二时钟输出口，所述第二工作时钟端口直接在第二芯片内部连接该同一时钟源，所述第一工作时钟端口就需要依次通过所述第一芯片上的第一时钟输入口和所述第二芯片上的第二时钟输出口连接该同一时钟源。
作为一种实施方式，所述同一时钟源也可以位于所述第一芯片和第二芯片的外部，此时，所述第一芯片上还包括第一时钟输入口，所述第二芯片上还包括第二时钟输入口；所述第一工作时钟端口通过第一时钟输入口连接该同一时钟源；所述第二工作时钟端口通过第二时钟输入口连接该同一时钟源。
参考图3所示的通信系统，通过端口1031与端口2131之间的连接，所述第一MAC可以向所述第二MAC发送数据；通过端口2031与端口1131之间的连接，第二MAC可以向所述第一MAC发送数据；其他互联的各端口提供各种指示以及工作时钟，保证第一MAC和第二MAC之间能够准确地进行数据传输。RMII接口模式下各端口的功能与现有技术中相同，在此不再一一赘述。
图3所示的通信系统中，两个MAC工作只能是全双工通信，并且需要软件将其配置成相同的速度模式。在RMII接口模式下，只使用图3所示的端口，不使用其他端口，故所述第一MAC和所述第二MAC未连接的端口中，MDC端口悬空，剩余端口接0。
本发明实施例还提供了一种芯片间的通信系统，如图4所示，所述通信系统包括：第一芯片和第二芯片；所述第一芯片包括第一MAC 1，所述第二芯片包括第二MAC 2。如图4所示的通信系统中，第一芯片和第二芯片间的MAC互联，互联的端口为同一MAC接口模式：千兆媒体独立接口(GMII，Gigabit Media Independent Interface)接口模式。
如图4所示，所述第一MAC发送端口包括：所述第一MAC 1的数据发送端口TXD[7:0]标号1041、数据发送使能端口TX_EN标号1042、数据发送错误提示端口TX_ER标号1043，所述第二MAC接收端口包括：所述第二MAC 2的数据接收端口RXD[7:0]标号2141、数据接收有效指示端口RX_DV端口2142、数据接收出错提示端口RX_ER标号2143。第一MAC 发送端口与第二MAC接收端口对应连接即如图4所示，端口1041连接端口2141，端口1042连接端口2142，端口1043连接端口2143。
如图4所示，所述第一MAC接收端口包括所述第一MAC 1的数据接收端口RXD[7:0]标号1141、数据接收有效指示端口RX_DV端口1142、数据接收出错提示端口RX_ER标号1143，所述第二MAC发送端口包括：所述第二MAC 2的数据发送端口TXD[7:0]标号2041、数据发送使能端口TX_EN标号2042、数据发送错误提示端口TX_ER标号2043。第一MAC接收端口与第二MAC发送端口对应连接即如图4所示，端口1141连接端口2041，端口1142连接端口2042，端口1143连接端口2043。
如图4所示，所述第一芯片还包括第一时钟源3和第一时钟输出口GTX_CLK_O标号为3141，所述第二芯片上还包括第二时钟源4和第二时钟输出口GTX_CLK_O标号为3241。
所述第一工作时钟端口中的第一MAC的接收时钟端口1241(rx_clk_i)通过第二时钟输出口3241连接所述第二时钟源4，所述第一工作时钟端口中的其他端口即发送时钟端口1242(tx_clk_i)直接在第一芯片内部连接所述第一时钟源3，所述第二工作时钟端口即第二MAC的接收时钟端口2241(rx_clk_i)通过第一时钟输出口3141连接所述第一时钟源3，所述第二工作时钟端口中的其他端口即发送时钟端口2242(tx_clk_i)直接在第二芯片内部连接所述第二时钟源4。
在这里需要说明的是，图4中的所述第一时钟源3和所述第二时钟源4分别是可以产生125MHz时钟的PLL。
参考图4所示的通信系统，通过端口1041与端口2141之间的连接，所述第一MAC可以向所述第二MAC发送数据；通过端口2041与端口1141之间的连接，第二MAC可以向所述第一MAC发送数据；其他互联的各端口提供各种指示以及工作时钟，保证第一MAC和第二MAC之间能够准确 地进行数据传输。GMII接口模式下各端口的功能与现有技术中相同，在此不再一一赘述。
图4所示的通信系统中，两个MAC工作只能是全双工通信，并且需要软件将其配置成1000Mbps的速度模式。在GMII接口模式下，只使用图4所示的端口，不使用其他端口，故所述第一MAC和所述第二MAC未连接的端口中，MDC端口悬空，剩余端口接0。
本发明实施例还提供了一种芯片间的通信系统，如图5所示，所述通信系统包括：第一芯片和第二芯片；所述第一芯片包括第一MAC 1，所述第二芯片包括第二MAC 2。如图5所示的通信系统中，第一芯片和第二芯片间的MAC互联，互联的端口为同一MAC接口模式：简化千兆媒体独立接口(RGMII，Reduced Gigabit Media Independent Interface)接口模式。
如图5所示，所述第一MAC 1发送端口包括：所述第一MAC 1的数据发送端口TXD[3:0]标号1051、数据发送使能端口TX_EN标号1052，所述第二MAC接收端口包括：所述第二MAC 2的数据接收端口RXD[3:0]标号2151、数据接收有效指示端口RX_DV端口2152。第一MAC发送端口与第二MAC接收端口对应连接即如图5所示，端口1051连接端口2151，端口1052连接端口2152。
如图5所示，所述第一MAC接收端口包括所述第一MAC 1的数据接收端口RXD[3:0]标号1151、数据接收有效指示端口RX_DV端口1152，所述第二MAC发送端口包括：所述第二MAC 2的数据发送端口TXD[3:0]标号2051、数据发送使能端口TX_EN标号2052。第一MAC接收端口与第二MAC发送端口对应连接即如图5所示，端口1151连接端口2051，端口1152连接端口2052。
如图5所示，所述第一芯片还包括第一时钟源3和第一时钟输出口GTX_CLK_O标号为3151，所述第二芯片上还包括第二时钟源4和第二时 钟输出口GTX_CLK_O标号为3251。
所述第一工作时钟端口中的第一MAC的接收时钟端口1251(rx_clk_i)通过第二时钟输出口3251在所述第二芯片内部将所述第二时钟源4做1/5/50分频以及延时后连接，所述第一工作时钟端口中的发送时钟端口1252(tx_clk_i)直接在第一芯片内部将所述第一时钟源3做1/5/50分频以及延时后连接，所述第一工作时钟端口中的接收反向时钟输入口1253(tx_clk_180_i)、发送反向时钟输入口1254(rx_clk_180_i)直接在第一芯片内部将所述第一时钟源3做1/5/50分频、延时以及取反向后连接，所述第二工作时钟端口中的接收时钟端口2251(rx_clk_i)通过第一时钟输出口3151在所述第一芯片内部将所述第一时钟源3做1/5/50分频以及延时后连接，所述第二工作时钟端口中的发送时钟端口2252(tx_clk_i)直接在所述第二芯片内部将所述第二时钟源4做1/5/50分频以及延时后连接，所述第二工作时钟端口中的接收反向时钟输入口2253(tx_clk_180_i)、发送反向时钟输入口2254(rx_clk_180_i)直接在所述第二芯片内部将所述第二时钟源4做1/5/50分频、延时以及取反向后连接。
在这里需要说明的是，图5中的所述第一时钟源3和所述第二时钟源4分别是可以产生125MHz时钟的PLL。
参考图5所示的通信系统，通过端口1051与端口2151之间的连接，所述第一MAC可以向所述第二MAC发送数据；通过端口2051与端口1151之间的连接，第二MAC可以向所述第一MAC发送数据；其他互联的各端口提供各种指示以及工作时钟，保证第一MAC和第二MAC之间能够准确地进行数据传输。RGMII接口模式下各端口的功能与现有技术中相同，在此不再一一赘述。
图5所示的通信系统中，两个MAC工作只能是全双工通信，并且需要软件将其配置成1000Mbps的速度模式。在RGMII接口模式下，只使用图 5所示的端口，不使用其他端口，故所述第一MAC和所述第二MAC未连接的端口中，MDC端口悬空，剩余端口接0。
本发明实施例还提供了一种芯片间的通信系统，如图6所示，所述通信系统包括：第一芯片和第二芯片；所述第一芯片包括第一MAC 1，所述第二芯片包括第二MAC 2。如图6所示的通信系统中，第一芯片和第二芯片间的MAC互联，互联的端口为同一MAC接口模式：串行媒体独立接口(SMII，Serial Media Independent Interface)接口模式。
如图6所示，所述第一MAC发送端口包括：所述第一MAC 1的数据发送端口TXD标号1061、数据发送使能端口TX_EN标号1062，所述第二MAC接收端口包括：所述第二MAC 2的数据接收端口RXD标号2161、数据接收有效指示端口RX_DV端口2162。第一MAC发送端口与第二MAC接收端口对应连接即如图6所示，端口1061连接端口2161，端口1062连接端口2162。
如图6所示，所述第一MAC接收端口包括所述第一MAC 1的数据接收端口RXD标号1161、数据接收有效指示端口RX_DV端口1162，所述第二MAC发送端口包括：所述第二MAC 2的数据发送端口TXD标号2061、数据发送使能端口TX_EN标号2062。第一MAC接收端口与第二MAC发送端口对应连接即如图6所示，端口1161连接端口2061，端口1162连接端口2062。
如图6所示，所述第一芯片上还包括第一时钟源3和第一时钟输出口SMII_CLK_O标号为3161，所述第二芯片上还包括第二时钟源4和第二时钟输出口SMII_CLK_O标号为3261。
所述第一工作时钟端口中的第一MAC的接收时钟端口1261(rx_clk_125_i)通过第二时钟输出口3261连接所述第二时钟源4，所述第一工作时钟端口中的发送时钟端口1262(tx_clk_125_i)直接在第一芯片内 部连接所述第一时钟源3，所述第一工作时钟端口中的工作时钟输入口1263(tx_clk_i)、工作时钟输入口1264(rx_clk_i)直接在第一芯片内部将所述第一时钟源3做5/50分频后连接，所述第二工作时钟端口中的接收时钟端口2261(rx_clk_125_i)通过第一时钟输出口3161连接所述第一时钟源3，所述第二工作时钟端口中的发送时钟端口2262(tx_clk_125_i)直接在所述第二芯片内部连接所述第二时钟源4，所述第二工作时钟端口中的工作时钟输入口2263(tx_clk_i)和工作时钟输入口2264(rx_clk_i)直接在所述第二芯片内部将所述第二时钟源4做5/50分频后连接。
在这里需要说明的是，图6中的所述第一时钟源3和所述第二时钟源4分别是可以产生125MHz时钟的PLL。
参考图6所示的通信系统，通过端口1061与端口2161之间的连接，所述第一MAC可以向所述第二MAC发送数据；通过端口2061与端口1161之间的连接，第二MAC可以向所述第一MAC发送数据；其他互联的各端口提供各种指示以及工作时钟，保证第一MAC和第二MAC之间能够准确地进行数据传输。SMII接口模式下各端口的功能与现有技术中相同，在此不再一一赘述。
图6所示的通信系统中，两个MAC工作只能是全双工通信，并且需要软件将其配置成相同的速度模式。在SMII接口模式下，只使用图6所示的端口，不使用其他端口，故所述第一MAC和所述第二MAC未连接的端口中，MDC端口悬空，剩余端口接0。
本发明实施例还提供了一种芯片间的通信系统，如图7所示，所述通信系统包括：第一芯片和第二芯片；所述第一芯片包括第一MAC 1，所述第二芯片包括第二MAC 2。如图7所示的通信系统中，第一芯片和第二芯片间的MAC互联，互联的端口为同一MAC接口模式：串行千兆媒体独立接口(SGMII，Serial Gigabit Media Independent Interface)接口模式。
如图7所示，所述第一MAC发送端口包括：所述第一MAC 1的数据发送端口TXD[7:0]标号1071、数据发送使能端口TX_EN标号1072、数据发送错误提示端口TX_ER标号1073，所述第二MAC接收端口包括：所述第二MAC 2的数据接收端口RXD[7:0]标号2171、数据接收有效指示端口RX_DV端口2172、数据接收出错提示端口RX_ER标号2173。第一MAC发送端口与第二MAC接收端口对应连接即如图7所示，端口1071连接端口2171，端口1072连接端口2172，端口1073连接端口2173。
如图7所示，所述第一MAC接收端口包括所述第一MAC 1的数据接收端口RXD[7:0]标号1171、数据接收有效指示端口RX_DV端口1172、数据接收出错提示端口RX_ER标号1173，所述第二MAC发送端口包括：所述第二MAC 2的数据发送端口TXD[7:0]标号2071、数据发送使能端口TX_EN标号2072、数据发送错误提示端口TX_ER标号2073。第一MAC接收端口与第二MAC发送端口对应连接即如图7所示，端口1171连接端口2071，端口1172连接端口2072，端口1173连接端口2073。
如图7所示，所述第一芯片上还包括第一时钟源3和第一时钟输出口sgmii_clk_o标号为3171，所述第二芯片上还包括第二时钟源4和第二时钟输出口sgmii_clk_O标号为3271。
所述第一工作时钟端口中的第一MAC的接收时钟端口(rx_clk_125_i)1271通过第二时钟输出口3271连接所述第二时钟源4，所述第一工作时钟端口中的其他端口即发送时钟端口(tx_clk_125_i)1272、工作时钟输入口(tx_clk_i)1273、工作时钟输入口(rx_clk_i)1274、发送反向时钟输入口(tx_clk_125_180_i)1275直接在第一芯片内部连接所述第一时钟源3；其中，所述第一时钟源3取反后连接发送反向时钟输入口1275，所述第一时钟源3做1/5/50分频后(1000Mbps是1分频；100Mbps是5分频；10Mbps是50分频)分别连接工作时钟输入口1273和工作时钟输入口1274。
所述第二工作时钟端口中的第二MAC的接收时钟端口2271通过第一时钟输出口3171连接所述第一时钟源3，所述第二工作时钟端口中的其他端口即发送时钟端口2272、工作时钟输入口(tx_clk_i)2273、工作时钟输入口(rx_clk_i)2274、发送反向时钟输入口(tx_clk_125_180_i)2275直接在第二芯片内部连接所述第二时钟源4；其中，所述第二时钟源4取反后连接发送反向时钟输入口2275，所述第二时钟源4做1/5/50分频后(1000Mbps是1分频；100Mbps是5分频；10Mbps是50分频)分别连接工作时钟输入口2273和工作时钟输入口2274。
在这里需要说明的是，图7中的所述第一时钟源3和所述第二时钟源4分别是可以产生125MHz时钟的PLL。
参考图7所示的通信系统，通过端口1071与端口2171之间的连接，所述第一MAC可以向所述第二MAC发送数据；通过端口2071与端口1171之间的连接，第二MAC可以向所述第一MAC发送数据；其他互联的各端口提供各种指示以及工作时钟，保证第一MAC和第二MAC之间能够准确地进行数据传输。SGMII接口模式下各端口的功能与现有技术中相同，在此不再一一赘述。
图7所示的通信系统中，两个MAC工作只能是全双工通信，并且需要软件将其配置成1000Mbps的速度模式。在SGMII接口模式下，只使用图7所示的端口，不使用其他端口，故所述第一MAC和所述第二MAC未连接的端口中，MDC端口悬空，剩余端口接0。
实施例3、
本发明实施例还提供了一种芯片间的通信方法，本实施例方法是应用实施例1和实施例2中所述的通信系统进行通信的方法，如图8所示，本实施例方法的处理流程包括以下步骤：
步骤801、第一MAC发送端口采用第一MAC的发送工作时钟，向第 二MAC接收端口发送第一数据。
步骤802、第二MAC接收端口采用第一MAC的发送随路时钟接收所述第一数据。
步骤803、第二MAC发送端口采用第二MAC的发送工作时钟，向第一MAC接收端口发送第二数据。
步骤804、所述第一MAC接收端口采用第二MAC的发送随路时钟，接收所述第二数据。
在这里需要说明的是，步骤801-802与步骤803-804之间并没有先后顺序，可以同时进行。
本领域内的技术人员应明白，本发明的实施例可提供为方法、系统、或计算机程序产品。因此，本发明可采用硬件实施例、软件实施例、或结合软件和硬件方面的实施例的形式。而且，本发明可采用在一个或多个其中包含有计算机可用程序代码的计算机可用存储介质(包括但不限于磁盘存储器和光学存储器等)上实施的计算机程序产品的形式。
本发明是参照根据本发明实施例的方法、设备(系统)、和计算机程序产品的流程图和/或方框图来描述的。应理解可由计算机程序指令实现流程图和/或方框图中的每一流程和/或方框、以及流程图和/或方框图中的流程和/或方框的结合。可提供这些计算机程序指令到通用计算机、专用计算机、嵌入式处理机或其他可编程数据处理设备的处理器以产生一个机器，使得通过计算机或其他可编程数据处理设备的处理器执行的指令产生用于实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能的装置。
这些计算机程序指令也可存储在能引导计算机或其他可编程数据处理设备以特定方式工作的计算机可读存储器中，使得存储在该计算机可读存储器中的指令产生包括指令装置的制造品，该指令装置实现在流程图一个 流程或多个流程和/或方框图一个方框或多个方框中指定的功能。
这些计算机程序指令也可装载到计算机或其他可编程数据处理设备上，使得在计算机或其他可编程设备上执行一系列操作步骤以产生计算机实现的处理，从而在计算机或其他可编程设备上执行的指令提供用于实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能的步骤。
以上所述，仅为本发明的较佳实施例而已，并非用于限定本发明的保护范围。
工业实用性
本发明实施例的技术方案通过将两个芯片上的MAC在同一MAC接口模式下的收发端口直接互联，且两个芯片上的MAC之间的数据传输采用各自的随路时钟，使得两个芯片间的MAC可以准确地进行数据交互，本发明实施例提供的通信系统中，两个MAC直接互联，简化了第一芯片和第二芯片之间的互联结构，数据无需经过一些复杂的中间处理(如PHY的处理)，直接通过MAC进行传输；该硬件结构省掉了两个PHY以及PHY的相关电路，节省了这部分的硬件成本，由于减少了这些电路，就减小了中间电路和电磁环境对数据信号的影响，降低了数据出错概率，提高了数据传输的可靠性和稳定性。

Claims (10)

  1. 一种芯片间的通信系统，所述通信系统包括：第一芯片和第二芯片；所述第一芯片包括第一媒体接入控制器MAC，所述第二芯片包括第二MAC；
    第一MAC发送端口对应连接第二MAC接收端口，第一MAC接收端口对应连接第二MAC发送端口；其中，所述第一MAC发送端口、第一MAC接收端口、第二MAC发送端口、第二MAC接收端口为同一MAC接口模式下的端口；
    所述第一MAC发送端口，配置为采用第一MAC的发送工作时钟，向所述第二MAC接收端口发送第一数据；
    所述第二MAC接收端口，配置为采用第一MAC的发送随路时钟，接收所述第一数据；
    所述第二MAC发送端口，配置为采用第二MAC的发送工作时钟，向所述第一MAC接收端口发送第二数据；
    所述第一MAC接收端口，配置为采用第二MAC的发送随路时钟，接收所述第二数据。
  2. 根据权利要求1所述的通信系统，其中，所述同一MAC接口模式包括以下接口模式中的一种：媒体独立接口MII接口模式，简化媒体独立接口RMII接口模式、串行媒体独立接口SMII接口模式、千兆媒体独立接口GMII接口模式、简化千兆媒体独立接口RGMII接口模式、串行千兆媒体独立接口SGMII接口模式。
  3. 根据权利要求2所述的通信系统，其中，在所述同一MAC接口模式为MII接口模式的情况下，所述第一MAC的第一工作时钟端口以及所述第二MAC的第二工作时钟端口连接在同一时钟源上；所述同一时钟源位于所述第一芯片时，所述第一芯片上还包括第一时钟输出口。
  4. 根据权利要求2所述的通信系统，其中，在所述同一MAC接口模式为MII接口模式的情况下，所述第一MAC的第一工作时钟端口以及所述第二MAC的第二工作时钟端口连接在同一时钟源上；所述同一时钟源位于所述第一芯片和第二芯片的外部时；
    所述第一工作时钟端口与所述第二工作时钟端口直接连接所述同一时钟源。
  5. 根据权利要求2所述的通信系统，其中，在所述同一MAC接口模式为RMII接口模式的情况下，所述第一MAC的第一工作时钟端口以及所述第二MAC的第二工作时钟端口连接在同一时钟源上；所述同一时钟源位于所述第一芯片时，所述第一芯片上还包括第一时钟输出口，所述第二芯片上还包括第二时钟输入口；
    所述第一工作时钟端口连接所述同一时钟源；
    所述第二工作时钟端口依次通过所述第二时钟输入口和所述第一时钟输出口连接所述同一时钟源。
  6. 根据权利要求2所述的通信系统，其中，在所述同一MAC接口模式为RMII接口模式的情况下，所述第一MAC的第一工作时钟端口以及所述第二MAC的第二工作时钟端口连接在同一时钟源上；所述同一时钟源位于所述第一芯片和第二芯片的外部时，所述第一芯片上还包括第一时钟输入口，所述第二芯片上还包括第二时钟输入口；
    所述第一工作时钟端口通过第一时钟输入口连接所述同一时钟源；
    所述第二工作时钟端口通过第二时钟输入口连接所述同一时钟源。
  7. 根据权利要求2所述的通信系统，其中，在所述同一MAC接口模式为所述SMII接口模式、GMII接口模式、RGMII接口模式或SGMII接口模式的情况下，所述第一MAC的第一工作时钟端口以及所述第二MAC的第二工作时钟端口连接在不同时钟源上；所述第一芯片上还包括第一时钟 源和第一时钟输出口，所述第二芯片上还包括第二时钟源和第二时钟输出口；
    所述第一工作时钟端口中的接收时钟输入端口通过第二时钟输出口连接所述第二时钟源，所述第一工作时钟端口中的其他端口连接所述第一时钟源；
    所述第二工作时钟端口中的接收时钟输入端口通过第一时钟输出口连接所述第一时钟源；所述第二工作时钟端口中的其他端口连接所述第二时钟源。
  8. 根据权利要求1-7任一项所述的芯片间的通信系统，其中，所述第一MAC和所述第二MAC未连接的端口中，物理层PHY配置时钟MDC端口悬空，剩余端口接0。
  9. 一种应用权利要求1-8所述的芯片间的通信系统的通信方法，其中，所述方法包括：
    第一MAC发送端口采用第一MAC的发送工作时钟，向第二MAC接收端口发送第一数据；
    第二MAC接收端口采用第一MAC的发送随路时钟接收所述第一数据；
    第二MAC发送端口采用第二MAC的发送工作时钟，向第一MAC接收端口发送第二数据；
    所述第一MAC接收端口采用第二MAC的发送随路时钟，接收所述第二数据。
  10. 一种计算机存储介质，所述计算机存储介质中存储有计算机可执行指令，所述计算机可执行指令用于执行权利要求9所述的芯片间的通信方法。
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CN102820966A (zh) * 2012-07-26 2012-12-12 武汉滨湖电子有限责任公司 一种串行数据的随路时钟提取方法

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