WO2016041278A1 - 时钟动态切换方法、装置及计算机可读介质 - Google Patents

时钟动态切换方法、装置及计算机可读介质 Download PDF

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Publication number
WO2016041278A1
WO2016041278A1 PCT/CN2014/093859 CN2014093859W WO2016041278A1 WO 2016041278 A1 WO2016041278 A1 WO 2016041278A1 CN 2014093859 W CN2014093859 W CN 2014093859W WO 2016041278 A1 WO2016041278 A1 WO 2016041278A1
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Prior art keywords
clock
signal
enable signal
clock enable
generating unit
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PCT/CN2014/093859
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English (en)
French (fr)
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夏茂盛
张庆
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深圳市中兴微电子技术有限公司
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Priority to EP14902034.9A priority Critical patent/EP3197054A4/en
Priority to US15/511,795 priority patent/US20170294903A1/en
Publication of WO2016041278A1 publication Critical patent/WO2016041278A1/zh

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/135—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals by the use of time reference signals, e.g. clock signals
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/08—Clock generators with changeable or programmable clock frequency
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/12—Synchronisation of different clock signals provided by a plurality of clock generators
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/125—Discriminating pulses
    • H03K5/1252—Suppression or limitation of noise or interference

Definitions

  • the present invention relates to digital circuit technologies, and in particular, to a clock dynamic switching method, apparatus, and computer readable medium.
  • the current clock dynamic switching technology has the following disadvantages: 1) The number of clocks to be switched is limited, generally only supports two clock switching; 2) the frequency of the clock to be switched is limited, for example, the frequency of the clock to be switched cannot be too different. Large or need to meet a certain multiple relationship; 3) The operation is more complicated, and it is necessary to operate the relevant registers multiple times during clock switching.
  • the related clock dynamic switching technology has the problems of the number of switching clocks, the limitation of frequency, and the cumbersome operation, and it is difficult to ensure good performance and high flexibility of the digital system.
  • the embodiment of the invention provides a clock dynamic switching method and device, which solves the problem that the number of clocks to be switched, the frequency is limited, and the operation is cumbersome when the clock is dynamically switched.
  • a clock dynamic switching device comprising: a clock selection signal generating unit, a clock enable signal generating unit, a synchronization unit and a gating unit;
  • the clock selection signal generating unit is configured to generate two or more clock selection signals And transmitted to the clock enable signal generating unit, the clock selection signal having the following characteristics: the number of clock selection signals is equal to the number of clocks to be switched; and at any time, one and only one clock selection signal is valid High or low; at any time, there are only two clock selection signals flipped in opposite directions;
  • the clock enable signal generating unit is configured to generate a clock enable signal based on the plurality of clock selection signals transmitted by the clock selection signal generating unit, and transmit the clock enable signal to the synchronization unit;
  • a synchronization unit configured to synchronize the clock enable signal and transmit the signal to the gating unit
  • the gating unit is configured to turn on or off the output of the clock signal based on the clock enable signal after the synchronization unit is synchronized.
  • the synchronization unit is further configured to perform synchronous processing on the clock enable signal and return the signal as the feedback control signal to the clock enable signal generating unit;
  • the clock enable signal generating unit is configured to generate the clock enable signal based on the clock selection signal and a feedback control signal returned by the synchronization unit; wherein, at any time, only one of the clock enable signals is Enabling.
  • the clock enable signal generating unit is further configured to delay processing the feedback control signal returned by the synchronization unit, and generate the clock enable based on the delayed processed feedback control signal and the currently input clock selection signal. signal.
  • the delay processing refers to delaying one clock cycle.
  • the clock selection signal generating unit is further configured to generate the clock selection signal based on a configuration clock domain.
  • a clock dynamic switching method comprising:
  • the clock selection signal generating unit generates two or more clock selection signals and transmits them to a clock enable signal generating unit, the clock selection signal having the following characteristics: a clock selection signal The number is equal to the number of clocks to be switched; at any time, there is only one clock selection signal that is active high or low; at any time, there are only two clock selection signals flipped in opposite directions ;
  • the clock enable signal generating unit generates two or more clock enable signals based on the two or more clock selection signals, and transmits the clock enable signal to the synchronization unit;
  • the synchronization unit synchronizes the clock enable signal and transmits the signal to the gating unit;
  • the gating unit turns the output of the clock signal on or off based on the synchronized clock enable signal.
  • the method further includes: the synchronization unit performs synchronous processing on the clock enable signal, and returns the feedback control signal to the clock enable signal generating unit; the clock enable signal generating unit selects based on the clock The signal, and the feedback control signal returned by the synchronization unit, generates the clock enable signal; wherein, at any time, only one of the clock enable signals is enabled.
  • the generating the clock enable signal based on the clock selection signal and the feedback control signal returned by the synchronization unit includes:
  • the clock enable signal generating unit delays the processing of the feedback control signal, and generates the clock enable signal based on the delayed processed feedback control signal and the currently input clock selection signal.
  • the delay processing is delayed by one clock cycle.
  • the clock selection signal generating unit generates the clock selection signal based on a configuration clock domain.
  • a computer readable medium having executable instructions stored in the computer readable medium, the executable instructions being configured to perform the clock dynamic switching method described above.
  • the number of clock selection signals generated by the clock selection signal generating unit is equal to the number of clocks to be switched; at any time, only one clock selection signal is a valid high level or a low level. There are only two clock selection signals flipped in opposite directions. There is no requirement for the number of clocks and the clock frequency. No additional processing is required before and after the clock switching. It is possible to achieve fast switching without glitch between multiple clock signals, and solve the number of clocks to be switched when the clock is dynamically switched. The limited frequency and cumbersome operation increase the ease of use and flexibility of the digital system.
  • FIG. 1 is a schematic structural diagram of a multi-selection clock dynamic switching device according to a first embodiment of the present invention
  • FIG. 2 is a schematic diagram of a coding mode of a clock selection signal in a 4-to-1 clock dynamic switching according to a second embodiment of the present invention
  • FIG. 3 is a schematic structural diagram and a signal logic diagram of a 4-to-1 clock dynamic switching apparatus according to a second embodiment of the present invention.
  • FIG. 4 is a waveform diagram of a clock selection signal processed by a clock selection signal generating unit according to Embodiment 2 of the present invention.
  • FIG. 5 is a waveform diagram of an output clock based on a delayed clock enable signal feedback control according to a second embodiment of the present invention.
  • FIG. 6 is a schematic flowchart of a multi-selection clock dynamic switching method according to Embodiment 3 of the present invention.
  • FIG. 1 is a multi-clock dynamic switching circuit, comprising a clock selection signal generating unit 11, a clock enable signal generating unit 12, a synchronizing unit 13 and a gating unit 14, wherein
  • the clock selection signal generating unit 11 generates a plurality of clock selection signals
  • the clock enable signal generating unit 12 generates a clock based on the plurality of clock selection signals.
  • the gating unit 14 turns the clock output on or off according to the synchronized clock enable signal.
  • the clock selection signal generating unit 11 is configured to generate a clock selection signal having the following characteristics: 1) the number of clock selection signals is equal to the number of clocks to be switched; 2) at any time, there is only one The clock selection signal is active high or low, and the remaining clock selection signals are inactive low or high; 3) at any time, there are only two clock selection signals flipped in opposite directions. For example, one flips from low to high and the other flips from high to low.
  • the clock selection signal generated by the clock selection signal generating unit 11 is from the configuration clock domain.
  • the clock domain if a signal is driven (or triggered) by the clock clk_in1, the signal is said to belong to the clk_in1 clock domain.
  • the clock selection signal can be generated by software configuration or hardware decoding. That is to say, the clock selection signal generating unit can be implemented by hardware or by software, but the clock selection signals generated by the two methods must have the above three features.
  • the clock selection signal generating unit 11 may be a circuit having the following functions: using the configuration clock (such as cfg_clk in FIG. 1) to input m (m is an integer not less than 2) initial selection signals. (such as sel[m:0] in Figure 1, representing binary code) encoding generates and outputs a unique heat code (such as clk_in_sel[0], clk_in_sel[1], ..., clk_in_sel[n-2] in Figure 1, Clk_in_sel[n-1], n is an integer not less than 2).
  • the one-hot code is the above-mentioned clock selection signal.
  • clk_in_sel[0], clk_in_sel[1], ..., clk_in_sel[n-2], clk_in_sel[n-1] shown in FIG. 1 are clock selection signals generated by the clock selection signal generating unit 11, and the present invention
  • the clock selection signal generating unit 11 in the embodiment can generate a plurality of (at least two or more) clock selection signals.
  • Clk_in[n-1:0] in Fig. 1 represents n-1 clock signals to be switched.
  • the clock enable signal generating unit 12 is configured to generate a plurality of the plurality of the clock selection signals Clock enable signal.
  • the clock enable signal generated by the clock enable signal generating unit 12 has the following characteristics: each clock has a separate clock enable signal, and only one clock enable signal is enabled at any time; the clock The enable signal is generated by the above-described clock selection signal and a feedback control signal returned by the synchronization unit.
  • the clock enable signal generating unit 12 is specifically a clock enable signal generated based on the plurality of clock selection signals generated by the clock selection signal generating unit 11 and the feedback control signal returned by the synchronization unit 13,
  • the feedback control signal is a clock enable signal that is synchronously processed via the synchronization unit 13, and the clock enable signal generation unit 12 delays the feedback control signal returned by the synchronization unit 13 (delay one clock cycle) and then combines each clock. A signal is selected to generate each clock enable signal. As shown in FIG.
  • the clock enable signal generating unit 12 processes based on n clock selection signals clk_in_sel[0], clk_in_sel[1], ..., clk_in_sel[n-2], clk_in_sel[n-1], and synchronized units. Then, it returns to the clock enable signal generating unit n (n is an integer not less than 2) clock enable signals clk_in_en_sync[n-1:0], and generates n new clock enable signals clk_in_en[0], clk_in_en [1], ..., clk_in_en[n-2], clk_in_en[n-1].
  • the synchronization unit 13 is configured to perform synchronization processing on the clock enable signal transmitted from the clock enable signal generating unit 12 to eliminate the influence of metastability.
  • the synchronizing unit 13 returns the synchronized clock enable signal to the clock enable signal generating unit 12 for generating a new clock enable signal and transmits it to the gating unit 14 to enable the gating unit 14 to control the signal output.
  • clk_in_en_sync[0] to clk_in_en_sync[n-1] are n clock enable signals that are synchronously processed by the synchronization unit 13, and are returned to the clock enable signal generating unit 12 on the one hand, and are passed to the gate on the other hand.
  • Unit 14 is configured to perform synchronization processing on the clock enable signal transmitted from the clock enable signal generating unit 12 to eliminate the influence of metastability.
  • the synchronizing unit 13 returns the synchronized clock enable signal to the clock enable signal generating unit 12 for generating a new clock enable signal and transmit
  • the gating unit 14 turns on or off the output of the clock signal according to the clock enable signal synchronized by the synchronizing unit 13, and the gated clock signal is output after the OR gate logic. As shown in FIG. 1, the gating unit 14 turns the clock on or off according to the clock enable signals clk_in_en_sync[0] to clk_in_en_sync[n-1] synchronized by the sync unit 13. Clk_out in Figure 1 The output phase of the clock phase after the gate is controlled.
  • each of the above devices can be implemented by a logic programmable gate array (FPGA).
  • FPGA logic programmable gate array
  • the clock dynamic switching can be made insensitive to the clock frequency, and has a wider application range and greater versatility.
  • the 4-to-1 clock dynamic switching device may include a clock selection signal generating unit 31, a clock enable signal generating unit, a synchronizing unit 33, and a gating unit 34.
  • the clock enable signal generating unit comprises two parts: a first part 321 and a second part 322, the first part 321 transmits a signal between the clock selection signal generating unit 31 and the synchronizing unit 33, and the second part 322 is in the synchronizing unit 33 and A signal is transmitted between the first portions 321 .
  • the clock selection signal generating unit 31 encodes the input n (n is an integer not less than 2) initial selection signals sel[n:0] by the configuration clock cfg_clk and outputs the unique heat code.
  • the unique heat code is the clock selection signal. If the clock enable signal generating unit 31 directly generates the clock selection signal with the input initial selection signal, the output clock is burred due to the transmission of the multi-bit data across the clock domain.
  • Clk_in[i] in Fig. 3 represents a clock signal to be switched. In this embodiment, the clock selection signal generating unit 31 adopts the encoding mode as shown in FIG. 2. In FIG.
  • the four states 00, 01, 10, and 11 of the binary code initial selection signal respectively correspond to the clock signal clk_in to be selected. 0], clk_in[1], clk_in[2], clk_in[3], if switching from clk_in[0] to clk_in[3], the initial selection signal needs to be changed from 00 to 11, without coding processing. May cause glitches on the output clock.
  • the clock selection signal generated by the clock enable signal generating unit 31 has the following characteristics: the number of clock selection signals is equal to the number of clocks to be switched; at any time, only one clock selection signal is valid.
  • the remaining clock selection signals are inactive low level (or high level); at any time, there are only two selection signals flipped in opposite directions, for example, a slave Low level flips to high level, one flips from high level to low level; clock selection signal comes from configuration clock domain, which can be generated by software configuration or hardware decoding.
  • the clock selection signal conforming to the above characteristics is adopted. As shown in FIG. 2, the four states 0001, 0010, 0100, and 1000 of the encoded clock selection signal respectively correspond to the selection clocks clk_in[0], clk_in[1], clk_in[2].
  • clk_in[3] at this time, when the clock signal clk_in[0] is switched to clk_in[3], the selection signal of clk_in[0] is changed from valid to invalid, and the selection signal of clk_in[3] is changed from invalid to valid.
  • the selection signals of clk_in[1] and clk_in[2] remain inactive, and the clock selection signal changes from state 0001 to state 1000. It does not occur when clk_in[1] and clk_in[3] are selected at the same time to avoid glitches on the output clock.
  • the cross-clock domain transmission of the multi-bit binary coded multi-bit clock selection signal is as shown in FIG. 4, where clk_in_sel[i] cfg_clk (0 ⁇ i ⁇ n-1) represents the generated clock selection signal, sel[1: 0] cfg_clk indicates the initial selection signal.
  • the clock enable signal generating unit When switching from the clock signal clk_in[0] to clk_in[3], the clock enable signal generating unit needs to generate a clock enable signal according to the clock selection signal, and on the other hand, the original clock needs to be disabled (clk_in[0] as described above). In addition, you need to enable a new clock (clk_in[3] as described above). In order to make the output clock glitch, you need to follow the original clock and disable the order of the new clock.
  • the clock enable signal generating unit generates a currently required clock enable signal based on the feedback control signal returned by the synchronization unit 33 and the clock selection signal currently generated by the clock selection signal generating unit 31. For example, as shown in FIG.
  • the clock selection signal clk_in_sel[i] cfg_clk (0 ⁇ i ⁇ n-1) currently generated by the clock selection signal generating unit 31 is output, and the clock enable signal generating unit is input after a certain delay.
  • a portion 321 labeled clk_in_sel[i] clk_in[i] in FIG. 3, represents a signal input to the clock enable signal generating unit after the clock selection signal clk_in_sel[i] cfg_clk outputted by the clock selection signal generating unit 31 is delayed.
  • the returned feedback control signal clk_in_en_sync[j] (0 ⁇ j ⁇ n-1 and j ⁇ i) is input to the second portion 322 of the clock enable signal generating unit, and the second portion 322 of the clock enable signal generating unit is input to
  • the feedback control signal clk_in_en_sync[j] is outputted to the first portion 321 after delay processing (i.e., delayed by one clock cycle), and clk_in_en_sync_dly[j] in Fig.
  • the feedback control signal clk_in_en_sync[j] is a signal that is output by the synchronization unit 33 after synchronizing the previously input clock enable signal clk_in_en[j].
  • the synchronized clock enable signal is used as an input of the clock enable signal generating unit, that is, as a feedback control signal for generating a new clock enable signal, and the clock enable signal generating unit determines all other clocks.
  • a new clock enable signal is enabled when the enable signal is low.
  • the feedback control signal of the input clock enable signal generating unit needs to be delayed by one clock cycle, as shown in FIG. 3, the action of the delay is performed by the second of the clock enable signal generating unit. Section 322 is executed. As shown in circle 1 in Fig.
  • clk_out_* refers to an output signal generated by using a clk_in_en_sync[i] signal instead of the delayed signal clk_in_en_sync_dly[i] as a feedback control signal; clk_out is an output signal generated by using clk_in_en_sync_dly[i] as a feedback control signal .
  • the output signal clk_out_* is generated by the output control signal clk_in_gate[0] and clk_in_gate[3]_* after the gating unit 34, and the clk_in_gate[3]_* is generated by using the signal clk_in_en_sync[i] as a feedback control signal.
  • the output signal clk_out is generated by the output control signal clk_in_gate[0] and clk_in_gate[3] after the gate unit 34, and the clk_in_gate[3] is the gate generated by using the delayed clk_in_en_sync_dly[i] as the feedback control signal. Control the clock signal.
  • the synchronization unit 33 is configured to synchronize the clock enable signal. As shown in FIG. 3, the synchronization unit 33 generates a signal clk_in_en_sync[i] after synchronizing the clock enable signals clk_in_en[i], and outputs them to the gate unit 34 and the second portion 322 of the clock enable signal generating unit, respectively.
  • the gating unit 34 is configured to turn off or turn on the clock based on the synchronized clock enable signal of the sync unit 33. As shown in FIG. 3, the synchronized clock enable signal clk_in_en_sync[i] passes through the gating unit 34 to generate the gated clock signals clk_in_gate[0] to clk_in_gate[3]. When the clock is switched from clk_in[0] to clk_in[3], the clocked phase of the clock or the output signal clk_out is generated.
  • the embodiment of the present invention provides a method for dynamically switching a clock.
  • the method is implemented by the clock dynamic switching device of the first embodiment. As shown in FIG. 7, the method may include the following steps:
  • Step 601 The clock selection signal generating unit generates two or more clock selection signals and transmits them to the clock enable signal generating unit, and the clock selection signal has the following characteristics: the number of clock selection signals and the number of clocks to be switched Equivalent; at any time, one and only one clock selection signal is active high or low; at any time, there are only two clock selection signals flipped in opposite directions;
  • the clock selection signal generating unit generates the clock selection signal based on a configuration clock domain.
  • Step 602 The clock enable signal generating unit generates two or more clock enable signals based on the two or more clock selection signals, and transmits the clock enable signal to the synchronization unit.
  • the synchronization unit returns the clock enable signal to the clock enable signal generating unit as a synchronous control signal to the clock enable signal; the clock enable signal generating unit is based on the The clock select signal and the feedback control signal returned by the synchronization unit generate the clock enable signal; wherein, at any time, only one of the clock enable signals is enabled.
  • the clock enable signal generating unit delays the processing of the feedback control signal, and generates the clock enable signal based on the delayed processed feedback control signal and the currently input clock selection signal.
  • the delay processing here is delayed by one clock cycle.
  • Step 603 The synchronization unit synchronizes the clock enable signal and transmits it to the gating unit.
  • Step 604 The gating unit turns on or off the output of the clock signal based on the synchronized clock enable signal.
  • the implementation details of the method provided in this embodiment may be directly obtained through the description of the first embodiment or the second embodiment, and details are not described herein again.
  • the method of the present embodiment is also applicable to the 4-to-1 clock dynamic switching device of the second embodiment.
  • the implementation process is the same as the above process, and details are not described herein.
  • modules or steps of the present invention described above can be implemented by a general-purpose computing device that can be centralized on a single computing device or distributed across a network of multiple computing devices. Alternatively, they may be implemented by program code executable by the computing device such that they may be stored in the storage device by the computing device and, in some cases, may be different from the order herein.
  • the steps shown or described are performed, or they are separately fabricated into individual integrated circuit modules, or a plurality of modules or steps thereof are fabricated as a single integrated circuit module.
  • the invention is not limited to any specific combination of hardware and software.

Abstract

本发明公开了一种时钟动态切换方法、装置及计算机可读介质；装置包括：时钟选择信号产生单元、时钟使能信号产生单元、同步单元和门控单元；所述时钟选择信号产生单元，配置为产生两个或两个以上时钟选择信号并传输给所述时钟使能信号产生单元；所述时钟使能信号产生单元，配置为基于所述时钟选择信号产生单元传过来的多个时钟选择信号产生时钟使能信号，并将所述时钟使能信号传输给所述同步单元；同步单元，配置为对所述时钟使能信号进行同步处理并传输给所述门控单元；门控单元，配置为基于所述同步单元同步后的时钟使能信号，打开或关闭时钟信号的输出。

Description

时钟动态切换方法、装置及计算机可读介质 技术领域
本发明涉及数字电路技术，尤其涉及一种时钟动态切换方法、装置及计算机可读介质。
背景技术
目前数字系统的功能越来越复杂，对功耗设计要求越来越高，根据功能及功耗需求，数字系统通常需要在多个不同的工作时钟之间进行动态切换。
目前的时钟动态切换技术存在以下一些缺陷：1)对待切换的时钟个数有限制，一般只支持两路时钟切换；2)对待切换的时钟的频率有限制，比如待切换时钟的频率相差不能太大或者需要满足一定的倍数关系；3)操作比较复杂，在进行时钟切换时需要多次操作相关寄存器。上述缺陷都会影响数字系统的性能和灵活性。
综上所述，相关时钟动态切换技术存在切换时钟的个数、频率有限制以及操作繁琐的问题，难以保证数字系统具有良好性能和较高的灵活性。
发明内容
本发明实施例提供一种时钟动态切换方法及装置，以解决时钟动态切换时对待切换时钟的个数、频率有限制以及操作繁琐的问题。
本发明实施例的技术方案是这样实现的：
一种时钟动态切换装置，所述装置包括：时钟选择信号产生单元、时钟使能信号产生单元、同步单元和门控单元；
所述时钟选择信号产生单元，配置为产生两个或两个以上时钟选择信 号并传输给所述时钟使能信号产生单元，所述时钟选择信号具有如下特征：时钟选择信号的个数与需要切换的时钟个数相等；在任意时刻，有且只有一个时钟选择信号是有效的高电平或低电平；在任意时刻，有且只有两个时钟选择信号向相反的方向翻转；
所述时钟使能信号产生单元，配置为基于所述时钟选择信号产生单元传过来的多个时钟选择信号产生时钟使能信号，并将所述时钟使能信号传输给所述同步单元；
同步单元，配置为对所述时钟使能信号进行同步处理并传输给所述门控单元；
门控单元，配置为基于所述同步单元同步后的时钟使能信号，打开或关闭时钟信号的输出。
优选的，所述同步单元，还配置为对所述时钟使能信号进行同步处理后作为所述反馈控制信号返回给所述时钟使能信号产生单元；
所述时钟使能信号产生单元，配置为基于所述时钟选择信号、以及所述同步单元返回的反馈控制信号产生所述时钟使能信号；其中，任意时刻，只有一个所述时钟使能信号是使能的。
优选的，所述时钟使能信号产生单元，还配置为对所述同步单元返回的反馈控制信号延迟处理，再基于延迟处理后的反馈控制信号和当前输入的时钟选择信号产生所述时钟使能信号。
优选的，所述延迟处理是指延迟一个时钟周期。
优选的，所述时钟选择信号产生单元，还配置为基于配置时钟域产生所述时钟选择信号。
一种时钟动态切换方法，所述方法包括：
时钟选择信号产生单元产生两个或两个以上时钟选择信号并传输给时钟使能信号产生单元，所述时钟选择信号具有如下特征：时钟选择信号的 个数与需要切换的时钟个数相等；在任意时刻，有且只有一个时钟选择信号是有效的高电平或低电平；在任意时刻，有且只有两个时钟选择信号向相反的方向翻转；
时钟使能信号产生单元基于所述两个或两个以上时钟选择信号产生两个或两个以上时钟使能信号，并将所述时钟使能信号传输给同步单元；
同步单元对所述时钟使能信号进行同步处理并传输给门控单元；
门控单元基于同步后的所述时钟使能信号，打开或关闭时钟信号的输出。
优选的，所述方法还包括：同步单元对所述时钟使能信号进行同步处理后作为所述反馈控制信号返回给所述时钟使能信号产生单元；时钟使能信号产生单元基于所述时钟选择信号、以及所述同步单元返回的反馈控制信号产生所述时钟使能信号；其中，任意时刻，只有一个所述时钟使能信号是使能的。
优选的，所述基于所述时钟选择信号、以及所述同步单元返回的反馈控制信号产生所述时钟使能信号，包括：
时钟使能信号产生单元对所述反馈控制信号延迟处理，再基于延迟处理后的反馈控制信号和当前输入的时钟选择信号产生所述时钟使能信号。
优选的，所述延迟处理为延迟一个时钟周期。
优选的，所述时钟选择信号产生单元基于配置时钟域产生所述时钟选择信号。
一种计算机可读介质，所述计算机可读介质中存储有可执行指令，所述可执行指令配置为执行以上所述的时钟动态切换方法。
本发明实施例中，时钟选择信号产生单元产生的时钟选择信号的个数与需要切换的时钟个数相等；在任意时刻，有且只有一个时钟选择信号是有效的高电平或低电平，有且只有两个时钟选择信号向相反的方向翻转， 对时钟个数和时钟频率均无要求，在时钟切换前后不需要做额外的处理，可以实现多个时钟信号之间无毛刺的快速切换，解决了时钟动态切换时的对待切换时钟的个数、频率有限制以及操作繁琐的问题，提高了数字系统的易用性和灵活性。
附图说明
图1为根据本发明实施例一的多选一时钟动态切换装置的组成结构示意图；
图2为根据本发明实施例二的4选1时钟动态切换中时钟选择信号的编码方式示意图；
图3为根据本发明实施例二的4选1的时钟动态切换装置的组成结构示意图及信号逻辑图；
图4为根据本发明实施例二的经过时钟选择信号产生单元处理后的时钟选择信号的波形图；
图5为根据本发明实施例二的基于延时时钟使能信号反馈控制的输出时钟波形图；
图6为根据本发明实施例三的多选一时钟动态切换方法的流程示意图。
具体实施方式
为使本发明的目的、技术方案和优点更加清楚明白，以下举实施例并参照附图，对本发明进一步详细说明。
实施例一
本发明提供的时钟动态切换装置结构如图1所示，是一种多时钟动态切换电路，包括时钟选择信号产生单元11、时钟使能信号产生单元12、同步单元13和门控单元14，其中，时钟选择信号产生单元11产生多个时钟选择信号，时钟使能信号产生单元12基于所述多个时钟选择信号产生时钟 使能信号并传递给同步单元13同步后，门控单元14根据同步后的时钟使能信号打开或关闭时钟输出。
其中，时钟选择信号产生单元11配置为产生时钟选择信号，该时钟选择信号具有如下特征：1)时钟选择信号的个数与需要切换的时钟个数相等；2)在任意时刻，有且只有一个时钟选择信号是有效的高电平或低电平，其余的时钟选择信号是无效的低电平或高电平；3)在任意时刻，有且只有两个时钟选择信号向相反的方向翻转，比如，一个从低电平向高电平翻转，另一个从高电平向低电平翻转。
本发明实施例中，时钟选择信号产生单元11产生的时钟选择信号来自配置时钟域，对于“时钟域”来说，如果一个信号由时钟clk_in1驱动(或触发)，就说该信号属于clk_in1时钟域。该时钟选择信号可以通过软件配置产生或硬件解码产生。也就是说，时钟选择信号产生单元既可以通过硬件的方式实现，也可以通过软件的方式来实现，但是这两种方式产生的时钟选择信号必须都具备上述3个特征。
本发明实施例中，上述的时钟选择信号产生单元11可以是具有如下功能的电路：用配置时钟(如图1中的cfg_clk)对输入的m(m为不小于2的整数)个初始选择信号(如图1中的sel[m:0]，表示二进制码)编码产生并输出独热码(如图1中的clk_in_sel[0]、clk_in_sel[1]、……、clk_in_sel[n-2]、clk_in_sel[n-1]，n为不小于2的整数)。这样的话，该独热码就是上述的时钟选择信号。也就是说，图1所示clk_in_sel[0]、clk_in_sel[1]、……、clk_in_sel[n-2]、clk_in_sel[n-1]即为时钟选择信号产生单元11产生的时钟选择信号，本发明实施例中的时钟选择信号产生单元11可以产生多个(至少两个或者两个以上)时钟选择信号。图1中的clk_in[n-1:0]表示待切换的n-1个时钟信号。
时钟使能信号产生单元12配置为基于多个所述时钟选择信号产生多个 时钟使能信号。本发明实施例中，时钟使能信号产生单元12产生的时钟使能信号具有如下特征：每一个时钟都有单独的时钟使能信号，任意时刻，只有一个时钟使能信号是使能的；时钟使能信号是由上述时钟选择信号和同步单元返回的反馈控制信号产生的。也就是说，本发明实施例中，时钟使能信号产生单元12具体是基于时钟选择信号产生单元11产生的多个时钟选择信号和同步单元13返回的反馈控制信号一起产生的时钟使能信号，例如，反馈控制信号为经由同步单元13同步处理后的时钟使能信号，时钟使能信号产生单元12对同步单元13返回的该反馈控制信号延迟处理(延迟一个时钟周期)后再结合每个时钟选择信号来产生每个时钟使能信号。如图1所示，时钟使能信号产生单元12基于n个时钟选择信号clk_in_sel[0]、clk_in_sel[1]、……、clk_in_sel[n-2]、clk_in_sel[n-1]和经同步单元处理之后并返回给时钟使能信号产生单元的n(n为不小于2的整数)个时钟使能信号clk_in_en_sync[n-1:0]，产生n个新的时钟使能信号clk_in_en[0]、clk_in_en[1]、……、clk_in_en[n-2]、clk_in_en[n-1]。
本发明实施例中，同步单元13配置为对时钟使能信号产生单元12传递过来的时钟使能信号进行同步处理，以消除亚稳态的影响。同步单元13将同步后的时钟使能信号返回给时钟使能信号产生单元12用以产生新的时钟使能信号，并传递给门控单元14，以使得门控单元14能够控制信号输出。如图1所示，clk_in_en_sync[0]～clk_in_en_sync[n-1]是经过同步单元13同步处理的n个时钟使能信号，一方面返回给时钟使能信号产生单元12，一方面传递给门控单元14。
本发明实施例中，门控单元14根据同步单元13同步后的时钟使能信号，打开或关闭时钟信号的输出，门控后的时钟信号经过或门逻辑后输出。如图1所示，门控单元14根据同步单元13同步后的时钟使能信号clk_in_en_sync[0]～clk_in_en_sync[n-1]打开或关闭时钟。图1中的clk_out 为门控后的时钟相或产生的输出信号。
实际应用中，上述装置中的各单元可以由逻辑可编程门阵列(FPGA)实现。
采用本发明实施例的上述装置，可以使时钟动态切换对时钟频率不敏感，具有更广泛的适用范围及更强的通用性。
实施例二
下面以4选1的时钟动态切换为例来说明本发明的具体实施过程。
本实施例中，对多个时钟进行选择时需要多位时钟选择信号，以4选1为例，需要两位时钟选择信号，采用如图2所示的编码方式。如图3所示，4选1的时钟动态切换装置可以包括时钟选择信号产生单元31、时钟使能信号产生单元、同步单元33和门控单元34。其中，时钟使能信号产生单元包含两个部分：第一部分321和第二部分322，第一部分321在时钟选择信号产生单元31与同步单元33之间传输信号，第二部分322在同步单元33和第一部分321之间传输信号。
如图3所示，本实施例中时钟选择信号产生单元31用配置时钟cfg_clk对输入的n(n为不小于2的整数)个初始选择信号sel[n:0]编码产生并输出独热码，该独热码即为时钟选择信号。若时钟使能信号产生单元31直接用输入的初始选择信号产生时钟选择信号，则由于多比特数据跨时钟域传输而导致输出时钟产生毛刺。图3中的clk_in[i]表示待切换的时钟信号。本实施例中，时钟选择信号产生单元31采用如图2所示的编码方式，图2中，二进制码初始选择信号的四种状态00、01、10、11分别对应待选择的时钟信号clk_in[0]、clk_in[1]、clk_in[2]、clk_in[3]，若从clk_in[0]切换到clk_in[3]，初始选择信号需由00改变为11，在不做编码处理的前提下，可能导致输出时钟产生毛刺。本发明实施例中，时钟使能信号产生单元31产生的时钟选择信号具有如下特征：时钟选择信号的个数与需要切换的时钟个数相等； 在任意时刻，有且只有一个时钟选择信号是有效的高电平(或低电平)，其余的时钟选择信号是无效的低电平(或高电平)；在任意时刻，有且只有两个选择信号向相反的方向翻转，比如，一个从低电平向高电平翻转，一个从高电平向低电平翻转；时钟选择信号来自配置时钟域，可通过软件配置产生或硬件解码产生。采用符合上述特征的时钟选择信号，如图2所示，编码后的时钟选择信号的4种状态0001、0010、0100和1000分别对应选择时钟clk_in[0]、clk_in[1]、clk_in[2]和clk_in[3]，此时，从时钟信号clk_in[0]切换到clk_in[3]时，clk_in[0]的选择信号由有效变为无效，clk_in[3]的选择信号由无效变为有效，clk_in[1]和clk_in[2]的选择信号依然保持无效，时钟选择信号由状态0001变为状态1000，不会出现同时选择clk_in[1]和clk_in[3]的情况，避免输出时钟产生毛刺，该多位二进制编码的多比特时钟选择信号的跨时钟域传输如图4所示，其中，clk_in_sel[i]cfg_clk(0≤i≤n-1)表示所产生的时钟选择信号，sel[1:0]cfg_clk表示初始选择信号。
从时钟信号clk_in[0]切换到clk_in[3]时，根据时钟选择信号，时钟使能信号产生单元需要产生时钟使能信号，一方面需要禁能原时钟(如上所述的clk_in[0])，另外还需要使能新的时钟(如上所述的clk_in[3])。为了使输出时钟无毛刺，需要遵循先禁能原时钟，再使能新时钟的顺序。本发明实施例中，时钟使能信号产生单元基于同步单元33返回的反馈控制信号和时钟选择信号产生单元31当前产生的时钟选择信号产生当前需要的时钟使能信号。例如，如图3所示，时钟选择信号产生单元31当前产生的时钟选择信号clk_in_sel[i]cfg_clk(0≤i≤n-1)输出，经过一定延时后输入时钟使能信号产生单元的第一部分321，图3中标记为clk_in_sel[i]clk_in[i]表示时钟选择信号产生单元31输出的时钟选择信号clk_in_sel[i]cfg_clk延时后输入到时钟使能信号产生单元的信号，从同步单元33返回的反馈控制信号clk_in_en_sync[j](0≤j≤n-1且j≠i)输入时钟使能信号产生单元的第二部分322，时钟使能 信号产生单元的第二部分322对输入的反馈控制信号clk_in_en_sync[j]进行延迟处理后(即延迟一个时钟周期)输出给第一部分321，图3中clk_in_en_sync_dly[j]是时钟使能信号产生单元的第二部分322对clk_in_en_sync[j]延时一个时钟周期产生的信号，第一部分321基于延迟处理后的反馈控制信号clk_in_en_sync_dly[j]和当前输入的时钟选择信号clk_in_sel[i]clk_in[i]进行组合逻辑处理后，产生当前需要的时钟使能信号clk_in_en[i]并输出给同步单元33。其中，反馈控制信号clk_in_en_sync[j]是由同步单元33对之前输入的时钟使能信号clk_in_en[j]进行同步处理后输出的信号。
本发明实施例采用将经过同步后的时钟使能信号作为时钟使能信号产生单元的输入，即作为产生新时钟使能信号的反馈控制信号，在时钟使能信号产生单元判断其它所有的时钟使能信号都为低电平时才使能新的时钟使能信号。为保证输出的时钟周期是完整的，需要对输入时钟使能信号产生单元的反馈控制信号延迟一个时钟周期再使用，如图3所示，该延迟的动作由时钟使能信号产生单元的第二部分322执行。如图5中的圈1所示，若采用延时前的时钟使能信号clk_in_en_sync[i]作为反馈控制信号，则输出时有可能原时钟信号最后一个周期没有完全输出就切换到了新的时钟信号；如图3所示，采用延时处理后的时钟使能信号clk_in_en_sync_dly[i]产生新的时钟使能信号的话，如图5中的圈2所示，输出时原时钟信号最后一个周期可以完整的输出后再切换到新的时钟信号。其中，图5中，clk_out_*是指采用clk_in_en_sync[i]信号而不是延迟后的信号clk_in_en_sync_dly[i]作为反馈控制信号产生的输出信号；clk_out是采用clk_in_en_sync_dly[i]作为反馈控制信号产生的输出信号。其中，输出信号clk_out_*由经过门控单元34之后的输出控制信号clk_in_gate[0]和clk_in_gate[3]_*相或产生，clk_in_gate[3]_*采用信号clk_in_en_sync[i]作为反馈控制信号产生的门控后 时钟信号；输出信号clk_out由经过门控单元34之后的输出控制信号clk_in_gate[0]和clk_in_gate[3]相或产生，clk_in_gate[3]是采用延迟后的clk_in_en_sync_dly[i]作为反馈控制信号产生的门控后时钟信号。
同步单元33配置为同步时钟使能信号。如图3所示，同步单元33对时钟使能信号clk_in_en[i]同步后产生信号clk_in_en_sync[i]，分别输出给门控单元34和时钟使能信号产生单元的第二部分322。
门控单元34配置为基于同步单元33同步后的时钟使能信号，关断或开启时钟。如图3所示，同步后的时钟使能信号clk_in_en_sync[i]经过门控单元34后产生门控后的时钟信号clk_in_gate[0]～clk_in_gate[3]。在时钟从clk_in[0]切换到clk_in[3]时，门控后的时钟相或产生输出信号clk_out。
实施例三
本发明实施例提供一种时钟动态切换方法，该方法通过上述实施例一的时钟动态切换装置执行，如图7所示，主要可以包括如下步骤：
步骤601：时钟选择信号产生单元产生两个或两个以上时钟选择信号并传输给时钟使能信号产生单元，所述时钟选择信号具有如下特征：时钟选择信号的个数与需要切换的时钟个数相等；在任意时刻，有且只有一个时钟选择信号是有效的高电平或低电平；在任意时刻，有且只有两个时钟选择信号向相反的方向翻转；
这里，所述时钟选择信号产生单元基于配置时钟域产生所述时钟选择信号。
步骤602：时钟使能信号产生单元基于所述两个或两个以上时钟选择信号产生两个或两个以上时钟使能信号，并将所述时钟使能信号传输给同步单元；
其中，同步单元对所述时钟使能信号进行同步处理后作为所述反馈控制信号返回给所述时钟使能信号产生单元；时钟使能信号产生单元基于所 述时钟选择信号、以及所述同步单元返回的反馈控制信号产生所述时钟使能信号；其中，任意时刻，只有一个所述时钟使能信号是使能的。
例如，时钟使能信号产生单元对所述反馈控制信号延迟处理，再基于延迟处理后的反馈控制信号和当前输入的时钟选择信号产生所述时钟使能信号。这里的延迟处理为延迟一个时钟周期。
步骤603：同步单元对所述时钟使能信号进行同步处理并传输给门控单元；
步骤604：门控单元基于同步后的所述时钟使能信号，打开或关闭时钟信号的输出。
本实施例提供的方法的实现细节可以通过实施例一或实施例二的描述直接获得，不再赘述。并且，本实施例的方法同样适用于实施例二的4选1时钟动态切换装置，实现过程与上述流程相同，不再赘述。
显然，本领域的技术人员应该明白，上述的本发明的各模块或各步骤可以用通用的计算装置来实现，它们可以集中在单个的计算装置上，或者分布在多个计算装置所组成的网络上，可选地，它们可以用计算装置可执行的程序代码来实现，从而，可以将它们存储在存储装置中由计算装置来执行，并且在某些情况下，可以以不同于此处的顺序执行所示出或描述的步骤，或者将它们分别制作成各个集成电路模块，或者将它们中的多个模块或步骤制作成单个集成电路模块来实现。这样，本发明不限制于任何特定的硬件和软件结合。
以上所述，仅为本发明的较佳实施例而已，并非用于限定本发明的保护范围。

Claims (11)

  1. 一种时钟动态切换装置，所述装置包括：时钟选择信号产生单元、时钟使能信号产生单元、同步单元和门控单元；
    所述时钟选择信号产生单元，配置为产生两个或两个以上时钟选择信号并传输给所述时钟使能信号产生单元，所述时钟选择信号具有如下特征：时钟选择信号的个数与需要切换的时钟个数相等；在任意时刻，有且只有一个时钟选择信号是有效的高电平或低电平；在任意时刻，有且只有两个时钟选择信号向相反的方向翻转；
    所述时钟使能信号产生单元，配置为基于所述时钟选择信号产生单元传过来的多个时钟选择信号产生时钟使能信号，并将所述时钟使能信号传输给所述同步单元；
    同步单元，配置为对所述时钟使能信号进行同步处理并传输给所述门控单元；
    门控单元，配置为基于所述同步单元同步后的时钟使能信号，打开或关闭时钟信号的输出。
  2. 根据权利要求1所述的装置，其中，
    所述同步单元，还配置为对所述时钟使能信号进行同步处理后作为所述反馈控制信号返回给所述时钟使能信号产生单元；
    所述时钟使能信号产生单元，配置为基于所述时钟选择信号、以及所述同步单元返回的反馈控制信号产生所述时钟使能信号；其中，任意时刻，只有一个所述时钟使能信号是使能的。
  3. 根据权利要求2所述的装置，其中，所述时钟使能信号产生单元，还配置为对所述同步单元返回的反馈控制信号延迟处理，基于延迟处理后的反馈控制信号和当前输入的时钟选择信号产生所述时钟使能信号。
  4. 根据权利要求3所述的装置，其中，所述延迟处理是指延迟一个时 钟周期。
  5. 根据权利要求1～4任一项所述的装置，其中，所述时钟选择信号产生单元，还配置为基于配置时钟域产生所述时钟选择信号。
  6. 一种时钟动态切换方法，所述方法包括：
    时钟选择信号产生单元产生两个或两个以上时钟选择信号并传输给时钟使能信号产生单元，所述时钟选择信号具有如下特征：时钟选择信号的个数与需要切换的时钟个数相等；在任意时刻，有且只有一个时钟选择信号是有效的高电平或低电平；在任意时刻，有且只有两个时钟选择信号向相反的方向翻转；
    时钟使能信号产生单元基于所述两个或两个以上时钟选择信号产生两个或两个以上时钟使能信号，并将所述时钟使能信号传输给同步单元；
    同步单元对所述时钟使能信号进行同步处理并传输给门控单元；
    门控单元基于同步后的所述时钟使能信号，打开或关闭时钟信号的输出。
  7. 根据权利要求6所述的方法，其中，所述方法还包括：
    同步单元对所述时钟使能信号进行同步处理后作为所述反馈控制信号返回给所述时钟使能信号产生单元；
    时钟使能信号产生单元基于所述时钟选择信号、以及所述同步单元返回的反馈控制信号产生所述时钟使能信号；其中，任意时刻，只有一个所述时钟使能信号是使能的。
  8. 根据权利要求7所述的方法，其中，所述基于所述时钟选择信号、以及所述同步单元返回的反馈控制信号产生所述时钟使能信号，包括：
    时钟使能信号产生单元对所述反馈控制信号延迟处理，基于延迟处理后的反馈控制信号和当前输入的时钟选择信号产生所述时钟使能信号。
  9. 根据权利要求8所述的方法，其中，所述延迟处理为延迟一个时钟 周期。
  10. 根据权利要求6～9任一项所述的方法，其中，所述时钟选择信号产生单元基于配置时钟域产生所述时钟选择信号。
  11. 一种计算机可读介质，所述计算机可读介质中存储有可执行指令，所述可执行指令配置为执行权利要求6至10任一项所述的时钟动态切换方法。
PCT/CN2014/093859 2014-09-16 2014-12-15 时钟动态切换方法、装置及计算机可读介质 WO2016041278A1 (zh)

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Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107453735A (zh) * 2016-05-30 2017-12-08 珠海市微半导体有限公司 高频时钟无缝切换电路及其方法
CN106774632A (zh) * 2016-12-15 2017-05-31 深圳市博巨兴实业发展有限公司 一种微控制器芯片中的时钟多路控制单元
CN108169738B (zh) * 2017-11-23 2021-06-15 北京遥感设备研究所 一种双带宽中频线性调频脉冲信号产生方法及系统
CN107991653B (zh) * 2017-11-24 2020-02-21 北京遥感设备研究所 一种双带宽线性调频脉冲信号基带数据同步传输方法
CN110289840B (zh) * 2019-06-27 2023-04-11 百度在线网络技术（北京）有限公司 时钟切换电路以及用于时钟切换电路的时钟切换方法
CN110308763B (zh) * 2019-06-28 2023-10-24 西安紫光国芯半导体有限公司 一种多时钟电路及基于该电路产生目标时钟的方法
CN110502066B (zh) * 2019-08-15 2021-03-02 Oppo广东移动通信有限公司 时钟切换装置、方法及电子设备
CN115242224A (zh) * 2022-05-16 2022-10-25 无锡华大国奇科技有限公司 一种多时钟无毛刺切换电路及切换方法

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102012717A (zh) * 2010-11-16 2011-04-13 青岛海信信芯科技有限公司 一种时钟切换方法及时钟切换装置
CN203117836U (zh) * 2012-12-19 2013-08-07 江苏东大集成电路系统工程技术有限公司 一种时钟切换电路
CN103546125A (zh) * 2013-09-24 2014-01-29 北京时代民芯科技有限公司 一种多选一无毛刺时钟切换电路

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4853653A (en) * 1988-04-25 1989-08-01 Rockwell International Corporation Multiple input clock selector
US6275546B1 (en) * 1998-06-30 2001-08-14 Hewlett-Packard Company Glitchless clock switch circuit
US6600345B1 (en) * 2001-11-15 2003-07-29 Analog Devices, Inc. Glitch free clock select switch
CN2872451Y (zh) * 2005-11-01 2007-02-21 智多微电子（上海）有限公司 新型时钟动态切换电路
JP4790060B2 (ja) * 2007-03-20 2011-10-12 富士通セミコンダクター株式会社 クロック信号選択回路

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102012717A (zh) * 2010-11-16 2011-04-13 青岛海信信芯科技有限公司 一种时钟切换方法及时钟切换装置
CN203117836U (zh) * 2012-12-19 2013-08-07 江苏东大集成电路系统工程技术有限公司 一种时钟切换电路
CN103546125A (zh) * 2013-09-24 2014-01-29 北京时代民芯科技有限公司 一种多选一无毛刺时钟切换电路

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP3197054A4 *

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