WO2015175131A1 - Flexible display and method of formation with sacrificial release layer - Google Patents

Flexible display and method of formation with sacrificial release layer Download PDF

Info

Publication number
WO2015175131A1
WO2015175131A1 PCT/US2015/025873 US2015025873W WO2015175131A1 WO 2015175131 A1 WO2015175131 A1 WO 2015175131A1 US 2015025873 W US2015025873 W US 2015025873W WO 2015175131 A1 WO2015175131 A1 WO 2015175131A1
Authority
WO
WIPO (PCT)
Prior art keywords
flexible display
substrate
layer
leds
flexible
Prior art date
Application number
PCT/US2015/025873
Other languages
French (fr)
Inventor
Andreas Bibl
Dariusz Golda
Original Assignee
LuxVue Technology Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by LuxVue Technology Corporation filed Critical LuxVue Technology Corporation
Publication of WO2015175131A1 publication Critical patent/WO2015175131A1/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H01L25/167—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits comprising optoelectronic devices, e.g. LED, photodiodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
    • G09F9/301—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements flexible foldable or roll-able electronic displays, e.g. thin LCD, OLED
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L24/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1218—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or structure of the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1262—Multistep manufacturing methods with a particular formation, treatment or coating of the substrate
    • H01L27/1266—Multistep manufacturing methods with a particular formation, treatment or coating of the substrate the substrate on which the devices are formed not being the final device substrate, e.g. using a temporary substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/15—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components with at least one potential-jump barrier or surface barrier specially adapted for light emission
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/189—Printed circuits structurally associated with non-printed electric components characterised by the use of a flexible or folded printed circuit
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H05K3/4682—Manufacture of core-less build-up multilayer circuits on a temporary carrier or on a metal foil
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68318—Auxiliary support including means facilitating the separation of a device or wafer from the auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68359—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during manufacture of interconnect decals or build up layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68381—Details of chemical or physical process used for separating the auxiliary support from a device or wafer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/114—Manufacturing methods by blanket deposition of the material of the bump connector
    • H01L2224/1146—Plating
    • H01L2224/11462—Electroplating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/1147—Manufacturing methods using a lift-off mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13109—Indium [In] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13111—Tin [Sn] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24101—Connecting bonding areas at the same height
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24105—Connecting bonding areas at different heights
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/24221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/24225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/24227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the HDI interconnect not connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the semiconductor or solid-state body being mounted in a cavity or on a protrusion of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/245—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/27—Manufacturing methods
    • H01L2224/274—Manufacturing methods by blanket deposition of the material of the layer connector
    • H01L2224/2746—Plating
    • H01L2224/27462—Electroplating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/27—Manufacturing methods
    • H01L2224/2747—Manufacturing methods using a lift-off mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/29109—Indium [In] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/29111—Tin [Sn] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/32227—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the layer connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73259—Bump and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73267—Layer and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/81001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector involving a temporary auxiliary member not forming part of the bonding apparatus
    • H01L2224/81005—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector involving a temporary auxiliary member not forming part of the bonding apparatus being a temporary or sacrificial substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81192—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8138—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/81399—Material
    • H01L2224/814—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/81417—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/81424—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8138—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/81399—Material
    • H01L2224/814—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/81438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8138—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/81399—Material
    • H01L2224/814—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/81438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/81444—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8138—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/81399—Material
    • H01L2224/814—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/81463—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/81466—Titanium [Ti] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8138—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/81399—Material
    • H01L2224/81486—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8138—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/81399—Material
    • H01L2224/8149—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H01L2224/81805—Soldering or alloying involving forming a eutectic alloy at the bonding interface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H01L2224/8182—Diffusion bonding
    • H01L2224/81825—Solid-liquid interdiffusion
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H01L2224/8182—Diffusion bonding
    • H01L2224/8183—Solid-solid interdiffusion
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H01L2224/82001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI] involving a temporary auxiliary member not forming part of the bonding apparatus
    • H01L2224/82005—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI] involving a temporary auxiliary member not forming part of the bonding apparatus being a temporary or sacrificial substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H01L2224/821—Forming a build-up interconnect
    • H01L2224/82101—Forming a build-up interconnect by additive methods, e.g. direct writing
    • H01L2224/82102—Forming a build-up interconnect by additive methods, e.g. direct writing using jetting, e.g. ink jet
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H01L2224/821—Forming a build-up interconnect
    • H01L2224/82101—Forming a build-up interconnect by additive methods, e.g. direct writing
    • H01L2224/82104—Forming a build-up interconnect by additive methods, e.g. direct writing using screen printing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H01L2224/821—Forming a build-up interconnect
    • H01L2224/82106—Forming a build-up interconnect by subtractive methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/83001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector involving a temporary auxiliary member not forming part of the bonding apparatus
    • H01L2224/83005—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector involving a temporary auxiliary member not forming part of the bonding apparatus being a temporary or sacrificial substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83399—Material
    • H01L2224/834—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/83417—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/83424—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83399—Material
    • H01L2224/834—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/83438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83399—Material
    • H01L2224/834—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/83438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/83444—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83399—Material
    • H01L2224/834—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/83463—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/83466—Titanium [Ti] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83399—Material
    • H01L2224/83486—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83399—Material
    • H01L2224/8349—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/83801—Soldering or alloying
    • H01L2224/83805—Soldering or alloying involving forming a eutectic alloy at the bonding interface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/83801—Soldering or alloying
    • H01L2224/8382—Diffusion bonding
    • H01L2224/83825—Solid-liquid interdiffusion
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/83801—Soldering or alloying
    • H01L2224/8382—Diffusion bonding
    • H01L2224/8383—Solid-solid interdiffusion
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92222—Sequential connecting processes the first connecting process involving a bump connector
    • H01L2224/92224—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a build-up interconnect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92244—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/27—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
    • H01L24/92—Specific sequence of method steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/075—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00
    • H01L25/0753—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/15—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components with at least one potential-jump barrier or surface barrier specially adapted for light emission
    • H01L27/153—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components with at least one potential-jump barrier or surface barrier specially adapted for light emission in a repetitive configuration, e.g. LED bars
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/15—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components with at least one potential-jump barrier or surface barrier specially adapted for light emission
    • H01L27/153—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components with at least one potential-jump barrier or surface barrier specially adapted for light emission in a repetitive configuration, e.g. LED bars
    • H01L27/156—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components with at least one potential-jump barrier or surface barrier specially adapted for light emission in a repetitive configuration, e.g. LED bars two-dimensional arrays
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/1015—Shape
    • H01L2924/1016—Shape being a cuboid
    • H01L2924/10161—Shape being a cuboid with a rectangular active surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/1015—Shape
    • H01L2924/1016—Shape being a cuboid
    • H01L2924/10162—Shape being a cuboid with a square active surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12041—LED
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H01L2924/15155—Shape the die mounting substrate comprising a recess for hosting the device the shape of the recess being other than a cuboid
    • H01L2924/15156—Side view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18161—Exposing the passive side of the semiconductor or solid-state body of a flip chip
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18162—Exposing the passive side of the semiconductor or solid-state body of a chip with build-up interconnect
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10007—Types of components
    • H05K2201/10106—Light emitting diode [LED]

Definitions

  • the present invention relates to display systems. More particularly embodiments of the present invention relate to flexible display systems having semiconductor microchips and LEDs on a flexible display substrate.
  • Display panels are critical components in modern mobile electronic devices, such as smartphones, tablets, and laptop/notebook computers. Through recent development, flexible display panels are becoming a viable replacement for conventional rigid display panels. Flexible display panels are display panels that are not formed with a rigid substrate so that they can be curved and bent. Currently, organic light emitting diode (OLED) technology is widely adopted for forming flexible display panels. Typical OLED display panels are constructed from a glass substrate, on top of which are a circuit containing thin-film transistors and a capacitor, then the light emitting OLED devices and, finally, a transparent, protective layer on top. The thin-film transistor circuit is formed within the OLED display substrate and is subjected to constricting forces during curving and bending of the display. Furthermore, OLEDs need to be hermetically sealed because they are hypersensitive to oxygen and water.
  • the method includes forming a sacrificial layer on a carrier substrate.
  • the method also includes forming a flexible display substrate on the sacrificial layer where the flexible display substrate includes a plurality of release openings that extend through the flexible display substrate to the sacrificial layer.
  • the method includes transferring an array of LEDs and a plurality of microchips onto the flexible display substrate.
  • the flexible display substrate is formed by spinning on a photo-definable material.
  • forming the flexible display substrate includes forming at least one photo-definable polymer layer and at least one metal layer.
  • Forming the at least one metal layer may be performed by sputtering.
  • the method further includes etching a plurality of openings in the sacrificial layer and forming the flexible display substrate on the sacrificial layer and within the openings to form a plurality of posts extending through the sacrificial layer.
  • the method further includes selectively removing the sacrificial layer and separating the flexible display substrate from the carrier substrate. Selectively removing the sacrificial layer may be performed by a process selected from the group consisting of a vapor etching process and a plasma etching process.
  • the method further includes forming a transparent contact for each LED in the array of LEDs, forming a black matrix layer on the flexible display substrate where the black matrix layer surrounds the array of LEDs, and covering the array of LEDs and the plurality of microchips with a protective material. Covering the array of LEDs may be performed by a process selected from the group consisting of a slit-coating process and a laminating process.
  • a flexible display panel includes a flexible substrate including a front surface, a back surface, and a display area on the front surface.
  • the flexible display panel also includes a plurality of interconnects that extend at least partially through the flexible substrate from the front surface to the back surface where the flexible substrate and the plurality of interconnects form a build-up structure.
  • the flexible display panel includes an array of light emitting diodes (LEDs) and a plurality of microchips on the front surface of the flexible display substrate in the display area and electrically coupled to the plurality of interconnects.
  • a plurality of release openings may extend through the flexible substrate from the front surface to the back surface.
  • Each microchip of the plurality of microchips may include a driving circuit to drive one or more LEDs to emit light.
  • the plurality of microchips are electrically coupled to the array of LEDs.
  • the flexible display panel further includes at least one display component electrically coupled to the array of microchips on the front surface of the flexible substrate through the plurality of interconnects, where the display component comprises a chip selected from the group consisting of a sense controller chip, a scan driver chip, a data driver chip, a processor chip, and a power supply.
  • the display component may be on the back surface of the flexible substrate. Further, the display component may be on the front surface of the flexible substrate outside of the display area.
  • the build-up structure includes at least one layer of polymer and at least one layer of metal.
  • a structure in an embodiment, includes a carrier substrate, a flexible substrate on the carrier substrate where the flexible substrate includes a plurality of electrical interconnects that extend at least partially between a front surface and a back surface of the flexible substrate, and an array of LEDs and a plurality of microchips on the front surface of the flexible display substrate.
  • the structure also includes a sacrificial release layer between the back surface of the flexible substrate and the carrier substrate within a display area on the front surface, and a plurality of release openings that extend through the flexible substrate from the front surface to the back surface and expose the sacrificial release layer.
  • the back surface of the flexible substrate includes a plurality of support posts. Each support post of the plurality of support posts may be laterally surrounded by the sacrificial release layer.
  • the sacrificial layer may include a material selected from the group consisting of an oxide and a nitride.
  • FIG. 1A is a cross-sectional side view illustration of an array of flexible display panels with covered release openings mounted on a carrier substrate in accordance with an embodiment of the invention.
  • FIG. IB is a cross-sectional side view illustration of an array of flexible display panels with exposed release openings mounted on a carrier substrate in accordance with an embodiment of the invention.
  • FIG. 1C is a schematic top view illustration of an array of flexible display panels with exposed release openings mounted on a carrier substrate in accordance with an embodiment of the invention.
  • FIG. 2 is a cross-sectional side view illustration of a flexible display substrate with LEDs and microchips on a front surface of the flexible display substrate and component bond pads on a back surface of the flexible display substrate in accordance with an embodiment of the invention.
  • FIG. 3 is a cross-sectional side view illustration of a flexible display substrate with LEDs and microchips on a front surface of the flexible display substrate and component bond pads on the front surface of the flexible display substrate in accordance with an embodiment of the invention.
  • FIGS. 4A-4P illustrate a method of fabricating a flexible display panel including a flexible display substrate with arrays of LEDs and microchips on a front surface of the flexible display substrate and a plurality of covered release openings in accordance with an embodiment of the invention.
  • FIGS. 4Q-4S illustrate a method of fabricating a flexible display panel including a flexible display substrate with arrays of LEDs and microchips on a front surface of the flexible display substrate and a plurality of exposed release openings in accordance with an embodiment of the invention.
  • FIG. 5 is a cross-sectional side view illustration of a flexible display panel being separated from a carrier substrate in accordance with an embodiment of the invention.
  • FIG. 6 is a perspective view of a flexible display panel illustrating an arrangement of
  • FIG. 7A is a cross-sectional side view illustration of a flexible display panel with back component bond pads after separation from a carrier substrate in accordance with an embodiment of the invention.
  • FIG. 7B is a cross-sectional side view illustration of a flexible display system including a flexible display panel and a plurality of display components mounted on a back surface of the flexible display panel in accordance with an embodiment of the invention.
  • FIG. 8A is a cross-sectional side view illustration of a flexible display panel with front component bond pads after separation from a carrier substrate in accordance with an embodiment of the invention.
  • FIG. 8B is a cross-sectional side view illustration of a flexible display system including a flexible display panel and a plurality of display components mounted on a front surface of the flexible display panel in accordance with an embodiment of the invention.
  • FIG. 9A is a schematic top view illustration of a back surface of a flexible display system including a flexible display panel and a plurality of display components mounted on a back surface of the flexible display panel in accordance with an embodiment of the invention.
  • FIG. 9B is a schematic top view illustration of a front surface of a flexible display system including a flexible display panel and a plurality of display components mounted on a front surface of the flexible display panel outside of a display area in accordance with an embodiment of the invention.
  • a method of manufacturing a flexible display system includes forming a sacrificial layer on a carrier substrate.
  • a flexible display substrate is formed on the sacrificial layer, with a plurality of release openings that extend through the flexible display substrate to the sacrificial layer.
  • the flexible display substrate is formed using a photo-definable polymer.
  • An array of light emitting diodes (LEDs) and a plurality of microchips are transferred onto the flexible display substrate to form a flexible display panel.
  • the sacrificial layer is selectively removed such that the flexible display panel attaches to the carrier substrate by a plurality of support posts.
  • the flexible display panel is removed from the carrier substrate and is electrically coupled with display components to form a flexible display system.
  • spanning may refer to a relative position of one layer with respect to other layers.
  • One layer “spanning”, “over” or “on” another layer or bonded “to” or in “contact” with another layer may be directly in contact with the other layer or may have one or more intervening layers.
  • One layer “between” layers may be directly in contact with the layers or may have one or more intervening layers.
  • the flexible display panel described herein includes a flexible display substrate having an array of LEDs and a plurality of microchips on a front surface of the flexible display substrate within a display area.
  • the flexible display substrate is a build-up structure that has more than one layer of insulating material and more than one layer of conductive material. At least one layer of conductive material within the flexible substrate electrically couples the array of LEDs to the plurality of microchips.
  • bond pads are exposed on a back surface of the flexible display substrate to which display components electrically connect.
  • bond pads are exposed on the front surface of the flexible display substrate outside of a display area.
  • the bond pads are electrically coupled to the plurality of microchips on the front surface of the flexible display substrate.
  • the conductive material within the flexible substrate electrically couples the bond pads to the plurality of microchips.
  • the flexible display panel is fabricated by forming a layer of sacrificial material on a carrier substrate. A plurality of openings is formed in the sacrificial layer, within which a portion of the flexible display substrate is formed. The portion of the flexible display substrate in the plurality of openings forms a plurality of posts that extends through the sacrificial layer.
  • the flexible display substrate is constructed by forming at least one layer of insulating material and one layer of conductive material. An array of LEDs and a plurality of microchips are then transferred onto a front surface of the flexible display substrate.
  • the array of LEDs and the plurality of microchips are transferred onto the flexible display substrate by mass transfer tools operating using electrostatic principles to pick up and transfer large arrays of LEDs and microchips. Electrostatic transfer enables driving circuitry to be located on the front surface of the flexible display substrate, rather than embedded within the flexible display substrate.
  • the array of LEDs and the plurality of microchips are covered with a transparent material to protect it from physical, environmental, and/or electrical disturbance while allowing for the visualization of light emitted from the array of LEDs.
  • the flexible substrate containing the array of LEDs and the plurality of microchips is separated from the carrier substrate by selectively removing the sacrificial layer and pulling the display substrate away from the carrier substrate, resulting in a flexible display panel that can be integrated with additional display components to form a display system.
  • a flexible display system includes a flexible display panel having an array of LEDs and a plurality of microchips on a front surface of the flexible display substrate.
  • a plurality of display components is electrically coupled to the plurality of microchips through the flexible display substrate.
  • the plurality of display components is located on the back surface of the flexible display substrate directly behind the display area.
  • the plurality of display components can include, but are not limited to, scan drivers, data drivers, sense controllers, write controllers, microcontrollers, and power supplies.
  • the plurality of display components is located on the front surface of the flexible display substrate outside of a display area.
  • the flexible display substrate is formed with one or more layers of insulating material and one or more layers of conductive material.
  • the layered structure of the flexible display substrate allows the flexible display panel to bend in various directions and to various degrees while maintaining electrical connectivity between the display components, microchips, and LEDs.
  • the flexible display system is enabled to display images or sense light while being bent in various directions.
  • the interactive display panel described herein is a micro LED active matrix display panel formed with semiconductor-based micro LEDs. Such a micro LED active matrix display panel utilizes the performance, efficiency, and reliability of semiconductor-based LEDs for emitting light.
  • a micro LED active matrix display panel enables a display panel to achieve high resolutions, pixel densities, and subpixel densities due to the small size of the micro LEDs and microchips.
  • the high resolutions, pixel densities, and subpixel densities are achieved due to the small size of the micro LEDs and microchips.
  • micro refers to the descriptive size of certain devices or structures in accordance with embodiments.
  • the term “micro” is meant to refer to the scale of 1 to 300 ⁇ or, more specifically, 1 to 100 ⁇ . In some embodiments, “micro” may even refer to the scale of 1 to 50 ⁇ , 1 to 20 ⁇ , or 1 to 10 ⁇ .
  • embodiments of the present invention are not necessarily so limited, and that certain aspects of the embodiments may be applicable to larger, and possibly smaller size scales.
  • a 55 inch interactive television panel with 1920 x 1080 resolution, and 40 pixels per inch (PPI) has an approximate RBG pixel pitch of (634 ⁇ x 634 ⁇ ) and subpixel pitch of (211 ⁇ x 634 ⁇ ).
  • each subpixel contains one or more micro LEDs having a maximum width of no more than 211 ⁇ .
  • the size of the micro LEDs may be further reduced.
  • a 5 inch interactive display panel with 1920 x 1080 resolution, and 440 pixels per inch (PPI) has an approximate RBG pixel pitch of (58 ⁇ x 58 ⁇ ) and subpixel pitch of (19 ⁇ x 58 ⁇ ).
  • each subpixel may additionally be reduced below the pixel pitch of 58 ⁇ . Accordingly, some embodiments combine with efficiencies of semiconductor-based LEDs for emitting light with the scalability of semiconductor-based LEDs, and optionally microchips, to the micro scale for implementation into high resolution and pixel density applications.
  • FIG. 1A is a cross-sectional side view illustration of a plurality of flexible display panels 103 with covered release openings 111 mounted on a carrier substrate 101 in accordance with an embodiment of the invention.
  • the illustrated embodiment depicts the plurality of flexible display panels 103 after removal of the sacrificial layer and before separation from the carrier substrate 101.
  • the flexible display panels 103 have multiple sections 102 that will be described in more detail when discussing the method of forming the flexible display panel 103 below.
  • the plurality of flexible display panels 103 is on the carrier substrate 101.
  • the carrier substrate 101 is any suitable substrate, such as glass, upon which the flexible display panel 103 can be formed.
  • the carrier substrate 101 is rigid enough to withstand process forces associated with the transfer of the array of LEDs and the plurality of microchips to the flexible display panel 103 with an electrostatic transfer head.
  • the carrier substrate 101 is formed of a material that can be reused for making new batches of flexible display panels 103.
  • Each flexible display panel 103 is separated from adjacent flexible display panels by a trench 109.
  • the trench 109 physically separates each flexible display panel 103 so that each flexible display panel 103 can be removed individually without interfering or damaging an adjacent flexible display panel.
  • the flexible display panel 103 includes a flexible substrate 105 formed from at least one layer of insulating material and at least one layer of conductive material.
  • the insulating material is a polymer.
  • the insulating material is a photo-definable polymer, such as an acrylic or an SU-8 photoresist (i.e., an epoxy photoresist).
  • the flexible substrate 105 is formed of at least one layer of photo- definable polyimide and at least one layer of metal. Although any insulating material may be used in embodiments, polyimide and metal may be a viable combination because of its ease of use and cost effectiveness.
  • An array of LEDs 106 and a plurality of microchips 108 are located on the flexible display substrate 105.
  • a transparent protective layer 107 is formed over the array of LEDs, plurality of microchips, and exposed top surfaces of the flexible display substrate 105.
  • the transparent protective layer 107 is polymethyl methacrylate (PMMA) or acrylic glass. Furthermore, a plurality of release openings 111 extends through the flexible display substrate 105. The release openings 111 and trenches 109 provide channels within which an etchant may flow to remove the sacrificial layer as will be discussed further below. In this embodiment, the release openings 111 are covered by the transparent protective layer 107 so that holes do not extend through the flexible display panel 103.
  • PMMA polymethyl methacrylate
  • acrylic glass acrylic glass
  • a plurality of release openings 111 extends through the flexible display substrate 105.
  • the release openings 111 and trenches 109 provide channels within which an etchant may flow to remove the sacrificial layer as will be discussed further below.
  • the release openings 111 are covered by the transparent protective layer 107 so that holes do not extend through the flexible display panel 103.
  • FIG. IB is a cross-sectional side view illustration of an array of flexible display panels 103 with exposed release openings 111 mounted on a carrier substrate 101 in accordance with an embodiment of the invention.
  • the illustrated embodiment depicts the plurality of flexible display panels 103 after removal of the sacrificial layer and before separation from the carrier substrate 101.
  • the plurality of flexible display panels 103 is on the carrier substrate 101.
  • Each flexible display panel 103 is separated from adjacent flexible display panels by a trench 109.
  • the trench 109 physically separates each flexible display panel 103 so that each flexible display panel 103 can be removed individually without interfering or damaging an adjacent flexible display panel.
  • An array of LEDs 106 and a plurality of microchips 108 are located on the flexible display substrate 105.
  • a transparent protective layer 107 such as PMMA, is formed over the array of LEDs, plurality of microchips, and exposed top surfaces of the flexible display substrate 105. Furthermore, a plurality of release openings 111 extends through the flexible display substrate 105. The release openings 111 provide a channel within which an etchant may flow to remove the sacrificial layer as will be discussed further below. In this embodiment, the transparent protective layer 107 does not cover the release openings 111. Rather, an opening is formed through the transparent protective layer 107 and the release openings 111. Accordingly, the plurality of exposed release openings 111 creates a perforated flexible display panel 103.
  • FIG. 1C is a schematic top view illustration of an array of flexible display panels 103 with release openings 111 mounted on a carrier substrate 101 in accordance with an embodiment of the invention.
  • Each flexible display panel 103 is separated from another flexible display panel by vertical and horizontal trenches 109.
  • Interspersed within the array of LEDs 106 is the plurality of microchips 108.
  • the plurality of microchips 108 controls the emission and/or sensing of the array of LEDs.
  • the transparent protective layer 107 covers the array of LEDs 106 and the plurality of microchips 108 to protect them from damage or electrical interference.
  • the array of LEDs 106 are covered with a transparent protective layer 107 to allow light to be emitted or sensed from the array of LEDs 106.
  • the plurality of release openings 111 is located within the inner area of the flexible display panels 103. In an embodiment, the release openings 111 are covered release openings. Alternatively, in an embodiment, the release openings 111 are uncovered release openings. Release openings 111 allow etchants to remove the sacrificial layer located directly below the flexible display panel 103. In an embodiment, the release openings 111 are equidistant from one another to so that etchants have the same amount of distance to travel between each release opening 111.
  • the release openings 111 may be designed to have a higher concentration or larger size in areas that are more difficult for etchants to reach, e.g., at locations farther away from trenches 109.
  • release openings 111 enable the complete removal of sacrificial material below the flexible display substrates 103.
  • FIG. 2 is a cross-sectional side view illustration of a flexible display substrate 105 with LEDs 106 and microchips 108 on a front surface of the flexible display substrate 105 and back component bond pads 213 on a back surface 225 of the flexible display substrate 105 in accordance with an embodiment of the invention.
  • the illustration in FIG. 2 depicts a section 102 of the flexible display panel 103 and does not show a cross-section of the whole flexible display 103.
  • the flexible display substrate 105 is formed on a carrier substrate 101, which may be formed of glass.
  • the flexible display substrate 105 is formed from at least one layer of insulating material and at least one layer of conductive material.
  • the insulating material is a polymer.
  • the insulating material is a photo-definable polymer, such as an acrylic or an SU-8 photoresist.
  • the insulating material is a photo-definable polyimide and the conductive material is a metal.
  • the flexible display substrate 105 is formed from more than one insulating layers 203, 205, 207, and 209 and more than one conductive layer 211, 217, and 218.
  • the insulating layers 203, 205, 207, and 209 are layered with the conductive layers 211, 217, and 218 to form a build-up structure in one embodiment.
  • the build-up structure is a series of insulating layers with interconnect structures and conductive lines formed within.
  • the interconnect structures electrically couple conductive lines to one another to form larger interconnect systems that span multiple layers.
  • the insulating layers 203, 205, 207, and 209 are in the range of 2 to 2.5 ⁇ thick to provide structural strength and sufficient electrical isolation between conductive layers when the flexible display panel is bent.
  • the conductive layers 211, 217, and 218 are structured so that the back surface 225 of the flexible display substrate 105 is electrically coupled to the front surface 223 of the flexible display substrate 105.
  • the front surface 223 of the flexible display substrate 105 includes a plurality of wells with side surfaces 221 in which the LEDs 106 and microchips 108 are transferred.
  • FIG. 2 depicts the LEDs 106 and the microchips 108 in wells
  • the front surface 223 of the flexible display substrate 105 may not have a plurality of wells, but rather have a flat surface upon which the LEDs and microchips are transferred.
  • the microchips 108 are electrically coupled to the LEDs through at least one of the conductive layers 211, 217, and 218 within the flexible display substrate 105.
  • the microchips 108 are electrically coupled to the back surface 225 of the flexible display substrate 105 through the conductive layers 211, 217, and 218.
  • the back surface 225 of the flexible display substrate 105 includes back component bond pads 213 having back component bonding surfaces 215 for electrical coupling to display components as will be discussed further below.
  • a transparent top contact 229 is located on the LEDs 106 to form an electrical connection between the LEDs 106 and a ground electrode (Vss) 233.
  • the transparency of the top contact 229 allows light emitting to or from the LEDs 106 to easily pass through the top contact 229.
  • the transparent contact 229 may be formed from any suitable transparent and conductive material, such as indium tin oxide ( ⁇ ) in one embodiment.
  • positive voltage may be applied by the microchip 108 to forward bias the LEDs 106, whose cathode electrode is grounded by the transparent top contact 229 and the metal ground electrode 223. It is to be appreciated that forward biasing the LEDs is but only one exemplary operation, to which other embodiments are not limited. For instance, the LEDs 106 may be reverse biased to sense light.
  • a sidewall passivation material 227 is located between the sidewalls 221 of the wells and the LEDs 106.
  • the sidewall passivation material 227 stabilizes the LEDs 106 and prevents particles from falling underneath the LEDs 106. Additionally, the sidewall passivation material 227 passivates sidewalls of the LEDs to prevent shorting of an active layer as well as provides step coverage for structures (e.g., metal contacts, transparent acrylics, transparent oxides, and/or transparent polymers, such as those that may form top contact 229) formed upon it.
  • a black matrix layer 231 is formed over the front surface 225 of the flexible display substrate 105. The black matrix layer 231 may absorb all wavelengths of visible light to prevent light from bleeding between adjacent LEDs. Accordingly, the black matrix layer 231 may mitigate any self- generated light disturbance within the flexible display panel 103 while the flexible display panel 103 is displaying an image.
  • a sacrificial layer 201 is formed in between the carrier substrate 101 and the flexible display substrate 105.
  • the sacrificial layer 201 may be formed from any suitable material that can be etched selective to the flexible display substrate 105 and the carrier substrate 101.
  • the sacrificial layer 201 is formed from silicon dioxide.
  • the sacrificial layer 201 acts as a support layer for the fabrication of the flexible display panel 103 as well as an adhesive to secure the flexible display substrate 105 during fabrication.
  • the sacrificial layer 201 may be selectively removed to allow separation of the flexible display panel 103 from the carrier substrate 101.
  • a plurality of posts 202 extends through the sacrificial layer
  • the structure of the posts 202 affects adhesion strength between the flexible display panel 103 and the carrier substrate 101 as well as the amount of force required to separate the flexible display panel 103 from the carrier substrate 101.
  • Wider posts 202 increase the adhesion strength and the required separation force due to an increase in surface area that makes contact with the carrier substrate 101.
  • the number of posts 202 affects adhesion strength and separation force as well. An increase in the number of posts 202 increases the surface area adhered to the carrier substrate 101. As such, an increase in posts 202 increases the adhesion strength and the required force to separate the flexible display panel 103 from the carrier substrate 101.
  • Trenches 109 are at the ends of the flexible display panel 103.
  • the sacrificial layer 201 extends from underneath the flexible display substrate 105 and forms a layer across the bottom of the trench 109.
  • the sacrificial layer 201 does not extend from underneath the flexible display substrate 105.
  • the trenches 109 expose the sacrificial layer 201 such that etchants may reach the sacrificial layer 201.
  • release openings 111 are formed through the flexible display substrate 105 to expose the sacrificial layer 201. The release openings 111 form a passageway for etchants to reach the sacrificial layer 201.
  • FIG. 3 is a cross-sectional side view illustration of a flexible display substrate 105 with LEDs 106 and microchips 108 on a front surface 223 of the flexible display substrate 105 and front component bond pads 301 on the front surface 223 of the flexible display substrate 105 in accordance with an embodiment of the invention.
  • the front component bond pads 301 are electrically coupled to the microchip 108 for sending electrical signals to the microchips 108.
  • a top surface 303 of the front component bond pad 301 is exposed to allow a display component to make electrical connection to the microchip 108 through at least one of the conductive layers 211, 217, and 218. Having the front component bond pads 301 on the front surface 223 of the flexible display substrate 105 allow display components to be placed on the front surface 223 of the flexible display panel 103 outside of a display area.
  • Trenches 109 are at the ends of the flexible display panel 103.
  • the trenches 109 expose the sacrificial layer 201 such that etchants may reach the sacrificial layer 201.
  • release openings 111 are formed through the flexible display substrate 105 to expose the sacrificial layer 201.
  • the release openings 111 form a passageway for etchants to reach the sacrificial layer 201.
  • FIGS. 4A-4S illustrate a method of fabricating a flexible display panel 103 including a flexible display substrate 105 with LEDs 106 and microchips 108 on a front surface 223 of the flexible display substrate in accordance with embodiments of the invention.
  • FIGS. 4A-4P illustrate a method of fabricating a flexible display panel 103 with LEDs 106 and microchips 108 on a front surface 223 of the flexible display substrate 105 with covered release openings 111.
  • FIGS. 4Q-4S illustrate a method of fabricating a flexible display panel 103 with LEDs 106 and microchips 108 on a front surface 223 of the flexible display substrate 105 with exposed release openings 111 as continued from FIG. 4N.
  • a sacrificial layer 201 is formed on a carrier substrate 101.
  • the carrier substrate 101 is glass.
  • the sacrificial layer 201 may be formed from any material that can be etched selective to the insulating material used to form the flexible display substrate 105 and the carrier substrate 101.
  • the sacrificial layer is formed from silicon dioxide.
  • the thickness of the sacrificial layer 201 ranges from 0.5 to 1.5 ⁇ .
  • the sacrificial layer may be formed by a deposition process such as, but not limited to, chemical vapor deposition (CVD) or physical vapor deposition (PVD).
  • openings 401 are etched into the sacrificial layer 201.
  • the openings 401 may be spaced evenly apart from one another or arranged in a specific pattern.
  • openings 401 are patterned so that there is an equal distribution of openings dispersed around the area within which the flexible display panel 103 is to be formed.
  • the placement of openings 401 determines the locations of posts 202 as shown in FIG. 4C.
  • a first layer 203 of the flexible display substrate 105 is formed on the sacrificial layer 201 and within the trench 109.
  • the first layer 203 is formed from an insulating material.
  • the insulating material may be a polymer or a photo-definable insulating material, such as a photo-definable polymer.
  • the photo-definable polymer may be an acrylic or an SU-8 photoresist.
  • the first layer 203 is formed from a photo-definable polyimide, so that exposure to electromagnetic radiation chemically modifies the molecular structure of the polyimide to allow solubility in a developer solution.
  • the photo-definable insulating material enables patterning without forming a separate mask layer, such as a photoresist. Therefore, having the photo-definable insulating material may reduce patterning operations and cost.
  • the first layer 203 fills in the openings 401 to form a plurality of posts 202.
  • the posts 202 are essentially an extension of the first layer 203 of insulating material such that the posts 202 and the first layer 203 form one integrated structure.
  • the first layer 203 of the flexible display substrate 105 may be formed by spinning on or spray coating a layer of insulating material. When the insulating material is spun on, it fills in the openings 401 and subsequently forms the plurality of posts 202.
  • via openings 403, release openings 111, and trenches 109 are etched into the first layer 203 of the flexible display substrate 105.
  • the trenches 109, via openings 403, and release openings 111 extend through the first layer 203 and expose the sacrificial layer 201 underneath.
  • the via openings 403 are openings used for forming an interconnect via to electrically couple structures above and below the first layer 203.
  • the release openings 111 and trenches 109 are openings used to provide a passageway for etchant chemicals to remove the sacrificial layer 201.
  • the via openings 403, release openings 111, and trenches 109 may be formed by conventional patterning and developing techniques.
  • patterned electromagnetic radiation such as visible or ultraviolet light
  • another suitable patterning technique may be used to form the openings 403, 111, 109 in the first layer 203.
  • a first conductive layer 405 is formed over the first layer 203 and within the via openings 403, release openings 111, and trenches 109.
  • the first conductive layer 405 may be formed from a conductive material, such as a metal or a metal alloy, or any combination of multiple layers of conductive materials.
  • the first conductive layer 405 is a titanium-gold-titanium (Ti-Au-Ti) layer stack where a layer of gold is sandwiched between two thin layers of titanium.
  • the first conductive layer 405 may be formed with Ti-Au-Ti because although gold is an excellent conductor and is highly resistant to oxidation, it does not adhere well with insulating materials, such as the first layer 203. As such, adding the outer layers of titanium, which adheres well with insulating material, allows the gold layer to be securely attached to the first layer 203. It is to be appreciated that the thickness of gold may be much greater than the thickness of titanium. In an embodiment, the gold to titanium layer thickness ratio ranges from 5: 1 to 10:1. Formation of the first metal layer 405 may be performed by a conformal deposition technique. In one embodiment, the first conductive layer 405, having multiple layers of conductive materials, is formed by sputtering.
  • openings 407 are etched in the first conductive layer 405 to form back component bond pads 213 having back component bonding surfaces 215 and a first conductive layer 211.
  • the back component bond pads 213 conform to the surfaces of the opening 403 and first layer 203 upon which they are formed.
  • first conductive layer 211 is a part of an electrical connection between two semiconductor devices within the flexible display substrate 105.
  • the conductive layer formed within the release openings 111 and trenches 109 is removed to expose the sacrificial layer 201 in order for an etchant to reach the sacrificial layer 201 by access through the release openings 111 and trench 109.
  • the openings 407 in the first conductive layer 405 may be etched by a mask and etch process, such as an anisotropic dry or plasma etch process.
  • FIG. 4G illustrates the flexible display substrate 105 subsequent to iterative formation of second and third insulating layers 205 and 207, respectively, and second and third conductive layers 217 and 218, respectively, with process techniques and conductive materials discussed in FIGS. 4C-4F according to an embodiment of the invention.
  • the third conductive layer 218 includes various device bond pads, such as a ground pad 411, LED pads 413, and microchip pads 415.
  • the second conductive layer 217 is an interconnect layer designed to form various interconnections between back component bond pads 213 and the ground pad 411, LED pads 413, and microchip pads 415.
  • the conductive layers 217 and 218 may be a single conductive layer or multiple conductive layers formed from any conductive material, such as but not limited to, amorphous silicon, conductive oxides, conductive polymers, metals, and metal alloys.
  • the conductive layers 217 and 218 are formed from aluminum, titanium, or an aluminum and titanium alloy.
  • the conductive layers 217 and 218 may be formed from more than one metal layer, such as a titanium- tungsten alloy and gold layer (TiW-Au) or a titanium and aluminum (Ti-Al) layer.
  • the back component bond pads 213 are electrically coupled to the microchip pads 415 of the flexible display substrate 105 through the second and third conductive layers 217 and 218, respectively.
  • FIG. 4G illustrates three insulating layers and three conductive layers, embodiments are not so limited.
  • Various openings 409 in the top conductive layer 218 have been etched to form the ground, LED, and microchip pads 411, 413, and 415, respectively.
  • release openings 111 and trenches 109 have continuously been etched to expose the sacrificial layer 201 such that etchants may access the sacrificial layer 201 through the release openings 111 and trenches 109.
  • a fourth layer 209 is formed on a portion of the exposed pads 411, 413, and 415 and on exposed top surfaces of the third layer 207 using any of a variety of techniques such as inkjet printing, screen printing, lamination, spin coating, spray coating, CVD, and PVD.
  • the fourth layer 209 may be formed of a variety of insulating materials such as, but not limited to, photo-definable acrylic, photoresist, silicon dioxide, silicon nitride, poly(methyl methacrylate) (PMMA), benzocyclobutene (BCB), polyimide, SU-8 photoresist, acrylate, epoxy, and polyester.
  • the fourth layer 209 is formed of an opaque material such as a black matrix material.
  • exemplary insulating black matrix materials include organic resins, glass pastes, and resins or pastes including a black pigment, metallic particles such as nickel, aluminum, molybdenum, and alloys thereof, metal oxide particles (e.g., chromium oxide), or metal nitride particles (e.g., chromium nitride).
  • the fourth layer 209 is formed from the same material as the first through third layers 203, 205, and 207, respectively, such as a photo- definable insulating material, or any other protective, flexible material.
  • the fourth layer 209 has openings 417 that expose the ground pad 411, LED pads 413, and microchip pads 415 to which electrical devices may be electrically coupled. As shown in FIG. 4H, the openings 417 in the fourth layer 209 have oblique sidewalls 221 that slope downward to form a well or a bank structure.
  • the well may be used for optical separation of adjacent LEDs to prevent optical interference. Additionally, in an embodiment, a surface of the well may be used to form mirrors to aid in light extraction.
  • the well may provide a structure for pooling sidewall passivation material 227 to passivate sidewalls of the LEDs to prevent shorting of an active layer, and may provide a structure for providing better step coverage for structures (e.g., top contact 229) formed upon it.
  • conductive ground electrodes 233 are formed on the fourth layer 209 and on the ground pad 411. Conductive ground electrodes 233 provide electrical
  • ground electrodes 233 are electrically coupled with at least the second conductive layer 217 through the ground pad 411 to form a connection to ground.
  • the conductive ground electrodes 233 may be formed by a deposition and etch technique. In an embodiment, the conductive ground electrodes 233 are formed by sputtering followed by an anisotropic etch process.
  • device bonding layers 222 are formed on the exposed LED pads 413 and microchip pads 415 to facilitate bonding of electrical devices.
  • the device bonding layers 222 are selected for its ability to be interdiffused with a bonding layer on the electrical devices (that are to be placed on the pads) through bonding mechanisms such as eutectic alloy bonding, transient liquid phase bonding, or solid state diffusion bonding.
  • the device bonding layers 222 have a melting temperature of 250°C or lower.
  • the device bonding layers 222 may include a solder material such as tin (232°C) or indium (156.7°C), or alloys thereof.
  • Device bonding layers 222 may also be in the shape of a post.
  • taller device bonding layers 222 may provide an additional degree of freedom for system component leveling, such as planarity of the electrical devices with the pad during device transfer operations and for variations in height of the devices, due to the change in height of the liquefied bonding layers as they spread out over the pad during bonding.
  • the width of the device bonding layers 222 may be less than a width of a bottom surface of the electrical devices to prevent wicking of the device bonding layers 222 around the sidewalls of the electrical devices which can cause electrical shorting.
  • the device bonding layers 222 may be formed by a photoresist lift-off technique or electroplating.
  • LEDs 106 and microchips 108 are transferred onto the device interconnect layers 222 such that the LEDs 106 and microchips 108 are electrically coupled to the LED pads 413 and microchip pads 415, respectively.
  • the LEDs 106 are micro LEDs having a device size of 1-20 ⁇ .
  • the LEDs 106 may be any color-emitting LED, such as a red-, green-, blue-, infrared-, cyan-, white-, yellow-, or any other color-emitting LED.
  • the microchips 108 may contain circuitry to receive signals from display components extraneous to the flexible display substrate 105 as well as circuitry to operate the LEDs 106 according to the received signals.
  • the microchips 108 contain driving circuitry to drive the LED in forward bias mode for emitting light.
  • the microchips 108 may also contain a selection device, such as a multiplexer, to disconnect the LED from the driving circuit and connect to a sensing circuit to operate the LED in reverse bias mode for sensing light.
  • FIG. 4K illustrates only two LEDs and one microchip 108, embodiments of the present invention are not limited to such configurations. Rather, any number of LEDs 106 and any number of microchips 108 may transferred onto the flexible display substrate 105. More specifically, the number and size of the LEDs and microchips 108 may scale according to the resolution or size of the flexible display panel 103.
  • LEDs and microchips 108 may be formed in flexible display panels that require higher resolutions and/or smaller flexible display panels 103.
  • the LEDs 106 and microchips 108 are electrostatically transferred onto the device bonding layers 222 by a pickup-and-placement method.
  • an electrostatic transfer head uses electrostatic force to pick up the LEDs 106 and microchips 108 and place them on the device bonding layers 222.
  • gaps between the LEDs 106 and microchips 108 and the sidewalls 221 of the wells in which they are bonded are filled to form sidewall passivation structures 227.
  • the sidewall passivation structures 227 pool around the LEDs 106 and microchips 108 within the wells in openings 417.
  • the sidewall passivation structures 227 attach to sidewalls of the LEDs 106 and microchips 108 and to the sidewalls 221 of the wells in openings 417. Additionally, the sidewall passivation structures 227 fill gaps underneath the LEDs 106 and microchips 108.
  • the sidewall passivation structures 227 are transparent or semi-transparent to the visible wavelength so as to not significantly degrade light extraction efficiency of the LED.
  • Sidewall passivation structures 227 may be formed of a variety of materials such as, but not limited to epoxy, poly(methyl methacrylate) (PMMA), benzocyclobutene (BCB), polyimide, and polyester.
  • the sidewall passivation structures 227 may be formed by a precision deposition technique such as, but not limited to, inkjet printing.
  • the sidewall passivation structures 227 may secure the LEDs 106 and microchips 108 in place to prevent electrical disconnection from the device bonding layers 222. Electrical disconnection from the device bonding layers 222 may render the LEDs and microchips 108 inoperable. Additionally, the sidewall passivation structures 227 may provide a surface for better step coverage for structures (e.g., top contact 229) formed on top of the sidewall passivation structures 227. Furthermore, the sidewall passivation structures 227 may insulate exposed sidewalls of the LEDs 106 in order to prevent short circuiting of active layers.
  • top contacts 229 are formed over the LEDs 106 to electrically couple the LEDs 106 to the metal ground electrodes 233.
  • top contacts 229 may be opaque, reflective, transparent, or semi-transparent to the visible wavelength spectrum.
  • Exemplary transparent conductive materials include amorphous silicon, transparent conductive oxides (TCO) such as indium-tin-oxide ( ⁇ ) and indium- zinc- oxide (IZO), carbon nanotube film, or a transparent conductive polymer such as poly(3,4- ethylenedioxythiophene) (PEDOT), polyaniline, polyacetylene, polypyrrole, and polythiophene.
  • the top conductive contact layer 155 includes nanoparticles such as silver, gold, aluminum, molybdenum, titanium, tungsten, ITO, and IZO.
  • the top contacts 229 are approximately 50 nm to 1 ⁇ thick. Methods of formation include CVD, PVD, spray coating, or spin coating depending upon the desired area to be coated and any thermal constraints.
  • the top contacts 229 are formed by inkjet printing or screen printing. In an embodiment, inkjet printing or screen printing provides a practical approach for patterning the individual top contacts 229 without requiring separate mask layers.
  • a black matrix layer 231 having openings 419 is formed over the exposed front surface 223 of the flexible display substrate 105, surrounding the LEDs 106.
  • exemplary black matrix materials include carbon, metal films (e.g., nickel, aluminum, molybdenum, and alloys thereof), metal oxide films (e.g., chromium oxide), metal nitride films (e.g., chromium nitride), organic resins, glass pastes, and resins or pastes including a black pigment or silver particles.
  • the black matrix layer 231 prevents light from bleeding between LEDs and/or being absorbed by adjacent LEDs. Presence of the black matrix layer 231, therefore, improves the contrast of images displayed on the flexible display panel 103.
  • portions of the black matrix layer 231 in the release openings 111 and trenches 109 are removed to maintain the release openings 111 and trenches 109.
  • the black matrix layer 231 can be formed from a method that is appropriate based upon the material used. For example, black matrix layer 231 can be applied using inkjet printing, sputter and etching, spin coating with lift-off, lamination, or a printing method.
  • the sacrificial layer 201 between the flexible display substrate 105 and carrier substrate 101 is removed by etching with an etchant 419 the sacrificial layer 201 selective to the flexible display substrate 105 and carrier substrate 101.
  • the etchant 419 reaches the sacrificial layer 201 through the release openings 111 and the trenches 109.
  • the sacrificial layer 201 is removed by an etchant that can penetrate through the small dimensions between the flexible display substrate 105 and the carrier substrate 101 such as a vapor or plasma etch process.
  • the sacrificial layer 201 is removed by a vapor etch process utilizing vaporized HF as the etchant.
  • the etchant is selective of the sacrificial layer 201 relative to the flexible display substrate 105 and the carrier substrate 101 such that the sacrificial layer 201 is substantially etched away while the flexible display substrate 105 and the carrier substrate 101 is not substantially etched away.
  • the flexible display substrate 105 and the carrier substrate 101 remain after removing the sacrificial layer 101.
  • the flexible display panel 103 rests upon the carrier substrate 101 by the plurality of posts 202.
  • the plurality of posts 202 are laterally surrounded by voids 423, which were previously occupied by the sacrificial layer 201.
  • the thin Ti layer of the first metal layer 405 for the back component bonding pads 213 formed of Ti-Au-Ti is simultaneously removed by the selective etch process. Accordingly, the gold layer is exposed to make electrical contact with any display component that electrically couples to it.
  • the gold layer is an excellent conductor and is highly resistive to oxidation.
  • a protective topcoat 107 is deposited over the display panel 103, including within the release openings 111.
  • the protective topcoat 107 may be formed by lamination, slit coating, inkjet printing, or any deposition and etch techniques. If deposited by a non-precise deposition technique, the protective topcoat 107 formed within the trenches 109 may be removed to maintain the trenches 109 to separate adjacent flexible display panels 103.
  • the protective topcoat 107 may be any suitable transparent, flexible, and protective material to seal the devices and structures that form the display panel 103. Transparency allows light to pass through the protective topcoat 107 to and from the LEDs 106.
  • the protective topcoat 107 is formed from a variety of materials such as, but not limited to, epoxy, acrylic (polyacrylate) such as benzocyclobutene (BCB), polyimide, and polyester.
  • the protective topcoat 107 is formed of poly(methyl methacrylate) (PMMA). Although thick layers of PMMA are rigid and inflexible, the thickness of the protective topcoat 107 is substantially thin to allow flexibility.
  • the thickness of the protective topcoat ranges from 15 to 20 ⁇ .
  • the protective topcoat 107 partially fills the release opening 111, or completely fills the release opening 111 such that a bottom surface 421 of the protective topcoat 107 reaches the back surface 225 of the flexible display substrate 105.
  • FIG. 4Q illustrates an alternative method of fabricating the flexible display panel 103 according to embodiments of the invention.
  • FIG. 4Q continues from FIG. 4N, where the black matrix layer 231 was formed and where the sacrificial layer 201 is still intact.
  • the protective topcoat 107 may be deposited over the flexible display substrate 103. Portions of the protective topcoat 107 that may be formed directly above or within the release openings 111 and trenches 109 are removed to expose the sacrificial layer 201 such that the sacrificial layer 201 can be accessed by a chemical etchant. Thereafter, in FIG.
  • the sacrificial release layer 201 may be removed by selectively etching the sacrificial release layer 201 with a selective etchant 419. Selectively removing the sacrificial layer 201 may be performed as discussed above with FIG. 40.
  • FIG. 4S the flexible display panel 103 is now ready to be separated from the carrier substrate 101. The flexible display panel 103 rests upon the carrier substrate 101 with the plurality of posts 202, where each post 202 is laterally surrounded by voids 423 that were previously filled with sacrificial layer 201. Release openings 111 remain exposed within the flexible display panel 103.
  • FIG. 5 is a schematic cross-sectional side view illustration of a flexible display panel 103 being separated from a carrier substrate 101 in accordance with an embodiment of the invention.
  • the flexible display panel 103 is separated by lifting a side of the flexible display panel 103 and peeling off the flexible display panel 103 as shown in FIG. 5.
  • the posts 202 may not break or shear when the flexible display panel 103 is separated from the carrier substrate 101, and may remain intact following the separation.
  • the flexible display panel 103 is vacuumed or electrostatically transferred off of the carrier substrate 101.
  • FIG. 6 is a perspective view of a flexible display panel 103 illustrating an arrangement of LEDs and microchips in accordance with an embodiment of the invention.
  • the flexible display substrate 105 in FIG. 6 is transparent to better illustrate the layout of the flexible display panel 103, and is not intended to be limiting.
  • the array of LEDs 106 and the plurality of microchips 108 are on a front surface 223 of the flexible display panel 103.
  • the conductive layers 211 and 218 are formed to electrically couple the array of LEDs 106 and the plurality of microchips 108 to one another.
  • the conductive layers 211 and 218 may be arranged horizontally and vertically as shown in FIG. 6, although embodiments are not limited to such arrangements for
  • the top contact 229 for each LED 106 in the array of LEDs 106 is transparent to allow transmission of light to and from the LEDs 106.
  • FIG. 7 A is a cross-sectional side view illustration of a flexible display panel 103 with back component bond pads 213 on the back surface 225 of the flexible display panel 103 after separation from a carrier substrate 101 in accordance with an embodiment of the invention.
  • the flexible display panel 103 has been separated from the carrier substrate 101 and is ready to be integrated into a flexible display system.
  • the flexible display panel 103 includes a front surface 223 that has an array of LEDs 106 and a plurality of microchips 108.
  • the flexible display panel 103 includes a back surface 225 that includes exposed back component bond pads 213 and a plurality of posts 202.
  • the array of LEDs 106 is electrically coupled to the plurality of microchips 108 such that the plurality of microchips 108 can control the operations of the LEDs 106.
  • the back component bond pads 213 located on the back surface 225 of the flexible display panel 103 are electrically coupled to the plurality of microchips 108 such that the microchips 108 are capable of receiving operating signals from the back component bond pads 213. Accordingly, the back component bond pads 213 are electrically coupled to the plurality of microchips 108 through the conductive layers 211, 217, and 218 in the flexible display substrate 105. As a result, the back surface 225 is electrically coupled with the front surface 223.
  • FIG. 7B is a cross-sectional side view illustration of a flexible display system 800 including a flexible display panel 103 and a plurality of display components 803 mounted on a back surface 225 of the flexible display panel 103 in accordance with an embodiment of the invention.
  • the flexible display panel 103 includes covered release openings 111 so that holes do not extend through the flexible display panel 103.
  • the release openings 111 extend from the front surface 223 to the back surface 225 of the flexible display substrate 105.
  • the release openings 111 are opened to form holes through the flexible display panel 103.
  • a plurality of display components 803 is electrically coupled to the back component bond pads 213.
  • the display components 803 are electrically coupled to the back component bond pads 213 through solder bumps 805 so that signals can be sent from the display components 803 to the microchips 108.
  • the conductive layers 211, 217, and 218 form the necessary interconnection between the display components 803 and the microchips 108 as well as between the microchips 108 and the LEDs 106.
  • the back component bonding surfaces 215 of the back component bond pads 213 are formed from gold following the release etch process discussed in FIG. 40 above.
  • the conductive layers 211, 217, and 218 extend from the front surface 223 to the back surface 225 of the flexible display substrate 105.
  • the display components 803 may be any microchip or microcontroller with circuitry or program instructions used to operate the flexible display panel 103.
  • the display component 803 is a scan driver chip, a sense controller chip, a data driver chip, a processor chip, or a power supply.
  • the power supply is a battery.
  • FIG. 8 A is a cross-sectional side view illustration of a flexible display panel 103 with front component bond pads 301 on the front surface 223 of the flexible display panel 103 after separation from a carrier substrate 101 in accordance with an embodiment of the invention.
  • the flexible display panel 103 has been separated from the carrier substrate 101 and is ready to be integrated into a flexible display system.
  • the flexible display substrate 103 includes a front surface 223 that has an array of LEDs 106, a plurality of microchips 108, and a plurality of front component bond pads 301 on the front surface 223.
  • the array of LEDs 106 is electrically coupled to the plurality of microchips 108 such that the plurality of microchips 108 can control the operations of the LEDs 106.
  • the front component bond pads 301 are electrically coupled to the plurality of microchips 108 through at least one of the conductive layers 211, 217, and 218 in the flexible display substrate 105.
  • FIG. 8B is a cross-sectional side view illustration of a flexible display system 800 including a flexible display panel 103 and a plurality of display components 803 mounted on a front surface 223 of the flexible display panel 103 in accordance with an embodiment of the invention.
  • the flexible display panel 103 includes covered release openings 111 so that holes do not extend through the flexible display panel 103.
  • the release openings 111 extend from the font surface 223 to the back surface 225 of the flexible display substrate 105.
  • the release openings 111 are opened to form holes through the flexible display panel 103.
  • a plurality of display components 803 is electrically coupled to the front component bond pads 301.
  • the display components 803 are electrically coupled to the microchips 108 through solder bumps 805 so that signals can be sent from the display components 803 to the microchips 108.
  • the conductive layers 211, 217, and 218 form the necessary interconnection between the display components 803 and the microchips 108 as well as between the microchips 108 and the LEDs 106.
  • the conductive layers 211, 217, and 218 extend at least partially through the flexible display substrate 105. As shown in FIG. 8B, the conductive layers 211, 217, and 218 extend more than half way through the flexible display substrate 105.
  • the conductive layers 211, 217, and 218 do not necessarily extend completely through the flexible display substrate 105 because there are no back component bond pads 513, although embodiments that do extend completely through the flexible display substrate 105 are envisioned in embodiments of the present invention.
  • the display components 803 may be any microchip or microcontroller with circuitry or program instructions used to operate the flexible display panel 103.
  • the display component 803 is a scan driver chip, a sense controller chip, a data driver chip, a processor chip, or a power supply.
  • the power supply is a battery.
  • FIG. 9A is a schematic top view illustration of a back surface 225 of a flexible display system 800 including a flexible display panel 103 and a plurality of display components 803 mounted on a back surface 225 of the flexible display panel 103 in accordance with an embodiment of the invention.
  • the side view illustration of the display system 800 shown in FIG. 9A is illustrated in FIG. 7B discussed above.
  • the array of LEDs 106 and plurality of microchips 108 are illustrated with dotted gray lines to indicate that these devices are located on the front surface 223 of the display panel 103.
  • the area of the flexible display panel 103 where the LEDs 106 and the microchips 108 are located forms a display area 901.
  • the display area 901 is delineated by the dotted gray line formed around the perimeter of the LEDs 106 and microchips 108.
  • the display area 901 is the area where the flexible display system 800 emits and senses light.
  • the plurality of display components 803 may be bonded to the back surface 225 of the flexible display panel 103 in any suitable orientation. As shown in FIG. 9A, the display components 803 are oriented in horizontal and vertical orientations. Furthermore, the display components 803 are electrically coupled with the back component bond pads 213 (not shown, as they are covered by the display components 803).
  • FIG. 9A depicts the display components 803 mounted on the back surface 225 of the flexible display panel 103 on the opposite side of the display area 901, the display components may be mounted on the back surface 225 of the flexible display panel 103 outside of the display area 901.
  • FIG. 9B is a schematic top view illustration of a front side 223 of a flexible display system 800 including a flexible display panel 103 and a plurality of display components 803 mounted on a front surface 223 of the flexible display panel 103 outside of a display area 901 in accordance with an embodiment of the invention.
  • the schematic side view illustration of the display system 800 shown in FIG. 9B is illustrated in FIG. 8B discussed above.
  • a marked difference between mounting the display components 803 on a front surface 223 of the flexible display panel 103 is the increase in surface area footprint of the flexible display system 800.
  • the display components 803 cannot be placed on the front surface 223 of the flexible display panel 103 because doing so would block the LEDs 106 from emitting light.
  • the display components 803 may be arranged in any orientation, not just in the horizontal and vertical orientations as illustrated in FIG. 9B.

Abstract

A flexible display panel (103) and method of formation with a sacrificial release layer are described. The method of manufacturing a flexible display system includes forming a sacrificial layer on a carrier substrate (101). A flexible display substrate (105) is formed on the sacrificial layer, with a plurality of release openings (111) that extend through the flexible display substrate (105) to the sacrificial layer. An array of LEDs (106) and a plurality of microchips (108) are transferred onto the flexible display substrate (105) to form a flexible display panel (103). The sacrificial layer is selectively removed such that the flexible display panel (103) attaches to the carrier substrate (101) by a plurality of support posts. The flexible display panel (103) is removed from the carrier substrate (101) and is electrically coupled with display components to form a flexible display system.

Description

FLEXIBLE DISPLAY AND METHOD OF FORMATION WITH SACRIFICIAL
RELEASE LAYER
BACKGROUND
FIELD
[0001] The present invention relates to display systems. More particularly embodiments of the present invention relate to flexible display systems having semiconductor microchips and LEDs on a flexible display substrate.
BACKGROUND INFORMATION
[0002] Display panels are critical components in modern mobile electronic devices, such as smartphones, tablets, and laptop/notebook computers. Through recent development, flexible display panels are becoming a viable replacement for conventional rigid display panels. Flexible display panels are display panels that are not formed with a rigid substrate so that they can be curved and bent. Currently, organic light emitting diode (OLED) technology is widely adopted for forming flexible display panels. Typical OLED display panels are constructed from a glass substrate, on top of which are a circuit containing thin-film transistors and a capacitor, then the light emitting OLED devices and, finally, a transparent, protective layer on top. The thin-film transistor circuit is formed within the OLED display substrate and is subjected to constricting forces during curving and bending of the display. Furthermore, OLEDs need to be hermetically sealed because they are hypersensitive to oxygen and water.
SUMMARY OF THE INVENTION
[0003] A method and apparatus for flexible light emitting diode (LED) display panels are described. In one embodiment, the method includes forming a sacrificial layer on a carrier substrate. The method also includes forming a flexible display substrate on the sacrificial layer where the flexible display substrate includes a plurality of release openings that extend through the flexible display substrate to the sacrificial layer. Furthermore, the method includes transferring an array of LEDs and a plurality of microchips onto the flexible display substrate. In an embodiment, the flexible display substrate is formed by spinning on a photo-definable material. Additionally, in an embodiment, forming the flexible display substrate includes forming at least one photo-definable polymer layer and at least one metal layer. Forming the at least one metal layer may be performed by sputtering. [0004] In an embodiment, the method further includes etching a plurality of openings in the sacrificial layer and forming the flexible display substrate on the sacrificial layer and within the openings to form a plurality of posts extending through the sacrificial layer. Additionally, in an embodiment, the method further includes selectively removing the sacrificial layer and separating the flexible display substrate from the carrier substrate. Selectively removing the sacrificial layer may be performed by a process selected from the group consisting of a vapor etching process and a plasma etching process. Additionally, in an embodiment, the method further includes forming a transparent contact for each LED in the array of LEDs, forming a black matrix layer on the flexible display substrate where the black matrix layer surrounds the array of LEDs, and covering the array of LEDs and the plurality of microchips with a protective material. Covering the array of LEDs may be performed by a process selected from the group consisting of a slit-coating process and a laminating process.
[0005] In an embodiment, a flexible display panel includes a flexible substrate including a front surface, a back surface, and a display area on the front surface. The flexible display panel also includes a plurality of interconnects that extend at least partially through the flexible substrate from the front surface to the back surface where the flexible substrate and the plurality of interconnects form a build-up structure. Further, the flexible display panel includes an array of light emitting diodes (LEDs) and a plurality of microchips on the front surface of the flexible display substrate in the display area and electrically coupled to the plurality of interconnects. A plurality of release openings may extend through the flexible substrate from the front surface to the back surface.
[0006] Each microchip of the plurality of microchips may include a driving circuit to drive one or more LEDs to emit light. In an embodiment, the plurality of microchips are electrically coupled to the array of LEDs. Additionally, in an embodiment, the flexible display panel further includes at least one display component electrically coupled to the array of microchips on the front surface of the flexible substrate through the plurality of interconnects, where the display component comprises a chip selected from the group consisting of a sense controller chip, a scan driver chip, a data driver chip, a processor chip, and a power supply. The display component may be on the back surface of the flexible substrate. Further, the display component may be on the front surface of the flexible substrate outside of the display area. In an embodiment, the build-up structure includes at least one layer of polymer and at least one layer of metal.
[0007] In an embodiment, a structure includes a carrier substrate, a flexible substrate on the carrier substrate where the flexible substrate includes a plurality of electrical interconnects that extend at least partially between a front surface and a back surface of the flexible substrate, and an array of LEDs and a plurality of microchips on the front surface of the flexible display substrate. The structure also includes a sacrificial release layer between the back surface of the flexible substrate and the carrier substrate within a display area on the front surface, and a plurality of release openings that extend through the flexible substrate from the front surface to the back surface and expose the sacrificial release layer. Additionally, in an embodiment, the back surface of the flexible substrate includes a plurality of support posts. Each support post of the plurality of support posts may be laterally surrounded by the sacrificial release layer. Further, the sacrificial layer may include a material selected from the group consisting of an oxide and a nitride.
BRIEF DESCRIPTION OF THE DRAWINGS
[0008] FIG. 1A is a cross-sectional side view illustration of an array of flexible display panels with covered release openings mounted on a carrier substrate in accordance with an embodiment of the invention.
[0009] FIG. IB is a cross-sectional side view illustration of an array of flexible display panels with exposed release openings mounted on a carrier substrate in accordance with an embodiment of the invention.
[0010] FIG. 1C is a schematic top view illustration of an array of flexible display panels with exposed release openings mounted on a carrier substrate in accordance with an embodiment of the invention.
[0011] FIG. 2 is a cross-sectional side view illustration of a flexible display substrate with LEDs and microchips on a front surface of the flexible display substrate and component bond pads on a back surface of the flexible display substrate in accordance with an embodiment of the invention.
[0012] FIG. 3 is a cross-sectional side view illustration of a flexible display substrate with LEDs and microchips on a front surface of the flexible display substrate and component bond pads on the front surface of the flexible display substrate in accordance with an embodiment of the invention.
[0013] FIGS. 4A-4P illustrate a method of fabricating a flexible display panel including a flexible display substrate with arrays of LEDs and microchips on a front surface of the flexible display substrate and a plurality of covered release openings in accordance with an embodiment of the invention.
[0014] FIGS. 4Q-4S illustrate a method of fabricating a flexible display panel including a flexible display substrate with arrays of LEDs and microchips on a front surface of the flexible display substrate and a plurality of exposed release openings in accordance with an embodiment of the invention.
[0015] FIG. 5 is a cross-sectional side view illustration of a flexible display panel being separated from a carrier substrate in accordance with an embodiment of the invention.
[0016] FIG. 6 is a perspective view of a flexible display panel illustrating an arrangement of
LEDs and microchips in accordance with an embodiment of the invention.
[0017] FIG. 7A is a cross-sectional side view illustration of a flexible display panel with back component bond pads after separation from a carrier substrate in accordance with an embodiment of the invention.
[0018] FIG. 7B is a cross-sectional side view illustration of a flexible display system including a flexible display panel and a plurality of display components mounted on a back surface of the flexible display panel in accordance with an embodiment of the invention.
[0019] FIG. 8A is a cross-sectional side view illustration of a flexible display panel with front component bond pads after separation from a carrier substrate in accordance with an embodiment of the invention.
[0020] FIG. 8B is a cross-sectional side view illustration of a flexible display system including a flexible display panel and a plurality of display components mounted on a front surface of the flexible display panel in accordance with an embodiment of the invention.
[0021] FIG. 9A is a schematic top view illustration of a back surface of a flexible display system including a flexible display panel and a plurality of display components mounted on a back surface of the flexible display panel in accordance with an embodiment of the invention.
[0022] FIG. 9B is a schematic top view illustration of a front surface of a flexible display system including a flexible display panel and a plurality of display components mounted on a front surface of the flexible display panel outside of a display area in accordance with an embodiment of the invention.
DETAILED DESCRIPTION OF THE INVENTION
[0023] Embodiments of the present invention describe flexible display systems and methods of manufacture thereof. In an embodiment, a method of manufacturing a flexible display system includes forming a sacrificial layer on a carrier substrate. A flexible display substrate is formed on the sacrificial layer, with a plurality of release openings that extend through the flexible display substrate to the sacrificial layer. In an embodiment, the flexible display substrate is formed using a photo-definable polymer. An array of light emitting diodes (LEDs) and a plurality of microchips are transferred onto the flexible display substrate to form a flexible display panel. The sacrificial layer is selectively removed such that the flexible display panel attaches to the carrier substrate by a plurality of support posts. The flexible display panel is removed from the carrier substrate and is electrically coupled with display components to form a flexible display system.
[0024] In various embodiments, description is made with reference to figures. However, certain embodiments may be practiced without one or more of these specific details, or in combination with other known methods and configurations. In the following description, numerous specific details are set forth, such as specific configurations, dimensions and processes, etc., in order to provide a thorough understanding of the present invention. In other instances, well-known processes and manufacturing techniques have not been described in particular detail in order to not unnecessarily obscure the present invention. Reference throughout this specification to "one embodiment" means that a particular feature, structure, configuration, or characteristic described in connection with the embodiment is included in at least one embodiment of the invention. Thus, the appearances of the phrase "in one embodiment" in various places throughout this specification are not necessarily referring to the same embodiment of the invention.
Furthermore, the particular features, structures, configurations, or characteristics may be combined in any suitable manner in one or more embodiments.
[0025] The terms "spanning", "over", "to", "between" and "on" as used herein may refer to a relative position of one layer with respect to other layers. One layer "spanning", "over" or "on" another layer or bonded "to" or in "contact" with another layer may be directly in contact with the other layer or may have one or more intervening layers. One layer "between" layers may be directly in contact with the layers or may have one or more intervening layers.
[0026] Embodiments of the invention enable the fabrication of flexible display panels whose operation does not require them to be held in a rigid structure. In an embodiment, the flexible display panel described herein includes a flexible display substrate having an array of LEDs and a plurality of microchips on a front surface of the flexible display substrate within a display area. In an embodiment, the flexible display substrate is a build-up structure that has more than one layer of insulating material and more than one layer of conductive material. At least one layer of conductive material within the flexible substrate electrically couples the array of LEDs to the plurality of microchips. In an embodiment, bond pads are exposed on a back surface of the flexible display substrate to which display components electrically connect. Alternatively, in an embodiment, bond pads are exposed on the front surface of the flexible display substrate outside of a display area. The bond pads are electrically coupled to the plurality of microchips on the front surface of the flexible display substrate. The conductive material within the flexible substrate electrically couples the bond pads to the plurality of microchips.
[0027] In an embodiment, the flexible display panel is fabricated by forming a layer of sacrificial material on a carrier substrate. A plurality of openings is formed in the sacrificial layer, within which a portion of the flexible display substrate is formed. The portion of the flexible display substrate in the plurality of openings forms a plurality of posts that extends through the sacrificial layer. In an embodiment, the flexible display substrate is constructed by forming at least one layer of insulating material and one layer of conductive material. An array of LEDs and a plurality of microchips are then transferred onto a front surface of the flexible display substrate. In an embodiment, the array of LEDs and the plurality of microchips are transferred onto the flexible display substrate by mass transfer tools operating using electrostatic principles to pick up and transfer large arrays of LEDs and microchips. Electrostatic transfer enables driving circuitry to be located on the front surface of the flexible display substrate, rather than embedded within the flexible display substrate. The array of LEDs and the plurality of microchips are covered with a transparent material to protect it from physical, environmental, and/or electrical disturbance while allowing for the visualization of light emitted from the array of LEDs. In an embodiment, the flexible substrate containing the array of LEDs and the plurality of microchips is separated from the carrier substrate by selectively removing the sacrificial layer and pulling the display substrate away from the carrier substrate, resulting in a flexible display panel that can be integrated with additional display components to form a display system.
[0028] In an embodiment, a flexible display system includes a flexible display panel having an array of LEDs and a plurality of microchips on a front surface of the flexible display substrate. A plurality of display components is electrically coupled to the plurality of microchips through the flexible display substrate. In an embodiment, the plurality of display components is located on the back surface of the flexible display substrate directly behind the display area. The plurality of display components can include, but are not limited to, scan drivers, data drivers, sense controllers, write controllers, microcontrollers, and power supplies. Alternatively, in an embodiment, the plurality of display components is located on the front surface of the flexible display substrate outside of a display area. In an embodiment, the flexible display substrate is formed with one or more layers of insulating material and one or more layers of conductive material. The layered structure of the flexible display substrate allows the flexible display panel to bend in various directions and to various degrees while maintaining electrical connectivity between the display components, microchips, and LEDs. As such, the flexible display system is enabled to display images or sense light while being bent in various directions. [0029] In accordance with some embodiments, the interactive display panel described herein is a micro LED active matrix display panel formed with semiconductor-based micro LEDs. Such a micro LED active matrix display panel utilizes the performance, efficiency, and reliability of semiconductor-based LEDs for emitting light. Furthermore, a micro LED active matrix display panel enables a display panel to achieve high resolutions, pixel densities, and subpixel densities due to the small size of the micro LEDs and microchips. In some embodiments, the high resolutions, pixel densities, and subpixel densities are achieved due to the small size of the micro LEDs and microchips.
[0030] For example, the term "micro" as used herein, particularly with regard to LEDs and microchips, refers to the descriptive size of certain devices or structures in accordance with embodiments. The term "micro" is meant to refer to the scale of 1 to 300 μιη or, more specifically, 1 to 100 μιη. In some embodiments, "micro" may even refer to the scale of 1 to 50 μιη, 1 to 20 μιη, or 1 to 10 μιη. However, it is to be appreciated that embodiments of the present invention are not necessarily so limited, and that certain aspects of the embodiments may be applicable to larger, and possibly smaller size scales. For example, a 55 inch interactive television panel with 1920 x 1080 resolution, and 40 pixels per inch (PPI) has an approximate RBG pixel pitch of (634 μιη x 634 μιη) and subpixel pitch of (211 μιη x 634 μιη). In this manner, each subpixel contains one or more micro LEDs having a maximum width of no more than 211 μιη. Furthermore, where real estate is reserved for microchips in addition to micro LEDs, the size of the micro LEDs may be further reduced. For example, a 5 inch interactive display panel with 1920 x 1080 resolution, and 440 pixels per inch (PPI) has an approximate RBG pixel pitch of (58 μιη x 58 μιη) and subpixel pitch of (19 μιη x 58 μιη). In such an embodiment, not only does each subpixel contain one or more micro LEDs having a maximum width of no more than 19 μιη, in order to not disturb the pixel arrangement, each microchip may additionally be reduced below the pixel pitch of 58 μιη. Accordingly, some embodiments combine with efficiencies of semiconductor-based LEDs for emitting light with the scalability of semiconductor-based LEDs, and optionally microchips, to the micro scale for implementation into high resolution and pixel density applications.
[0031] FIG. 1A is a cross-sectional side view illustration of a plurality of flexible display panels 103 with covered release openings 111 mounted on a carrier substrate 101 in accordance with an embodiment of the invention. The illustrated embodiment depicts the plurality of flexible display panels 103 after removal of the sacrificial layer and before separation from the carrier substrate 101. As shown in FIG. 1A, the flexible display panels 103 have multiple sections 102 that will be described in more detail when discussing the method of forming the flexible display panel 103 below. The plurality of flexible display panels 103 is on the carrier substrate 101. In an embodiment, the carrier substrate 101 is any suitable substrate, such as glass, upon which the flexible display panel 103 can be formed. In embodiments, the carrier substrate 101 is rigid enough to withstand process forces associated with the transfer of the array of LEDs and the plurality of microchips to the flexible display panel 103 with an electrostatic transfer head. In an embodiment, the carrier substrate 101 is formed of a material that can be reused for making new batches of flexible display panels 103. Each flexible display panel 103 is separated from adjacent flexible display panels by a trench 109. The trench 109 physically separates each flexible display panel 103 so that each flexible display panel 103 can be removed individually without interfering or damaging an adjacent flexible display panel. In an embodiment, the flexible display panel 103 includes a flexible substrate 105 formed from at least one layer of insulating material and at least one layer of conductive material. In an embodiment, the insulating material is a polymer. Alternatively, in an embodiment, the insulating material is a photo-definable polymer, such as an acrylic or an SU-8 photoresist (i.e., an epoxy photoresist). In a particular embodiment, the flexible substrate 105 is formed of at least one layer of photo- definable polyimide and at least one layer of metal. Although any insulating material may be used in embodiments, polyimide and metal may be a viable combination because of its ease of use and cost effectiveness. An array of LEDs 106 and a plurality of microchips 108 are located on the flexible display substrate 105. A transparent protective layer 107 is formed over the array of LEDs, plurality of microchips, and exposed top surfaces of the flexible display substrate 105. In an embodiment, the transparent protective layer 107 is polymethyl methacrylate (PMMA) or acrylic glass. Furthermore, a plurality of release openings 111 extends through the flexible display substrate 105. The release openings 111 and trenches 109 provide channels within which an etchant may flow to remove the sacrificial layer as will be discussed further below. In this embodiment, the release openings 111 are covered by the transparent protective layer 107 so that holes do not extend through the flexible display panel 103.
[0032] FIG. IB is a cross-sectional side view illustration of an array of flexible display panels 103 with exposed release openings 111 mounted on a carrier substrate 101 in accordance with an embodiment of the invention. The illustrated embodiment depicts the plurality of flexible display panels 103 after removal of the sacrificial layer and before separation from the carrier substrate 101. The plurality of flexible display panels 103 is on the carrier substrate 101. Each flexible display panel 103 is separated from adjacent flexible display panels by a trench 109. The trench 109 physically separates each flexible display panel 103 so that each flexible display panel 103 can be removed individually without interfering or damaging an adjacent flexible display panel. An array of LEDs 106 and a plurality of microchips 108 are located on the flexible display substrate 105. A transparent protective layer 107, such as PMMA, is formed over the array of LEDs, plurality of microchips, and exposed top surfaces of the flexible display substrate 105. Furthermore, a plurality of release openings 111 extends through the flexible display substrate 105. The release openings 111 provide a channel within which an etchant may flow to remove the sacrificial layer as will be discussed further below. In this embodiment, the transparent protective layer 107 does not cover the release openings 111. Rather, an opening is formed through the transparent protective layer 107 and the release openings 111. Accordingly, the plurality of exposed release openings 111 creates a perforated flexible display panel 103.
[0033] FIG. 1C is a schematic top view illustration of an array of flexible display panels 103 with release openings 111 mounted on a carrier substrate 101 in accordance with an embodiment of the invention. Each flexible display panel 103 is separated from another flexible display panel by vertical and horizontal trenches 109. Interspersed within the array of LEDs 106 is the plurality of microchips 108. The plurality of microchips 108 controls the emission and/or sensing of the array of LEDs. The transparent protective layer 107 covers the array of LEDs 106 and the plurality of microchips 108 to protect them from damage or electrical interference.
Furthermore, the array of LEDs 106 are covered with a transparent protective layer 107 to allow light to be emitted or sensed from the array of LEDs 106. The plurality of release openings 111 is located within the inner area of the flexible display panels 103. In an embodiment, the release openings 111 are covered release openings. Alternatively, in an embodiment, the release openings 111 are uncovered release openings. Release openings 111 allow etchants to remove the sacrificial layer located directly below the flexible display panel 103. In an embodiment, the release openings 111 are equidistant from one another to so that etchants have the same amount of distance to travel between each release opening 111. Alternatively, the release openings 111 may be designed to have a higher concentration or larger size in areas that are more difficult for etchants to reach, e.g., at locations farther away from trenches 109. In an embodiment, release openings 111 enable the complete removal of sacrificial material below the flexible display substrates 103.
[0034] FIG. 2 is a cross-sectional side view illustration of a flexible display substrate 105 with LEDs 106 and microchips 108 on a front surface of the flexible display substrate 105 and back component bond pads 213 on a back surface 225 of the flexible display substrate 105 in accordance with an embodiment of the invention. The illustration in FIG. 2 depicts a section 102 of the flexible display panel 103 and does not show a cross-section of the whole flexible display 103. In an embodiment, the flexible display substrate 105 is formed on a carrier substrate 101, which may be formed of glass.
[0035] In an embodiment, the flexible display substrate 105 is formed from at least one layer of insulating material and at least one layer of conductive material. In an embodiment, the insulating material is a polymer. Alternatively, in an embodiment, the insulating material is a photo-definable polymer, such as an acrylic or an SU-8 photoresist. In a particular embodiment, the insulating material is a photo-definable polyimide and the conductive material is a metal. As depicted in FIG. 2, the flexible display substrate 105 is formed from more than one insulating layers 203, 205, 207, and 209 and more than one conductive layer 211, 217, and 218. Although the embodiment depicted in FIG. 2 illustrates four layers of insulating materials and three layers of conductive materials, embodiments of the present invention are not limited to such
arrangements. The insulating layers 203, 205, 207, and 209 are layered with the conductive layers 211, 217, and 218 to form a build-up structure in one embodiment. The build-up structure is a series of insulating layers with interconnect structures and conductive lines formed within. The interconnect structures electrically couple conductive lines to one another to form larger interconnect systems that span multiple layers. In an embodiment, the insulating layers 203, 205, 207, and 209 are in the range of 2 to 2.5 μιη thick to provide structural strength and sufficient electrical isolation between conductive layers when the flexible display panel is bent. The conductive layers 211, 217, and 218 are structured so that the back surface 225 of the flexible display substrate 105 is electrically coupled to the front surface 223 of the flexible display substrate 105.
[0036] In an embodiment, the front surface 223 of the flexible display substrate 105 includes a plurality of wells with side surfaces 221 in which the LEDs 106 and microchips 108 are transferred. Although FIG. 2 depicts the LEDs 106 and the microchips 108 in wells,
embodiments are not limited to such arrangements. For example, the front surface 223 of the flexible display substrate 105 may not have a plurality of wells, but rather have a flat surface upon which the LEDs and microchips are transferred. In an embodiment, the microchips 108 are electrically coupled to the LEDs through at least one of the conductive layers 211, 217, and 218 within the flexible display substrate 105. In an embodiment, the microchips 108 are electrically coupled to the back surface 225 of the flexible display substrate 105 through the conductive layers 211, 217, and 218. The back surface 225 of the flexible display substrate 105 includes back component bond pads 213 having back component bonding surfaces 215 for electrical coupling to display components as will be discussed further below. A transparent top contact 229 is located on the LEDs 106 to form an electrical connection between the LEDs 106 and a ground electrode (Vss) 233. The transparency of the top contact 229 allows light emitting to or from the LEDs 106 to easily pass through the top contact 229. The transparent contact 229 may be formed from any suitable transparent and conductive material, such as indium tin oxide (ΓΓΟ) in one embodiment. As such, during operation, positive voltage may be applied by the microchip 108 to forward bias the LEDs 106, whose cathode electrode is grounded by the transparent top contact 229 and the metal ground electrode 223. It is to be appreciated that forward biasing the LEDs is but only one exemplary operation, to which other embodiments are not limited. For instance, the LEDs 106 may be reverse biased to sense light.
[0037] To ensure stability and protection of the electric connection to the LEDs 106, a sidewall passivation material 227 is located between the sidewalls 221 of the wells and the LEDs 106. The sidewall passivation material 227 stabilizes the LEDs 106 and prevents particles from falling underneath the LEDs 106. Additionally, the sidewall passivation material 227 passivates sidewalls of the LEDs to prevent shorting of an active layer as well as provides step coverage for structures (e.g., metal contacts, transparent acrylics, transparent oxides, and/or transparent polymers, such as those that may form top contact 229) formed upon it. In an embodiment, a black matrix layer 231 is formed over the front surface 225 of the flexible display substrate 105. The black matrix layer 231 may absorb all wavelengths of visible light to prevent light from bleeding between adjacent LEDs. Accordingly, the black matrix layer 231 may mitigate any self- generated light disturbance within the flexible display panel 103 while the flexible display panel 103 is displaying an image.
[0038] In an embodiment, a sacrificial layer 201 is formed in between the carrier substrate 101 and the flexible display substrate 105. The sacrificial layer 201 may be formed from any suitable material that can be etched selective to the flexible display substrate 105 and the carrier substrate 101. In an embodiment, the sacrificial layer 201 is formed from silicon dioxide. The sacrificial layer 201 acts as a support layer for the fabrication of the flexible display panel 103 as well as an adhesive to secure the flexible display substrate 105 during fabrication. The sacrificial layer 201 may be selectively removed to allow separation of the flexible display panel 103 from the carrier substrate 101. In an embodiment, a plurality of posts 202 extends through the sacrificial layer
201 to support the flexible display panel 103 after removal of the sacrificial layer 201. The posts
202 are a portion of the flexible display substrate 105 extending from the back surface 225 of the flexible display substrate 105. The bottom surface 204 of the posts 202 adhere to the carrier substrate 101 until the flexible display panel 103 is separated. In an embodiment, the structure of the posts 202 affects adhesion strength between the flexible display panel 103 and the carrier substrate 101 as well as the amount of force required to separate the flexible display panel 103 from the carrier substrate 101. Wider posts 202 increase the adhesion strength and the required separation force due to an increase in surface area that makes contact with the carrier substrate 101. In addition to the size of the posts 202, the number of posts 202 affects adhesion strength and separation force as well. An increase in the number of posts 202 increases the surface area adhered to the carrier substrate 101. As such, an increase in posts 202 increases the adhesion strength and the required force to separate the flexible display panel 103 from the carrier substrate 101.
[0039] Trenches 109 are at the ends of the flexible display panel 103. In an embodiment, the sacrificial layer 201 extends from underneath the flexible display substrate 105 and forms a layer across the bottom of the trench 109. Alternatively, in an embodiment, the sacrificial layer 201 does not extend from underneath the flexible display substrate 105. The trenches 109 expose the sacrificial layer 201 such that etchants may reach the sacrificial layer 201. Furthermore, in an embodiment, release openings 111 are formed through the flexible display substrate 105 to expose the sacrificial layer 201. The release openings 111 form a passageway for etchants to reach the sacrificial layer 201.
[0040] FIG. 3 is a cross-sectional side view illustration of a flexible display substrate 105 with LEDs 106 and microchips 108 on a front surface 223 of the flexible display substrate 105 and front component bond pads 301 on the front surface 223 of the flexible display substrate 105 in accordance with an embodiment of the invention. In an embodiment, the front component bond pads 301 are electrically coupled to the microchip 108 for sending electrical signals to the microchips 108. A top surface 303 of the front component bond pad 301 is exposed to allow a display component to make electrical connection to the microchip 108 through at least one of the conductive layers 211, 217, and 218. Having the front component bond pads 301 on the front surface 223 of the flexible display substrate 105 allow display components to be placed on the front surface 223 of the flexible display panel 103 outside of a display area.
[0041] Trenches 109 are at the ends of the flexible display panel 103. The trenches 109 expose the sacrificial layer 201 such that etchants may reach the sacrificial layer 201. Furthermore, in an embodiment, release openings 111 are formed through the flexible display substrate 105 to expose the sacrificial layer 201. The release openings 111 form a passageway for etchants to reach the sacrificial layer 201.
[0042] FIGS. 4A-4S illustrate a method of fabricating a flexible display panel 103 including a flexible display substrate 105 with LEDs 106 and microchips 108 on a front surface 223 of the flexible display substrate in accordance with embodiments of the invention. FIGS. 4A-4P illustrate a method of fabricating a flexible display panel 103 with LEDs 106 and microchips 108 on a front surface 223 of the flexible display substrate 105 with covered release openings 111. FIGS. 4Q-4S illustrate a method of fabricating a flexible display panel 103 with LEDs 106 and microchips 108 on a front surface 223 of the flexible display substrate 105 with exposed release openings 111 as continued from FIG. 4N.
[0043] With reference to FIG. 4A, a sacrificial layer 201 is formed on a carrier substrate 101. In an embodiment, the carrier substrate 101 is glass. The sacrificial layer 201 may be formed from any material that can be etched selective to the insulating material used to form the flexible display substrate 105 and the carrier substrate 101. In an embodiment, the sacrificial layer is formed from silicon dioxide. Furthermore, in an embodiment, the thickness of the sacrificial layer 201 ranges from 0.5 to 1.5 μιη. The sacrificial layer may be formed by a deposition process such as, but not limited to, chemical vapor deposition (CVD) or physical vapor deposition (PVD).
[0044] As shown in FIG. 4B, openings 401 are etched into the sacrificial layer 201. The openings 401 may be spaced evenly apart from one another or arranged in a specific pattern. In an embodiment, openings 401 are patterned so that there is an equal distribution of openings dispersed around the area within which the flexible display panel 103 is to be formed. The placement of openings 401 determines the locations of posts 202 as shown in FIG. 4C.
[0045] In FIG. 4C, a first layer 203 of the flexible display substrate 105 is formed on the sacrificial layer 201 and within the trench 109. In an embodiment, the first layer 203 is formed from an insulating material. The insulating material may be a polymer or a photo-definable insulating material, such as a photo-definable polymer. In an embodiment, the photo-definable polymer may be an acrylic or an SU-8 photoresist. In a particular embodiment, the first layer 203 is formed from a photo-definable polyimide, so that exposure to electromagnetic radiation chemically modifies the molecular structure of the polyimide to allow solubility in a developer solution. The photo-definable insulating material enables patterning without forming a separate mask layer, such as a photoresist. Therefore, having the photo-definable insulating material may reduce patterning operations and cost. During its formation, the first layer 203 fills in the openings 401 to form a plurality of posts 202. The posts 202 are essentially an extension of the first layer 203 of insulating material such that the posts 202 and the first layer 203 form one integrated structure. The first layer 203 of the flexible display substrate 105 may be formed by spinning on or spray coating a layer of insulating material. When the insulating material is spun on, it fills in the openings 401 and subsequently forms the plurality of posts 202.
[0046] As shown in FIG. 4D, via openings 403, release openings 111, and trenches 109 are etched into the first layer 203 of the flexible display substrate 105. In an embodiment, the trenches 109, via openings 403, and release openings 111 extend through the first layer 203 and expose the sacrificial layer 201 underneath. In an embodiment, the via openings 403 are openings used for forming an interconnect via to electrically couple structures above and below the first layer 203. In an embodiment, the release openings 111 and trenches 109 are openings used to provide a passageway for etchant chemicals to remove the sacrificial layer 201. The via openings 403, release openings 111, and trenches 109 may be formed by conventional patterning and developing techniques. In an embodiment, patterned electromagnetic radiation, such as visible or ultraviolet light, is exposed onto the first layer 203. Parts of the first layer 203 that are exposed to the electromagnetic radiation become cross-linked. As such, when the first layer 203 is submerged in a developer solution, unexposed regions are removed to form the patterned openings 403, 111, and 109. Alternatively, if the first layer 203 is not formed from photo- definable material, then another suitable patterning technique may be used to form the openings 403, 111, 109 in the first layer 203.
[0047] As shown in FIG. 4E, a first conductive layer 405 is formed over the first layer 203 and within the via openings 403, release openings 111, and trenches 109. The first conductive layer 405 may be formed from a conductive material, such as a metal or a metal alloy, or any combination of multiple layers of conductive materials. In an embodiment, the first conductive layer 405 is a titanium-gold-titanium (Ti-Au-Ti) layer stack where a layer of gold is sandwiched between two thin layers of titanium. One reason why the first conductive layer 405 may be formed with Ti-Au-Ti is because although gold is an excellent conductor and is highly resistant to oxidation, it does not adhere well with insulating materials, such as the first layer 203. As such, adding the outer layers of titanium, which adheres well with insulating material, allows the gold layer to be securely attached to the first layer 203. It is to be appreciated that the thickness of gold may be much greater than the thickness of titanium. In an embodiment, the gold to titanium layer thickness ratio ranges from 5: 1 to 10:1. Formation of the first metal layer 405 may be performed by a conformal deposition technique. In one embodiment, the first conductive layer 405, having multiple layers of conductive materials, is formed by sputtering.
[0048] As shown in FIG. 4F, openings 407 are etched in the first conductive layer 405 to form back component bond pads 213 having back component bonding surfaces 215 and a first conductive layer 211. The back component bond pads 213 conform to the surfaces of the opening 403 and first layer 203 upon which they are formed. In an embodiment, first conductive layer 211 is a part of an electrical connection between two semiconductor devices within the flexible display substrate 105. The conductive layer formed within the release openings 111 and trenches 109 is removed to expose the sacrificial layer 201 in order for an etchant to reach the sacrificial layer 201 by access through the release openings 111 and trench 109. The openings 407 in the first conductive layer 405 may be etched by a mask and etch process, such as an anisotropic dry or plasma etch process.
[0049] FIG. 4G illustrates the flexible display substrate 105 subsequent to iterative formation of second and third insulating layers 205 and 207, respectively, and second and third conductive layers 217 and 218, respectively, with process techniques and conductive materials discussed in FIGS. 4C-4F according to an embodiment of the invention. The third conductive layer 218 includes various device bond pads, such as a ground pad 411, LED pads 413, and microchip pads 415. The second conductive layer 217 is an interconnect layer designed to form various interconnections between back component bond pads 213 and the ground pad 411, LED pads 413, and microchip pads 415. The conductive layers 217 and 218 may be a single conductive layer or multiple conductive layers formed from any conductive material, such as but not limited to, amorphous silicon, conductive oxides, conductive polymers, metals, and metal alloys. For example, in an embodiment, the conductive layers 217 and 218 are formed from aluminum, titanium, or an aluminum and titanium alloy. Additionally, the conductive layers 217 and 218 may be formed from more than one metal layer, such as a titanium- tungsten alloy and gold layer (TiW-Au) or a titanium and aluminum (Ti-Al) layer. In an embodiment, the back component bond pads 213 are electrically coupled to the microchip pads 415 of the flexible display substrate 105 through the second and third conductive layers 217 and 218, respectively. Although the embodiment depicted in FIG. 4G illustrates three insulating layers and three conductive layers, embodiments are not so limited. Various openings 409 in the top conductive layer 218 have been etched to form the ground, LED, and microchip pads 411, 413, and 415, respectively.
Throughout the processes up to this point, release openings 111 and trenches 109 have continuously been etched to expose the sacrificial layer 201 such that etchants may access the sacrificial layer 201 through the release openings 111 and trenches 109.
[0050] In FIG. 4H, a fourth layer 209 is formed on a portion of the exposed pads 411, 413, and 415 and on exposed top surfaces of the third layer 207 using any of a variety of techniques such as inkjet printing, screen printing, lamination, spin coating, spray coating, CVD, and PVD. The fourth layer 209 may be formed of a variety of insulating materials such as, but not limited to, photo-definable acrylic, photoresist, silicon dioxide, silicon nitride, poly(methyl methacrylate) (PMMA), benzocyclobutene (BCB), polyimide, SU-8 photoresist, acrylate, epoxy, and polyester. In an embodiment, the fourth layer 209 is formed of an opaque material such as a black matrix material. Exemplary insulating black matrix materials include organic resins, glass pastes, and resins or pastes including a black pigment, metallic particles such as nickel, aluminum, molybdenum, and alloys thereof, metal oxide particles (e.g., chromium oxide), or metal nitride particles (e.g., chromium nitride). In an embodiment, the fourth layer 209 is formed from the same material as the first through third layers 203, 205, and 207, respectively, such as a photo- definable insulating material, or any other protective, flexible material.
[0051] In an embodiment, the fourth layer 209 has openings 417 that expose the ground pad 411, LED pads 413, and microchip pads 415 to which electrical devices may be electrically coupled. As shown in FIG. 4H, the openings 417 in the fourth layer 209 have oblique sidewalls 221 that slope downward to form a well or a bank structure. In an embodiment, the well may be used for optical separation of adjacent LEDs to prevent optical interference. Additionally, in an embodiment, a surface of the well may be used to form mirrors to aid in light extraction.
Furthermore, in an embodiment, the well may provide a structure for pooling sidewall passivation material 227 to passivate sidewalls of the LEDs to prevent shorting of an active layer, and may provide a structure for providing better step coverage for structures (e.g., top contact 229) formed upon it.
[0052] As shown in FIG. 41, conductive ground electrodes 233 are formed on the fourth layer 209 and on the ground pad 411. Conductive ground electrodes 233 provide electrical
connections to ground (Vss) for any device to which it is coupled. In an embodiment, the ground electrodes 233 are electrically coupled with at least the second conductive layer 217 through the ground pad 411 to form a connection to ground. The conductive ground electrodes 233 may be formed by a deposition and etch technique. In an embodiment, the conductive ground electrodes 233 are formed by sputtering followed by an anisotropic etch process.
[0053] In FIG. 4J, device bonding layers 222 are formed on the exposed LED pads 413 and microchip pads 415 to facilitate bonding of electrical devices. In an embodiment, the device bonding layers 222 are selected for its ability to be interdiffused with a bonding layer on the electrical devices (that are to be placed on the pads) through bonding mechanisms such as eutectic alloy bonding, transient liquid phase bonding, or solid state diffusion bonding. In an embodiment, the device bonding layers 222 have a melting temperature of 250°C or lower. For example, the device bonding layers 222 may include a solder material such as tin (232°C) or indium (156.7°C), or alloys thereof. Device bonding layers 222 may also be in the shape of a post. In accordance with some embodiments of the invention, taller device bonding layers 222 may provide an additional degree of freedom for system component leveling, such as planarity of the electrical devices with the pad during device transfer operations and for variations in height of the devices, due to the change in height of the liquefied bonding layers as they spread out over the pad during bonding. The width of the device bonding layers 222 may be less than a width of a bottom surface of the electrical devices to prevent wicking of the device bonding layers 222 around the sidewalls of the electrical devices which can cause electrical shorting. The device bonding layers 222 may be formed by a photoresist lift-off technique or electroplating.
[0054] As shown in FIG. 4K, LEDs 106 and microchips 108 are transferred onto the device interconnect layers 222 such that the LEDs 106 and microchips 108 are electrically coupled to the LED pads 413 and microchip pads 415, respectively. In an embodiment, the LEDs 106 are micro LEDs having a device size of 1-20 μιη. The LEDs 106 may be any color-emitting LED, such as a red-, green-, blue-, infrared-, cyan-, white-, yellow-, or any other color-emitting LED. The microchips 108 may contain circuitry to receive signals from display components extraneous to the flexible display substrate 105 as well as circuitry to operate the LEDs 106 according to the received signals. In an embodiment, the microchips 108 contain driving circuitry to drive the LED in forward bias mode for emitting light. Optionally, the microchips 108 may also contain a selection device, such as a multiplexer, to disconnect the LED from the driving circuit and connect to a sensing circuit to operate the LED in reverse bias mode for sensing light. Although FIG. 4K illustrates only two LEDs and one microchip 108, embodiments of the present invention are not limited to such configurations. Rather, any number of LEDs 106 and any number of microchips 108 may transferred onto the flexible display substrate 105. More specifically, the number and size of the LEDs and microchips 108 may scale according to the resolution or size of the flexible display panel 103. Higher numbers and smaller sizes of LEDs and microchips 108 may be formed in flexible display panels that require higher resolutions and/or smaller flexible display panels 103. The LEDs 106 and microchips 108 are electrostatically transferred onto the device bonding layers 222 by a pickup-and-placement method. In one embodiment, an electrostatic transfer head uses electrostatic force to pick up the LEDs 106 and microchips 108 and place them on the device bonding layers 222.
[0055] Thereafter, in FIG. 4L, gaps between the LEDs 106 and microchips 108 and the sidewalls 221 of the wells in which they are bonded are filled to form sidewall passivation structures 227. In embodiments, the sidewall passivation structures 227 pool around the LEDs 106 and microchips 108 within the wells in openings 417. The sidewall passivation structures 227 attach to sidewalls of the LEDs 106 and microchips 108 and to the sidewalls 221 of the wells in openings 417. Additionally, the sidewall passivation structures 227 fill gaps underneath the LEDs 106 and microchips 108. In accordance with embodiments of the invention, the sidewall passivation structures 227 are transparent or semi-transparent to the visible wavelength so as to not significantly degrade light extraction efficiency of the LED. Sidewall passivation structures 227 may be formed of a variety of materials such as, but not limited to epoxy, poly(methyl methacrylate) (PMMA), benzocyclobutene (BCB), polyimide, and polyester. The sidewall passivation structures 227 may be formed by a precision deposition technique such as, but not limited to, inkjet printing.
[0056] The sidewall passivation structures 227 may secure the LEDs 106 and microchips 108 in place to prevent electrical disconnection from the device bonding layers 222. Electrical disconnection from the device bonding layers 222 may render the LEDs and microchips 108 inoperable. Additionally, the sidewall passivation structures 227 may provide a surface for better step coverage for structures (e.g., top contact 229) formed on top of the sidewall passivation structures 227. Furthermore, the sidewall passivation structures 227 may insulate exposed sidewalls of the LEDs 106 in order to prevent short circuiting of active layers.
[0057] As shown in FIG. 4M, top contacts 229 are formed over the LEDs 106 to electrically couple the LEDs 106 to the metal ground electrodes 233. Depending upon the particular application, top contacts 229 may be opaque, reflective, transparent, or semi-transparent to the visible wavelength spectrum. Exemplary transparent conductive materials include amorphous silicon, transparent conductive oxides (TCO) such as indium-tin-oxide (ΓΓΟ) and indium- zinc- oxide (IZO), carbon nanotube film, or a transparent conductive polymer such as poly(3,4- ethylenedioxythiophene) (PEDOT), polyaniline, polyacetylene, polypyrrole, and polythiophene. In an embodiment, the top conductive contact layer 155 includes nanoparticles such as silver, gold, aluminum, molybdenum, titanium, tungsten, ITO, and IZO. In an embodiment, the top contacts 229 are approximately 50 nm to 1 μιη thick. Methods of formation include CVD, PVD, spray coating, or spin coating depending upon the desired area to be coated and any thermal constraints. In some embodiments, the top contacts 229 are formed by inkjet printing or screen printing. In an embodiment, inkjet printing or screen printing provides a practical approach for patterning the individual top contacts 229 without requiring separate mask layers.
[0058] In FIG. 4N, a black matrix layer 231 having openings 419 is formed over the exposed front surface 223 of the flexible display substrate 105, surrounding the LEDs 106. Exemplary black matrix materials include carbon, metal films (e.g., nickel, aluminum, molybdenum, and alloys thereof), metal oxide films (e.g., chromium oxide), metal nitride films (e.g., chromium nitride), organic resins, glass pastes, and resins or pastes including a black pigment or silver particles. The black matrix layer 231 prevents light from bleeding between LEDs and/or being absorbed by adjacent LEDs. Presence of the black matrix layer 231, therefore, improves the contrast of images displayed on the flexible display panel 103. In an embodiment, portions of the black matrix layer 231 in the release openings 111 and trenches 109 are removed to maintain the release openings 111 and trenches 109. The black matrix layer 231 can be formed from a method that is appropriate based upon the material used. For example, black matrix layer 231 can be applied using inkjet printing, sputter and etching, spin coating with lift-off, lamination, or a printing method.
[0059] As shown in FIG. 40, the sacrificial layer 201 between the flexible display substrate 105 and carrier substrate 101 is removed by etching with an etchant 419 the sacrificial layer 201 selective to the flexible display substrate 105 and carrier substrate 101. The etchant 419 reaches the sacrificial layer 201 through the release openings 111 and the trenches 109. The sacrificial layer 201 is removed by an etchant that can penetrate through the small dimensions between the flexible display substrate 105 and the carrier substrate 101 such as a vapor or plasma etch process. In an embodiment, the sacrificial layer 201 is removed by a vapor etch process utilizing vaporized HF as the etchant. The etchant is selective of the sacrificial layer 201 relative to the flexible display substrate 105 and the carrier substrate 101 such that the sacrificial layer 201 is substantially etched away while the flexible display substrate 105 and the carrier substrate 101 is not substantially etched away. In an embodiment, the flexible display substrate 105 and the carrier substrate 101 remain after removing the sacrificial layer 101. After removing the sacrificial layer 201, the flexible display panel 103 rests upon the carrier substrate 101 by the plurality of posts 202. The plurality of posts 202 are laterally surrounded by voids 423, which were previously occupied by the sacrificial layer 201. In an embodiment, the thin Ti layer of the first metal layer 405 for the back component bonding pads 213 formed of Ti-Au-Ti is simultaneously removed by the selective etch process. Accordingly, the gold layer is exposed to make electrical contact with any display component that electrically couples to it. The gold layer is an excellent conductor and is highly resistive to oxidation.
[0060] As shown in FIG. 4P, a protective topcoat 107 is deposited over the display panel 103, including within the release openings 111. The protective topcoat 107 may be formed by lamination, slit coating, inkjet printing, or any deposition and etch techniques. If deposited by a non-precise deposition technique, the protective topcoat 107 formed within the trenches 109 may be removed to maintain the trenches 109 to separate adjacent flexible display panels 103. The protective topcoat 107 may be any suitable transparent, flexible, and protective material to seal the devices and structures that form the display panel 103. Transparency allows light to pass through the protective topcoat 107 to and from the LEDs 106. Furthermore, flexibility allows the flexible display panel 103 to bend and flex in a variety of positions without fracturing the protective topcoat 107. Additionally, the protective property of the protective topcoat 107 seals the devices and structures of the flexible display panel 103 from the environment and protects it from physical intrusion and/or electrical interference. In an embodiment, the protective topcoat 107 is formed from a variety of materials such as, but not limited to, epoxy, acrylic (polyacrylate) such as benzocyclobutene (BCB), polyimide, and polyester. In a specific embodiment, the protective topcoat 107 is formed of poly(methyl methacrylate) (PMMA). Although thick layers of PMMA are rigid and inflexible, the thickness of the protective topcoat 107 is substantially thin to allow flexibility. In an embodiment, the thickness of the protective topcoat ranges from 15 to 20 μιη. In an embodiment, the protective topcoat 107 partially fills the release opening 111, or completely fills the release opening 111 such that a bottom surface 421 of the protective topcoat 107 reaches the back surface 225 of the flexible display substrate 105. Once the protective topcoat 107 is formed, the flexible display panel 103 is now ready to be separated from the carrier substrate 101.
[0061] FIG. 4Q illustrates an alternative method of fabricating the flexible display panel 103 according to embodiments of the invention. FIG. 4Q continues from FIG. 4N, where the black matrix layer 231 was formed and where the sacrificial layer 201 is still intact. Following formation of the black matrix layer 231, in FIG. 4Q, the protective topcoat 107 may be deposited over the flexible display substrate 103. Portions of the protective topcoat 107 that may be formed directly above or within the release openings 111 and trenches 109 are removed to expose the sacrificial layer 201 such that the sacrificial layer 201 can be accessed by a chemical etchant. Thereafter, in FIG. 4R, the sacrificial release layer 201 may be removed by selectively etching the sacrificial release layer 201 with a selective etchant 419. Selectively removing the sacrificial layer 201 may be performed as discussed above with FIG. 40. As shown in FIG. 4S, the flexible display panel 103 is now ready to be separated from the carrier substrate 101. The flexible display panel 103 rests upon the carrier substrate 101 with the plurality of posts 202, where each post 202 is laterally surrounded by voids 423 that were previously filled with sacrificial layer 201. Release openings 111 remain exposed within the flexible display panel 103.
[0062] FIG. 5 is a schematic cross-sectional side view illustration of a flexible display panel 103 being separated from a carrier substrate 101 in accordance with an embodiment of the invention. In one embodiment, the flexible display panel 103 is separated by lifting a side of the flexible display panel 103 and peeling off the flexible display panel 103 as shown in FIG. 5. The posts 202 may not break or shear when the flexible display panel 103 is separated from the carrier substrate 101, and may remain intact following the separation. Alternatively, in an embodiment, the flexible display panel 103 is vacuumed or electrostatically transferred off of the carrier substrate 101. Harsh, chemical etchants are not needed to remove the flexible display panel 103 because the adhesion force between the plurality of posts 202 and the carrier substrate 101 is low enough to allow physical, dry separation. However, using wet chemical solutions to separate the flexible display panel 103 from the carrier substrate 101 is a viable method of separation that is envisioned in embodiments of the invention.
[0063] FIG. 6 is a perspective view of a flexible display panel 103 illustrating an arrangement of LEDs and microchips in accordance with an embodiment of the invention. The flexible display substrate 105 in FIG. 6 is transparent to better illustrate the layout of the flexible display panel 103, and is not intended to be limiting. The array of LEDs 106 and the plurality of microchips 108 are on a front surface 223 of the flexible display panel 103. The conductive layers 211 and 218 are formed to electrically couple the array of LEDs 106 and the plurality of microchips 108 to one another. The conductive layers 211 and 218 may be arranged horizontally and vertically as shown in FIG. 6, although embodiments are not limited to such arrangements for
interconnecting the plurality of microchips 108 with the array of LEDs 106. Additionally, the top contact 229 for each LED 106 in the array of LEDs 106 is transparent to allow transmission of light to and from the LEDs 106.
[0064] FIG. 7 A is a cross-sectional side view illustration of a flexible display panel 103 with back component bond pads 213 on the back surface 225 of the flexible display panel 103 after separation from a carrier substrate 101 in accordance with an embodiment of the invention. The flexible display panel 103 has been separated from the carrier substrate 101 and is ready to be integrated into a flexible display system. The flexible display panel 103 includes a front surface 223 that has an array of LEDs 106 and a plurality of microchips 108. Furthermore, the flexible display panel 103 includes a back surface 225 that includes exposed back component bond pads 213 and a plurality of posts 202. The array of LEDs 106 is electrically coupled to the plurality of microchips 108 such that the plurality of microchips 108 can control the operations of the LEDs 106. In an embodiment, the back component bond pads 213 located on the back surface 225 of the flexible display panel 103 are electrically coupled to the plurality of microchips 108 such that the microchips 108 are capable of receiving operating signals from the back component bond pads 213. Accordingly, the back component bond pads 213 are electrically coupled to the plurality of microchips 108 through the conductive layers 211, 217, and 218 in the flexible display substrate 105. As a result, the back surface 225 is electrically coupled with the front surface 223.
[0065] FIG. 7B is a cross-sectional side view illustration of a flexible display system 800 including a flexible display panel 103 and a plurality of display components 803 mounted on a back surface 225 of the flexible display panel 103 in accordance with an embodiment of the invention. The flexible display panel 103 includes covered release openings 111 so that holes do not extend through the flexible display panel 103. The release openings 111 extend from the front surface 223 to the back surface 225 of the flexible display substrate 105. In an alternative embodiment, the release openings 111 are opened to form holes through the flexible display panel 103. A plurality of display components 803 is electrically coupled to the back component bond pads 213. In an embodiment, the display components 803 are electrically coupled to the back component bond pads 213 through solder bumps 805 so that signals can be sent from the display components 803 to the microchips 108. The conductive layers 211, 217, and 218 form the necessary interconnection between the display components 803 and the microchips 108 as well as between the microchips 108 and the LEDs 106. In an embodiment, the back component bonding surfaces 215 of the back component bond pads 213 are formed from gold following the release etch process discussed in FIG. 40 above. In an embodiment, the conductive layers 211, 217, and 218 extend from the front surface 223 to the back surface 225 of the flexible display substrate 105. The display components 803 may be any microchip or microcontroller with circuitry or program instructions used to operate the flexible display panel 103. For example, in an embodiment, the display component 803 is a scan driver chip, a sense controller chip, a data driver chip, a processor chip, or a power supply. In an embodiment, the power supply is a battery.
[0066] FIG. 8 A is a cross-sectional side view illustration of a flexible display panel 103 with front component bond pads 301 on the front surface 223 of the flexible display panel 103 after separation from a carrier substrate 101 in accordance with an embodiment of the invention. The flexible display panel 103 has been separated from the carrier substrate 101 and is ready to be integrated into a flexible display system. The flexible display substrate 103 includes a front surface 223 that has an array of LEDs 106, a plurality of microchips 108, and a plurality of front component bond pads 301 on the front surface 223. The array of LEDs 106 is electrically coupled to the plurality of microchips 108 such that the plurality of microchips 108 can control the operations of the LEDs 106. The front component bond pads 301 are electrically coupled to the plurality of microchips 108 through at least one of the conductive layers 211, 217, and 218 in the flexible display substrate 105.
[0067] FIG. 8B is a cross-sectional side view illustration of a flexible display system 800 including a flexible display panel 103 and a plurality of display components 803 mounted on a front surface 223 of the flexible display panel 103 in accordance with an embodiment of the invention. The flexible display panel 103 includes covered release openings 111 so that holes do not extend through the flexible display panel 103. The release openings 111 extend from the font surface 223 to the back surface 225 of the flexible display substrate 105. In an alternative embodiment, the release openings 111 are opened to form holes through the flexible display panel 103. A plurality of display components 803 is electrically coupled to the front component bond pads 301. Accordingly, in an embodiment, the display components 803 are electrically coupled to the microchips 108 through solder bumps 805 so that signals can be sent from the display components 803 to the microchips 108. The conductive layers 211, 217, and 218 form the necessary interconnection between the display components 803 and the microchips 108 as well as between the microchips 108 and the LEDs 106. The conductive layers 211, 217, and 218 extend at least partially through the flexible display substrate 105. As shown in FIG. 8B, the conductive layers 211, 217, and 218 extend more than half way through the flexible display substrate 105. The conductive layers 211, 217, and 218 do not necessarily extend completely through the flexible display substrate 105 because there are no back component bond pads 513, although embodiments that do extend completely through the flexible display substrate 105 are envisioned in embodiments of the present invention. The display components 803 may be any microchip or microcontroller with circuitry or program instructions used to operate the flexible display panel 103. For example, in an embodiment, the display component 803 is a scan driver chip, a sense controller chip, a data driver chip, a processor chip, or a power supply. In an embodiment, the power supply is a battery.
[0068] FIG. 9A is a schematic top view illustration of a back surface 225 of a flexible display system 800 including a flexible display panel 103 and a plurality of display components 803 mounted on a back surface 225 of the flexible display panel 103 in accordance with an embodiment of the invention. The side view illustration of the display system 800 shown in FIG. 9A is illustrated in FIG. 7B discussed above. As shown in FIG. 9A, the array of LEDs 106 and plurality of microchips 108 are illustrated with dotted gray lines to indicate that these devices are located on the front surface 223 of the display panel 103. The area of the flexible display panel 103 where the LEDs 106 and the microchips 108 are located forms a display area 901. The display area 901 is delineated by the dotted gray line formed around the perimeter of the LEDs 106 and microchips 108. The display area 901 is the area where the flexible display system 800 emits and senses light. The plurality of display components 803 may be bonded to the back surface 225 of the flexible display panel 103 in any suitable orientation. As shown in FIG. 9A, the display components 803 are oriented in horizontal and vertical orientations. Furthermore, the display components 803 are electrically coupled with the back component bond pads 213 (not shown, as they are covered by the display components 803). It is to be appreciated that placing the display components 803 on the backside of the display panel 103 allows the construction of a display panel system 800 to have a smaller surface area footprint than the surface area footprint of a display panel system 800 with display components 803 mounted on the font surface 223 of the flexible display panel 103 shown in FIG. 9B. Although FIG. 9A depicts the display components 803 mounted on the back surface 225 of the flexible display panel 103 on the opposite side of the display area 901, the display components may be mounted on the back surface 225 of the flexible display panel 103 outside of the display area 901.
[0069] FIG. 9B is a schematic top view illustration of a front side 223 of a flexible display system 800 including a flexible display panel 103 and a plurality of display components 803 mounted on a front surface 223 of the flexible display panel 103 outside of a display area 901 in accordance with an embodiment of the invention. The schematic side view illustration of the display system 800 shown in FIG. 9B is illustrated in FIG. 8B discussed above. A marked difference between mounting the display components 803 on a front surface 223 of the flexible display panel 103 is the increase in surface area footprint of the flexible display system 800. The display components 803 cannot be placed on the front surface 223 of the flexible display panel 103 because doing so would block the LEDs 106 from emitting light. However, placing the display components on the front surface 223 of the flexible display substrate 103 outside of the display area 901 may allow the flexible display system 800 to have a thinner profile. It is to be appreciated that the display components 803 may be arranged in any orientation, not just in the horizontal and vertical orientations as illustrated in FIG. 9B.
[0070] In utilizing the various aspects of this invention, it would become apparent to one skilled in the art that combinations or variations of the above embodiments are possible for emitting light with a flexible display panel. Although the present invention has been described in language specific to structural features and/or methodological acts, it is to be understood that the invention defined in the appended claims is not necessarily limited to the specific features or acts described. The specific features and acts disclosed are instead to be understood as particularly graceful implementations of the claimed invention useful for illustrating the present invention.

Claims

CLAIMS What is claimed is:
1. A method, comprising:
forming a sacrificial layer on a carrier substrate;
forming a flexible display substrate on the sacrificial layer, the flexible display substrate comprising a plurality of release openings that extend through the flexible display substrate to the sacrificial layer; and
transferring an array of light-emitting diodes (LEDs) and a plurality of microchips onto the flexible display substrate.
2. The method of claim 1, wherein forming the flexible display substrate comprises spinning on a photo-definable material.
3. The method of claim 1, wherein forming the flexible display substrate comprises forming at least one photo-definable polymer and at least one metal layer.
4. The method of claim 2, wherein forming the at least one metal layer comprises sputtering.
5. The method of claim 1, further comprising:
etching a plurality of openings in the sacrificial layer; and
forming the flexible display substrate on the sacrificial layer and within the openings to form a plurality of posts extending through the sacrificial layer.
6. The method of claim 1, further comprising:
selectively removing the sacrificial layer; and
separating the flexible display substrate from the carrier substrate.
7. The method of claim 6, wherein selectively removing the sacrificial layer is performed by a process selected from the group consisting of a vapor etching process and a plasma etching process.
8. The method of claim 1, further comprising:
forming a transparent contact for each LED in the array of LEDs; forming a black matrix layer on the flexible display substrate, the black matrix layer surrounding the array of LEDs; and
covering the array of LEDs and the plurality of microchips with a protective material.
9. The method of claim 8, wherein covering the array of LEDs is performed by a process selected from the group consisting of a slit-coating process and a laminating process.
10. A flexible display panel, comprising:
a flexible substrate comprising a front surface, a back surface, and a display area on the front surface;
a plurality of interconnects that extend at least partially through the flexible substrate from the front surface to the back surface, wherein the flexible substrate and the plurality of interconnects form a build-up structure;
an array of light emitting diodes (LEDs) and a plurality of microchips on the front surface of the flexible substrate in the display area and electrically coupled to the plurality of
interconnects; and
a plurality of release openings extending through the flexible substrate from the front surface to the back surface.
11. The flexible display panel of claim 10, wherein each microchip comprises a driving circuit to drive one or more LEDs to emit light.
12. The flexible display panel of claim 10, wherein the plurality of microchips are electrically coupled to the array of LEDs.
13. The flexible display panel of claim 10, further comprising:
at least one display component electrically coupled to the array of microchips on the front surface of the flexible substrate through the plurality of interconnects, wherein the display component comprises a chip selected from the group consisting of a sense controller chip, a scan driver chip, a data driver chip, a processor chip, and a power supply.
14. The flexible display panel of claim 13, wherein the display component is on the back surface of the flexible substrate.
15. The flexible display panel of claim 13, wherein the display component is on the front surface of the flexible substrate outside of the display area.
16. The flexible display panel of claim 10, wherein the build-up structure comprises at least one layer of polymer and at least one layer of metal.
17. A structure, comprising:
a carrier substrate;
a flexible substrate on the carrier substrate, the flexible substrate comprising a plurality of electrical interconnects that extend at least partially between a front surface and a back surface of the flexible substrate;
an array of LEDs and a plurality of microchips on the front surface of the flexible substrate;
a sacrificial release layer between the back surface of the flexible substrate and the carrier substrate within a display area on the front surface; and
a plurality of release openings that extend through the flexible substrate from the front surface to the back surface and expose the sacrificial release layer.
18. The structure of claim 17, wherein the back surface of the flexible substrate comprises a plurality of support posts.
19. The structure of claim 18, wherein each support post of the plurality of support posts is laterally surrounded by the sacrificial release layer.
20. The structure of claim 17, wherein the sacrificial layer comprises a material selected from the group consisting of an oxide and a nitride.
PCT/US2015/025873 2014-05-15 2015-04-15 Flexible display and method of formation with sacrificial release layer WO2015175131A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US14/278,778 2014-05-15
US14/278,778 US9318475B2 (en) 2014-05-15 2014-05-15 Flexible display and method of formation with sacrificial release layer

Publications (1)

Publication Number Publication Date
WO2015175131A1 true WO2015175131A1 (en) 2015-11-19

Family

ID=53177868

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2015/025873 WO2015175131A1 (en) 2014-05-15 2015-04-15 Flexible display and method of formation with sacrificial release layer

Country Status (3)

Country Link
US (1) US9318475B2 (en)
TW (1) TWI570908B (en)
WO (1) WO2015175131A1 (en)

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2017142817A1 (en) * 2016-02-18 2017-08-24 Sxaymiq Technologies Llc Backplane structure and process for microdriver and micro led
EP3316302A1 (en) * 2016-10-28 2018-05-02 LG Display Co., Ltd. Light emitting diode display device
KR20180046494A (en) * 2016-10-28 2018-05-09 엘지디스플레이 주식회사 Light emitting diode display apparatus
WO2019150093A1 (en) * 2018-01-30 2019-08-08 Pragmatic Printing Ltd. Integrated circuit on flexible substrat manufacturing process
EP3503186A4 (en) * 2016-08-19 2020-03-11 Boe Technology Group Co. Ltd. Array substrate and preparation method thereof, and display device
CN113421839A (en) * 2015-12-23 2021-09-21 歌尔股份有限公司 Micro light emitting diode transfer method and manufacturing method
JP2023063266A (en) * 2021-10-22 2023-05-09 隆達電子股▲ふん▼有限公司 Micro light emitting diode package structure
US11960167B2 (en) 2020-02-17 2024-04-16 BOE MLED Technology Co., Ltd. Backplane and method for manufacturing the same, and display device

Families Citing this family (56)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102107456B1 (en) * 2013-12-10 2020-05-08 삼성디스플레이 주식회사 Flexible display device and method for manufacturing the same
US10319878B2 (en) 2014-10-31 2019-06-11 eLux, Inc. Stratified quantum dot phosphor structure
US10381332B2 (en) 2014-10-31 2019-08-13 eLux Inc. Fabrication method for emissive display with light management system
US10446728B2 (en) 2014-10-31 2019-10-15 eLux, Inc. Pick-and remove system and method for emissive display repair
US10520769B2 (en) 2014-10-31 2019-12-31 eLux, Inc. Emissive display with printed light modification structures
US9825202B2 (en) 2014-10-31 2017-11-21 eLux, Inc. Display with surface mount emissive elements
US10535640B2 (en) 2014-10-31 2020-01-14 eLux Inc. System and method for the fluidic assembly of micro-LEDs utilizing negative pressure
US10418527B2 (en) 2014-10-31 2019-09-17 eLux, Inc. System and method for the fluidic assembly of emissive displays
US10236279B2 (en) 2014-10-31 2019-03-19 eLux, Inc. Emissive display with light management system
US10381335B2 (en) 2014-10-31 2019-08-13 ehux, Inc. Hybrid display using inorganic micro light emitting diodes (uLEDs) and organic LEDs (OLEDs)
US10543486B2 (en) 2014-10-31 2020-01-28 eLux Inc. Microperturbation assembly system and method
US10242977B2 (en) 2014-10-31 2019-03-26 eLux, Inc. Fluid-suspended microcomponent harvest, distribution, and reclamation
US9633883B2 (en) 2015-03-20 2017-04-25 Rohinni, LLC Apparatus for transfer of semiconductor devices
KR102469186B1 (en) * 2015-04-30 2022-11-21 삼성디스플레이 주식회사 Flexible organic light emitting diode display and method for manufacturing flexible organic light emitting diode display
CN104992944B (en) * 2015-05-26 2018-09-11 京东方科技集团股份有限公司 A kind of production method of Flexible Displays motherboard and flexible display panels
KR102354973B1 (en) 2015-06-10 2022-01-25 삼성디스플레이 주식회사 Flexible display apparatus and manufacturing method thereof
TWI665800B (en) * 2015-06-16 2019-07-11 友達光電股份有限公司 Light emitting diode display and manufacturing method thereof
US10373856B2 (en) 2015-08-03 2019-08-06 Mikro Mesa Technology Co., Ltd. Transfer head array
US9969078B2 (en) * 2015-08-03 2018-05-15 Mikro Mesa Technology Co., Ltd. Transfer head array and transferring method
EP3234992B1 (en) * 2016-01-29 2018-09-26 JENOPTIK Optical Systems GmbH Method and appartus for detaching a micro-chip from a wafer and placement of the micro-chip on a substrate
TWI618266B (en) * 2016-09-07 2018-03-11 友達光電股份有限公司 Interposer structure of mirco-light emitting diode unit and fabricating method thereof, mirco-light emitting diode unit and fabricating method thereof and mirco-light emitting diode apparatus
KR102634305B1 (en) * 2016-10-11 2024-02-08 주식회사 루멘스 LED pixel unit
US10141215B2 (en) 2016-11-03 2018-11-27 Rohinni, LLC Compliant needle for direct transfer of semiconductor devices
US10504767B2 (en) 2016-11-23 2019-12-10 Rohinni, LLC Direct transfer apparatus for a pattern array of semiconductor device die
US10471545B2 (en) 2016-11-23 2019-11-12 Rohinni, LLC Top-side laser for direct transfer of semiconductor devices
CN106653812B (en) * 2016-12-20 2019-10-11 武汉华星光电技术有限公司 The production method of flexible display panels
US10062588B2 (en) 2017-01-18 2018-08-28 Rohinni, LLC Flexible support substrate for transfer of semiconductor devices
US20180240931A1 (en) * 2017-02-23 2018-08-23 Novatek Microelectronics Corp. Micro-device panel and manufacturing process thereof
CN106952583B (en) * 2017-05-23 2019-04-30 深圳市华星光电技术有限公司 The production method of flexible array substrate
KR102236769B1 (en) * 2017-07-18 2021-04-06 삼성전자주식회사 Led module manufacturing device and method of manufacturing led module
DE102017123290A1 (en) 2017-10-06 2019-04-11 Osram Opto Semiconductors Gmbh Light-emitting component, display device and method for producing a display device
CN107871752B (en) * 2017-10-17 2019-11-15 深圳市华星光电技术有限公司 Miniature LED display panel and miniature light-emitting diode display
TWI648883B (en) * 2018-02-14 2019-01-21 友達光電股份有限公司 Micro illuminator
WO2019178507A1 (en) * 2018-03-16 2019-09-19 The Regents Of The University Of California Flexible spinal cord stimulators for pain and trauma management through neuromodulation
US10410905B1 (en) 2018-05-12 2019-09-10 Rohinni, LLC Method and apparatus for direct transfer of multiple semiconductor devices
TWI797140B (en) * 2018-06-25 2023-04-01 晶元光電股份有限公司 Light emitting device with extendable and flexible carrier
CN110797372A (en) * 2018-08-01 2020-02-14 创王光电股份有限公司 Flexible display
US11094571B2 (en) 2018-09-28 2021-08-17 Rohinni, LLC Apparatus to increase transferspeed of semiconductor devices with micro-adjustment
KR102657129B1 (en) * 2018-10-11 2024-04-16 삼성디스플레이 주식회사 Light emitting device, fabricating method thereof, and display device including the same
DE102018129209B4 (en) 2018-11-20 2022-04-14 OSRAM Opto Semiconductors Gesellschaft mit beschränkter Haftung MULTI-PIXEL DISPLAY DEVICE
KR20200070493A (en) * 2018-12-07 2020-06-18 삼성디스플레이 주식회사 Display device and manufacturing method thereof
US11282729B2 (en) * 2018-12-27 2022-03-22 Areesys Technologies, Inc. Method and apparatus for poling polymer thin films
US11910715B2 (en) 2018-12-27 2024-02-20 Creesense Microsystems Inc. Method and apparatus for poling polymer thin films
US11552163B2 (en) * 2019-02-22 2023-01-10 Vuereal Inc. Staggered and tile stacked microdevice integration and driving
US11246251B2 (en) 2019-05-02 2022-02-08 Seagate Technology Llc Micro-component transfer systems, methods, and devices
US10923378B2 (en) 2019-05-13 2021-02-16 Seagate Technology Llc Micro-component batch transfer systems, methods, and devices
US11665929B2 (en) * 2019-06-13 2023-05-30 Intel Corporation Micro light-emitting diode displays with improved power efficiency
US10706800B1 (en) 2019-07-02 2020-07-07 A.U. Vista, Inc. Bendable flexible active matrix display panel
TWI779242B (en) * 2019-10-28 2022-10-01 錼創顯示科技股份有限公司 Micro light-emitting diode device
CN113126792A (en) * 2019-12-31 2021-07-16 瀚宇彩晶股份有限公司 Method for manufacturing flexible panel
CN115413372A (en) * 2020-04-21 2022-11-29 上海显耀显示科技有限公司 Light emitting diode chip structure with reflecting element
DE21792668T1 (en) 2020-04-21 2023-06-22 Jade Bird Display (shanghai) Limited Light-emitting diode chip structure with reflective elements
TW202228111A (en) 2020-06-03 2022-07-16 中國大陸商上海顯耀顯示科技有限公司 Systems and methods for multi-color led pixel unit with horizontal light emission
EP3958245A1 (en) * 2020-08-21 2022-02-23 ams International AG A display, a display device and method to operate a display
KR20220038229A (en) * 2020-09-18 2022-03-28 삼성디스플레이 주식회사 Display device and manufacturing method thereof
US20230395484A1 (en) * 2022-06-01 2023-12-07 Innolux Corporation Electronic device and manufacturing method thereof

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2003060986A2 (en) * 2002-01-11 2003-07-24 The Pennsylvania State University Method of forming a removable support with a sacrificial layers and of transferring devices
WO2014030830A1 (en) * 2012-08-21 2014-02-27 Lg Electronics Inc. Display device using semiconductor light emitting device and method of fabricating the same
CN103681733A (en) * 2012-08-30 2014-03-26 财团法人工业技术研究院 Flexible display and manufacturing method thereof
US20140104793A1 (en) * 2012-10-17 2014-04-17 Electronics And Telecommunication Research Institute Stretchable electronic device and method of manufacturing same

Family Cites Families (134)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3717743A (en) 1970-12-07 1973-02-20 Argus Eng Co Method and apparatus for heat-bonding in a local area using combined heating techniques
US3935986A (en) 1975-03-03 1976-02-03 Texas Instruments Incorporated Solid state bonding process employing the isothermal solidification of a liquid interface
US5131582A (en) 1989-06-30 1992-07-21 Trustees Of Boston University Adhesive metallic alloys and methods of their use
US5300788A (en) 1991-01-18 1994-04-05 Kopin Corporation Light emitting diode bars and arrays and method of making same
US5156998A (en) 1991-09-30 1992-10-20 Hughes Aircraft Company Bonding of integrated circuit chip to carrier using gold/tin eutectic alloy and refractory metal barrier layer to block migration of tin through via holes
JPH0760675A (en) 1993-08-27 1995-03-07 Tokin Corp Electrostatic attracting hand
US5435857A (en) 1994-01-06 1995-07-25 Qualitek International, Inc. Soldering composition
US5592358A (en) 1994-07-18 1997-01-07 Applied Materials, Inc. Electrostatic chuck for magnetic flux processing
JP3271475B2 (en) 1994-08-01 2002-04-02 株式会社デンソー Electrical element joining material and joining method
TW311927B (en) 1995-07-11 1997-08-01 Minnesota Mining & Mfg
JP3132353B2 (en) 1995-08-24 2001-02-05 松下電器産業株式会社 Chip mounting device and mounting method
KR100186752B1 (en) 1995-09-04 1999-04-15 황인길 Semiconductor chip bonding method
US5888847A (en) 1995-12-08 1999-03-30 Lsi Logic Corporation Technique for mounting a semiconductor die
US5858099A (en) 1996-04-09 1999-01-12 Sarnoff Corporation Electrostatic chucks and a particle deposition apparatus therefor
JPH1126733A (en) 1997-07-03 1999-01-29 Seiko Epson Corp Transfer method of thin film device, thin film device, thin film integrated circuit device, active matrix substrate, liquid crystal display and electronic equipment
KR100278137B1 (en) 1997-09-04 2001-01-15 가나이 쓰도무 Method of mounting semiconductor device and system thereof, method of manufacturing semiconductor device isolator and IC card
US5903428A (en) 1997-09-25 1999-05-11 Applied Materials, Inc. Hybrid Johnsen-Rahbek electrostatic chuck having highly resistive mesas separating the chuck from a wafer supported thereupon and method of fabricating same
JP3406207B2 (en) 1997-11-12 2003-05-12 シャープ株式会社 Method of forming transistor array panel for display
US6071795A (en) 1998-01-23 2000-06-06 The Regents Of The University Of California Separation of thin films from transparent substrates by selective optical processing
US6080650A (en) 1998-02-04 2000-06-27 Texas Instruments Incorporated Method and apparatus for attaching particles to a substrate
US6081414A (en) 1998-05-01 2000-06-27 Applied Materials, Inc. Apparatus for improved biasing and retaining of a workpiece in a workpiece processing system
JP3504543B2 (en) 1999-03-03 2004-03-08 株式会社日立製作所 Semiconductor device separation method and device, and semiconductor device mounting method
US6335263B1 (en) 2000-03-22 2002-01-01 The Regents Of The University Of California Method of forming a low temperature metal bond for use in the transfer of bulk and thin film materials
JP4489904B2 (en) 2000-04-14 2010-06-23 株式会社アルバック Vacuum processing apparatus and substrate holding method
US6558109B2 (en) 2000-05-26 2003-05-06 Automation Technology, Inc. Method and apparatus for separating wafers
US6683368B1 (en) 2000-06-09 2004-01-27 National Semiconductor Corporation Lead frame design for chip scale package
JP4467720B2 (en) 2000-06-15 2010-05-26 株式会社アルバック Substrate transfer device
JP3906653B2 (en) 2000-07-18 2007-04-18 ソニー株式会社 Image display device and manufacturing method thereof
JP4491948B2 (en) * 2000-10-06 2010-06-30 ソニー株式会社 Device mounting method and image display device manufacturing method
DE10051159C2 (en) 2000-10-16 2002-09-19 Osram Opto Semiconductors Gmbh LED module, e.g. White light source
JP2002134822A (en) 2000-10-24 2002-05-10 Sharp Corp Semiconductor light emitting device and method of manufacturing the same
JP4780828B2 (en) 2000-11-22 2011-09-28 三井化学株式会社 Adhesive tape for wafer processing, method for producing the same and method for using the same
JP2002164695A (en) 2000-11-29 2002-06-07 Mitsubishi Paper Mills Ltd Electrostatic attraction plate for transporting electronic material
US7022546B2 (en) 2000-12-05 2006-04-04 Analog Devices, Inc. Method and device for protecting micro electromechanical systems structures during dicing of a wafer
JP4514321B2 (en) 2000-12-08 2010-07-28 パナソニック株式会社 Component mounting equipment
US6791119B2 (en) 2001-02-01 2004-09-14 Cree, Inc. Light emitting diodes including modifications for light extraction
JP2002240943A (en) 2001-02-13 2002-08-28 Ricoh Co Ltd Electrostatic transporter, developer, image former, and classifier
JP3747807B2 (en) 2001-06-12 2006-02-22 ソニー株式会社 Device mounting substrate and defective device repair method
US6787435B2 (en) 2001-07-05 2004-09-07 Gelcore Llc GaN LED with solderable backside metal
JP3989254B2 (en) 2002-01-25 2007-10-10 日本碍子株式会社 Dissimilar material joined body and manufacturing method thereof
US6793829B2 (en) 2002-02-27 2004-09-21 Honeywell International Inc. Bonding for a micro-electro-mechanical system (MEMS) and MEMS based devices
US7033842B2 (en) 2002-03-25 2006-04-25 Matsushita Electric Industrial Co., Ltd. Electronic component mounting apparatus and electronic component mounting method
US20030189215A1 (en) 2002-04-09 2003-10-09 Jong-Lam Lee Method of fabricating vertical structure leds
TWI249148B (en) 2004-04-13 2006-02-11 Epistar Corp Light-emitting device array having binding layer
JP4147073B2 (en) 2002-09-02 2008-09-10 シャープ株式会社 Manufacturing method of light emitting diode
DE10245631B4 (en) 2002-09-30 2022-01-20 OSRAM Opto Semiconductors Gesellschaft mit beschränkter Haftung semiconductor device
US7180099B2 (en) 2002-11-11 2007-02-20 Oki Data Corporation Semiconductor apparatus with thin semiconductor film
US7585703B2 (en) 2002-11-19 2009-09-08 Ishikawa Seisakusho, Ltd. Pixel control element selection transfer method, pixel control device mounting device used for pixel control element selection transfer method, wiring formation method after pixel control element transfer, and planar display substrate
JP4766831B2 (en) 2002-11-26 2011-09-07 株式会社村田製作所 Manufacturing method of electronic parts
GB0229191D0 (en) 2002-12-14 2003-01-22 Plastic Logic Ltd Embossing of polymer devices
US6786390B2 (en) 2003-02-04 2004-09-07 United Epitaxy Company Ltd. LED stack manufacturing method and its structure thereof
JP4334892B2 (en) 2003-03-20 2009-09-30 パナソニック株式会社 Component mounting method
WO2005015647A1 (en) 2003-08-08 2005-02-17 Vichel Inc. Nitride micro light emitting diode with high brightness and method of manufacturing the same
US20050087522A1 (en) * 2003-10-24 2005-04-28 Yunlong Sun Laser processing of a locally heated target material
MXPA06011114A (en) 2004-03-29 2007-01-25 Articulated Technologies Llc Roll-to-roll fabricated light sheet and encapsulated semiconductor circuit devices.
DE602005009344D1 (en) 2004-03-31 2008-10-09 Applied Materials Inc METHOD AND DEVICE FOR TRANSMITTING CONDUCTIVE PARTS IN THE MANUFACTURE OF SEMICONDUCTOR COMPONENTS
US7462861B2 (en) 2004-04-28 2008-12-09 Cree, Inc. LED bonding structures and methods of fabricating LED bonding structures
KR100630698B1 (en) 2004-08-17 2006-10-02 삼성전자주식회사 Semiconductor package improving a solder joint reliability and method for manufacturing the same
US7187078B2 (en) 2004-09-13 2007-03-06 Taiwan Semiconductor Manufacturing Co. Ltd. Bump structure
US8174037B2 (en) 2004-09-22 2012-05-08 Cree, Inc. High efficiency group III nitride LED with lenticular surface
US7165863B1 (en) * 2004-09-23 2007-01-23 Pricilla G. Thomas Illumination system
US7563625B2 (en) 2005-01-11 2009-07-21 SemiLEDs Optoelectronics Co., Ltd. Method of making light-emitting diodes (LEDs) with improved light extraction by roughening
US7195944B2 (en) 2005-01-11 2007-03-27 Semileds Corporation Systems and methods for producing white-light emitting diodes
KR100707955B1 (en) 2005-02-07 2007-04-16 (주) 비앤피 사이언스 Light emitting diode and manufacturing method for the same
DE102005009060A1 (en) 2005-02-28 2006-09-07 Osram Opto Semiconductors Gmbh Module with radiation-emitting semiconductor bodies
US7205652B2 (en) 2005-03-23 2007-04-17 Delphi Technologies, Inc Electronic assembly including multiple substrates
US7628309B1 (en) 2005-05-03 2009-12-08 Rosemount Aerospace Inc. Transient liquid phase eutectic bonding
US7498240B2 (en) 2005-08-31 2009-03-03 Micron Technology, Inc. Microfeature workpieces, carriers, and associated methods
KR20070042214A (en) 2005-10-18 2007-04-23 김성진 Nitride-based light emitting diode and manufacturing of the same
US7737451B2 (en) 2006-02-23 2010-06-15 Cree, Inc. High efficiency LED with tunnel junction layer
US7910945B2 (en) 2006-06-30 2011-03-22 Cree, Inc. Nickel tin bonding system with barrier layer for semiconductor wafers and devices
JP2008053685A (en) 2006-08-23 2008-03-06 Samsung Electro Mech Co Ltd Vertical-structure gallium nitride light-emitting diode element, and its manufacturing method
JP4535053B2 (en) 2006-10-12 2010-09-01 ソニー株式会社 LIGHT EMITTING DIODE WIRING FORMING METHOD, LIGHT EMITTING DIODE MOUNTING BOARD, DISPLAY, BACKLIGHT, LIGHTING DEVICE, AND ELECTRONIC DEVICE
TWI320963B (en) * 2006-12-06 2010-02-21 Princo Corp Method of manufacturing hybrid structure of multi-layer substrates and hybrid structure thereof
JP4980709B2 (en) 2006-12-25 2012-07-18 ローム株式会社 Semiconductor device
KR101519038B1 (en) 2007-01-17 2015-05-11 더 보오드 오브 트러스티스 오브 더 유니버시티 오브 일리노이즈 Optical systems fabricated by printing-based assembly
TW200834962A (en) 2007-02-08 2008-08-16 Touch Micro System Tech LED array package structure having Si-substrate and method of making the same
JP2008200821A (en) 2007-02-21 2008-09-04 Denso Corp Method for manufacturing honeycomb object molding die
FR2913145B1 (en) 2007-02-22 2009-05-15 Stmicroelectronics Crolles Sas ASSEMBLY OF TWO PARTS OF INTEGRATED ELECTRONIC CIRCUIT
JP4341693B2 (en) 2007-05-16 2009-10-07 ウシオ電機株式会社 LED element and manufacturing method thereof
JP4942055B2 (en) 2007-05-20 2012-05-30 シルバーブルック リサーチ ピーティワイ リミテッド How to remove a MEMS device from a handle substrate
WO2009004980A1 (en) 2007-06-29 2009-01-08 Showa Denko K.K. Method for manufacturing light emitting diode
US8030757B2 (en) 2007-06-29 2011-10-04 Intel Corporation Forming a semiconductor package including a thermal interface material
US7838410B2 (en) 2007-07-11 2010-11-23 Sony Corporation Method of electrically connecting element to wiring, method of producing light-emitting element assembly, and light-emitting element assembly
US20090072382A1 (en) 2007-09-18 2009-03-19 Guzek John S Microelectronic package and method of forming same
JP5629580B2 (en) 2007-09-28 2014-11-19 テッセラ，インコーポレイテッド Flip chip interconnect with double posts
KR101438811B1 (en) 2008-01-03 2014-09-05 엘지이노텍 주식회사 Semiconductor light emitting device and fabrication method thereof
KR101475520B1 (en) 2008-01-14 2014-12-23 삼성전자주식회사 Quantum dot ink composition for inkjet printing and electronic device using the same
CN101919074B (en) 2008-03-26 2011-11-16 晶能光电（江西）有限公司 Method for fabricating robust light-emitting diodes
JP4479827B2 (en) 2008-05-12 2010-06-09 ソニー株式会社 Light emitting diode display device and manufacturing method thereof
DE102008050538B4 (en) 2008-06-06 2022-10-06 OSRAM Opto Semiconductors Gesellschaft mit beschränkter Haftung Optoelectronic component and method for its production
CN101603636B (en) 2008-06-10 2012-05-23 展晶科技(深圳)有限公司 Light source device
US7927976B2 (en) 2008-07-23 2011-04-19 Semprius, Inc. Reinforced composite stamp for dry transfer printing of semiconductor elements
KR101332794B1 (en) 2008-08-05 2013-11-25 삼성전자주식회사 Light emitting device, light emitting system comprising the same, and fabricating method of the light emitting device and the light emitting system
US7999454B2 (en) 2008-08-14 2011-08-16 Global Oled Technology Llc OLED device with embedded chip driving
JPWO2010021267A1 (en) 2008-08-21 2012-01-26 株式会社村田製作所 Electronic component device and manufacturing method thereof
JP5522045B2 (en) 2008-08-21 2014-06-18 株式会社村田製作所 Electronic component device and manufacturing method thereof
WO2010020077A1 (en) 2008-08-22 2010-02-25 Lattice Power (Jiangxi) Corporation Method for fabricating ingaain light-emitting device on a combined substrate
JP2010056458A (en) 2008-08-29 2010-03-11 Kyocera Corp Method of manufacturing light emitting element
TWI467691B (en) 2008-10-15 2015-01-01 Creative Tech Corp Electrostatic chuck and its manufacturing method
US7854365B2 (en) 2008-10-27 2010-12-21 Asm Assembly Automation Ltd Direct die attach utilizing heated bond head
JP5359734B2 (en) 2008-11-20 2013-12-04 豊田合成株式会社 Light emitting device and manufacturing method thereof
JP2010161212A (en) 2009-01-08 2010-07-22 Hitachi Cable Ltd Method of manufacturing wafer for semiconductor light-emitting element
KR101809472B1 (en) 2009-01-14 2018-01-18 삼성전자주식회사 Light emitting device for improving light extraction efficiency
KR101001454B1 (en) 2009-01-23 2010-12-14 삼성모바일디스플레이주식회사 Electrostatic Chuck and Manufacturing Device of Organic Light Emitting Diode Having the Same
KR100974776B1 (en) 2009-02-10 2010-08-06 엘지이노텍 주식회사 Light emitting device
JP2010186829A (en) 2009-02-10 2010-08-26 Toshiba Corp Method for manufacturing light emitting element
JP5146356B2 (en) 2009-02-24 2013-02-20 豊田合成株式会社 Light emitting device and manufacturing method thereof
JP2010199204A (en) 2009-02-24 2010-09-09 Sony Corp Light-emitting device and method of manufacturing the same
JP5470601B2 (en) 2009-03-02 2014-04-16 新光電気工業株式会社 Electrostatic chuck
US8877648B2 (en) 2009-03-26 2014-11-04 Semprius, Inc. Methods of forming printable integrated circuit devices by selective etching to suspend the devices from a handling substrate and devices formed thereby
EP2249406B1 (en) 2009-05-04 2019-03-06 LG Innotek Co., Ltd. Light emitting diode
US7989266B2 (en) 2009-06-18 2011-08-02 Aptina Imaging Corporation Methods for separating individual semiconductor devices from a carrier
US8173456B2 (en) 2009-07-05 2012-05-08 Industrial Technology Research Institute Method of manufacturing a light emitting diode element
KR100973928B1 (en) 2009-12-10 2010-08-03 (주)옵토니카 Process for led die bonding
US8334152B2 (en) 2009-12-18 2012-12-18 Cooledge Lighting, Inc. Method of manufacturing transferable elements incorporating radiation enabled lift off for allowing transfer from host substrate
TWI467798B (en) 2009-12-28 2015-01-01 Hon Hai Prec Ind Co Ltd Method for making light emitting diode chip
JP4996706B2 (en) 2010-03-03 2012-08-08 株式会社東芝 Semiconductor light emitting device and manufacturing method thereof
US9496155B2 (en) 2010-03-29 2016-11-15 Semprius, Inc. Methods of selectively transferring active components
KR101028277B1 (en) 2010-05-25 2011-04-11 엘지이노텍 주식회사 Light emitting device, method for fabricating the light emitting device, light emitting device package and lighting unit
CN101872824A (en) 2010-06-07 2010-10-27 厦门市三安光电科技有限公司 Gallium nitride-based inverted light-emitting diode (LED) with two reflecting layers on lateral surfaces and preparation method thereof
US8381965B2 (en) 2010-07-22 2013-02-26 Taiwan Semiconductor Manufacturing Company, Ltd. Thermal compress bonding
JP5700504B2 (en) 2010-08-05 2015-04-15 株式会社デンソー Semiconductor device bonding materials
US8563334B2 (en) 2010-09-14 2013-10-22 Tsmc Solid State Lighting Ltd. Method to remove sapphire substrate
JP5740939B2 (en) 2010-11-29 2015-07-01 住友電気工業株式会社 Manufacturing method of semiconductor device
GB201112376D0 (en) 2011-07-19 2011-08-31 Rolls Royce Plc Boding of metal components
JP5881992B2 (en) 2011-08-09 2016-03-09 太陽誘電株式会社 Multilayer inductor and manufacturing method thereof
CA2775545A1 (en) * 2011-09-16 2013-03-16 Joseph Tsui Led light fixture
US8349116B1 (en) 2011-11-18 2013-01-08 LuxVue Technology Corporation Micro device transfer head heater assembly and method of transferring a micro device
US8794501B2 (en) 2011-11-18 2014-08-05 LuxVue Technology Corporation Method of transferring a light emitting diode
US8518204B2 (en) 2011-11-18 2013-08-27 LuxVue Technology Corporation Method of fabricating and transferring a micro device and an array of micro devices utilizing an intermediate electrically conductive bonding layer
US9620478B2 (en) 2011-11-18 2017-04-11 Apple Inc. Method of fabricating a micro device transfer head
JP5961377B2 (en) 2011-12-21 2016-08-02 スタンレー電気株式会社 Semiconductor light emitting device
US9367094B2 (en) 2013-12-17 2016-06-14 Apple Inc. Display module and system applications

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2003060986A2 (en) * 2002-01-11 2003-07-24 The Pennsylvania State University Method of forming a removable support with a sacrificial layers and of transferring devices
WO2014030830A1 (en) * 2012-08-21 2014-02-27 Lg Electronics Inc. Display device using semiconductor light emitting device and method of fabricating the same
CN103681733A (en) * 2012-08-30 2014-03-26 财团法人工业技术研究院 Flexible display and manufacturing method thereof
US20140104793A1 (en) * 2012-10-17 2014-04-17 Electronics And Telecommunication Research Institute Stretchable electronic device and method of manufacturing same

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
TAKAHASHI K ET AL: "HIGH DENSITY LED DISPLAY PANEL ON SILICON MICROREFLECTOR AND INTEGRATED CIRCUIT", 1995 JAPAN IEMT SYMPOSIUM. PROCEEDINGS OF THE 1995 JAPAN INTERNATIONAL ELECTRONIC MANUFACTURING TECHNOLOGY SYMPOSIUM. OMIYA, DEC. 4 - 6, 1995; [PROCEEDINGS OF THE (JAPAN) INTERNATIONAL ELECTRONIC MANUFACTURING TECHNOLOGY SYMPOSIUM], NEW YORK, IEEE, U, 4 December 1995 (1995-12-04), pages 272 - 275, XP000686779, ISBN: 978-0-7803-3623-0 *

Cited By (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113421839B (en) * 2015-12-23 2022-03-18 歌尔股份有限公司 Micro light emitting diode transfer method and manufacturing method
CN113421839A (en) * 2015-12-23 2021-09-21 歌尔股份有限公司 Micro light emitting diode transfer method and manufacturing method
US10546796B2 (en) 2016-02-18 2020-01-28 Apple Inc. Backplane structure and process for microdriver and micro LED
CN108701691B (en) * 2016-02-18 2022-05-27 苹果公司 Backplane structure and method for micro-drivers and micro-LEDs
KR20180103093A (en) * 2016-02-18 2018-09-18 애플 인크. Backplane architecture and process for micro drivers and micro LEDs
CN108701691A (en) * 2016-02-18 2018-10-23 苹果公司 Floor structure and method for microdrive and micro- LED
KR102159873B1 (en) * 2016-02-18 2020-10-15 애플 인크. Backplane structure and process for microdrivers and micro LEDs
WO2017142817A1 (en) * 2016-02-18 2017-08-24 Sxaymiq Technologies Llc Backplane structure and process for microdriver and micro led
US10700103B2 (en) 2016-08-19 2020-06-30 Boe Technology Group Co., Ltd. Array substrate with inorganic light-emitting diode and display device with inorganic light-emitting diode
EP3503186A4 (en) * 2016-08-19 2020-03-11 Boe Technology Group Co. Ltd. Array substrate and preparation method thereof, and display device
KR102633079B1 (en) * 2016-10-28 2024-02-01 엘지디스플레이 주식회사 Light emitting diode display apparatus
US10325936B2 (en) 2016-10-28 2019-06-18 Lg Display Co., Ltd. Display device having light emitting diode disposed in the concave portion of the planarization layer
KR20180046491A (en) * 2016-10-28 2018-05-09 엘지디스플레이 주식회사 Light emitting diode display apparatus
KR20180046494A (en) * 2016-10-28 2018-05-09 엘지디스플레이 주식회사 Light emitting diode display apparatus
EP3316302A1 (en) * 2016-10-28 2018-05-02 LG Display Co., Ltd. Light emitting diode display device
KR102651097B1 (en) * 2016-10-28 2024-03-22 엘지디스플레이 주식회사 Light emitting diode display apparatus
GB2571203B (en) * 2018-01-30 2022-07-06 Pragmatic Printing Ltd Integrated circuit manufacturing process
US11462575B2 (en) 2018-01-30 2022-10-04 Pragmatic Printing Ltd. Integrated circuit on flexible substrate manufacturing process
WO2019150093A1 (en) * 2018-01-30 2019-08-08 Pragmatic Printing Ltd. Integrated circuit on flexible substrat manufacturing process
US11960167B2 (en) 2020-02-17 2024-04-16 BOE MLED Technology Co., Ltd. Backplane and method for manufacturing the same, and display device
JP2023063266A (en) * 2021-10-22 2023-05-09 隆達電子股▲ふん▼有限公司 Micro light emitting diode package structure
JP7469428B2 (en) 2021-10-22 2024-04-16 隆達電子股▲ふん▼有限公司 Micro light emitting diode package structure

Also Published As

Publication number Publication date
US9318475B2 (en) 2016-04-19
TWI570908B (en) 2017-02-11
US20150333221A1 (en) 2015-11-19
TW201547015A (en) 2015-12-16

Similar Documents

Publication Publication Date Title
US9318475B2 (en) Flexible display and method of formation with sacrificial release layer
US11670626B2 (en) Display with embedded pixel driver chips
US10749140B2 (en) Organic light-emitting display device
US20210202572A1 (en) Micro device integration into system substrate
US10290774B2 (en) Wearable display having an array of LEDs on a conformable silicon substrate
US10514137B2 (en) Joining structure of light emitting units
JP7045471B2 (en) Display with embedded pixel driver chip
EP3336667A1 (en) Display device with an integrated touch sensor
CN109326213B (en) Organic light emitting display device
EP1618615B1 (en) Interconnection for organic devices
CN107873110A (en) Flexible base board and its support and separation method
CN109300932B (en) LED display and manufacturing method thereof
US10847571B2 (en) Micro device integration into system substrate
CN112133729A (en) Display substrate, preparation method thereof and display device
WO2017123658A1 (en) Light emitting diode display
CN112151445A (en) Preparation method of display substrate, display substrate and display device
KR102619978B1 (en) Flexible display device
JP2018194600A (en) Display
US20120168790A1 (en) Display device structure and manufacturing method thereof
US20120193656A1 (en) Display device structure and manufacturing method thereof
CN214505497U (en) Display panel and display device
US20230225158A1 (en) Display device and method of manufacturing the same
KR20240056853A (en) Display device, method of fabricating the same, and tile shaped display device including the same
CN114530474A (en) Display panel, display device and manufacturing method of display panel

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 15722605

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 15722605

Country of ref document: EP

Kind code of ref document: A1