CN214505497U

CN214505497U - Display panel and display device

Info

Publication number: CN214505497U
Application number: CN202022465101.XU
Authority: CN
Inventors: 文平; 张顺; 张元其; 罗昶; 王威; 王裕; 刘庭良; 曾扬; 张毅
Original assignee: BOE Technology Group Co Ltd; Chengdu BOE Optoelectronics Technology Co Ltd
Current assignee: BOE Technology Group Co Ltd; Chengdu BOE Optoelectronics Technology Co Ltd
Priority date: 2020-10-30
Filing date: 2020-10-30
Publication date: 2021-10-26
Anticipated expiration: 2030-10-30

Abstract

The present disclosure relates to a display panel and a display device. The display panel includes: a display substrate having a display area and a non-display area surrounding the display area, the display substrate including a substrate and an integrated circuit joint portion disposed at one side of the substrate and located at the non-display area, wherein the integrated circuit joint portion includes: a pin; the first passivation layer is positioned on one side of the substrate, which is adjacent to the pins, covers the peripheral areas of the pins and exposes the central areas of the pins; the first spacing layer is positioned on one side of the first passivation layer, which is far away from the substrate, and covers the first passivation layer and the edge of the first passivation layer, which is connected with the pin; and the first metal layer is positioned on one side of the first spacing layer, which is far away from the substrate, at least covers the central part of the pin, and is electrically connected with the pin.

Description

Display panel and display device

Technical Field

The present disclosure relates to the field of display technologies, and in particular, to a display panel and a display device.

Background

In some related technologies of Organic Light-Emitting Diode (OLED) display devices, a Flexible Multi-Layer On-Film (FMLOC) method is used to dispose a touch element between a display substrate and a cover glass, which are subjected to Thin Film Encapsulation (TFE) process. The bonding pad of the bonding area (i.e., the IC bonding area) of the integrated circuit chip of the display substrate is covered by an organic material film, such as a Planarization Layer (PLN) or a Pixel Definition Layer (PDL).

Disclosure of Invention

In one aspect of the present disclosure, there is provided a display panel including:

a display substrate having a display region and a non-display region surrounding the display region, the display substrate including a substrate and an Integrated Circuit (IC) joint portion disposed on one side of the substrate and located in the non-display region, wherein the IC joint portion includes:

a pin;

the first passivation layer is positioned on one side of the substrate, which is adjacent to the pins, covers the peripheral areas of the pins and exposes the central areas of the pins;

the first spacing layer is positioned on one side of the first passivation layer, which is far away from the substrate, and covers the first passivation layer and the edge of the first passivation layer, which is connected with the pin; and

and the first metal layer is positioned on one side of the first spacing layer, which is far away from the substrate, at least covers the central part of the pin, and is electrically connected with the pin.

In some embodiments, the display panel further comprises:

the IC chip is provided with a chip pin and is positioned on one side of the first metal layer, which is far away from the substrate; and

and the conductive adhesive film is positioned between the chip pin of the IC chip and the first metal layer and is electrically connected with the chip pin of the IC chip and the first metal layer.

In some embodiments, the display panel further comprises:

the touch structure is at least positioned in the display area of the display substrate;

wherein the display substrate further comprises:

a plurality of light emitting elements disposed on a side of the substrate adjacent to the IC bonding portion and located in the display region; and

and the packaging layer is positioned between the plurality of light-emitting elements and the touch structure and is configured to package the display substrate.

In some embodiments, the touch structure includes:

and the second spacer layer is positioned on one side of the packaging layer, which is far away from the substrate, and covers the surface of the packaging layer.

In some embodiments, the touch structure further comprises:

the first touch electrode layer is provided with a first touch electrode pattern and is positioned on one side, far away from the substrate, of the second interlayer;

the touch insulating layer is provided with a touch insulating pattern and is positioned on one side, far away from the substrate, of the first touch electrode layer; and

and the second touch electrode layer is provided with a second touch electrode pattern and is positioned on one side of the touch insulating layer far away from the substrate, and part of the second touch electrode pattern is electrically connected with the first touch electrode pattern through a via hole penetrating through the touch insulating layer.

In some embodiments, the touch structure further comprises:

and the insulating protection layer is provided with an insulating protection pattern, is positioned on one side of the second touch electrode layer away from the substrate, and is configured to perform insulating protection on the second touch electrode layer.

In some embodiments, the second spacer layer is on the same layer and of the same material as the first spacer layer.

In some embodiments, the touch insulating layer and the first spacing layer are located on the same layer and are made of the same material, and the second touch electrode layer and the first metal layer are located on the same layer and are made of the same material.

In some embodiments, the display substrate further comprises:

a first insulating layer between the first passivation layer and the substrate; and

a second insulating layer between the first insulating layer and the first passivation layer,

wherein the pin comprises:

and the first pin metal layer is positioned on the surface of one side of the first insulating layer, which is far away from the substrate, and is partially covered by the second insulating layer.

In some embodiments, the display substrate further comprises:

a third insulating layer between the second insulating layer and the first passivation layer,

wherein the pin further comprises:

and the second pin metal layer is positioned on the surface of one side, far away from the substrate, of the third insulating layer, is electrically connected with the first pin metal layer through a via hole penetrating through the second insulating layer and the third insulating layer, and is also electrically connected with the first metal layer.

In some embodiments, the display substrate further comprises:

the thin film transistor device comprises an active layer, a grid electrode, a source electrode and a drain electrode, wherein the active layer is positioned between the first insulating layer and the substrate, the grid electrode is positioned on the surface of one side, away from the substrate, of the first insulating layer, and the source electrode and the drain electrode are positioned on the surface of one side, away from the substrate, of the third insulating layer and are respectively and electrically connected with the active layer through via holes penetrating through the first insulating layer, the second insulating layer and the third insulating layer; and

the capacitor device comprises a first capacitor plate and a second capacitor plate, the first capacitor plate is positioned on the surface of one side, away from the substrate, of the first insulating layer, and the second capacitor plate is positioned on the surface of one side, away from the substrate, of the second insulating layer;

the grid electrode, the first capacitor plate and the first pin metal layer are located on the same layer and are made of the same material, and the source electrode, the drain electrode and the second pin metal layer are located on the same layer and are made of the same material.

In some embodiments, the display substrate further comprises:

the second passivation layer is positioned on one side, far away from the substrate, of the third insulating layer and covers the source electrode and the drain electrode; and

a planarization layer on a side of the second passivation layer away from the substrate,

the plurality of light emitting elements are positioned between the planarization layer and the packaging layer, and the second passivation layer and the first passivation layer are positioned on the same layer and are made of the same material.

In another aspect of the present disclosure, a display device is provided, which includes the aforementioned display panel.

In still another aspect of the present disclosure, there is provided a method of manufacturing a display panel, including:

forming a display substrate having a display area and a non-display area surrounding the display area, the display substrate including a substrate and an IC bonding portion formed on a side of the substrate and located in the non-display area,

wherein the step of forming the IC joint comprises:

forming a pin on one side of the substrate;

forming a first passivation layer on one side of the substrate adjacent to the pins, covering the first passivation layer on the peripheral areas of the pins and exposing the central areas of the pins;

forming a first spacing layer on one side of the first passivation layer, which is far away from the substrate, and enabling the first spacing layer to cover the first passivation layer and the edge of the first passivation layer, which is connected with the pin; and

and forming a first metal layer on one side of the first spacing layer, which is far away from the substrate, and enabling the first metal layer to at least cover the central part of the pin and be electrically connected with the pin.

In some embodiments, between the step of forming the first passivation layer and the step of forming the first spacer layer, further comprising:

forming a planarization layer on one side of the first passivation layer away from the substrate;

removing at least a portion of the planarization layer corresponding to the leads.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the disclosure and together with the description, serve to explain the principles of the disclosure.

The present disclosure may be more clearly understood from the following detailed description, taken with reference to the accompanying drawings, in which:

FIG. 1A is a schematic view of an overall layout of a display substrate according to an embodiment of a display panel of the present disclosure;

FIG. 1B is a schematic view of a portion B of the IC bond of FIG. 1A;

FIG. 2 is a schematic cross-sectional view of an AA in an area where an IC bonding portion is located according to an embodiment of the display panel of the present disclosure;

FIG. 3 is a schematic cross-sectional view of a display area in an embodiment of a display panel according to the present disclosure;

FIG. 4 is a schematic flow diagram of the formation of IC joints in a manufacturing flow of an embodiment of a display panel according to the present disclosure;

fig. 5 is a schematic flow chart of forming a light emitting device, an encapsulation layer, and a touch structure in a manufacturing process according to an embodiment of the display panel of the present disclosure.

It should be understood that the dimensions of the various parts shown in the figures are not drawn to scale. Further, the same or similar reference numerals denote the same or similar components.

Detailed Description

Various exemplary embodiments of the present disclosure will now be described in detail with reference to the accompanying drawings. The description of the exemplary embodiments is merely illustrative and is in no way intended to limit the disclosure, its application, or uses. The present disclosure may be embodied in many different forms and is not limited to the embodiments described herein. These embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art. It should be noted that: the relative arrangement of parts and steps, the composition of materials, numerical expressions and numerical values set forth in these embodiments are to be construed as merely illustrative, and not as limitative, unless specifically stated otherwise.

The use of "first," "second," and similar terms in this disclosure is not intended to indicate any order, quantity, or importance, but rather are used to distinguish one element from another. The word "comprising" or "comprises", and the like, means that the element preceding the word covers the element listed after the word, and does not exclude the possibility that other elements are also covered. "upper", "lower", "left", "right", and the like are used merely to indicate relative positional relationships, and when the absolute position of the object being described is changed, the relative positional relationships may also be changed accordingly.

In the present disclosure, when a specific device is described as being located between a first device and a second device, there may or may not be intervening devices between the specific device and the first device or the second device. When a particular device is described as being coupled to other devices, that particular device may be directly coupled to the other devices without intervening devices or may be directly coupled to the other devices with intervening devices.

All terms (including technical or scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs unless specifically defined otherwise. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

Techniques, methods, and apparatus known to those of ordinary skill in the relevant art may not be discussed in detail but are intended to be part of the specification where appropriate.

In some related art, the bonding part leads of the IC bonding region (IC bonding region) of the display substrate are covered by an organic material film layer (e.g., planarization layer). It was found that, in the FMLOC process, when a spacer layer (i.e., barrier layer) is formed in the IC bonding region, the adhesion of the spacer layer to the organic material film layer is poor. Moreover, the edge part of the organic material film layer which is not covered by the spacing layer is exposed. This all makes the organic material film layer easily absorb water in the water washing step in the FMLOC process. When the subsequent display substrate is subjected to a test, such as a reliability test of high temperature and high humidity, the absorbed moisture in the organic material film layer expands due to heat, which may cause the spacer layer and the metal layer in the IC bonding region to peel off.

In other related arts, when the spacer layer is formed, the spacer layer is made to cover the edge portion of the organic material film layer without being exposed. It has been found that when such a structure is adopted, the metal layer covering the bonding pad leads of the IC bonding region also covers the spacer layer covering the organic material film layer, so that the height difference between the edge region and the central region not covered by the spacer layer and the organic material film layer can reach 1.2 μm. Thus, when the electrical connection between the metal layer and the pin of the IC chip is realized through the Anisotropic Conductive Film (ACF), the Conductive particles in the ACF corresponding to the edge region of the metal layer are stressed greatly and easily crack the spacer layer, so that the organic material Film layer is easily absorbed by water through the crack of the spacer layer in the water washing step in the FMLOC process. When the subsequent display substrate is subjected to a test, such as a reliability test of high temperature and high humidity, the absorbed moisture in the organic material film layer expands due to heat, which may cause the spacer layer and the metal layer in the IC bonding region to peel off.

In view of the above, the present disclosure provides a display panel and a display device, which can improve the peeling of the spacer layer and the metal layer in the IC bonding region.

Fig. 1A is a schematic overall layout diagram of a display substrate according to an embodiment of a display panel of the present disclosure. FIG. 1B is a schematic view of a portion B of the IC bond of FIG. 1A. Fig. 2 is an AA cross-sectional structure diagram of an area where an IC bonding portion is located according to an embodiment of the display panel of the present disclosure.

Referring to fig. 1A and 1B, in some embodiments, a display panel includes a display substrate 1. The display substrate 1 has a display area 10A and a non-display area 10B surrounding the display area 10A. The display area 10A is used to display an image, and the non-display area 10B is used to arrange related circuits and related electronic components to support the display of the display area 10A.

The specific shape of the display area 10A is not limited, and is, for example, circular, elliptical, polygonal, or the like. Referring to fig. 1A and 1B, in some embodiments, the display area 10A is substantially polygonal, such as substantially rectangular as shown in fig. 1A. The display area 10A here being substantially polygonal can be understood as: the display area 10A is shaped as a polygon after ignoring a round chamfer, an oblique chamfer, or a process error of the display area.

In fig. 1A and 1B, the display substrate 1 includes a substrate 10 and an IC bonding portion 20 provided on a side of the substrate 10 and located in the non-display region 10B. The IC bonding section 20 is configured to connect pins of an IC chip that can supply a driving signal, a data signal, a clock signal, and the like to display pixels in the display substrate, and supply a detection signal and the like to the display substrate.

In some embodiments, the display substrate 1 is an Active Matrix Organic Light-Emitting Diode (AMOLED) display substrate or a Passive Matrix Organic Light-Emitting Diode (PMOLED) display substrate. For example, when the display substrate 10 is an AMOLED display substrate, the substrate 10 thereof may be a flexible substrate (e.g., a polyimide material) or a rigid substrate (e.g., a glass or resin material).

In fig. 2, the IC bonding portion 20 includes: a lead 21, a first passivation layer (PVX)22, a first spacer layer 23 and a first metal layer 24. The first passivation layer 22 is disposed on a side of the substrate 10 adjacent to the leads 21, and covers a peripheral region of the leads 21 and exposes a central region of the leads 21. The first passivation layer 22 may be formed of an inorganic material, such as silicon compound, e.g., silicon oxide SiOx, silicon nitride SiNx, or silicon oxynitride SiNO.

A first spacer layer 23 is located on a side of the first passivation layer 22 away from the substrate 10 and covers the passivation layer 22 and an edge of the first passivation layer 22 where the leads 21 meet. The first spacer layer 23 may be made of an insulating material, such as silicon nitride SiNx. The first metal layer 24 is located on a side of the first spacing layer 23 away from the substrate 10, covers at least a central portion of the lead 21, and is electrically connected to the lead 21.

Compared with the structure that the peripheral region of the lead is coated by the organic material film layer such as the planarization layer in the IC bonding region in the related art, the peripheral region of the lead 21 is coated by the first passivation layer 22, the adhesion between the peripheral region and the first spacing layer 23 is superior to the adhesion between the organic material film layer and the spacing layer in the related art, the lead is not easily peeled off from the first passivation layer 22, the situation that the spacing layer and the metal layer are peeled off due to the fact that the organic material film layer absorbs water vapor and is thermally expanded can also be avoided, and the first spacing layer 23 and the first metal layer 24 in the IC bonding portion are further made to be less prone to peeling off.

Referring to fig. 2, in some embodiments, the display panel further includes: an IC chip 4 and a conductive adhesive film 41. The IC chip 4 has chip pins 42, and the IC chip 4 is located on a side of the first metal layer 24 away from the substrate 10. The conductive adhesive film 41 is located between the chip pin 42 of the IC chip 4 and the first metal layer 24, and is electrically connected to both the chip pin 42 of the IC chip 4 and the first metal layer 24. The conductive adhesive film 41 may be ACF.

Compared with the related art in which the spacing layer is used to cover the edge portion of the organic material film layer, and the ACF is used to connect the metal layer and the pins of the IC chip, in this embodiment, the first spacing layer 23 is directly covered on the first passivation layer 22, so that the height difference between the edge and the center of the first metal layer 24 formed on the first spacing layer 23 and the IC chip 4 is relatively small, so that the conductive particles at the position of the conductive adhesive film 41 corresponding to the edge are relatively small in stress, and the first spacing layer 23 is not easily fractured. On the other hand, the situation that the organic material film layer absorbs water vapor through the crack of the spacing layer and expands due to heating to cause the peeling of the spacing layer and the metal layer can be avoided, and the first spacing layer 23 and the first metal layer 24 in the IC joint part are further not easy to peel.

In fig. 2, the display substrate further includes: a first insulating layer 12a and a second insulating layer 12 b. A first insulating layer 12a is located between the first passivation layer 22 and the substrate 10. The second insulating layer 12b is located between the first insulating layer 12a and the first passivation layer 22.

The materials of the first insulating layer (e.g., the first gate insulating layer GI1)12a and the second insulating layer (e.g., the second gate insulating layer GI2)12b may each include a silicon compound or a metal oxide, such as silicon oxynitride SiNO, silicon oxide SiOx, silicon nitride SiNx, silicon oxycarbide SiCxOy, silicon carbide SiCxNy, aluminum oxide AlOx, aluminum nitride AlNx, tantalum oxide TaOx, hafnium oxide HfOx, zirconium oxide ZrOx, titanium oxide TiOx, or the like. The first insulating layer 12a and the second insulating layer 12b may be a single layer or a multilayer.

The leads 21 in the IC bonding portion 20 may be formed simultaneously during the formation of the display pixels in the display substrate 1. Referring to fig. 2, in some embodiments, the lead 21 includes a first lead metal layer 21 a. The first lead metal layer 21a is located on a surface of the first insulating layer 12a on a side away from the substrate 10, and is partially covered by the second insulating layer 12 b.

Referring to fig. 2, in some embodiments, the display substrate further includes a third insulating layer 12 c. A third insulating layer 12c is located between the second insulating layer 12b and the first passivation layer 22. The material of the third insulating layer (e.g., interlayer insulating layer ILD)12c may include a silicon compound, a metal oxide, and the like. The silicon compounds and metal oxides listed above may be selected in particular and will not be described in further detail here.

In fig. 2, the lead 21 further includes a second lead metal layer 21 b. The second pin metal layer 21b is located on a surface of the third insulating layer 12c on a side away from the substrate 10, and is electrically connected to the first pin metal layer 21a through a via hole penetrating through the second insulating layer 12b and the third insulating layer 12c, and the second pin metal layer 21b is further electrically connected to the first metal layer 24.

Fig. 3 is a schematic cross-sectional structure diagram of a display area in an embodiment of a display panel according to the present disclosure.

Referring to fig. 3, in some embodiments, the display panel further includes a touch structure 30. The touch structure 30 is formed on the display substrate 1 by using the FMLOC process. The touch structure 30 is at least located in the display area 10A of the display substrate 1. In some embodiments, the touch structure 30 is located in the display area 10A. In other embodiments, the touch structure 30 is located in the display area 10A and the non-display area 10B.

For the touch structure 30 formed by using the FMLOC process, since the display substrate needs to be washed before each Photo Mask (Photo Mask) process in the process, the organic material film layer in the IC bonding region in the related art is likely to absorb water in the washing process, and the IC bonding portion in the embodiment uses the first passivation layer 22 to cover the peripheral region of the pin 21, so that the problem that the organic material is likely to absorb water when the pin is covered by the organic material film layer is avoided.

In fig. 3, the display substrate 1 further includes: a plurality of light emitting elements 15 and an encapsulation layer 19. A plurality of light emitting elements 15 are provided on a side of the substrate 10 adjacent to the IC bonding portion 20 and located in the display region 10A. For an AMOLED display substrate, the display substrate 1 may further include a thin film transistor device 13 and a capacitance device 14. The thin film transistor device 13 is electrically connected to the light emitting elements 15 so as to control the light emitting elements 15 to cause the respective light emitting elements 15 to emit light independently.

The thin film transistor device 13 may include an active layer 13a, a gate electrode 13b, a source electrode 13c, and a drain electrode 13 d. The active layer 13a is located between the first insulating layer 12a and the substrate 10, the gate 13b is located on a surface of the first insulating layer 12a on a side away from the substrate 10, and the source 13c and the drain 13d are located on a surface of the third insulating layer 12c on a side away from the substrate 10, and are electrically connected to the active layer 13a through vias penetrating through the first insulating layer 12a, the second insulating layer 12b, and the third insulating layer 12c, respectively.

The material of the active layer 13a may include an inorganic semiconductor material (e.g., polysilicon or amorphous silicon, etc.), an organic semiconductor material, or an oxide semiconductor material. The material of the gate electrode 13b may include metal, metal alloy, metal nitride, conductive metal oxide, transparent conductive material, or the like, such as silver, copper, aluminum alloy, aluminum nitride, tin oxide, indium tin oxide, or the like. The material of the source electrode 13c and the drain electrode 13d may include a metal, an alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, or the like, for example, a multi-layered metal of Mo-Al-Mo or Ti-Al-Ti.

The capacitor device 14 may comprise a first capacitor plate 14a and a second capacitor plate 14b, the first capacitor plate 14a being located on a surface of the first insulating layer 12a on a side away from the substrate 10, and the second capacitor plate 14b being located on a surface of the second insulating layer 12b on a side away from the substrate 10.

In some embodiments, the gate 13b, the first capacitor plate 14a and the first lead metal layer 21a are located on the same layer and have the same material, which is beneficial to form the gate 13b, the first capacitor plate 14a and the first lead metal layer 21a through the same patterning process, thereby simplifying the process. In some embodiments, the source electrode 13c, the drain electrode 13d and the second lead metal layer 21b are located on the same layer and have the same material, which is advantageous for the source electrode 13c, the drain electrode 13d and the second lead metal layer 21b to be formed through the same patterning process, thereby simplifying the process.

The structure of the same layer and the same material as mentioned later herein may be a layer structure formed by forming a film layer having a specific pattern by the same film forming process and then patterning the film layer by a single patterning process using the same mask plate. Depending on the specific pattern, one patterning process may include multiple exposure, development or etching processes, and the specific pattern in the formed layer structure may be continuous or discontinuous. These specific patterns may also be at different heights or have different thicknesses.

In fig. 2 and 3, a buffer layer 11 may be further disposed between the first insulating layer 12a and the substrate 10. The buffer layer 11 serves to prevent or reduce diffusion of metal atoms or impurities from the substrate into the active layer of the transistor. The buffer layer 11 may include an inorganic material such as silicon oxide SiOx, silicon nitride SiNx, or silicon oxynitride SiNO, and may be formed in a single layer or multiple layers.

Referring to fig. 3, in some embodiments, the display substrate 1 further includes: a second passivation layer 16 and a planarization layer 17. A second passivation layer 16 is located on a side of the third insulating layer 12c away from the substrate 10 and covers the source electrode 13c and the drain electrode 13 d. In some embodiments, the second passivation layer 16 is formed in the same layer and material as the first passivation layer 22, which is advantageous for forming through the same patterning process, thereby simplifying the process.

A planarization layer 17 is located on the side of the second passivation layer 16 remote from the substrate 10. A plurality of light emitting elements 15 are located between the planarization layer 17 and the encapsulation layer 19. The material of the planarization layer may include an organic insulating material, such as resin-based materials, such as polyimide, epoxy, acryl, polyester, photoresist, polyacrylate, polyamide, and siloxane, or elastic materials, such as urethane and thermoplastic polyurethane.

In forming the planarization layer 17, the planarization layer 17 may also be formed on the IC bonding area, for example, on the surface of the first passivation layer 22 on the side away from the substrate 10. In order to avoid the problem that the planarization layer including the organic material in the related art is liable to absorb water, at least a portion of the planarization layer 17 corresponding to the lead 21 may be removed by etching or the like.

Referring to fig. 3, the light emitting element 15 may be an OLED light emitting element. The light emitting element may include a first electrode layer 15a, an organic light emitting layer 15b, and a second electrode layer 15 c. The first electrode layer 15a is located between the planarization layer 17 and the pixel defining layer 18, the organic light emitting layer 15b is located in the pixel opening defined by the pixel defining layer 18, and the second electrode layer 15c is located on the side of the organic light emitting layer 15b away from the substrate 10. The first electrode layer 15a may be electrically connected to the drain electrode 13d through a via hole penetrating the planarization layer 17 and the second passivation layer 16.

In some embodiments, the first electrode layer 15a serves as an anode layer of the light emitting element 15, and the second electrode layer 15c serves as a cathode of the light emitting element 15. The first electrode layer 15a and the second electrode layer 15b may be made of a metal, a metal alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, or the like. The organic light emitting layer 15b may include a small molecule organic material or a polymer molecule organic material, such as a fluorescent light emitting material or a phosphorescent light emitting material, and may emit red, green, blue, or white light.

Referring to fig. 3, in some embodiments, the touch structure 30 includes a second spacer layer 31. The second spacer layer 31 is located on a side of the encapsulation layer 19 away from the substrate 10, and covers a surface of the encapsulation layer 19. In some embodiments, the second spacer layer 31 is located on the same layer and has the same material as the first spacer layer 23, which facilitates the formation of the second spacer layer 31 and the first spacer layer 23 through the same patterning process, thereby simplifying the process.

Referring to fig. 3, in some embodiments, the touch structure 30 includes a first touch electrode layer 32. The first touch electrode layer 32 has a first touch electrode pattern (TSP Metal a, abbreviated as TMA), and is located on a side of the second spacer layer 31 away from the substrate 10. The material of the first touch electrode layer 32 may include a metal, an alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, or the like, for example, a multi-layer metal of Mo-Al-Mo or Ti-Al-Ti.

The first touch electrode pattern can be used for forming a lower channel of the bridging area, and can also be used for the vertical access of the peripheral touch driving electrode TX and the horizontal access of the touch sensing electrode RX signal routing. In other embodiments, the touch driving electrodes TX and the touch sensing electrodes RX may be arranged in the horizontal and vertical directions, respectively, or in other arrangements as needed.

In fig. 3, the touch structure 30 further includes: a touch insulating layer 33 and a second touch electrode layer 34. The touch insulating layer 33 has a touch insulating pattern and is located on a side of the first touch electrode layer 32 away from the substrate 10. The material of the touch insulating layer 33 may include an inorganic material, such as silicon oxide SiOx, silicon nitride SiNx, or silicon oxynitride SiNO, which may serve as an interlayer dielectric layer for insulation. In some embodiments, the touch insulating layer 33 and the first spacer layer 23 are located on the same layer and have the same material, which is beneficial for the touch insulating layer 33 and the first spacer layer 23 to be formed by the same patterning process, thereby simplifying the process.

The second touch electrode layer 34 has a second touch electrode pattern (TSP Metal B, abbreviated as TMB) and is located on a side of the touch insulating layer 33 away from the substrate 10, and a portion of the second touch electrode pattern is electrically connected to the first touch electrode pattern through a via hole penetrating the touch insulating layer 33. The second touch electrode pattern can be used for forming an upper layer channel of the bridging area, and can also be used for forming a metal mesh electrode outside the bridging area and signal routing lines positioned on the periphery. In some embodiments, the second touch electrode layer 34 and the first metal layer 24 are located on the same layer and have the same material, which is beneficial for the second touch electrode layer 34 and the first metal layer 24 to be formed through the same patterning process, thereby simplifying the process.

Referring to fig. 3, in some embodiments, the touch structure 30 further includes an insulating protection layer 35. The insulating protection layer 35 has an insulating protection pattern, is located on a side of the second touch electrode layer 34 away from the substrate 10, and is configured to perform insulating protection on the second touch electrode layer 34. The material of the insulating protective layer 35 may include an inorganic insulating material or an organic insulating material, such as polyimide.

The display panel embodiment of the present disclosure is applicable to various display devices. Therefore, the present disclosure also provides a display device including the aforementioned display panel. The display device may be: any product or component with a display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator and the like.

Fig. 4 is a schematic flow diagram of forming an IC joint in a manufacturing flow according to an embodiment of a display panel of the present disclosure.

Referring to fig. 4 and the foregoing display panel embodiments of the present disclosure, in some embodiments, a manufacturing process of a display panel includes: a display substrate 1 having a display area 10A and a non-display area 10B surrounding the display area 10A is formed, the display substrate 1 including a substrate 10 and an IC bonding portion 20 formed on one side of the substrate 10 and located in the non-display area 10B. In the process of forming the display substrate 1, the step of forming the IC bonding part 20 may include steps 110 to 140.

Prior to step 110, a substrate 10 is formed. In step 110, leads 21 are formed on one side of the substrate 10. In step 120, a first passivation layer 22 is formed on a side of the substrate 10 adjacent to the lead 21, and the first passivation layer 22 covers a peripheral region of the lead 21 and exposes a central region of the lead 21.

In step 130, a first spacer layer 23 is formed on a side of the first passivation layer 22 away from the substrate 10, and the first spacer layer 23 covers the first passivation layer 22 and an edge of the first passivation layer 22 where the lead 21 meets. In step 140, a first metal layer 24 is formed on a side of the first spacer layer 23 away from the substrate 10, and the first metal layer 24 covers at least a central portion of the lead 21 and is electrically connected to the lead 21.

In some embodiments, between the step 120 of forming the first passivation layer 22 and the step 130 of forming the first spacer layer 23 in fig. 4, the method may further include: forming a planarization layer 17 on the side of the first passivation layer 22 away from the substrate 10; at least the portion of the planarization layer 17 corresponding to the lead 21 is removed. In removing the planarization layer, the planarization layer material may be removed by means of laser or chemical etching. In other embodiments, the opening position of the mask of the planarization layer may be set after step 120 so that the planarization layer does not cover the first passivation layer 22 and the leads 21 in the IC bonding region.

Referring to fig. 5, in some embodiments, the step of forming the display substrate 1 further includes steps 210 and 220. In step 210, a plurality of light emitting elements 15 are formed at positions on the substrate 10 adjacent to the IC bonding portion 20 and corresponding to the display region 10A. In step 220, an encapsulation layer 19 is formed on a side of the light emitting elements 15 away from the substrate 10 to encapsulate the display substrate 1.

In some embodiments, the manufacturing process of the display panel further includes: a touch structure 30 is formed on a side of the encapsulation layer 19 away from the substrate 10. The touch structure 30 may be formed by an FMLOC process. Referring to fig. 5, the step of forming the touch structure 30 may include steps 230 to 270. In step 230, a second spacer layer 31 is formed on a side of the encapsulation layer 19 away from the substrate 10, and the second spacer layer 31 covers a surface of the encapsulation layer 19.

In step 240, a first touch electrode layer 32 having a first touch electrode pattern is formed on a side of the second spacer layer 31 away from the substrate 10. In step 250, a touch insulating layer 33 having a touch insulating pattern is formed on a side of the first touch electrode layer 32 away from the substrate 10.

In step 260, a second touch electrode layer 34 having a second touch electrode pattern is formed on a side of the touch insulating layer 33 away from the substrate 10, and a portion of the second touch electrode pattern is electrically connected to the first touch electrode pattern through a via hole penetrating through the touch insulating layer 33. In step 270, an insulating protection layer 35 having an insulating protection pattern is formed on a side of the second touch electrode layer 34 away from the substrate 10, so as to protect the second touch electrode layer 34 in an insulating manner.

In the above embodiments, the second spacer layer 31 and the first spacer layer 23 are formed by the same patterning process, and the second touch electrode layer 34 and the first metal layer 24 are formed by the same patterning process. This is advantageous in simplifying the process. In other embodiments, the touch insulating layer 33 and the first spacer layer 23 are formed by the same patterning process, which is advantageous for simplifying the process.

In the above steps 240 to 270, a first touch electrode pattern, a second touch electrode pattern, a touch insulating pattern and an insulating protection pattern may be formed by using a Photo Mask (Photo Mask) process. In other embodiments, the patterns may also be formed by a Chemical Vapor Deposition (CVD) process.

In the present specification, a plurality of embodiments are described in a progressive manner, the emphasis of each embodiment is different, and the same or similar parts between the embodiments are referred to each other.

Thus, various embodiments of the present disclosure have been described in detail. Some details that are well known in the art have not been described in order to avoid obscuring the concepts of the present disclosure. It will be fully apparent to those skilled in the art from the foregoing description how to practice the presently disclosed embodiments.

Although some specific embodiments of the present disclosure have been described in detail by way of example, it should be understood by those skilled in the art that the foregoing examples are for purposes of illustration only and are not intended to limit the scope of the present disclosure. It will be understood by those skilled in the art that various changes may be made in the above embodiments or equivalents may be substituted for elements thereof without departing from the scope and spirit of the present disclosure. The scope of the present disclosure is defined by the appended claims.

Claims

1. A display panel, comprising:

a display substrate having a display area and a non-display area surrounding the display area, the display substrate including a substrate and an integrated circuit joint portion disposed at one side of the substrate and located at the non-display area, wherein the integrated circuit joint portion includes:

a pin;

2. The display panel according to claim 1, further comprising:

the integrated circuit chip is provided with a chip pin and is positioned on one side of the first metal layer away from the substrate; and

and the conductive adhesive film is positioned between the chip pin of the integrated circuit chip and the first metal layer and is electrically connected with the chip pin of the integrated circuit chip and the first metal layer.

3. The display panel according to claim 1 or 2, characterized by further comprising:

wherein the display substrate further comprises:

a plurality of light emitting elements disposed on a side of the substrate adjacent to the integrated circuit bonding portion and located in the display region; and

4. The display panel according to claim 3, wherein the touch structure comprises:

5. The display panel of claim 4, wherein the touch structure further comprises:

6. The display panel of claim 5, wherein the touch structure further comprises:

7. The display panel of claim 4, wherein the second spacer layer is on the same layer as the first spacer layer and is made of the same material.

8. The display panel according to claim 5, wherein the touch insulating layer and the first spacing layer are located on the same layer and are made of the same material, and the second touch electrode layer and the first metal layer are located on the same layer and are made of the same material.

9. The display panel of claim 3, wherein the display substrate further comprises:

wherein the pin comprises:

10. The display panel of claim 9, wherein the display substrate further comprises:

wherein the pin further comprises:

11. The display panel of claim 10, wherein the display substrate further comprises:

12. The display panel of claim 11, wherein the display substrate further comprises:

13. A display device, comprising:

the display panel according to any one of claims 1 to 12.