CN115835691A

CN115835691A - Substrate, display panel and display device comprising same

Info

Publication number: CN115835691A
Application number: CN202211121031.3A
Authority: CN
Inventors: 张银洙; S·崔; 奇男
Original assignee: LG Display Co Ltd
Current assignee: LG Display Co Ltd
Priority date: 2021-09-15
Filing date: 2022-09-15
Publication date: 2023-03-21
Also published as: US20230083578A1; KR20230040134A

Abstract

A substrate, a display panel and a display device including the display panel are provided. The present disclosure provides a display panel and a display device including the same, the display panel including: a first optoelectronic device located at a lower portion or a lower portion of the display panel and overlapping at least a portion of a first optical area included in a display area; a first substrate disposed in at least a portion of the non-optical region; a second substrate disposed on the first substrate; a third substrate disposed in the first optical zone and having a higher transmittance than the first and second substrates; and a bonding layer disposed on at least one surface of the third substrate.

Description

Substrate, display panel and display device comprising same

Technical Field

The present disclosure relates to an electronic device, and more particularly, to a display panel and a display device including the same.

Background

As display technology advances, display devices may provide increased functions such as an image capturing function, a sensing function, and the like, as well as an image display function. For this reason, the display device needs to include an optical electronic device (also referred to as a light detector, a light receiver, or a light sensing device), such as a camera and/or a sensor for detecting an image, or the like.

In order to receive light passing through the front surface of the display device, it is desirable that the opto-electronic devices be located in an area of the display device that is capable of advantageously receiving or detecting incident light from the front surface. Therefore, in such typical display devices, a camera (e.g., a camera lens) or/and a sensor for detecting an image are generally located in front of the display device so as to be effectively exposed to incident light. According to such an embodiment, in order to mount the camera and/or the sensor, an enlarged bezel of the display device is designed, or a notch or a hole is formed in a display area of a display panel of the display device.

In view of such circumstances, the display device is required to have a higher transmittance to perform a desired function even when an optical electronic device (e.g., a camera and/or a sensor, etc.) that receives or detects incident light and performs a predetermined function is provided in the display device.

Disclosure of Invention

The present inventors have studied a technique for arranging one or more opto-electronic devices such as cameras and/or sensors in a display device without reducing the area of the display area of the associated display panel. Through such research, the inventors have invented a display panel and a display device having a light transmission structure, in which an optoelectronic device can normally receive or detect light even when the optoelectronic device is located below a display area of the display panel and thus is not exposed in a front surface of the display device.

Further, the inventors have invented a display panel and a display device having a structure having high transmittance and excellent heat resistance in a region where an optoelectronic device is located, and further causing no process defects even in a subsequent process.

Embodiments of the present disclosure provide a display panel and a display device capable of reducing a non-display area of the display panel by disposing an optical electronic device such as a camera and/or a sensor, etc. below or at a lower portion of a display area of the display panel and not exposing the optical electronic device in a front surface of the display panel.

Embodiments of the present disclosure provide a display panel and a display device having a light transmission structure for enabling an optoelectronic device below or at a lower portion of a display area of the display panel to normally receive light transmitted through the display panel.

Embodiments of the present disclosure provide a display panel and a display device capable of normally performing display driving in an optical region that is included in a display region of the display panel and overlaps with an optical electronic device.

According to an aspect of the present disclosure, there is provided a display panel and a display device including: a display area including a first optical area including a plurality of light emitting areas and a plurality of first transmission areas, and a non-optical area outside the first optical area and including a plurality of light emitting areas; a non-display area; and a first optoelectronic device located at a lower portion or a lower portion of the display panel and overlapping at least a portion of the first optical area included in the display area, the display panel including: a first substrate disposed on at least a portion of the non-optical area; a second substrate disposed on the first substrate; a third substrate disposed in the first optical area and having a higher transmittance than the first and second substrates; and a bonding layer provided on at least one surface or part of the third substrate.

Embodiments of the present disclosure may provide a display panel and a display device including the same capable of reducing a non-display area of the display panel and not exposing an optical electronic device such as a camera and/or a sensor in a front surface of the display panel by disposing the optical electronic device below or at a lower portion of a display area of the display panel.

Embodiments of the present disclosure may provide a display panel having a light-transmitting structure for enabling an optoelectronic device at a lower portion or below a display area of the display panel to normally receive light transmitted through the display panel, and a display device including the same.

Embodiments of the present disclosure may provide a display panel capable of normally performing display driving in an optical region that is included in a display region of the display panel and overlaps with an optical electronic device, and a display device including the display panel.

Embodiments of the present disclosure may provide a display panel having a structure having high transmittance and excellent heat resistance in a region where an optoelectronic device is located, and further causing no process defects even in a subsequent process, and a display device including the same.

Drawings

The accompanying drawings, which are included to provide a further understanding of the disclosure and are incorporated in and constitute a part of this disclosure, illustrate aspects of the disclosure and together with the description serve to explain the principles of the disclosure. In the drawings:

fig. 1A, 1B, and 1C are plan views illustrating a display device according to aspects of the present disclosure;

fig. 2 illustrates a system configuration of a display device according to an aspect of the present disclosure;

FIG. 3 illustrates an equivalent circuit of a sub-pixel in a display panel in accordance with aspects of the present disclosure;

fig. 4 illustrates an arrangement of sub-pixels included in three regions among a display region of a display panel according to an aspect of the present disclosure;

fig. 5A illustrates an arrangement of signal lines in each of a first optical region and a non-optical region in a display panel according to aspects of the present disclosure;

fig. 5B illustrates an arrangement of signal lines in each of the second optical region and the non-optical region in the display panel according to aspects of the present disclosure;

fig. 6 to 8 are cross-sectional views of a non-optical area, a first optical area, and a second optical area included in a display area of a display panel according to an aspect of the present disclosure;

FIG. 9 is a cross-sectional view in an outer edge of a display panel according to aspects of the present disclosure;

fig. 10-17 illustrate a process of forming a substrate in a display device according to aspects of the present disclosure; and

fig. 18 shows the transmittance of light for each wavelength in the embodiment and the comparative examples 1, 2 in the display device according to the aspect of the present disclosure.

Detailed Description

In the following description of examples or embodiments of the present disclosure, reference is made to the accompanying drawings, in which is shown by way of illustration specific examples or embodiments that may be practiced, and in which the same reference numerals and symbols may be used to designate the same or similar components, even though they are shown in different drawings from each other. Furthermore, in the following description of examples or embodiments of the present disclosure, a detailed description of known functions and components incorporated herein will be omitted when it is determined that such description may make the subject matter in some embodiments of the present disclosure rather unclear. Terms such as "comprising," having, "" including, "" constituting, "" composing, "and" forming, "as used herein, are generally intended to allow for the addition of other components unless such terms are used in conjunction with the term" only. As used herein, the singular forms are intended to include the plural forms unless the context clearly indicates otherwise.

Terms such as "first," "second," "a," "B," "a" or "(B)" may be used herein to describe elements of the disclosure. Each of these terms is not intended to define the nature, order, sequence or number of elements, etc., but rather is intended to distinguish the corresponding element from other elements.

When it is mentioned that a first element is "connected or coupled", "contacted or overlapped" with a second element, etc., it is to be understood that not only the first element may be "directly connected or coupled" or "directly contacted or overlapped" with the second element, but also a third element may be "interposed" between the first and second elements, or the first and second elements may be "connected or coupled", "contacted or overlapped" with each other via a fourth element, etc. Here, the second element may be included in at least one of two or more elements that are "connected or coupled", "contacted or overlapped" with each other, etc.

When time-related terms (e.g., "after," "next," "before," etc.) are used to describe a process or operation of an element or configuration, or a flow or step in an operation, process, manufacturing method, these terms may be used to describe non-sequential or non-sequential process or operation, unless the terms "directly" or "immediately" are used simultaneously.

In addition, when referring to any dimension, relative dimension, or the like, a numerical value or corresponding information (e.g., level, range, etc.) of an element or feature should be considered to include a tolerance or error range that may be caused by various factors (e.g., process factors, internal or external influences, noise, etc.) even if the relevant description is not specified. Furthermore, the term "can" fully encompasses all of the meanings of the term "can".

Hereinafter, various embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

Fig. 1A, 1B, and 1C are plan views illustrating a display device 100 according to aspects of the present disclosure.

Referring to fig. 1A, 1B, and 1C, a display device 100 according to an aspect of the present disclosure may include a display panel 110 for displaying an image and one or more optoelectronic devices (11, 12).

The display panel 110 may include a display area DA displaying an image and a non-display area NDA not displaying an image.

A plurality of sub-pixels may be arranged in the display area DA, and several types of signal lines for driving the plurality of sub-pixels may be arranged in the display area DA.

The non-display area NDA may refer to an area other than the display area DA. Several types of signal lines may be provided in the non-display area NDA, and several types of driving circuits may be connected to the several types of signal lines. At least a portion of the non-display area NDA may be bent to be invisible from the front of the display panel, or may be covered by the display panel 110 or a case (not shown) of the display device 100. The non-display area NDA may also be referred to as a bezel or a bezel area.

Referring to fig. 1A, 1B, and 1C, in a display device 100 according to an aspect of the present disclosure, one or more optoelectronic devices (11, 12) may be located below or in a lower portion (a side opposite to a viewing surface of the display panel 110) of the display panel 110.

Light may enter the front surface (viewing surface) of the display panel 110, pass through the display panel 110, and reach one or more optoelectronic devices (11, 12) located below or in a lower portion (side opposite the viewing surface) of the display panel 110.

One or more opto-electronic devices (11, 12) may receive or detect light transmitted through the display panel 110 and perform a predetermined function based on the received light. For example, the one or more opto-electronic devices (11, 12) may comprise one or more of an image capture device such as a camera (image sensor) and a sensor such as a proximity sensor and/or an illuminance sensor.

Referring to fig. 1A, 1B, and 1C, in some embodiments, the display area DA of the display panel 110 may include one or more optical areas (OA 1, OA 2) and a non-optical area NA.

Referring to fig. 1A, 1B and 1C, the one or more optical areas (OA 1, OA 2) may be one or more areas overlapping with the one or more opto-electronic devices (11, 12).

According to the example of fig. 1A, the display area DA may include the first optical area OA1 and the non-optical area NA. In some embodiments, at least a portion of the first optical area OA1 may overlap the first opto-electronic device 11.

According to the example of fig. 1B, the display area DA may include a first optical area OA1, a second optical area OA2, and a non-optical area NA. In the example of fig. 1B, at least a portion of the non-optical area NA may be present between the first optical area OA1 and the second optical area OA2. In some embodiments, at least a portion of the first optical area OA1 may overlap the first opto-electronic device 11 and at least a portion of the second optical area OA2 may overlap the second opto-electronic device 12.

According to the example of fig. 1C, the display area DA may include the first optical area OA1, the second optical area OA2, and the non-optical area NA. In the example of fig. 1C, the non-optical area NA may not exist between the first optical area OA1 and the second optical area OA2. For example, the first optical area OA1 and the second optical area OA2 may contact each other. In some embodiments, at least a portion of the first optical area OA1 may overlap the first opto-electronic device 11 and at least a portion of the second optical area OA2 may overlap the second opto-electronic device 12.

It is necessary to form both the image display structure and the light transmission structure in one or more optical areas (OA 1, OA 2). In some embodiments, since one or more optical regions (OA 1, OA 2) are one or more portions of the display region DA, it is necessary to provide sub-pixels for displaying an image in the one or more optical regions (OA 1, OA 2). Further, in order to enable light to transmit one or more optical areas (OA 1, OA 2), a light transmission structure needs to be formed in the one or more optical areas (OA 1, OA 2).

According to the above-described embodiment, although one or more optoelectronic devices (11, 12) are actually required to receive or detect light, the one or more optoelectronic devices (11, 12) are sometimes located on the back side of the display panel 110 (below or in the lower portion of the display panel 110, i.e., the side opposite to the viewing surface), and therefore, light that has been transmitted through the display panel 110 can be received.

For example, one or more of the optoelectronic devices (11, 12) may not be exposed in the front surface (viewing surface) of the display panel 110. Thus, when a user views the front face of the display device 100, one or more of the opto-electronic devices (11, 12) are positioned so as to be invisible to the user.

In one embodiment, the first opto-electronic device 11 may be a camera and the second opto-electronic device 12 may be a sensor such as a proximity sensor and/or an illuminance sensor, etc. For example, the sensor may be an infrared sensor capable of detecting infrared rays.

In another embodiment, the first opto-electronic device 11 may be a sensor and the second opto-electronic device 12 may be a camera.

Hereinafter, for convenience of description, embodiments will be discussed in which the first opto-electronic device 11 is a camera, and the second opto-electronic device 12 is a sensor such as a proximity sensor, an illuminance sensor, an infrared sensor, or the like. For example, the camera may be a camera lens, an image sensor, or a unit including at least one of the camera lens and the image sensor.

In an example where the first opto-electronic device 11 is a camera, the camera may be located at the back of the display panel 110 (in a lower part or a lower part of the display panel 110) and be a front camera capable of capturing an object or an image in a front direction of the display panel 110. Accordingly, the user may capture an image or an object invisible on the viewing surface through the camera while viewing the viewing surface of the display panel 110.

Although the non-optical area NA and the one or more optical areas (OA 1, OA 2) included in the display area DA in each of fig. 1A to 1C are areas where an image can be displayed, the non-optical area NA is an area where a light transmission structure is not required to be formed, the one or more optical areas (OA 1, OA 2) are areas where a light transmission structure is required to be formed.

Accordingly, one or more optical areas (OA 1, OA 2) may have a transmittance greater than or equal to a predetermined level (i.e., a relatively high transmittance), and the non-optical area NA may have no light transmittance or a transmittance less than the predetermined level (i.e., a relatively low transmittance).

For example, the one or more optical areas (OA 1, OA 2) may have different resolutions from the non-optical area NA, a sub-pixel arrangement structure, a number of sub-pixels per unit area, an electrode structure, a line structure, an electrode arrangement structure, and/or a line arrangement structure, and the like.

In one embodiment, the number of sub-pixels per unit area in the one or more optical areas (OA 1, OA 2) may be less than the number of sub-pixels per unit area in the non-optical area NA. For example, the resolution of the one or more optical zones (OA 1, OA 2) may be lower than the resolution of the non-optical zone NA. Here, the number of sub-pixels per unit area may be a unit for measuring resolution, for example, referred to as a Pixel Per Inch (PPI), which represents the number of pixels within 1 inch.

In one embodiment, in each of fig. 1A to 1C, the number of sub-pixels per unit area in the first optical area OA1 may be less than the number of sub-pixels per unit area in the non-optical area NA. In one embodiment, in each of fig. 1B and 1C, the number of sub-pixels per unit area in the second optical area OA2 may be greater than or equal to the number of sub-pixels per unit area in the first optical area OA1.

In each of fig. 1A to 1C, the first optical area OA1 may have various shapes such as a circle, an ellipse, a quadrangle, a hexagon, an octagon, etc. In each of fig. 1B to 1C, the second optical area OA2 may have various shapes such as a circle, an ellipse, a quadrangle, a hexagon, an octagon, and the like. The first and second optical areas OA1 and OA2 may have the same shape or different shapes.

Referring to fig. 1C, in an example in which the first and second optical areas OA1 and OA2 contact each other, the entire optical area including the first and second optical areas OA1 and OA2 may also have various shapes such as a circle, an ellipse, a quadrangle, a hexagon, an octagon, and the like.

Hereinafter, for convenience of description, discussion will be made based on an embodiment in which each of the first and second optical areas OA1 and OA2 has a circular shape.

Here, the display device 100 having a structure in which the first opto-electronic device 11 positioned to be covered under the display panel 110 or in the lower portion of the display panel 110 without being exposed to the outside according to aspects of the present disclosure is a camera may be referred to as a display (or display device) to which an under-display camera (UDC) technology is applied.

The display device 100 according to this configuration may have an advantage of preventing the size of the display area DA from being reduced because it is not necessary to form a recess or a camera hole for exposing the camera in the display panel 110.

Since it is not necessary to form a recess or a camera hole for camera exposure in the display panel 110, the display device 100 may have further advantages of reducing the size of the bezel area and improving the degree of freedom of design (since such a restriction on design is eliminated).

Although according to aspects of the present disclosure, one or more opto-electronic devices (11, 12) are positioned to be covered under the back of the display panel 110 (in the lower or lower portion of the display panel 110), i.e., hidden from exposure to the outside, in the display device 100, it is desirable that the one or more opto-electronic devices (11, 12) be capable of receiving or detecting light for normally performing a predetermined function.

Further, in the display device 100 according to an aspect of the present disclosure, although one or more opto-electronic devices (11, 12) are positioned to be covered under the back of the display panel 110 (under the display panel 110 or in a lower portion of the display panel 110) and positioned to overlap the display area DA, it is necessary to normally perform image display in one or more optical areas (OA 1 ) overlapping the one or more opto-electronic devices (11, 12) in the area DA.

Fig. 2 illustrates a system configuration of the display apparatus 100 according to an aspect of the present disclosure.

Referring to fig. 2, the display device 100 may include a display driving circuit and a display panel 110 as components for displaying an image.

The display driving circuit is a circuit for driving the display panel 110, and may include a data driving circuit 220, a gate driving circuit 230, a display controller 240, and the like.

The display panel 110 may include a display area DA displaying an image and a non-display area NDA not displaying an image. The non-display area NDA may be an area other than the display area DA, and may also be referred to as an edge area or a bezel area. All or a portion of the non-display area NDA may be an area visible from the front surface of the display device 100 or may be an area not visible from the front surface of the display device 100 due to bending of the corresponding portion.

The display panel 110 may include a substrate SUB and a plurality of subpixels SP disposed on the substrate SUB. The display panel 110 may further include various types of signal lines to drive the plurality of subpixels SP.

The display device 100 according to an aspect of the present disclosure may be a liquid crystal display device or the like, or a self-light emitting display device that emits light from the display panel 110 itself. In an example in which the display device 100 according to an aspect of the present disclosure is a self-light emitting display device, each of the plurality of sub-pixels SP may include a light emitting element.

In one embodiment, the display device 100 according to an aspect of the present disclosure may be an organic light emitting display device in which a light emitting element is implemented using an Organic Light Emitting Diode (OLED). For another embodiment, the display device 100 according to aspects of the present disclosure may be an inorganic light emitting display device in which a light emitting element is implemented using a light emitting diode based on an inorganic material. In still another embodiment, the display device 100 according to an aspect of the present disclosure may be a quantum dot display device in which a light emitting element is realized using quantum dots as a self-luminous semiconductor crystal.

The structure of each of the plurality of subpixels SP may vary according to the type of the display device 100. In an example where the display device 100 is a self-light emitting display device including self-light emitting sub-pixels SP, each sub-pixel SP may include a self-light emitting element, one or more transistors, and one or more capacitors.

The various types of signal lines disposed in the display device 100 may include, for example, a plurality of data lines DL for carrying data signals (also referred to as data voltages or image signals), a plurality of gate lines GL for carrying gate signals (also referred to as scan signals), and the like.

The plurality of data lines DL and the plurality of gate lines GL may cross each other. Each of the plurality of data lines DL may be disposed to extend in the first direction. Each of the gate lines GL of the plurality of gate lines GL may be disposed to extend in the second direction.

For example, the first direction may be a column direction or a vertical direction, and the second direction may be a row direction or a horizontal direction. In another example, the first direction may be a row direction and the second direction may be a column direction.

The data driving circuit 220 is a circuit for driving the plurality of data lines DL, and may supply a data signal to the plurality of data lines DL. The gate driving circuit 230 is a circuit for driving a plurality of gate lines GL, and may supply gate signals to the plurality of gate lines GL.

The display controller 240 is a device for controlling the data driving circuit 220 and the gate driving circuit 230, and may control driving timings of the plurality of data lines DL and driving timings of the plurality of gate lines GL.

The display controller 240 may provide the data driving control signal DCS to the data driving circuit 220 to control the data driving circuit 220 and the gate driving control signal GCS to the gate driving circuit 230 to control the gate driving circuit 230.

The display controller 240 may receive input image Data from the host system 250 and provide the image Data to the Data driving circuit 220 based on the input image Data.

The data driving circuit 220 may supply the data signal to the plurality of data lines DL according to driving timing control of the display controller 240.

The Data driving circuit 220 may receive digital image Data from the display controller 240, convert the received image Data into analog Data signals, and supply the resultant analog Data signals to the plurality of Data lines DL.

The gate driving circuit 230 may supply gate signals to the plurality of gate lines GL according to timing control of the display controller 240. The gate driving circuit 230 may receive a first gate voltage corresponding to an on-level voltage and a second gate voltage corresponding to an off-level voltage together with various gate driving control signals GCS, generate gate signals, and supply the generated gate signals to the plurality of gate lines GL.

In some embodiments, the data driving circuit 220 may be connected to the display panel 110 in a Tape Automated Bonding (TAB) type, or connected to a conductive pad, such as a bonding pad, of the display panel 110 in a Chip On Glass (COG) type or a Chip On Panel (COP) type, or connected to the display panel 110 in a Chip On Film (COF) type.

In some embodiments, the gate driving circuit 230 may be connected to the display panel 110 in a Tape Automated Bonding (TAB) type, or connected to a conductive pad, such as a bonding pad, of the display panel 110 in a Chip On Glass (COG) type or a Chip On Panel (COP) type, or connected to the display panel 110 in a Chip On Film (COF) type. In another embodiment, the gate driving circuit 230 may be disposed in a gate-in-panel (GIP) type in the non-display area NDA of the display panel 110. The gate driving circuit 230 may be disposed on or above the substrate, or connected to the substrate. That is, in the case of the GIP type, the gate driving circuit 230 may be disposed in the non-display region NDA of the substrate. In the case of a Chip On Glass (COG) type, a Chip On Film (COF) type, or the like, the gate driving circuit 230 may be connected to a substrate.

At least one of the data driving circuit 220 and the gate driving circuit 230 may be disposed in the display area DA of the display panel 110. For example, at least one of the data driving circuit 220 and the gate driving circuit 230 may be disposed not to overlap the sub-pixels SP, or disposed to overlap one or more or all of the sub-pixels SP.

The data driving circuit 220 may also be located only on one side or a portion (e.g., an upper edge or a lower edge) of the display panel 110, but is not limited thereto. In some embodiments, the data driving circuit 220 may be located in, but not limited to, two sides or portions (e.g., upper and lower edges) of the display panel 110 or at least two of four sides or portions (e.g., upper, lower, left and right edges) of the display panel 110 according to a driving scheme, a panel design scheme, and the like.

The gate driving circuit 230 may be located at only one side or a portion (e.g., a left edge or a right edge) of the display panel 110. In some embodiments, the gate driving circuit 230 may be connected to or located at two sides or portions (e.g., left and right edges) of the display panel 110, or at least two of four sides or portions (e.g., upper, lower, left and right edges) of the display panel 110, according to a driving scheme, a panel design scheme, or the like.

The display controller 240 may be implemented in a component separate from the data driving circuit 220, or may be integrated with the data driving circuit 220 and thus implemented in an integrated circuit.

The display controller 240 may be a timing controller used in a typical display technology, or may be a controller or control device capable of additionally performing other control functions in addition to the functions of a typical timing controller. In some embodiments, the display controller 140 may be a different controller or control device than the timing controller, or a circuit or component included in the controller or control device. Display controller 240 may be implemented with various circuits or electronic components such as an Integrated Circuit (IC), a Field Programmable Gate Array (FPGA), an Application Specific Integrated Circuit (ASIC), and/or a processor, among others.

The display controller 240 may be mounted on a printed circuit board and/or a flexible printed circuit, etc., and electrically connected to the gate driving circuit 230 and the data driving circuit 220 through the printed circuit board and/or the flexible printed circuit, etc.

The display controller 240 may send signals to and receive signals from the data driving circuitry 220 via one or more predefined interfaces. In some embodiments, such interfaces may include a Low Voltage Differential Signaling (LVDS) interface, an EPI interface, a serial peripheral interface (SP), and the like.

In some embodiments, to further provide a touch sensing function as well as an image display function, the display device 100 may include at least one touch sensor and a touch sensing circuit capable of detecting whether a touch event occurs by a touch object such as a finger, a pen, or the like by sensing the touch sensor or capable of detecting a corresponding touch position.

The touch sensing circuit may include a touch driving circuit 260 capable of generating and providing touch sensing data by driving and sensing the touch sensor, a touch controller 270 capable of detecting the occurrence of a touch event or detecting a touch position using the touch sensing data, and the like.

The touch sensor may include a plurality of touch electrodes. The touch sensor may further include a plurality of touch lines for electrically connecting the plurality of touch electrodes to the touch driving circuit 260.

The touch sensor may be implemented as a touch panel or in the form of a touch panel outside the display panel 110, or implemented inside the display panel 110. When the touch sensor is implemented as a touch panel or in the form of a touch panel outside the display panel 110, such a touch sensor is referred to as an additional type. When additional types of touch sensors are provided, the touch panel and the display panel 110 may be separately manufactured and coupled during an assembly process. Additional types of touch panels can include a touch panel substrate and a plurality of touch electrodes on the touch panel substrate.

When the touch sensor is implemented inside the display panel 110, the touch sensor may be disposed on the substrate SUB together with signal lines and electrodes related to display driving during a process of manufacturing the display panel 110.

The touch driving circuit 260 may provide a touch driving signal to at least one of the plurality of touch electrodes and sense the at least one of the plurality of touch electrodes to generate touch sensing data.

The touch sensing circuit may perform touch sensing using a self capacitance sensing method or a mutual capacitance sensing method.

When the touch sensing circuit performs touch sensing in the self-capacitance sensing method, the touch sensing circuit may perform touch sensing based on a capacitance between each touch electrode and a touch object (e.g., a finger, a pen, etc.).

According to the self-capacitance sensing method, each of the plurality of touch electrodes may serve as both a driving touch electrode and a sensing touch electrode. The touch driving circuit 260 may drive all or one or more touch electrodes of the plurality of touch electrodes and sense all or one or more touch electrodes of the plurality of touch electrodes.

When the touch sensing circuit performs touch sensing in the mutual capacitance sensing method, the touch sensing circuit may perform touch sensing based on capacitance between touch electrodes.

According to the mutual capacitance sensing method, a plurality of touch electrodes are divided into driving touch electrodes and sensing touch electrodes. The touch driving circuit 260 may drive the driving touch electrodes and sense the sensing touch electrodes.

The touch driving circuit 260 and the touch controller 270 included in the touch sensing circuit may be implemented in separate devices or in a single device. Further, the touch driving circuit 260 and the data driving circuit 220 may be implemented in separate devices or in a single device.

The display device 100 may further include a power supply circuit for supplying various types of power to the display driving circuit and/or the touch sensing circuit.

The display device 100 according to aspects of the present disclosure may be a mobile terminal such as a smart phone, a tablet computer, or the like, or a monitor, a Television (TV), or the like. Such devices may be of various types, sizes and shapes. The display device 100 according to the embodiment of the present disclosure is not limited thereto, and includes various types, sizes, and shapes of displays for displaying information or images.

As described above, the display area DA of the display panel 110 may include the non-optical area NA and one or more optical areas (OA 1, OA 2), for example, as shown in fig. 1A to 1C.

The non-optical area NA and the one or more optical areas (OA 1, OA 2) are areas where an image can be displayed. However, the non-optical area NA is an area where the light transmission structure is not required to be implemented, and the one or more optical areas OA1, OA2 are areas where the light transmission structure is required to be implemented.

As discussed above with respect to the example of fig. 1A to 1C, although the display area DA of the display panel 110 may include one or more optical areas (OA 1, OA 2) in addition to the non-optical area NA, for convenience of description, it is assumed in the following discussion that the display area DA includes the first and second optical areas (OA 1, OA 2) and the non-optical area NA, and the non-optical area NA thereof includes the non-optical area NA in fig. 1A to 1C, and the first and second optical areas (OA 1, OA 2) thereof include the first optical area OA1 in fig. 1A to 1C and the second optical area OA2 in fig. 1B and 1C, respectively, unless explicitly stated otherwise.

Fig. 3 illustrates an equivalent circuit of the sub-pixel SP in the display panel 110 according to an aspect of the present disclosure.

Each of the sub-pixels SP disposed in the non-optical area NA, the first optical area OA1 and the second optical area OA2 included in the display area DA of the display panel 110 may include a light emitting element ED, a driving transistor DRT for driving the light emitting element ED, a scan transistor SCT for transmitting a data voltage VDATA to a first node N1 of the driving transistor DRT, a storage capacitor Cst for maintaining the voltage at an approximately constant level during one frame, and the like.

The driving transistor DRT may include a first node N1 to which the data voltage is applied, a second node N2 electrically connected to the light emitting element ED, and a third node N3 to which the driving voltage ELVDD is applied through a driving voltage line DVL. In the driving transistor DRT, the first node N1 may be a gate node, the second node N2 may be a source node or a drain node, and the third node N3 may be a drain node or a source node.

The light emitting element ED may include an anode electrode AE, a light emitting layer EL, and a cathode electrode CE. The anode electrode AE may be a pixel electrode disposed in each of the sub-pixels SP, and may be electrically connected to the second node N2 of the driving transistor DRT of each of the sub-pixels SP. The cathode electrode CE may be a common electrode commonly disposed in the plurality of sub-pixels SP, and a base voltage ELVSS such as a low-level voltage may be applied to the cathode electrode CE.

For example, the anode electrode AE may be a pixel electrode and the cathode electrode CE may be a common electrode. In another example, the anode electrode AE may be a common electrode and the cathode electrode CE may be a pixel electrode. For convenience of description, in the following discussion, it is assumed that the anode electrode AE is a pixel electrode and the cathode electrode CE is a common electrode unless otherwise explicitly stated.

The light emitting element ED may be, for example, an Organic Light Emitting Diode (OLED), an inorganic light emitting diode, a quantum dot light emitting element, or the like. In an example where an organic light emitting diode is used as the light emitting element ED, the light emitting layer EL included in the light emitting element ED may include an organic light emitting layer containing an organic material.

The SCAN transistor SCT may be turned on and off by a SCAN signal SCAN which is a gate signal applied through the gate line GL, and electrically connected between the first node N1 of the driving transistor DRT and the data line DL.

The storage capacitor Cst may be electrically connected between the first node N1 and the second node N2 of the driving transistor DRT.

As shown in fig. 3, each sub-pixel SP may include two transistors (2t.

The storage capacitor Cst may be an external capacitor intentionally designed to be located outside the driving transistor DRT, rather than an internal capacitor such as a parasitic capacitor (e.g., cgs, cgd) that may exist between the first node N1 and the second node N2 of the driving transistor DRT.

Each of the driving transistor DRT and the scan transistor SCT may be an n-type transistor or a p-type transistor.

Since the circuit element (specifically, the light emitting element ED) in each sub-pixel SP is easily affected by external moisture or oxygen, an encapsulation layer ENCAP may be provided in the display panel 110 to prevent external moisture or oxygen from penetrating into the circuit element (specifically, the light emitting element ED). The encapsulation layer ENCAP may be disposed to cover the light emitting element ED.

Fig. 4 illustrates an arrangement of the subpixels SP included in three areas (NA, OA1, and OA 2) in the display area DA of the display panel 110 according to an aspect of the present disclosure.

Referring to fig. 4, a plurality of sub-pixels SP may be disposed in each of the non-optical area NA, the first optical area OA1 and the second optical area OA2 included in the display area DA.

The plurality of sub-pixels SP may include, for example, a red sub-pixel (red SP) emitting red light, a green sub-pixel (green SP) emitting green light, and a blue sub-pixel (blue SP) emitting blue light.

Accordingly, each of the non-optical area NA, the first optical area OA1 and the second optical area OA2 may include one or more light emitting areas EA of one or more red sub-pixels (red SP), one or more light emitting areas EA of one or more green sub-pixels (green SP), and one or more light emitting areas EA of one or more blue sub-pixels (blue SP).

Referring to fig. 4, the non-optical area NA may not include a light transmitting structure but may include a light emitting area EA.

However, the first and second optical areas OA1 and OA2 need to include both the light emitting area EA and the light transmitting structure.

Accordingly, the first optical area OA1 may include the light emitting area EA and the first transmission area TA1, and the second optical area OA2 may include the light emitting area EA and the second transmission area TA2.

The light emitting area EA and the transmission areas (TA 1, TA 2) may be different depending on whether or not transmission of light is allowed. That is, the light emitting region EA may be a region that does not allow light to transmit, and the transmission regions TA1, TA2 may be regions that allow light to transmit.

The light emitting area EA and the transmissive areas TA1, TA2 may also differ depending on whether or not the specific metal layer CE is included. For example, the cathode electrode CE may be disposed in the light emitting area EA, and the cathode electrode CE may not be disposed in the transmissive area (TA 1, TA 2). Further, the light shielding layer may be provided in the light emitting area EA, and the light shielding layer may not be provided in the transmissive area (TA 1, TA 2).

Since the first optical area OA1 includes the first transmission area TA1 and the second optical area OA2 includes the second transmission area TA2, both the first optical area OA1 and the second optical area OA2 are areas through which light may pass.

In one embodiment, the transmittance (transmittance) of the first optical area OA1 and the transmittance (transmittance) of the second optical area OA2 may be substantially equal.

For example, the first and second transmission areas TA1 and TA2 of the first and second optical areas OA1 and OA2 may have substantially equivalent shapes or sizes. In another example, even when the first and second transmission areas TA1 and TA2 of the first and second optical areas OA1 and OA2 have different shapes or sizes, the ratio of the first and second transmission areas TA1 and TA2 to the first and second optical areas OA1 and OA2 may be substantially equal.

In another embodiment, the transmittance (transmittance) of the first optical area OA1 and the transmittance (transmittance) of the second optical area OA2 may be different.

For example, the first transmission area TA1 of the first optical area OA1 and the second transmission area TA2 of the second optical area OA2 may have different shapes or sizes. In another example, even when the first and second transmission areas TA1 and TA2 of the first and second optical areas OA1 and OA2 have substantially equivalent shapes or sizes, the ratio of the first and second transmission areas TA1 and TA2 to the first and second optical areas OA1 and OA2 may be different from each other.

For example, in a case where the first optoelectronic device 11 overlapping the first optical area OA1 is a camera and the second optoelectronic device 12 overlapping the second optical area OA2 is a sensor for detecting an image, the camera may require a larger amount of light than the sensor.

Accordingly, the transmittance (transmittance) of the first optical area OA1 may be greater than the transmittance (transmittance) of the second optical area OA2.

For example, the first transmission area TA1 of the first optical area OA1 may have a size greater than the second transmission area TA2 of the second optical area OA2. In another example, even when the first and second transmission areas TA1 and TA2 of the first and second optical areas OA1 and OA2 have substantially equivalent sizes, a ratio of the first transmission area TA1 to the first optical area OA1 may be greater than a ratio of the second transmission area TA2 to the second optical area OA2.

For convenience of description, the following discussion is made based on an embodiment in which the transmittance (transmittance) of the first optical area OA1 is greater than the transmittance (transmittance) of the second optical area OA2.

Further, the transmission regions (TA 1, TA 2) as shown in fig. 4 may be referred to as transparent regions, and the term transmittance may be referred to as transparency.

Further, in the following discussion, as shown in fig. 4, it is assumed that the first and second optical areas OA1 and OA2 are located in an upper edge of the display area DA of the display panel 110, and the first and second optical areas OA1 and OA2 are disposed horizontally adjacent to each other, for example, in a direction in which the upper edge extends, unless otherwise specifically noted. Embodiments of the present disclosure are not limited thereto. For example, the first and second optical areas OA1 and OA2 may be located in any position of the display area DA of the display panel 110. For example, the first and second optical areas OA1 and OA2 may be located in any position of the upper edge, the lower edge, the left edge, the right edge, and the central area of the display area DA of the display panel 110. For example, the first and second optical areas OA1 and OA2 may be arranged in an arbitrary direction in the display panel 110.

Referring to fig. 4, a horizontal display region in which the first and second optical regions OA1 and OA2 are disposed is referred to as a first horizontal display region HA1, and another horizontal display region in which the first and second optical regions OA1 and OA2 are not disposed is referred to as a second horizontal display region HA2.

Referring to fig. 4, the first horizontal display area HA1 may include a portion of the non-optical area NA, the first optical area OA1, and the second optical area OA2. The second horizontal display area HA2 may include only another portion of the non-optical area NA.

Fig. 5A illustrates an arrangement of signal lines in each of the first optical area OA1 and the non-optical area NA of the display panel 110 according to an aspect of the present disclosure, and fig. 5B illustrates an arrangement of signal lines in each of the second optical area OA2 and the non-optical area NA of the display panel 110 according to an aspect of the present disclosure.

The first horizontal display area HA1 shown in fig. 5A and 5B is a portion of the first horizontal display area HA1 of the display panel 110, and the second horizontal display area HA2 thereof is a portion of the second horizontal display area HA2 of the display panel 110.

The first optical area OA1 shown in fig. 5A is a portion of the first optical area OA1 of the display panel 110, and the second optical area OA2 shown in fig. 5B is a portion of the second optical area OA2 of the display panel 110.

Referring to fig. 5A and 5B, the first horizontal display area HA1 may include a portion of the non-optical area NA, the first optical area OA1, and the second optical area OA2. The second horizontal display area HA2 may include another portion of the non-optical area NA.

Various types of horizontal lines HL1, HL2 and various types of vertical lines VLn, VL1, VL2 may be disposed in the display panel 110.

Here, the term "horizontal" and the term "vertical" are used to refer to two directions intersecting the display panel; however, it should be noted that the horizontal direction and the vertical direction may be changed according to the viewing direction. The horizontal direction may refer to, for example, a direction in which one gate line GL is disposed to extend, and the vertical direction may refer to, for example, a direction in which one data line DL is disposed to extend. Thus, the terms horizontal and vertical are used to denote two directions.

Referring to fig. 5A and 5B, the horizontal lines disposed in the display panel 110 may include a first horizontal line HL1 disposed in the first horizontal display region HA1 and a second horizontal line HL2 disposed on the second horizontal display region HA2.

The horizontal line disposed in the display panel 110 may be a gate line GL. That is, the first and second horizontal lines HL1 and HL2 may be the gate lines GL. The gate line GL may include various types of gate lines according to the structure of one or more sub-pixels SP.

Referring to fig. 5A and 5B, the vertical lines disposed in the display panel 110 may include a general vertical line VLn disposed only in the non-optical area NA, a first vertical line VL1 passing through both the first optical area OA1 and the non-optical area NA, and a second vertical line VL2 passing through both the second optical area OA2 and the non-optical area NA.

The vertical lines provided in the display panel 110 may include data lines DL, driving voltage lines DVL, and the like, and may further include reference voltage lines, initialization voltage lines, and the like. That is, the general vertical line VLn, the first vertical line VL1, and the second vertical line VL2 may include the data line DL, the driving voltage line DVL, and the like, and may further include the reference voltage line, the initialization voltage line, and the like.

In some embodiments, it should be noted that the term "horizontal" in the second horizontal line HL2 may only mean that a signal is transmitted from the left side to the right side (or from the right side to the left side) of the display panel, and may not mean that the second horizontal line HL2 travels only in a straight line in a direct horizontal direction. For example, in fig. 5A and 5B, although the second horizontal lines HL2 are illustrated in straight lines, one or more of the second horizontal lines HL2 may include one or more bent portions or folded portions differently from the configuration thereof. Likewise, one or more of the first horizontal lines HL1 may also include one or more bent portions or folded portions.

In some embodiments, it should be noted that the term "vertical" in the general vertical line VLn may only mean that signals are transferred from the upper portion to the lower portion (or from the lower portion to the upper portion) of the display panel, and may not mean that the general vertical line VLn travels only in a straight line in a direct vertical direction. For example, in fig. 5A and 5B, although the general vertical lines VLn are illustrated as straight lines, one or more of the general vertical lines VLn may include one or more bent or folded portions differently from the configuration thereof. Likewise, one or more of the first vertical lines VL1 and one or more of the second vertical lines VL2 may also include one or more curved portions or folded portions.

Referring to fig. 5A, the first optical area OA1 included in the first horizontal display area HA1 may include a light emitting area EA and a first transmission area TA1. In the first optical area OA1, each outer area of the first transmission area TA1 may include a corresponding light emitting area EA.

Referring to fig. 5A, in order to improve the transmittance of the first optical area OA1, the first horizontal line HL1 may pass through the first optical area OA1 by avoiding the first transmissive area TA1 in the first optical area OA1.

Accordingly, each first horizontal line HL1 passing through the first optical area OA1 may include one or more curved (curved) portions or bent portions running around one or more respective outer edges of one or more of the first transmission areas TA1.

Accordingly, the first horizontal line HL1 disposed in the first horizontal display region HA1 and the second horizontal line HL2 disposed in the second horizontal display region HA2 may have different shapes or lengths. For example, the first horizontal line HL1 passing through the first optical area OA1 and the second horizontal line HL2 not passing through the first optical area OA1 may have different shapes or lengths.

Further, in order to improve the transmittance of the first optical area OA1, the first vertical lines VL1 may pass through the first optical area OA1 by avoiding the first transmissive area TA1 in the first optical area OA1.

Accordingly, each first vertical line VL1 passing through the first optical area OA1 may include one or more curved portions or bent portions running around one or more respective outer edges of one or more of the first transmission areas TA1.

Accordingly, the first vertical line VL1 passing through the first optical area OA1 and the general vertical line VLn disposed in the non-optical area NA without passing through the first optical area OA1 may have different shapes or lengths.

Referring to fig. 5A, the first transmission regions TA1 included in the first optical regions OA1 in the first horizontal display region HA1 may be arranged in an oblique direction (directional direction).

Referring to fig. 5A, in the first optical area OA1 in the first horizontal display area HA1, one or more light emitting areas EA may be disposed between two horizontally adjacent first transmission areas TA1. In the first optical area OA1 in the first horizontal display area HA1, one or more light emitting areas EA may be disposed between two vertically adjacent first transmission areas TA1.

Referring to fig. 5A, the first horizontal lines HL1 disposed in the first horizontal display area HA1, i.e., the first horizontal lines HL1 passing through the first optical areas OA1, may each include one or more curved portions or bent portions running around one or more corresponding outer edges of one or more of the first transmission areas TA1.

Referring to fig. 5B, the second optical area OA2 included in the first horizontal display area HA1 may include a light emitting area EA and a second transmission area TA2. In the second optical area OA2, each outer area of the second transmission area TA2 may include a corresponding light emitting area EA.

In one embodiment, the light emitting area EA and the second transmission area TA2 in the second optical area OA2 may have substantially equivalent positions and arrangements to the light emitting area EA and the first transmission area TA1 in the first optical area OA1 of fig. 5A.

In another embodiment, as shown in fig. 5B, the light emitting area EA and the second transmission area TA2 in the second optical area OA2 may have different positions and arrangements from the light emitting area EA and the first transmission area TA1 in the first optical area OA1 of fig. 5A.

For example, referring to fig. 5B, the second transmission areas TA2 in the second optical area OA2 may be arranged in a horizontal direction (left-to-right or right-to-left direction). The light emitting region EA may not be disposed between two second transmission regions TA2 adjacent to each other in the horizontal direction. Further, one or more of the light emitting areas EA in the second optical area OA2 may be disposed between the second transmission areas TA2 adjacent to each other in the vertical direction (up-down or down-up direction). For example, one or more light emitting areas EA may be disposed between two rows of second transmissive areas.

When passing through the second optical area OA2 and the non-optical area NA adjacent to the second optical area OA2 in the first horizontal display area HA1, the first horizontal line HL1 may have substantially the same arrangement as the first horizontal line HL1 of fig. 5A in one embodiment.

In another embodiment, as shown in fig. 5B, when the second optical area OA2 and the non-optical area NA adjacent to the second optical area OA2 are passed in the first horizontal display area HA1, the first horizontal line HL1 may have a different arrangement from the first horizontal line HL1 of fig. 5A.

This is because the light emitting area EA and the second transmission area TA2 in the second optical area OA2 of fig. 5B have different positions and arrangements from the light emitting area EA and the first transmission area TA1 in the first optical area OA1 of fig. 5A.

Referring to fig. 5B, when the first horizontal line HL1 passes through the second optical area OA2 and the non-optical area NA adjacent to the second optical area OA2 in the first horizontal display area HA1, the first horizontal line HL1 may travel in a straight line without a curved portion or a bent portion between the vertically adjacent second transmission areas TA2.

For example, one first horizontal line HL1 may have one or more curved portions or bent portions in the first optical area OA1, but may not have the curved portions or bent portions in the second optical area OA2.

In order to improve the transmittance of the second optical area OA2, the second vertical lines VL2 may pass through the second optical area OA2 by avoiding the second transmissive area TA2 in the second optical area OA2.

Accordingly, each second vertical line VL2 passing through the second optical area OA2 may include one or more curved portions or bent portions running around one or more respective outer edges of one or more of the second transmission areas TA2.

Accordingly, the second vertical line VL2 passing through the second optical area OA2 and the general vertical line VLn disposed in the non-optical area NA without passing through the second optical area OA2 may have different shapes or lengths.

As shown in fig. 5A, each or one or more of the first horizontal lines HL1 passing through the first optical areas OA1 may have one or more curved portions or bent portions running around one or more respective outer edges of one or more of the first transmission areas TA1.

Accordingly, the length of the first horizontal line HL1 passing through the first and second optical areas OA1 and OA2 may be slightly longer than the length of the second horizontal line HL2 disposed only in the non-optical area NA without passing through the first and second optical areas OA1 and OA2.

Accordingly, the resistance of the first horizontal line HL1 passing through the first and second optical areas OA1 and OA2 (referred to as a first resistance) may be slightly greater than the resistance of the second horizontal line HL2 disposed only in the non-optical area NA without passing through the first and second optical areas OA1 and OA2 (referred to as a second resistance).

Referring to fig. 5A and 5B, according to the light transmission structure, since the first optical area OA1 at least partially overlapping the first optoelectronics 11 includes the first transmission area TA1 and the second optical area OA2 at least partially overlapping the second optoelectronics 12 includes the second transmission area TA2, the first and second optical areas OA1 and OA2 may have the number of sub-pixels per unit area smaller than the non-optical area NA.

Accordingly, the number of sub-pixels connected to each or one or more of the first horizontal lines HL1 passing through the first and second optical areas OA1 and OA2 may be different from the number of sub-pixels connected to each or one or more of the second horizontal lines HL2 disposed only in the non-optical area NA and not passing through the first and second optical areas OA1 and OA2.

The number of sub-pixels connected to each or one or more of the first horizontal lines HL1 passing through the first and second optical areas OA1 and OA2 (referred to as a first number) may be less than the number of sub-pixels connected to each or one or more of the second horizontal lines HL2 disposed only in the non-optical area NA without passing through the first and second optical areas OA1 and OA2 (referred to as a second number).

The difference between the first and second numbers may vary according to a difference between the resolution of each of the first and second optical areas OA1 and OA2 and the resolution of the non-optical area NA. For example, as the difference between the resolution of each of the first and second optical areas OA1 and OA2 and the resolution of the non-optical area NA increases, the difference between the first and second numbers may increase.

As described above, since the number (first number) of sub-pixels connected to each or one or more of the first horizontal lines HL1 passing through the first and second optical areas OA1 and OA2 is less than the number (second number) of sub-pixels connected to each or one or more of the second horizontal lines HL2 disposed only in the non-optical area NA and not passing through the first and second optical areas OA1 and OA2, a region where the first horizontal line HL1 overlaps with one or more other electrodes or lines adjacent to the first horizontal line HL1 may be less than a region where the second horizontal line HL2 overlaps with one or more other electrodes or lines adjacent to the second horizontal line HL2.

Accordingly, a parasitic capacitance (referred to as a first capacitance) formed between the first horizontal line HL1 and one or more other electrodes or lines adjacent to the first horizontal line HL1 may be much smaller than a parasitic capacitance (referred to as a second capacitance) formed between the second horizontal line HL2 and one or more other electrodes or lines adjacent to the second horizontal line HL2.

Considering the magnitude relationship between the first resistance and the second resistance (the first resistance ≧ the second resistance) and the magnitude relationship between the first capacitance and the second capacitance (the first capacitance < < the second capacitance), the resistance-capacitance (RC) value (referred to as a first RC value) of the first horizontal line HL1 passing through the first optical area OA1 and the second optical area OA2 may be much smaller than the RC value (referred to as a second RC value) of the second horizontal line HL2 disposed only in the non-optical area NA without passing through the first optical area OA1 and the second optical area OA2, i.e., resulting in the first RC value < < the second RC value.

Due to such a difference (referred to as an RC load difference) between the first RC value of the first horizontal line HL1 and the second RC value of the second horizontal line HL2, a signal transmission characteristic through the first horizontal line HL1 may be different from a signal transmission characteristic through the second horizontal line HL2.

Fig. 6 to 8 are sectional views of the non-optical area NA, the first optical area OA1 and the second optical area OA2 included in the display area DA of the display panel 110 according to an aspect of the present disclosure.

Fig. 6 and 7 are sectional views of the display panel 110 in an example in which a touch sensor in the form of a touch panel is provided outside the display panel 110. Fig. 8 is a sectional view of the display panel 110 in an example in which the touch sensor TS is integrated inside the display panel 110.

Fig. 6 to 8 are sectional views of the non-optical area NA, the first optical area OA1 and the second optical area OA2 included in the display area DA.

The laminated structure of the non-optical area NA will be described with reference to fig. 6 and 7. Each of the light emitting areas EA of the first and second optical areas OA1 and OA2 may have the same laminate structure as the light emitting area EA of the non-optical area NA 1.

Referring to fig. 6 and 7, the substrate SUB may include a first substrate SUB1, an interlayer insulating layer IPD, and a second substrate SUB2. An interlayer insulating layer IPD may be interposed between the first substrate SUB1 and the second substrate SUB2. Since the substrate SUB includes the first substrate SUB1, the interlayer insulating layer IPD, and the second substrate SUB2, the substrate SUB may prevent penetration of moisture. The first substrate SUB1 and the second substrate SUB2 may be, for example, polyimide (PI) substrates. The first substrate SUB1 may be referred to as a main PI substrate, and the second substrate SUB2 may be referred to as a SUB PI substrate. Embodiments of the present disclosure are not limited thereto. For example, the substrate SUB may also include a single substrate, or three or more substrates. And other materials for the substrate are possible.

Referring to fig. 6 and 7, various types of patterns ACT, SD1, GATE for providing one or more transistors such as the driving transistor DRT, various types of insulating layers MBUF, ABUF1, ABUF2, GI, ILD1, ILD2, PAS0, and various types of metal patterns TM, GM, ML1, ML2 may be provided on or over the substrate SUB.

Referring to fig. 6 and 7, a multi-buffer layer MBUF may be disposed on the second substrate SUB2, and a first active buffer layer ABUF1 may be disposed on the multi-buffer layer MBUF.

The first and second metal layers ML1 and ML2 may be disposed on the first active buffer layer ABUF 1. The first and second metal layers ML1 and ML2 may be, for example, a light shielding layer LS for shielding light.

The second active buffer layer ABUF2 may be disposed on the first and second metal layers ML1 and ML 2. The active layer ACT of the driving transistor DRT may be disposed on the second active buffer layer ABUF 2.

The gate insulating layer GI may be disposed to cover the active layer ACT.

The GATE electrode GATE of the driving transistor DRT may be disposed on the GATE insulating layer GI. Further, the GATE material layer GM may be disposed on the GATE insulating layer GI together with the GATE electrode GATE of the driving transistor DRT at a position different from the position where the driving transistor DRT is disposed.

The first interlayer insulating layer ILD1 may be disposed to cover the GATE electrode GATE and the GATE material layer GM. The metal pattern TM may be disposed on the first interlayer insulating layer ILD 1. The metal pattern TM may be located at a position different from a position where the driving transistor DRT is formed. The second interlayer insulating layer ILD2 may be disposed to cover the metal pattern TM on the first interlayer insulating layer ILD 1.

Two first source-drain electrode patterns SD1 may be disposed on the second interlayer insulating layer ILD 2. One of the two first source-drain electrode patterns SD1 may be a source node of the driving transistor DRT, and the other may be a drain node of the driving transistor DRT.

The two first source-drain electrode patterns SD1 may be electrically connected to the first and second sides of the active layer ACT through contact holes formed in the second interlayer insulating layer ILD2, the first interlayer insulating layer ILD1, and the gate insulating layer GI, respectively.

A portion of the active layer ACT overlapping the GATE electrode GATE may serve as a channel region. One of the two first source-drain electrode patterns SD1 may be connected to a first side of the channel region of the active layer ACT, and the other of the two first source-drain electrode patterns SD1 may be connected to a second side of the channel region of the active layer ACT.

The passivation layer PAS0 may be disposed to cover the two first source-drain electrode patterns SD1. The planarization layer PLN may be disposed on the passivation layer PAS 0. The planarization layer PLN may include a first planarization layer PLN1 and a second planarization layer PLN2.

The first planarization layer PLN1 may be disposed on the passivation layer PAS 0.

The second source-drain electrode pattern SD2 may be disposed on the first planarization layer PLN 1. The second source-drain electrode pattern SD2 may be connected to one of the two first source-drain electrode patterns SD1 (corresponding to the second node N2 of the driving transistor DRT in the sub-pixel SP of fig. 3) through a contact hole formed in the first planarization layer PLN 1.

The second planarization layer PLN2 may be disposed to cover the second source-drain electrode pattern SD2. The light emitting element ED may be disposed on the second planarization layer PLN2.

According to an example laminated structure of the light emitting element ED, the anode electrode AE may be disposed on the second planarizing layer PLN2. The anode electrode AE may be electrically connected to the second source-drain electrode pattern SD2 through a contact hole formed in the second planarization layer PLN2.

The BANK portion BANK may be disposed to cover a portion of the anode electrode AE. A portion of the BANK corresponding to the emission area EA of the sub-pixel SP may be opened.

A part of the anode electrode AE may be exposed through an opening (opening portion) of the BANK. The light emitting layer EL may be located on the side surfaces of the BANK and in the opening (opening portion) of the BANK. All or at least a part of the light emitting layer EL may be positioned between the adjacent banks.

In the opening of the BANK, the light emitting layer EL may contact the anode electrode AE. The cathode electrode CE may be disposed on the light emitting layer EL.

As described above, the light emitting element ED may be formed by including the anode electrode AE, the light emitting layer EL, and the cathode electrode CE. The light emitting layer EL may include an organic layer.

The encapsulation layer ENCAP may be provided on the stack of light emitting elements ED.

The encapsulation layer ENCAP may have a single-layer structure or a multi-layer structure. For example, as shown in fig. 6 and 7, the encapsulation layer ENCAP may have, for example, a single layer structure or a multi-layer structure, and the encapsulation layer ENCAP may include a first encapsulation layer PAS1, a second encapsulation layer PCL, and a third encapsulation layer PAS2.

The first and third encapsulation layers PAS1, PAS2 may be, for example, inorganic layers, and the second encapsulation layer PCL may be, for example, an organic layer. Of the first, second, and third encapsulation layers PAS1, PCL, and PAS2, the second encapsulation layer PCL may be the thickest and serve as a planarization layer.

The first encapsulation layer PAS1 may be disposed on the cathode electrode CE, and may be disposed closest to the light emitting element ED. The first encapsulation layer PAS1 may include an inorganic insulating material that can be deposited using low temperature deposition. For example, the first encapsulation layer PAS1 may include, but is not limited to, silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiON), aluminum oxide (Al) ₂ O ₃ ) And the like. Since the first encapsulation layer PAS1 may be deposited in a low temperature atmosphere, the first encapsulation layer PAS1 may prevent the light emitting layer EL including an organic material susceptible to a high temperature atmosphere from being damaged during a deposition process.

The second encapsulation layer PCL may have a smaller area or size than the first encapsulation layer PAS 1. For example, the second encapsulation layer PCL may be disposed to expose both ends or edges of the first encapsulation layer PAS 1. The second encapsulation layer PCL may serve as a buffer for relieving stress between corresponding layers when the display device 100 is curved or bent, and also serve to enhance planarization performance. For example, the second encapsulation layer PCL may include an organic insulating material such as acrylic resin, epoxy resin, polyimide, polyethylene, silicon oxycarbide (SiOC), and the like. The second encapsulation layer PCL may be provided, for example, using an inkjet scheme.

The inorganic third encapsulation layer PAS2 may be disposed on the substrate SUB on which the second encapsulation layer PCL is disposed such that the inorganic third encapsulation layer PAS2 covers respective top and side surfaces of the second encapsulation layer PCL and the first encapsulation layer PAS 1. The third encapsulation layer PAS2 may minimize or prevent external moisture or oxygen from penetrating into the inorganic first encapsulation layer PAS1 and the organic second encapsulation layer PCL. For example, the third encapsulation layer PAS2 may include an inorganic insulating material such as silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiON), aluminum oxide (Al) ₂ O ₃ ) And the like.

Next, a stacked structure of the first optical area OA1 will be described with reference to fig. 6 and 7.

Referring to fig. 6, the third substrate SUB3 may be disposed in the first optical area OA1.

The material of the third substrate SUB3 may be different from the respective materials of the first substrate SUB1 and the second substrate SUB2. For example, the third substrate SUB3 may be a glass substrate.

The transmittance of the third substrate SUB3 may be higher than those of the first and second substrates SUB1 and SUB2.

Since the third substrate SUB3 is disposed to correspond to the first optical area OA1, the third substrate SUB3 may overlap the first transmissive area TA1.

The first optical area OA1 may be an area requiring higher transmittance than the second optical area OA2 and the non-optical area NA.

Accordingly, since the third substrate SUB3 disposed to correspond to the first optical area OA1 has a higher transmittance than the first and second substrates SUB1 and SUB2 disposed to correspond to the second optical area OA2 and the non-optical area NA, the transmittance of the first optical area OA1 may be higher than the transmittance of the second optical area OA2 and the non-optical area NA.

In an example in which the same substrate as the first and second substrates SUB1 and SUB2 is used in the first optical area OA1, since the colors of the first and second substrates SUB1 and SUB2 are opaque, the transmittance of the first optical area OA1 may be reduced.

In an example in which the transparent polyimide is applied to the first optical area OA1, the thermal resistance may be reduced, and further, the substrate SUB may be damaged (floating of the substrate) due to heat generated in a process of forming a plurality of insulating layers and electrodes disposed on the substrate SUB, or process defects may be caused by impurities generated from the substrate SUB.

Therefore, by applying the third substrate SUB3 having a high transmittance to a region where such a high transmittance is desired, the transmittance of at least a part of the third substrate SUB3 may be increased, and the substrate SUB may be prevented from being damaged due to heat generated in a process of forming a plurality of insulating layers and electrodes provided on the substrate SUB. In addition, since the first substrate SUB1 and the second substrate SUB2 having excellent bending or folding characteristics are applied in regions other than the region where high transmittance is desired, the display device 100 that is not affected by bending and/or folding can be provided.

The first bonding layer 650 may be disposed on at least one surface of the third substrate SUB3.

For example, the first bonding layer 650 may be disposed on at least one side surface and a top surface of the third substrate SUB3.

However, embodiments of the present disclosure with respect to the position of the first bonding layer 650 are not limited thereto. For example, the first bonding layer 650 may be provided only on at least one side surface of the third substrate SUB3, or on all or a part of at least one side surface and all or a part of the top surface of the third substrate SUB3.

As shown in fig. 6, at least a portion of the first bonding layer 650 may be disposed in the non-optical area NA. For example, the first bonding layer 650 coupled to at least one side surface or portion of the third substrate SUB3 may be located in the non-optical region. This example may correspond to the structure of fig. 1A and 1B in a display device 100 according to aspects of the present disclosure; however, the embodiments of the present disclosure are not limited thereto.

The first bonding layer 650 may be used to connect respective at least one side surface of the first substrate SUB1, the interlayer insulating layer IPD and the second substrate SUB2, which are disposed in the non-optical area NA or the second optical area OA2 located around the first optical area OA1, with at least one side surface of the third substrate SUB3.

The material of the first bonding layer 650 may be a material including an amino group (amino group).

The material of the first bonding layer 650 may be coupled to one side surface of the third substrate SUB3, and the amino group of the material of the first bonding layer 650 may be coupled to respective at least one side surfaces of the first substrate SUB1 and the second substrate SUB2 adjacent to the third substrate SUB3.

The oxygen of the first bonding layer 650 may be coupled to the third substrate SUB3.

In an example in which the first and second substrates SUB1 and SUB2 are polyimide substrates, the amino group of the first bonding layer 650 may be coupled to an imide ring (imide ring) of the first and second substrates SUB1 and SUB2.

Accordingly, since the third substrate SUB3 is coupled to the first substrate SUB1 and the second substrate SUB2 through the first bonding layer 650, the third substrate SUB3 may not be separated.

Further, the third substrate SUB3 having a higher transmittance than the first and second substrates SUB1 and SUB2 may be disposed to correspond to all the first optical areas OA.

Referring to fig. 7, the third substrate SUB3 may be disposed to extend up to at least a portion of the second optical area OA2 and the first optical area OA1.

For example, the third substrate SUB3 may correspond to a portion of the second optical area OA2, but may not overlap the second transmissive area TA2.

However, the embodiments of the present disclosure are not limited thereto. For example, the third substrate SUB3 may be disposed to correspond to all of the second optical areas OA2.

The first bonding layer 650 may be disposed on at least one side of at least a portion of the third substrate SUB3 extending up to the second optical area OA2. For example, as shown in fig. 7, the first bonding layer 650 may be provided only on at least one side surface of the third substrate SUB3, or may be provided on all or a part of at least one side surface and all or a part of the top surface of the third substrate SUB3.

The first bonding layer 650 may overlap a portion of the second optical area OA2, but may not overlap the second transmissive area TA2.

Although fig. 7 illustrates a structure in which the third substrate SUB3 is disposed only in a portion of the second optical area OA2, embodiments of the present disclosure are not limited thereto. In an example where it is desired that the second optical areas OA2 have high transmittance, the third substrate SUB3 may be disposed to correspond to all of the second optical areas OA2.

Accordingly, since the third substrate SUB3 is disposed to extend up to at least a portion of the second optical area OA2, the third substrate has a higher transmittance than the first substrate SUB1 and the second substrate SUB2 even if a process error occurs. The third substrate SUB3 may be disposed to overlap all of the first optical areas OA.

Even in this example, the first bonding layer 650 may be provided on at least one side of the third substrate SUB3 so that the third substrate SUB3 and the first and second substrates SUB1 and SUB2 can be coupled to each other.

Referring to fig. 6 and 7, the light emitting area EA of the first optical area OA1 may have the same laminate structure as that of the light emitting area EA in the non-optical area NA. Therefore, in the following discussion, instead of repeatedly describing the light emitting region EA in the first optical region OA1, the stacked structure of the first transmission region TA1 in the first optical region OA1 will be described in detail below.

The cathode electrode CE may be disposed in the light emitting area EA included in the non-optical area NA and the first optical area OA1, but may not be disposed in the first transmission area TA1 in the first optical area OA1. For example, the first transmission area TA1 in the first optical area OA1 may correspond to the opening of the cathode electrode CE.

Further, the light shielding layer LS including at least one of the first and second metal layers ML1 and ML2 may be disposed in the light emitting area EA included in the non-optical area NA and the first optical area OA1, but may not be disposed in the first transmission area TA1 in the first optical area OA1. For example, the first transmissive area TA1 in the first optical area OA1 may correspond to the opening of the light shielding layer LS.

The various types of insulating layers (MBUF, ABUF1, ABUF2, GI, ILD1, ILD2, PAS0, PLN (PLN 1, PLN 2), BANK, ENCAP (PAS 1, PCL, PAS 2), T-BUF, T-ILD, PAC) and the substrate SUB disposed in the light emitting area EA included in the non-optical area NA and the first optical area OA1 may be equally, substantially equally or similarly disposed in the first transmission area TA1 in the first optical area OA1.

However, all or one or more of one or more material layers (e.g., a metallic material layer, a semiconductor layer, etc.) having electrical characteristics other than an insulating material or layer, which are disposed in the light emitting area EA included in the non-optical area NA and the first optical area OA1, may not be disposed in the first transmissive area TA1 in the first optical area OA1.

For example, referring to fig. 6 and 7, all or one or more of the metal material layers (ML 1, ML2, GATE, GM, TM, SD1, SD 2) and the semiconductor layer ACT related to the at least one transistor may not be disposed in the first transmissive area TA1.

Further, referring to fig. 6 and 7, the anode electrode AE and the cathode electrode CE included in the light emitting element ED may not be disposed in the first transmissive area TA1. In some embodiments, the light emitting layer EL of the light emitting element ED may or may not be disposed in the first transmission region TA1 according to design requirements.

Accordingly, since a material layer (e.g., a metal material layer, a semiconductor layer, etc.) having electrical characteristics is not disposed in the first transmissive area TA1 in the first optical area OA1, the light transmittance of the first transmissive area TA1 in the first optical area OA1 may be provided or improved. Accordingly, the first opto-electronic device 11 can perform a predetermined function (e.g., image sensing) by receiving the light transmitted through the first transmission area TA1.

Since all or one or more of the first transmission areas TA1 in the first optical area OA1 overlap the first optoelectronic device 11, in order to enable the first optoelectronic device 11 to operate normally, it is necessary to further increase the transmittance of the first transmission areas TA1 in the first optical area OA1.

For this, in some embodiments, the first transmissive area TA1 formed in the first optical area OA1 of the display panel 110 of the display device 100 may have the transmittance improvement structure TIS.

Referring to fig. 6 and 7, the plurality of insulating layers included in the display panel 110 may include at least one buffer layer (MBUF, ABUF1, ABUF 2) between at least one substrate (SUB 1, SUB 2) and at least one transistor (DRT, SCT), at least one planarization layer (PLN 1, PLN 2) between the transistor DRT and the light emitting element ED, at least one encapsulation layer ENCAP on the light emitting element ED, and the like.

Referring to fig. 6 and 7, the first transmission area TA1 in the first optical area OA1 may have the following structure as the transmittance improvement structure TIS: wherein the first planarization layer PLN1 and the passivation layer PAS0 have recess portions extending downward from the respective surfaces thereof.

Referring to fig. 6 and 7, the first planarization layer PLN1 may include at least one depression (or a recess, a groove, a recess, a protrusion, etc.) in the plurality of insulation layers. The first planarization layer PLN1 may be, for example, an organic insulating layer.

In an example where the first planarization layer PLN1 has a concave portion extending downward from the surface thereof, the second planarization layer PLN2 may be substantially used for planarization. In one embodiment, the second planarization layer PLN2 may also have a concave portion extending downward from a surface thereof. In this embodiment, the second encapsulation layer PCL may be substantially used for planarization.

Referring to fig. 6 and 7, the recess portions of the first planarization layer PLN1 and the passivation layer PAS0 may PASs through the insulating layer, such as the first interlayer insulating layer ILD, the second interlayer insulating layer ILD2, the gate insulating layer GI, etc., for forming the transistor DRT, and the buffer layer, such as the first active buffer layer ABUF1, the second active buffer layer ABUF2, the multi-buffer layer MBUF, etc., under the insulating layer, and extend up to the upper portion of the second substrate SUB2.

Referring to fig. 6 and 7, the substrate SUB may include at least one recess or depression as the transmittance improvement structure TIS. For example, in the first transmissive area TA1, an upper portion of the second substrate SUB2 may be recessed or depressed downward, or the second substrate SUB2 may be perforated.

Referring to fig. 6 and 7, the first and second encapsulation layers PAS1 and PCL included in the encapsulation layer ENCAP may also have a transmittance improvement structure TIS in which the first and second encapsulation layers PAS1 and PCL have concave portions extending downward from the respective surfaces thereof. The second encapsulation layer PCL may be, for example, an organic insulating layer.

Referring to fig. 6 and 7, the light emitting area EA of the second optical area OA2 may have the same laminate structure as that of the light emitting area EA in the non-optical area NA. Therefore, in the following discussion, instead of repeatedly describing the light emitting area EA in the second optical area OA2, a laminated structure of the second transmission area TA2 in the second optical area OA2 will be described in detail below.

The cathode electrode CE may be disposed in the light emitting area EA included in the non-optical area NA and the second optical area OA2, but may not be disposed in the second transmission area TA2 in the second optical area OA2. For example, the second transmission area TA2 in the second optical area OA2 may correspond to the opening of the cathode electrode CE.

Further, the light shielding layer LS including at least one of the first and second metal layers ML1 and ML2 may be disposed in the light emitting area EA included in the non-optical area NA and the second optical area OA2, but may not be disposed in the second transmission area TA2 in the second optical area OA2. For example, the second transmissive area TA2 in the second optical area OA2 may correspond to the opening of the light shielding layer LS.

In an example in which the transmittance of the second optical area OA2 is the same as that of the first optical area OA1, the stacked structure of the second transmission area TA2 in the second optical area OA2 may be the same as that of the first transmission area TA1 in the first optical area OA1.

In another example in which the transmittance of the second optical area OA2 and the transmittance of the first optical area OA1 are different, the laminated structure of the second transmission area TA2 in the second optical area OA2 may be different from the laminated structure of the first transmission area TA1 in the first optical area OA1 in at least a part.

For example, as shown in fig. 6 and 7, when the transmittance of the second optical area OA2 is less than that of the first optical area OA1, the second transmissive area TA2 in the second optical area OA2 may not have the transmittance improvement structure TIS. As a result, the first planarization layer PLN1 and the passivation layer PAS0 may not be recessed or depressed. Further, the width of the second transmission area TA2 in the second optical area OA2 may be smaller than the width of the first transmission area TA1 in the first optical area OA1.

The various types of insulating layers (MBUF, ABUF1, ABUF2, GI, ILD1, ILD2, PAS0, PLN (PLN 1, PLN 2), BANK, ENCAP (PAS 1, PCL, PAS 2), T-BUF, T-ILD, PAC) and the substrate SUB disposed in the light emitting area EA included in the non-optical area NA and the second optical area OA2 may be equally, substantially equally or similarly disposed in the second transmission area TA2 in the second optical area OA2.

However, all or one or more of one or more material layers (e.g., a metallic material layer, a semiconductor layer, etc.) having electrical characteristics other than an insulating material or layer, which are disposed in the light emitting area EA included in the non-optical area NA and the second optical area OA2, may not be disposed in the second transmissive area TA2 in the second optical area OA2.

For example, referring to fig. 6 and 7, all or one or more of the metallic material layers (ML 1, ML2, GATE, GM, TM, SD1, SD 2) and the semiconductor layer ACT related to the at least one transistor may not be disposed in the second transmissive area TA2 in the second optical area OA2.

Further, referring to fig. 6 and 7, the anode electrode AE and the cathode electrode CE included in the light emitting element ED may not be disposed in the second transmissive area TA2. In some embodiments, the light emitting layer EL of the light emitting element ED may or may not be disposed in the second transmission region TA2 according to design requirements.

Referring to fig. 8, in an example in which the touch sensor TS is embedded in the display panel 110, the touch sensor TS may be disposed on the encapsulation layer ENCAP. The structure disposed below the encapsulation layer ENCAP has been described with reference to fig. 6; however, the embodiments of the present disclosure are not limited thereto. The structure disposed under the encapsulation layer ENCAP shown in fig. 8 may be substantially or almost identical to the structure of fig. 7.

Next, the structure of the touch sensor of fig. 8 will be described in detail.

Referring to fig. 8, in an example in which the touch sensor TS is embedded in the display panel 110, the touch sensor TS may be disposed on the encapsulation layer ENCAP. The structure of the touch sensor will be described in detail as follows.

The touch buffer layer T-BUF may be disposed on the encapsulation layer ENCAP in the non-optical area NA, the first optical area OA1, and the second optical area OA2. The touch sensor TS may be disposed on the touch buffer layer T-BUF.

The touch sensor TS may include a touch sensor metal TSM and at least one bridge metal BRG located in different layers.

The touch interlayer insulating layer T-ILD may be disposed between the touch sensor metal TSM and the bridge metal BRG.

For example, the touch sensor metal TSM may include a first touch sensor metal TSM, a second touch sensor metal TSM, and a third touch sensor metal TSM disposed adjacent to each other. In an embodiment where the third touch sensor metal TSM is disposed between the first and second touch sensor metals TSM and the first and second touch sensor metals TSM need to be electrically connected to each other, the first and second touch sensor metals TSM and TSM may be electrically connected to each other through a bridge metal BRG located in a different layer. The bridge metal BRG may be electrically insulated from the third touch sensor metal TSM by the touch interlayer insulating layer T-ILD.

When the touch sensor TS is disposed on the display panel 110, a chemical solution (developer or etchant, etc.) used in a corresponding process or moisture from the outside may be generated or introduced. By disposing the touch sensor TS on the touch buffer layer T-BUF, it is possible to prevent a chemical solution or moisture from penetrating into the light emitting layer EL including an organic material during the manufacturing process of the touch sensor TS. Therefore, the touch buffer layer T-BUF may prevent damage to the light emitting layer EL, which is susceptible to chemical solution or moisture.

In order to prevent damage to the light emitting layer EL including an organic material susceptible to high temperature, the touch buffer layer T-BUF may be formed at a low temperature of less than or equal to a predetermined temperature (e.g., 100 degrees (° c)), and formed using an organic insulating material having a low dielectric constant of 1 to 3. For example, the touch buffer layer T-BUF may include an acrylic-based, epoxy-based, or siloxane-based material. When the display device 100 is bent, the encapsulation layer ENCAP may be damaged, and the touch sensor metal on the touch buffer layer T-BUF may be cracked or broken. The touch buffer layer T-BUF having a planarization property as an organic insulating material may prevent damage of the encapsulation layer ENCAP and/or cracking or breaking of metals (TSM, BRG) included in the touch sensor TS even when the display device 100 is bent.

The protection layer PAC may be disposed to cover the touch sensor TS. The protective layer PAC may be, for example, an organic insulating layer.

The touch sensor metal TSM and the bridge metal BRG included in the touch sensor TS may not be disposed in the first transmissive area TA1 in the first optical area OA1.

In order to protect the touch sensor TS, the protection layer PAC may be disposed to cover the touch sensor TS on the encapsulation layer ENCAP.

Referring to fig. 8, the protection layer PAC may have at least one depression (or a concave portion, a groove, a concave portion, a protrusion, etc.) as the transmittance improvement structure TIS in a portion overlapping the first transmissive area TA1. The protective layer PAC may be, for example, an organic insulating layer.

Referring to fig. 8, the touch sensor TS may include one or more touch sensor metals TSM having a mesh type. In an example in which the touch sensor metal TSM is formed in a mesh type, a plurality of openings may be formed in the touch sensor metal TSM. Each of the plurality of apertures may be positioned to correspond to the light emitting area EA of the sub-pixel SP.

In order for the first optical area OA1 to have a transmittance higher than that of the non-optical area NA, an area or size of the touch sensor metal TSM per unit area in the first optical area OA1 may be smaller than that of the touch sensor metal TSM per unit area in the non-optical area NA.

Referring to fig. 8, the touch sensor TS may be disposed in the light emitting area EA in the first optical area OA1, but may not be disposed in the first transmission area TA1 in the first optical area OA1. In addition, the touch sensor metal TSM and the bridge metal BRG included in the touch sensor TS may not be disposed in the first transmissive area TA1 in the first optical area OA1.

The touch sensor metal TSM and the bridge metal BRG included in the touch sensor TS may not be disposed in the second transmissive area TA2 in the second optical area OA2.

Accordingly, since a material layer (e.g., a metal material layer, a semiconductor layer, etc.) having electrical characteristics is not disposed in the second transmissive area TA2 in the second optical area OA2, the light transmittance of the second transmissive area TA2 in the second optical area OA2 may be provided or improved. Accordingly, the second optoelectronics 12 may perform a predetermined function (e.g., proximity detection of an object or a human body, external illumination detection, etc.) by receiving the light transmitted through the second transmission area TA2.

Fig. 9 is a cross-sectional view in an outer edge of the display panel 110 according to aspects of the present disclosure.

For simplicity, fig. 9 shows a single substrate SUB including a first substrate SUB1 and a second substrate SUB2, and also shows a layer or a portion located under the BANK portion BANK in a simplified structure. Likewise, fig. 9 shows a single planarization layer PLN including the first and second planarization layers PLN1 and PLN2, and a single interlayer insulating layer INS including the second and first interlayer insulating layers ILD2 and ILD1 under the planarization layer PLN.

Referring to fig. 9, the first encapsulation layer PAS1 may be disposed on the cathode electrode CE and disposed closest to the light emitting element ED. The second encapsulation layer PCL may have a smaller area or size than the first encapsulation layer PAS 1. For example, the second encapsulation layer PCL may be disposed to expose both ends or edges of the first encapsulation layer PAS 1.

The inorganic third encapsulation layer PAS2 may be disposed on the substrate SUB on which the second encapsulation layer PCL is disposed such that the inorganic third encapsulation layer PAS2 covers respective top and side surfaces of the second encapsulation layer PCL and the first encapsulation layer PAS 1.

The third encapsulation layer PAS2 may minimize or prevent external moisture or oxygen from penetrating into the inorganic first encapsulation layer PAS1 and the organic second encapsulation layer PCL.

Referring to fig. 9, in order to prevent the encapsulation layer ENCAP from collapsing, the display panel 110 may include one or more barriers (DAM 1, DAM 2) at or near an end or edge of the inclined surface SLP of the encapsulation layer ENCAP. One or more barriers (DAM 1, DAM 2) may exist at or near a boundary point between the display area DA and the non-display area NDA.

One or more barriers (DAM 1, DAM 2) may comprise the same material DFP as the BANK.

Referring to fig. 9, in one embodiment, the second encapsulation layer PCL including an organic material may be located only inside the first barrier DAM1, among which the first barrier DAM1 is located closest to the inclined surface SLP of the encapsulation layer ENCAP. For example, the second encapsulation layer PCL may not be located on all barriers (DAM 1, DAM 2). In another embodiment, a second encapsulation layer PCL including an organic material may be positioned on at least the first barrier DAM1 of the first and second barrier DAMs DAM1 and DAM 2.

For example, the second encapsulation layer PCL may extend only to all or at least a portion of the upper portion of the first barrier DAM 1. In another embodiment, the second encapsulation layer PCL may extend over an upper portion of the first barrier DAM1 and to all or at least a portion of an upper portion of the second barrier DAM 2.

Referring to fig. 9, a touch pad TP to which the touch driving circuit 260 is electrically connected may be disposed on a portion of the substrate SUB located outside one or more barriers (DAM 1, DAM 2).

The touch line TL may electrically connect a touch sensor metal TSM or a bridge metal BRG included in or used as a touch electrode disposed in the display area DA to the touch pad TP.

One end or edge of the touch line TL may be electrically connected to the touch sensor metal TSM or the bridge metal BRG, and the other end or edge of the touch line TL may be electrically connected to the touch pad TP.

The touch line TL may travel down the inclined surface SLP of the encapsulation layer ENCAP, travel along respective upper portions of the barriers DAM1, DAM2, and extend up to the touch pad TP disposed outside the barriers (DAM 1, DAM 2).

Referring to fig. 9, in one embodiment, the touch line TL may be a bridge metal BRG. In another embodiment, the touch line TL may be a touch sensor metal TSM.

Fig. 10-17 illustrate a process of forming a substrate in a display device 100 according to aspects of the present disclosure.

Referring to fig. 10, a sacrificial layer 1020 may be disposed on the support layer 1010. The support layer 1010 may be glass and the sacrificial layer 1020 may be an amorphous silicon (a-Si) layer, however, embodiments of the present disclosure are not limited thereto.

Thereafter, the surface treatment of the sacrificial layer 1020 may be performed using plasma or UV. The sacrificial layer 1020 to which the surface treatment has been applied may be in a state of forming a ligand (ligand) to improve adhesion with a different material. For example, oxygen ligands may be formed in the sacrificial layer 1020.

As shown in fig. 11, the material of the second bonding layer 1150 may be deposited on the sacrificial layer 1020.

The material of the second bonding layer 1150 may include a silane coupling agent.

The material of the second bonding layer 1150 may correspond to the material of the first bonding layer 650 described with reference to fig. 6 to 8.

For example, the material of the second bonding layer 1150 may include an aminosilane-based material.

The second bonding layer 1150 may be coupled by the oxygen ligands of the sacrificial layer 1020. Further, the third substrate SUB3 may be coupled by oxygen in the second bonding layer 1150.

The third substrate SUB3 may be disposed on the second bonding layer 1150.

The second bonding layer 1150 may be used to couple the third substrate SUB3 to the sacrificial layer 1020.

The width of the second bonding layer 1150 may correspond to the width of the third substrate SUB3. The width of the second bonding layer 1150 and the width of the third substrate SUB3 may refer to a length in a direction perpendicular to a direction in which the sacrificial layer 1020 is stacked on the support layer 1010.

Meanwhile, the region where the third substrate SUB3 is disposed may include a region corresponding to the first optical region OA1.

For example, as shown in fig. 11, the region where the third substrate SUB3 is disposed and the first optical region OA1 may correspond to each other.

However, the embodiments of the present disclosure are not limited thereto. For example, the region where the third substrate SUB3 is disposed may correspond to the first optical area OA1 and a portion of the non-optical area NA located around the first optical area OA1. The region where the third substrate SUB3 is disposed may correspond to a portion or the whole of the second optical area OA2 and the first optical area OA1.

In an example in which the region where the third substrate SUB3 is disposed and the first optical region OA1 correspond to each other, the remaining region except for the region where the third substrate SUB3 is disposed may correspond to the non-optical region NA and the second optical region OA2.

In another example in which the region where the third substrate SUB3 is disposed corresponds to the first optical region OA1 and a portion of the non-optical region NA located around the first optical region OA1, the remaining region except for the region where the third substrate SUB3 is disposed may correspond to a portion of the non-optical region NA and the second optical region OA2.

In another example in which the region where the third substrate SUB3 is disposed corresponds to a portion of the second optical area OA2 and the first optical area OA1, the remaining region except for the region where the third substrate SUB3 is disposed may correspond to a portion of the second optical area OA2 and the non-optical area NA. In still another example in which the region where the third substrate SUB3 is disposed corresponds to all of the first optical regions OA1 and all of the second optical regions OA2, the remaining regions other than the region where the third substrate SUB3 is disposed may correspond to the non-optical regions NA.

As shown in fig. 12A to 12C, a first bonding layer 650 may be provided on at least one side of the third substrate SUB3.

For example, the first bonding layer 650 may be disposed on all or at least a portion of at least one side surface and all or at least a portion of a top surface of the third substrate SUB3.

Thereafter, as illustrated in fig. 12A to 12C, surface treatment may be performed on the top surface of the first bonding layer 650 and the top surface of the sacrificial layer 1020 on which the third substrate SUB3 is disposed using plasma or UV.

Specifically, the surface treatment of the sacrificial layer 1020 may be performed in the remaining region except the region where the third substrate SUB3 is provided, and the surface treatment may be performed on the entire top surface of the first bonding layer 650.

As shown in fig. 12A, in an example (e.g., the structure in fig. 11) in which the area where the third substrate SUB3 is disposed and the first optical area OA1 correspond to each other, a portion of the first bonding layer 650 disposed on the top surface of the third substrate SUB3 may be disposed to correspond to the first optical area OA1, and a portion of the first bonding layer 650 disposed on at least one side surface of the third substrate SUB3 may be disposed to correspond to the non-optical area NA or the second optical area OA2.

However, the embodiments of the present disclosure are not limited thereto. For example, as shown in fig. 12B, in an example in which an area where the third substrate SUB3 is disposed corresponds to the first optical area OA1 and a portion of the non-optical area NA located around the first optical area OA1, a portion of the first bonding layer 650 disposed on the top surface of the third substrate SUB3 may be disposed to correspond to the first optical area OA1 and a portion of the non-optical area NA located around the first optical area OA1, and a portion of the first bonding layer 650 disposed on at least one side surface of the third substrate SUB3 may be disposed to correspond to the non-optical area NA or the second optical area OA2.

Further, as shown in fig. 12C, in an example in which the region where the third substrate SUB3 is disposed corresponds to at least a portion of the second optical region OA2 and the first optical region OA1, a portion of the first bonding layer 650 disposed on the upper surface of the third substrate SUB3 may be disposed to correspond to a portion of the second optical region OA2 and the first optical region OA1, and a portion of the first bonding layer 650 disposed on at least one side surface of the third substrate SUB3 may be disposed to correspond to at least one of the second optical region OA2 and the non-optical region NA.

Further, in an example in which the first and second optical areas OA1 and OA2 are spaced apart from each other as shown in fig. 1B, the third substrate SUB3 may be disposed not only to correspond to the first and second optical areas OA1 and OA2 but also in the non-optical area NA between the first and second optical areas OA1 and OA2. For example, the first bonding layer 650 disposed on the top surface of the third substrate SUB3 may be disposed to overlap the first optical area OA1, at least a portion of the non-optical area NA, and at least a portion of the second optical area OA2.

Therefore, according to the embodiment of the present disclosure, since the third substrate SUB3 is disposed not only in the first optical area OA1 but also in the second optical area OA2, the transmittance may be adjusted for each area.

Referring to fig. 13, a first substrate material 1330 may be disposed on the sacrificial layer 1020 and the first bonding layer 650, which have been surface-treated.

The material of the first substrate SUB1 may be polyimide PI.

The thickness of the first substrate material 1330 disposed on the top surface of the sacrificial layer 1020 may be greater than the thickness of the first substrate material 1330 disposed on the top surfaces of the third substrate SUB3 and the first bonding layer 650. However, the first substrate material 1330 according to an embodiment of the present disclosure is not limited thereto and may have various thicknesses at one or more positions, for example.

In an example where the apparatus or device for depositing the first substrate material 1330 has the capability of identifying the height of the object on which the material is deposited and adjusting the amount of material to be sprayed, a small amount of material may be sprayed in a portion of the object having a relatively large height, and a large amount of material may be sprayed in a portion of the object having a relatively small height.

For example, since the height of the region where the third substrate SUB3 and the first bonding layer 650 are provided is greater than one or more other regions, a small amount of the first substrate material 1330 may be sprayed in the region. Accordingly, the thickness of the first substrate material 1330 disposed on the top surfaces of the first bonding layer 160 and the third substrate SUB3 may be smaller than the thickness of the first substrate material 1330 disposed on the top surface of the sacrificial layer 1020.

The first substrate material 1330 may be coupled to the first bonding layer 650 and the sacrificial layer 1020 on which the surface treatment has been performed.

For example, as shown in fig. 13, the sacrificial layer 1020 and the first substrate material 1330 may be coupled to each other by an oxygen ligand of the sacrificial layer 1020 generated by the surface treatment. In this case, the oxygen ligand of the sacrificial layer 1020 and the sacrificial layer 1020 may be coupled to each other due to electron attraction.

Further, the oxygen ligands of the first bonding layer 650 may be coupled to the third substrate SUB3, and the amino groups of the first bonding layer 650 may be coupled to the first substrate material 1330.

Thereafter, as shown in fig. 14, an interlayer insulating layer material 1440 may be disposed on the sacrificial layer 1020 on which the first substrate material 1330 is disposed.

A second substrate material 1450 may be disposed on sacrificial layer 1020 having interlayer insulating layer material 1440 disposed thereon.

The thickness of the second substrate material 1450 on the sacrificial layer 1020 may be greater than the thickness of the second substrate material 1450 disposed over the first bonding layer 650. However, the thickness of the second substrate material 1450 according to embodiments of the present disclosure is not limited thereto.

Referring to fig. 15, the first substrate material 1330, the interlayer insulating layer material 1440, and the second substrate material 1450 disposed on the third substrate SUB3 and the first bonding layer 650 may be removed to planarize a surface of a substrate used in the display device. For this, a dry etching process may be used, but the embodiments of the present disclosure are not limited thereto.

By removing the first substrate material 1330, the interlayer insulating layer material 1440, and the second substrate material 1450 disposed on the third substrate SUB3 and the first bonding layer 650, the first substrate SUB1, the second substrate SUB2, and the third substrate SUB3, the interlayer insulating layer IPD, and the first bonding layer 650 may be disposed on the sacrificial layer 1020.

Thereafter, laser light may be irradiated to separate the support layer 1010 and the sacrificial layer 1020 from the first substrate SUB1 and the third substrate SUB3.

Thereby, the sacrificial layer 1020 and the second bonding layer 1150 may be separated from the first substrate SUB1 and the third substrate SUB3, and thus, the substrate SUB including the first substrate SUB1, the second substrate SUB2, the third substrate SUB3, the interlayer insulating layer IPD, and the first bonding layer 650 may be formed as shown in fig. 16.

In some cases, a portion of the second bonding layer 1150 may remain on the rear surface of the third substrate SUB3.

The sum H1 of the heights of each of the first substrate SUB1, the interlayer insulating layer IPD, and the second substrate SUB2 may be substantially equal to the sum H1 of the heights of each of the third substrate SUB3 and the first bonding layer 650 disposed on the third substrate SUB3. This results in the top surface of the substrate SUB being planarized.

In some embodiments, in the process of fig. 15 of removing the first substrate material 1330, the interlayer insulating layer material 1440, and the second substrate material 1450 disposed on the top surface of the first bonding layer 650, a portion of the first bonding layer 650 and the second substrate material 1450 disposed on the third substrate SUB3 may be removed, and thus, as shown in fig. 17, the first bonding layer 650 may not exist on the third substrate SUB3.

In this example, the first bonding layer 650 may be provided only at the boundary between the third substrate SUB3, the first substrate SUB1, the interlayer insulating layer IPD, and the second substrate SUB2.

In one example, a sum H1 of respective heights of the first substrate SUB1, the interlayer insulating layer IPD, and the second substrate SUB2 may correspond to a height H3 of the third substrate SUB3. This results in the top surface of the substrate SUB being planarized.

The height H3 of the third substrate SUB3 may be greater than or equal to 30 μm (the third substrate SUB3 may be successfully manufactured at 30 μm), but the embodiment of the present disclosure is not limited thereto.

In this way, since the first bonding layer 650 is provided at the boundary between the third substrate SUB3, the first substrate SUB1, the interlayer insulating layer IPD, and the second substrate SUB2, the third substrate SUB3 can be fixed without being separated from the first substrate SUB1, the interlayer insulating layer IPD, and the second substrate SUB2.

For example, the first bonding layer 650 may have a structure in which: wherein the first bonding layer 650 is coupled to the third substrate SUB3 and each of the first substrate SUB1, the interlayer insulating layer IPD and the second substrate SUB2 such that at least one side of the first bonding layer 650 is coupled to the substrate SUB3 and the other side of the first bonding layer 650 is coupled or coated to the respective at least one side of the first substrate SUB1, the interlayer insulating layer IPD and the second substrate SUB2.

Fig. 18 shows transmittance of light for each wavelength in comparative examples 1, 2, an embodiment in a display device according to an aspect of the present disclosure.

In fig. 18, the display device of comparative example 1 may include a first optical region, a second optical region, and a non-optical region including a first substrate and a second substrate; the display device of comparative example 2 may include a transparent first optical region, a second optical region, and a non-optical region including a transparent resin substrate; and the display device according to the embodiment may be a display device having a structure shown in fig. 6.

Referring to fig. 18, it can be seen that the display device of the embodiment to which the third substrate is applied has the highest transmittance at each wavelength of 430nm, 470nm, 555nm, and 650 nm.

In particular, the transmittance of the display device of the embodiment with respect to light having a short wavelength of 430nm may be two times or more of the respective transmittances of the display devices of comparative examples 1 and 2.

Embodiments described herein provide a display panel 110 and a display device 100 capable of reducing the size of a non-display area NDA of the display panel 110 and not exposing the optical electronic devices (11, 12) in a front surface of the display device 100 by positioning the optical electronic devices (11, 12) such as cameras, sensors, etc. at a lower portion or below a display area DA of the display panel 110.

Embodiments described herein provide a display panel 110 and a display device 100 having a light transmission structure for enabling an optoelectronic device at a lower portion or below a display area of the display panel to normally receive light transmitted through the display panel.

According to the embodiments described herein, the display panel may include a display area including a first optical area OA1 and a non-optical area NA, the first optical area OA1 including a plurality of emission areas and a plurality of first transmission areas TA1, and the non-optical area NA located outside the first optical area OA1 and including a plurality of emission areas.

The display device may include a first optoelectronic device 11, the first optoelectronic device 11 being located at a lower portion or a lower portion of the display panel and overlapping at least a portion of the first optical area OA1 included in the display area. The display panel may include a first substrate SUB1 disposed in at least a portion of the non-optical area NA, a second substrate SUB2 disposed on the first substrate, a third substrate SUB3 disposed in the first optical area OA1 and having a higher transmittance than the first substrate SUB1 and the second substrate SUB2, and a first bonding layer 650 disposed on at least one surface of the third substrate SUB3.

The first bonding layer 650 may be disposed on all one or more side surfaces of the third substrate SUB3. Further, the first bonding layer 650 may be disposed on the entire top surface of the third substrate SUB3.

The material of the first bonding layer 650 may include an amino group.

The material of the third substrate SUB3 may be different from the respective materials of the first substrate SUB1 and the second substrate SUB2.

At least a portion of the first bonding layer 650 may be coupled to at least a portion of respective at least one side surface of the first substrate SUB1 and the second substrate SUB2.

A region where the first substrate SUB1, the second substrate SUB2, and the first bonding layer 650 are coupled may be disposed in the non-optical region NA.

The display device may include an interlayer insulating layer IPD disposed between the first substrate SUB1 and the second substrate SUB2. The sum of the heights of the first substrate SUB1, the interlayer insulating layer IPD, and the second substrate SUB2 may correspond to or be greater than the height of the third substrate SUB3.

One side of the interlayer insulating layer IPD may contact the first bonding layer 650.

The maximum width of the third substrate SUB3 may correspond to or be greater than the maximum width of the first optical area OA1. The maximum width of the third substrate SUB3 and the maximum width of the first optical area OA1 may refer to a width in the longest length direction of the display panel or a width in a direction crossing the longest length direction of the display panel.

The third substrate SUB3 may also be disposed in at least a portion of the second optical area OA2.

The regions of the first bonding layer 650 coupled to the respective at least one sides of the first and second substrates SUB1 and SUB2 may be disposed in at least a portion of the second optical area OA2 or in the non-optical area NA.

Embodiments described herein provide a display panel having a structure having high transmittance and excellent heat resistance in a region where an optoelectronic device is disposed and thus causing no process defects even in a subsequent process, and a display device including the same.

The previous description is presented to enable any person skilled in the art to make and use the technical concept of the invention, and is provided in the context of a particular application and its requirements. Various modifications, additions and substitutions to the described embodiments will be apparent to those skilled in the art, and the general principles defined herein may be applied to other embodiments and applications without departing from the spirit and scope of the invention. The above description and the drawings provide examples of the technical idea of the present invention for illustrative purposes only. That is, the disclosed embodiments are intended to illustrate the scope of the technical idea of the present invention. Thus, the scope of the present invention is not limited to the embodiments shown, but is to be accorded the widest scope consistent with the claims. The scope of the present invention should be construed based on the appended claims, and all technical ideas within the equivalent scope thereof should be construed as being included in the scope of the present invention.

Cross Reference to Related Applications

This patent application claims the benefit of priority of korean patent application No.10-2021-0123365, filed on 9/15/2021 to the korean intellectual property office, which is incorporated herein by reference in its entirety.

Claims

1. A display device, the display device comprising:

a display panel including a display region and a non-display region, the display region including a first optical region including a plurality of light emitting regions and a plurality of first transmission regions, and a non-optical region located outside the first optical region and including a plurality of light emitting regions; and

a first opto-electronic device located below the display panel and overlapping at least a portion of the first optical area included in the display area,

wherein the display panel further comprises:

a base substrate disposed in at least a portion of the non-optical region;

a third substrate disposed in the first optical zone and having a higher transmittance than the base substrate; and

a bonding layer disposed on at least one side surface of the third substrate.

2. The display device of claim 1, wherein the base substrate comprises a first substrate and a second substrate disposed on the first substrate.

3. The display device according to claim 1, wherein the bonding layer is provided over all side surfaces of the third substrate, and is also provided over an entire top surface of the third substrate.

4. The display device according to claim 1, wherein a material of the bonding layer comprises an amino group.

5. The display device of claim 1, wherein a material of the third substrate is different from a material of the base substrate, wherein the base substrate comprises polyimide and the third substrate comprises glass.

6. The display device of claim 1, wherein at least a portion of the bonding layer is coupled to at least a portion of at least one side surface of the base substrate, wherein a region of the base substrate coupled to the bonding layer is disposed in the non-optical region.

7. The display device according to claim 2, wherein the base substrate further comprises an interlayer insulating layer provided between the first substrate and the second substrate,

wherein a sum of respective heights of the first substrate, the interlayer insulating layer, and the second substrate corresponds to or is greater than a height of the third substrate, wherein at least one side surface of the interlayer insulating layer contacts the bonding layer.

8. The display device according to claim 1, wherein a width of the third substrate corresponds to or is greater than a width of the first optical region.

9. The display device of claim 1, wherein the number of sub-pixels per unit area in the first optical region is less than the number of sub-pixels per unit area in the non-optical region.

10. The display device according to claim 1, wherein the first and second light sources are arranged in a matrix,

wherein the display area further comprises a second optical area that is different from the first optical area and the non-optical area;

wherein the display device further comprises a second opto-electronic device underlying the display panel and overlapping at least a portion of the second optical area, and

wherein the non-optical region is disposed or not disposed between the first optical region and the second optical region.

11. The display device of claim 10, wherein the third substrate is disposed in at least a portion of the second optical region, wherein a region of the bonding layer coupled to the base substrate is disposed in at least a portion of the second optical region or in the non-optical region.

12. The display device of claim 10, wherein the first optoelectronic device is a camera and the second optoelectronic device is a sensor.

13. The display device according to claim 1, wherein the display panel further comprises a cathode electrode provided in the plurality of light emitting areas included in the non-optical area and the plurality of light emitting areas in the first optical area, and not provided in the plurality of first transmission areas in the first optical area.

14. The display device according to claim 1, wherein the display panel further comprises a light-shielding layer which is provided below the transistors in the plurality of light-emitting areas and is not provided in the plurality of first transmission areas.

15. The display device of claim 1, wherein gate lines disposed in the display panel pass through the first optical region by avoiding the plurality of first transmissive regions in the first optical region, wherein each of the gate lines passing through the first optical region includes one or more curved portions running around an outer edge of one or more of the plurality of first transmissive regions.

16. The display device of claim 1, wherein gate lines of the display panel passing through the first optical region and gate lines of the display panel not passing through the first optical region have different lengths.

17. The display device according to claim 1, wherein the number of sub-pixels connected to one or more of the gate lines of the display panel that pass through the first optical region is different from the number of sub-pixels connected to each of the gate lines of the display panel that do not pass through the first optical region.

18. The display device of claim 1, wherein an area of the touch sensor metal per unit area in the first optical region is less than an area of the touch sensor metal per unit area in the non-optical region.

19. A substrate for a display panel, the substrate comprising:

a base substrate;

a third substrate having a higher transmittance than the base substrate;

a bonding layer provided on at least one side surface of the third substrate for bonding the base substrate and the third substrate,

wherein the base substrate comprises polyimide and the third substrate comprises glass, and

wherein the material of the bonding layer includes an amino group.

20. The substrate of claim 19, wherein the base substrate comprises a first substrate, a second substrate disposed on the first substrate, and an interlayer insulating layer disposed between the first substrate and the second substrate; and is

Wherein a sum of respective heights of the first substrate, the interlayer insulating layer, and the second substrate corresponds to or is greater than a height of the third substrate.