WO2015172406A1 - 栅极侧扇出区域电路结构 - Google Patents

栅极侧扇出区域电路结构 Download PDF

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Publication number
WO2015172406A1
WO2015172406A1 PCT/CN2014/078673 CN2014078673W WO2015172406A1 WO 2015172406 A1 WO2015172406 A1 WO 2015172406A1 CN 2014078673 W CN2014078673 W CN 2014078673W WO 2015172406 A1 WO2015172406 A1 WO 2015172406A1
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Prior art keywords
terminal
circuit module
gate
input
amplitude voltage
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PCT/CN2014/078673
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English (en)
French (fr)
Inventor
黄笑宇
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TCL China Star Optoelectronics Technology Co Ltd
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Shenzhen China Star Optoelectronics Technology Co Ltd
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Priority to KR1020167017233A priority Critical patent/KR101876657B1/ko
Priority to JP2016552587A priority patent/JP6452710B2/ja
Priority to US14/371,733 priority patent/US9306557B2/en
Priority to GB1610211.3A priority patent/GB2535675B/en
Publication of WO2015172406A1 publication Critical patent/WO2015172406A1/zh
Anticipated expiration legal-status Critical
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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0291—Details of output amplifiers or buffers arranged for use in a driving circuit

Definitions

  • the present invention relates to liquid crystal display technology, and more particularly to a circuit structure of a gate side fan-out area. Background technique
  • TFT-LCD Thin Film Transistor Liquid Crystal Display
  • TFT-LCD Thin Film Transistor Liquid Crystal Display
  • the TFT-LCD uses an active component such as a thin-film transistor (TFT) to control the turn-on and turn-off of each pixel unit, and controls the transmittance of the liquid crystal material according to the image signal to display an image.
  • the liquid crystal display is provided with a display panel including a pixel array, and a driving circuit for driving the liquid crystal display panel.
  • the display panel is provided with a plurality of parallel data lines and scan lines, the data lines and the scan lines are vertically interlaced with each other, and the pixel unit switches and the thin film transistor switches for controlling the pixel units are arranged at the interlaced portions.
  • the driver circuit includes a source driver and a gate driver, the source driver provides a signal for the data line associated with the display image, and the gate driver provides a signal for the scan line to turn the thin film transistor on or off.
  • FIG. 1 it is a schematic diagram of a TFT-LCD driving structure in the prior art.
  • the main driving principles of the existing TFT-LCD include: the system motherboard will compress R/G/B signals, control signals, and power.
  • the wire is connected to a connector on the PCB 1, and the PCB passes through an S-COF chip (Source-Chip on Film) 2 and a G-COF (Gate-Chip on Film).
  • S-COF chip Source-Chip on Film
  • G-COF Gate-Chip on Film
  • the gate chip 3 is connected to a display area 4 so that the LCD obtains the required power and signals.
  • the technology of driving chip packaging is also toward the trend of thinner thickness and smaller area.
  • the gate chip and the source chip are all made of thin film. Chip on Film (COF) type packaging.
  • COF Chip on Film
  • the fan out area 5 is a portion where the signal line of the display area 4 is connected to the driving chip, and the gate signal line and the source data line are connected to the S-COF chip 2 and G via the fan-out area 5.
  • the COF chip 3, the fan-out region 5 on the side of the gate drive chip G-COF chip 3, may be referred to as a gate side fan-out region.
  • a liquid crystal display device having a resolution of mxn is taken as an example, and 3 m source data lines and n gate scan lines are required. If the channels of the data driver and the scan driver are a and b, respectively, the number of required data drivers and scan drivers is 3 m/a and n/b, respectively.
  • the data driver is relatively expensive compared to the scan driver, and the number of data drivers is large, resulting in high production costs.
  • a common solution is to arrange the R pixel electrode, the G pixel electrode, and the B pixel electrode in the scanning line direction, respectively.
  • m data lines and 3n scan lines are required, correspondingly required data drivers and sweeps
  • the number of drivers is m/a and 3n/b, respectively, and the number of data drivers is reduced by 1/3, so the cost can be reduced to some extent, but the number of scan drivers is increased by three times, which is also not conducive to cost. The reduction.
  • the resolution of the liquid crystal display device is proportional to the number of gate scan lines.
  • the present invention provides a gate side fan-out area circuit structure, including: a first circuit module, a second circuit module, a third circuit module, and a first transistor; a gate connection of the first transistor a first input end, a drain and a source are respectively connected to the second input end and the Nth stage gate scan line, and N is a natural number;
  • the first terminal of the first circuit module is connected to the first input end, the second terminal is connected to the second input end, and the third terminal is connected to the N+1th level gate scan line;
  • the first terminal and the second terminal of the second circuit module are connected to the second input end, and the third terminal Connecting the Nth-level gate scan line;
  • the first terminal and the second terminal of the third circuit module are connected to the second input end, and the third terminal is connected to the N+1th level gate scan line;
  • the periodic square wave is input from the first input end, and the gate scan signal is input from the second input end, and the period of the periodic square wave is twice the scanning period of the gate scan signal;
  • the second terminal and the third terminal are cut off; when the first terminal of the first circuit module is When the input voltage is equal to the second amplitude voltage of the periodic square wave, the second terminal and the third terminal are electrically connected;
  • the second terminal and the third terminal are cut off; when the first terminal of the second circuit module When the input voltage is equal to the second amplitude voltage of the periodic square wave, the second terminal and the third terminal are electrically connected;
  • the first transistor (T1) is an NMOS transistor.
  • the circuit structure of the first circuit module, the second circuit module and the third circuit module is the same.
  • the first circuit module includes a second NMOS transistor and a third NMOS transistor; a gate of the second NMOS transistor serves as a first terminal of the first circuit module, and a source and a drain respectively input the first amplitude voltage And a second amplitude voltage; a gate of the third NMOS transistor is input to the first amplitude voltage, and a source and a drain are respectively used as a second terminal and a third terminal of the first circuit module.
  • the second circuit module includes a second NMOS transistor and a third NMOS transistor; the gate of the second NMOS transistor serves as a first terminal of the second circuit module, and the source and the drain respectively input the first amplitude voltage And a second amplitude voltage; a gate of the third NMOS transistor inputs the first amplitude voltage, and a source and a drain respectively serve as a second terminal and a third terminal of the second circuit module.
  • the third circuit module includes a second NMOS transistor and a third NMOS transistor; the gate of the second NMOS transistor serves as a first terminal of the third circuit module, and the source and the drain respectively input the first amplitude voltage And a second amplitude voltage; a gate of the third NMOS transistor is input to the first amplitude voltage, and a source and a drain are respectively used as second terminals of the third circuit module The third terminal of the mouth.
  • the first amplitude voltage is preferably 3.3V.
  • the second amplitude voltage is preferably -7V.
  • the first amplitude voltage and the second amplitude voltage are used to control the first circuit module, and the second circuit module ⁇ and the third circuit module are turned on or not, so the specific value is not limited to 3.3V/-7V, Other suitable values may be selected, preferably selected from existing gate side circuit voltage design specifications.
  • the gate scan signal is from a G-COF chip.
  • the gate scan signal is from a gate driving circuit.
  • the present invention also provides a gate side fan-out area circuit structure, comprising: a first circuit module, a second circuit module, a third circuit module, and a first transistor;
  • the gate of the first transistor is connected to the first input end, and the drain and the source are respectively connected to the second input end and the Nth stage gate scan line, where N is a natural number;
  • the first terminal of the first circuit module is connected to the first input end, the second terminal is connected to the second input end, and the third terminal is connected to the N+1th level gate scan line;
  • the first terminal and the second terminal of the second circuit module are connected to the second input terminal, and the third terminal is connected to the Nth-level gate scan line;
  • the first terminal and the second terminal of the third circuit module are connected to the second input end, and the third terminal Connecting the N+l-level gate scan line;
  • the periodic square wave is input from the first input end, and the gate scan signal is input from the second input end, and the period of the periodic square wave is twice the scanning period of the gate scan signal;
  • the second terminal and the third terminal are cut off; when the first terminal of the first circuit module is When the input voltage is equal to the second amplitude voltage of the periodic square wave, the second terminal and the third terminal are electrically connected;
  • the second terminal and the third terminal are cut off; when the first terminal of the second circuit module When the input voltage is equal to the second amplitude voltage of the periodic square wave, the second terminal and the third terminal are electrically connected;
  • the second terminal and the third terminal are cut off; when the first terminal of the third circuit module is When the input voltage is equal to the second amplitude voltage of the periodic square wave, the second terminal and the third terminal are electrically connected;
  • the first transistor is an NMOS transistor
  • the first circuit module includes a second NMOS transistor and a third NMOS transistor; a gate of the second NMOS transistor serves as a first terminal of the first circuit module, and a source and a drain respectively input the first amplitude voltage And a second amplitude voltage; a gate of the third NMOS transistor is input to the first amplitude voltage, and a source and a drain are respectively used as a second terminal and a third terminal of the first circuit module;
  • the second circuit module includes a second NMOS transistor and a third NMOS transistor; the gate of the second NMOS transistor serves as a first terminal of the second circuit module, and the source and the drain respectively input the first amplitude voltage And a second amplitude voltage; a gate of the third NMOS transistor is input to the first amplitude voltage, and a source and a drain are respectively used as a second terminal and a third terminal of the second circuit module;
  • the third circuit module includes a second NMOS transistor and a third NMOS transistor; the gate of the second NMOS transistor serves as a first terminal of the third circuit module, and the source and the drain respectively input the first amplitude voltage And a second amplitude voltage; a gate of the third NMOS transistor is input to the first amplitude voltage, and a source and a drain are respectively used as a second terminal and a third terminal of the third circuit module.
  • the first amplitude voltage is 3.3V.
  • the second amplitude voltage is -7V.
  • the gate scan signal is from a G-COF chip.
  • the gate scan signal is from a gate drive circuit
  • the circuit structure of the gate side fan-out area of the present invention can greatly reduce the cost of the G-COF chip without adding additional equipment costs, thereby improving product quality and enhancing product competitiveness.
  • FIG. 1 is a schematic diagram of a TFT-LCD driving architecture in the prior art
  • FIG. 2 is a circuit schematic diagram of a circuit structure of a gate side fan-out area according to a preferred embodiment of the present invention
  • FIG. 3 is a circuit diagram of a circuit module used in the preferred embodiment
  • FIG. 4 is a waveform diagram of a periodic square wave used in the preferred embodiment. detailed description
  • FIG. 2 it is a circuit of a circuit structure of a gate side fan-out area according to the present invention.
  • the gate side fan-out area circuit structure of the preferred embodiment mainly includes: a first circuit module, a second circuit module, a third circuit module, and a first NMOS transistor T1; in the preferred embodiment, the first transistor T1 employs an NMOS transistor, and those skilled in the art will appreciate that other types of transistors that can replace the function of the NMOS transistor can also be selected as the invention;
  • the gate of the first NMOS transistor T1 is connected to the first input terminal A, and the drain and the source are respectively connected to the second input terminal B and the Nth gate scanning line N, and N is a natural number;
  • the first terminal 1 of the first circuit module is connected to the first input terminal A, the second terminal 2 is connected to the second input terminal B, and the third terminal 3 is connected to the N+1th level gate scanning line N+1;
  • the first terminal 1 and the second terminal 2 of the second circuit module are connected to the second input terminal B, and the third terminal 3 is connected to the Nth gate scanning line N;
  • the first terminal 1 and the second terminal 2 of the third circuit module are connected to the second input terminal B, and the third terminal 3 is connected to the N+1th level gate scanning line N+1;
  • a periodic square wave is input from the first input terminal A, and a gate scan signal is input from the second input terminal B, and the period of the periodic square wave is twice the scanning period of the gate scan signal;
  • the second terminal 2 and the third terminal 3 are cut off; when the first circuit module is When the input voltage of the first terminal 1 is equal to the second amplitude voltage of the periodic square wave, the second terminal 2 and the third terminal 3 are electrically connected;
  • the second terminal 2 and the third terminal 3 are cut off; when the second circuit module is When the input voltage of a terminal 1 is equal to the second amplitude voltage of the periodic square wave, the second terminal 2 and the third terminal 3 are electrically connected;
  • the second terminal 2 and the third terminal 3 are cut off; when the third circuit module is When the input voltage of one terminal 1 is equal to the second amplitude voltage of the periodic square wave, the second terminal 2 and the third terminal 3 are electrically connected.
  • FIG. 3 is a circuit structural diagram of a circuit module used in the preferred embodiment
  • FIG. 4 is a periodic square wave waveform diagram used in the preferred embodiment.
  • the first square A is a periodic square wave with an amplitude of 3.3V/-7V input to the first input terminal A, and the period is twice the scanning period of the gate scan line.
  • the signal input to the second input terminal B which may be the actual G-COF chip, may also be a signal from a similar gate driving circuit for outputting the gate scan signal.
  • the first circuit module, the second circuit module, and the third circuit module used in the present invention have the same functions, and when the input voltage of the one end is 3.3V, the cutoff between 2 and 3; when 1 When the input voltage of the terminal is -7V, the conduction between 2 and 3. Therefore, in order to simplify the circuit, the first circuit module, the second circuit module, and the third circuit module employ the same circuit configuration in this embodiment.
  • Each circuit module includes a second NMOS transistor T2 and a third NMOS transistor T3; a gate of the second NMOS transistor T2 serves as a first terminal 1 of each circuit module, and the source and the drain respectively input the first amplitude voltage and the first The second amplitude voltage; the gate of the third NMOS transistor T3 inputs the first amplitude voltage, and the source and the drain respectively serve as the second terminal 2 and the third terminal 3 of each circuit module.
  • the resistor R in FIG. 3 is the equivalent resistance when the NMOS is turned on.
  • the second circuit module and the third circuit module are turned off.
  • the output of the first input terminal A is 3.3V
  • the first circuit module is turned off, and the gate scan line N Output high voltage
  • the output of the gate scan line N+1 is 0
  • the output of the first input terminal A is -7V
  • the first circuit module is turned on, the gate scan line N outputs 0V
  • the gate scan line N+1 is output.
  • the output of the second input terminal B is a low voltage
  • the second circuit module and the third circuit module are turned on, and the gate scan line N and the gate scan line N+1 are both output as low voltages. That is, the 1-channel output of the existing G-COF chip can correspond to 2 scan lines.
  • the present invention solves the problem of increasing demand for resolution and product cost in the market.
  • a combination circuit between multiple NMOSs is used on the gate side fan-out area, and an additional structure is added to realize the 1-channel output corresponding to the G-COF chip.
  • the function of two scanning lines greatly reduces the cost of the G-COF chip without adding additional equipment costs, thereby improving product quality and enhancing product competitiveness.

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  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Liquid Crystal Display Device Control (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Liquid Crystal (AREA)

Abstract

一种栅极侧扇出区域电路结构包括：第一晶体管（Ｔ１），栅极连接第一输入端（Ａ），漏极和源极分别连接第二输入端（Ｂ）和第Ｎ级栅极扫描线（Ｎ）；第一电路模块的第一端子（１）连接第一输入端（Ａ），第二端子（２）连接第二输入端（Ｂ），第三端子（３）连接第Ｎ＋１级栅极扫描线（Ｎ＋１）；第二电路模块的第一端子（１）和第二端子（２）连接第二输入端（Ｂ），第三端子（３）连接第Ｎ级栅极扫描线（Ｎ）；第三电路模块的第一端子（１）和第二端子（２）连接该第二输入端（Ｂ），第三端子（３）连接该第Ｎ＋１级栅极扫描线（Ｎ＋１）；周期性方波自该第一输入端（Ａ）输入，栅极扫描信号自该第二输入端（Ｂ）输入。该电路结构可以大幅降低Ｇ－ＣＯＦ芯片成本。

Description

栅极侧扇出区域电踣结构 技术领域
本发明涉及液晶显示技术，尤其涉及一种栅极侧扇出区域电路结构。 背景技术
TFT-LCD ( Thin Film Transistor Liquid Crystal Display ,薄膜晶体管液 晶显示器 )是当前平板显示的主要品种之一，已经成为了现代 IT、 视讯产 品中重要的显示平台。 TFT-LCD使用薄膜晶体管 (thin-film transistor, TFT) 等主动式组件来控制每一像素单元的开启与关闭，并根据影像信号来控制 液晶材质对光线的穿透率以显示影像。 液晶显示器上设有包含像素阵列的 显示面板，及用来驱动液晶显示面板的驱动电路。 显示面板上设有多条平 行的数据线和扫描线，数据线和扫描线彼此垂直交错，且在交错处设有像 素单元及控制像素单元的薄膜晶体管开关。 驱动电路包含源极驱动器与栅 极驱动器，源极驱动器提供数据线相关于显示影像的信号，而栅极驱动器 提供扫描线开启或关闭薄膜晶体管的讯号。
如图 1所示，其为现有技术中 TFT-LCD驱动架构示意图，现有 TFT- LCD主要驱动原理包括：系统主板将 R/G/B压缩信号、 控制信号及动力通 过线材与 PCB板 1上的连接器 ( connector )相连接， PCB板通过 S-COF 芯片（ Source-Chip on Film ,薄膜上源极芯片 ) 2和 G-COF ( Gate-Chip on Film ,薄膜上栅极芯片）芯片 3与显示区域（ Display Area ) 4连接，从而 使得 LCD获得所需的电源、 以及信号。 为了实施窄边框设计，并因应电 子产品朝轻薄短小、 功能好及速度快发展，驱动芯片封装的技术也朝向厚 度愈薄、 面积愈小的趋势发展，栅极芯片及源极芯片都采用了薄膜上芯片 (Chip on Film , COF)型封装方式。 图 1中可见，扇出区域（ Fan Out Area ) 5是显示区域 4信号线路与驱动芯片连接的部分，栅极信号线及源极数据 线经由扇出区域 5连接至 S-COF芯片 2和 G-COF芯片 3 ,位于栅极驱动 芯片 G-COF芯片 3—侧的扇出区域 5可以称为栅极侧扇出区域。
在现有结构下，以分辨率为 mxn的液晶显示装置为例，需要 3m条源 极数据线，及 n条栅极扫描线。 若数据驱动器和扫描驱动器的通道分别为 a和 b ,则所需数据驱动器和扫描驱动器的数目分别为 3m/a和 n/b。 数据 驱动器相较扫描驱动器的价格比较高，数据驱动器的数目较多因而导致生 产成本较高。 一种通常的解决方案是将 R像素电极、 G像素电极以及 B 像素电极分别沿扫描线方向排列。 对于相同分辨率为 mxn的液晶显示装 置，则需要 m条数据线以及 3n条扫描线，对应地所需的数据驱动器和扫 描驱动器的数目分别是 m/a和 3n/b ,数据驱动器的数目减少了 1/3 ,因此 在一定程度上可降低成本，但是扫描驱动器的数目则增加为原来的 3倍， 也不利于成本的降低。
无论如何，液晶显示装置分辨率都与栅极扫描线数量成正比。 随着巿 场对液晶显示装置分辨率需求的上升，只能通过增加 G-COF颗数或者增 加单颗 G-COF 的输出通道（ Output Channel )数量来满足实际的应用需 求，造成产品成本的上升和绑定 ( Bonding )良率的下降。 发明内容
因此，本发明的目的在于提供一种可以降低 G-COF芯片成本的栅极 侧扇出区域电路设计方案。
为实现上述目的，本发明提供了一种栅极侧扇出区域电路结构，包 括：第一电路模块，第二电路模块，第三电路模块，以及第一晶体管； 该第一晶体管的栅极连接第一输入端，漏极和源极分别连接第二输入 端和第 N级栅极扫描线， N为自然数；
该第一电路模块的第一端子连接该第一输入端，第二端子连接该第二 输入端，第三端子连接第 N+1级栅极扫描线；
该第二电路模块的第一端子和第二端子连接该第二输入端，第三端子 连接该第 N级栅极扫描线；
该第三电路模块的第一端子和第二端子连接该第二输入端，第三端子 连接该第 N+1级栅极扫描线；
周期性方波自该第一输入端输入，栅极扫描信号自该第二输入端输 入，该周期性方波的周期为该栅极扫描信号的扫描周期的 2倍；
当该第一电路模块的第一端子的输入电压等于该周期性方波的第一幅 值电压时，其第二端子和第三端子之间截止；当该第一电路模块的第一端 子的输入电压等于该周期性方波的第二幅值电压时，其第二端子和第三端 子之间导通；
当该第二电路模块的第一端子的输入电压等于该周期性方波的第一幅 值电压时，其第二端子和第三端子之间截止；当该第二电路模块的第一端 子的输入电压等于该周期性方波的第二幅值电压时，其第二端子和第三端 子之间导通；
当该第三电路模块的第一端子的输入电压等于该周期性方波的第一幅 值电压时，其第二端子和第三端子之间截止；当该第三电路模块的第一端 子的输入电压等于该周期性方波的第二幅值电压时，其第二端子和第三端 子之间导通。 其中，该第一晶体管（ Tl )为 NM0S晶体管。
其中，该第一电路模块，第二电路模块及第三电路模块的电路结构相 同。
其中，该第一电路模块包括第二 NM0S 晶体管和第三 NM0S 晶体 管；该第二 NM0S晶体管的栅极作为该第一电路模块的第一端子，源极和 漏极分别输入该第一幅值电压和第二幅值电压；该第三 NM0S晶体管的栅 极输入该第一幅值电压，源极和漏极分别作为该第一电路模块的第二端子 禾口第三端子。
其中，该第二电路模块包括第二 NM0S 晶体管和第三 NMOS 晶体 管；该第二 NMOS晶体管的栅极作为该第二电路模块的第一端子，源极和 漏极分别输入该第一幅值电压和第二幅值电压；该第三 NMOS晶体管的栅 极输入该第一幅值电压，源极和漏极分别作为该第二电路模块的第二端子 禾口第三端子。
其中，该第三电路模块包括第二 NMOS 晶体管和第三 NMOS 晶体 管；该第二 NMOS晶体管的栅极作为该第三电路模块的第一端子，源极和 漏极分别输入该第一幅值电压和第二幅值电压；该第三 NMOS晶体管的栅 极输入该第一幅值电压，源极和漏极分别作为该第三电路模块的第二端子 禾口第三端子。
其中，该第一幅值电压优选为 3.3V。
其中，该第二幅值电压优选为 -7V。
该第一幅值电压及第二幅值电压用于控制第一电路模块，第二电路模 ±夬及第三电路模块导通与否，因此其具体取值不限于 3.3V/-7V ,也可选用 其它适当的值，优选从现有的栅极侧电路电压设计规格中选取。
其中，所述栅极扫描信号来自 G-COF芯片。
其中，所述栅极扫描信号来自栅极驱动电路。
本发明还提供一种栅极侧扇出区域电路结构，包括：第一电路模块， 第二电路模块，第三电路模块，以及第一晶体管；
该第一晶体管的栅极连接第一输入端，漏极和源极分别连接第二输入 端和第 N级栅极扫描线， N为自然数；
该第一电路模块的第一端子连接该第一输入端，第二端子连接该第二 输入端，第三端子连接第 N+1级栅极扫描线；
该第二电路模块的第一端子和第二端子连接该第二输入端，第三端子 连接该第 N级栅极扫描线；
该第三电路模块的第一端子和第二端子连接该第二输入端，第三端子 连接该第 N+l级栅极扫描线；
周期性方波自该第一输入端输入，栅极扫描信号自该第二输入端输 入，该周期性方波的周期为该栅极扫描信号的扫描周期的 2倍；
当该第一电路模块的第一端子的输入电压等于该周期性方波的第一幅 值电压时，其第二端子和第三端子之间截止；当该第一电路模块的第一端 子的输入电压等于该周期性方波的第二幅值电压时，其第二端子和第三端 子之间导通；
当该第二电路模块的第一端子的输入电压等于该周期性方波的第一幅 值电压时，其第二端子和第三端子之间截止；当该第二电路模块的第一端 子的输入电压等于该周期性方波的第二幅值电压时，其第二端子和第三端 子之间导通；
当该第三电路模块的第一端子的输入电压等于该周期性方波的第一幅 值电压时，其第二端子和第三端子之间截止；当该第三电路模块的第一端 子的输入电压等于该周期性方波的第二幅值电压时，其第二端子和第三端 子之间导通；
其中，该第一晶体管为 NMOS晶体管；
其中，该第一电路模块，第二电路模块及第三电路模块的电路结构相 同；
其中，该第一电路模块包括第二 NM0S 晶体管和第三 NMOS 晶体 管；该第二 NMOS晶体管的栅极作为该第一电路模块的第一端子，源极和 漏极分别输入该第一幅值电压和第二幅值电压；该第三 NMOS晶体管的栅 极输入该第一幅值电压，源极和漏极分别作为该第一电路模块的第二端子 禾口第三端子；
其中，该第二电路模块包括第二 NMOS 晶体管和第三 NMOS 晶体 管；该第二 NMOS晶体管的栅极作为该第二电路模块的第一端子，源极和 漏极分别输入该第一幅值电压和第二幅值电压；该第三 NMOS晶体管的栅 极输入该第一幅值电压，源极和漏极分别作为该第二电路模块的第二端子 禾口第三端子；
其中，该第三电路模块包括第二 NMOS 晶体管和第三 NMOS 晶体 管；该第二 NMOS晶体管的栅极作为该第三电路模块的第一端子，源极和 漏极分别输入该第一幅值电压和第二幅值电压；该第三 NMOS晶体管的栅 极输入该第一幅值电压，源极和漏极分别作为该第三电路模块的第二端子 禾口第三端子。
该第一幅值电压为 3.3V。 该第二幅值电压为 -7V。
所述栅极扫描信号来自 G-COF芯片。
所述栅极扫描信号来自栅极驱动电路
综上所述，本发明栅极侧扇出区域电路结构可以大幅降 ί氏 G-COF芯 片成本，且不会增加额外的设备成本，从而提升产品品质，提升产品竞争 力。 附图说明
下面结合附图，通过对本发明的具体实施方式详细描述，将使本发明 的技术方案及其他有益效果显而易见。
附图中，
图 1为现有技术中 TFT-LCD驱动架构示意图；
图 2为本发明栅极侧扇出区域电路结构一较佳实施例的电路原理图； 图 3为该较佳实施例中所采用电路模块的电路结构图；
图 4为该较佳实施例所采用的周期性方波波形图。 具体实施方式
参见图 2 ,其为本发明栅极侧扇出区域电路结构一较佳实施例的电路 原理图。 该较佳实施例的栅极侧扇出区域电路结构主要包括：第一电路模 块，第二电路模块，第三电路模块，以及第一 NMOS晶体管 T1；在此较 佳实施例中，第一晶体管 T1采用了 NMOS晶体管，本领域技术人员可以 理解，可以代替 NMOS晶体管功能的其它类型晶体管也可作为本发明的选 择；
该第一 NMOS晶体管 T1的栅极连接第一输入端 A ,漏极和源极分别 连接第二输入端 B和第 N级栅极扫描线 N , N为自然数；
该第一电路模块的第一端子 1连接该第一输入端 A ,第二端子 2连接 该第二输入端 B ,第三端子 3连接第 N+1级栅极扫描线 N+1；
该第二电路模块的第一端子 1和第二端子 2连接该第二输入端 B ,第 三端子 3连接该第 N级栅极扫描线 N；
该第三电路模块的第一端子 1和第二端子 2连接该第二输入端 B ,第 三端子 3连接该第 N+1级栅极扫描线 N+1；
周期性方波自该第一输入端 A输入，栅极扫描信号自该第二输入端 B 输入，该周期性方波的周期为该栅极扫描信号的扫描周期的 2倍；
当该第一电路模块的第一端子 1 的输入电压等于该周期性方波的第一 幅值电压时，其第二端子 2和第三端子 3之间截止；当该第一电路模块的 第一端子 1 的输入电压等于该周期性方波的第二幅值电压时，其第二端子 2和第三端子 3之间导通；
当该第二电路模块的第一端子 1 的输入电压等于该周期性方波的第一 幅值电压时，其第二端子 2和第三端子 3之间截止；当该第二电路模块的 第一端子 1 的输入电压等于该周期性方波的第二幅值电压时，其第二端子 2和第三端子 3之间导通；
当该第三电路模块的第一端子 1 的输入电压等于该周期性方波的第一 幅值电压时，其第二端子 2和第三端子 3之间截止；当该第三电路模块的 第一端子 1 的输入电压等于该周期性方波的第二幅值电压时，其第二端子 2和第三端子 3之间导通。
再结合图 3和图 4来理解本发明，图 3为该较佳实施例中所采用电路 模块的电路结构图，图 4为该较佳实施例所采用的周期性方波波形图。 其 中，输入第一输入端 A的为幅值 3.3V/-7V的周期性方波，其周期为栅极 扫描线扫描周期的 2倍。 输入第二输入端 B的可以为实际的 G-COF芯片 所输出的信号，也可以是来自类似的用于输出栅极扫描信号的栅极驱动电 路的信号。 本发明所采用的第一电路模块，第二电路模块，及第三电路模 块的功能相同，均是当 1端的输入电压为 3.3V时， 2与 3之间截止；当 1 端的输入电压为 -7V时， 2与 3之间导通。 因此，为了简化电路，在此实 施例中第一电路模块，第二电路模块，及第三电路模块采用了相同的电路 结构。 各电路模块包括第二 NMOS晶体管 T2和第三 NMOS晶体管 T3； 该第二 NMOS晶体管 T2的栅极作为各电路模块的第一端子 1 ,源极和漏 极分别输入该第一幅值电压和第二幅值电压；该第三 NMOS晶体管 T3的 栅极输入该第一幅值电压，源极和漏极分别作为各电路模块的第二端子 2 和第三端子 3。 图 3中的电阻 R为 NMOS导通时的等效电阻。 本领域技术 人员可以理解，其它可以实现类似功能的电路模块也适用于本发明。
系统工作中，当第二输入端 B输出为高电压时，第二电路模块，第三 电路模块截止，当第一输入端 A输出为 3.3V时，第一电路模块截止，栅 极扫描线 N输出高电压，栅极扫描线 N+1输出为 0 ；当第一输入端 A输 出为 -7V时，第一电路模块导通，栅极扫描线 N输出 0V ,栅极扫描线 N+1输出为高电压；当第二输入端 B输出为低电压时，第二电路模块，第 三电路模块导通，栅极扫描线 N和栅极扫描线 N+1 均输出为低电压。 即，利用现有 G-COF 芯片的 1 通道输出可以对应 2 条扫描线（ Scan Line )。
综上所述，本发明为解决巿场对分辨率需求的不断提高与产品成本需 要持续减低的矛盾，在传统 G-COF芯片的设计基础上，在栅极侧扇出区 域上利用多个 NMOS之间的组合电路，增加额外结构以实现利用 G-COF 芯片的 1通道输出对应 2条扫描线的功能，大幅降低 G-COF芯片成本， 且不会增加额外的设备成本，从而提升产品品质，提升产品竞争力。
以上所述，对于本领域的普通技术人员来说，可以根据本发明的技术 方案和技术构思作出其他各种相应的改变和变形，而所有这些改变和变形 都应属于本发明后附的权利要求的保护范围。

Claims

杈 利 要 求
1、 一种栅极侧扇出区域电路结构，包括：第一电路模块，第二电路 模块，第三电路模块，以及第一晶体管；
该第一晶体管的栅极连接第一输入端，漏极和源极分别连接第二输入 端和第 N级栅极扫描线， N为自然数；
该第一电路模块的第一端子连接该第一输入端，第二端子连接该第二 输入端，第三端子连接第 N+1级栅极扫描线；
该第二电路模块的第一端子和第二端子连接该第二输入端，第三端子 连接该第 N级栅极扫描线；
该第三电路模块的第一端子和第二端子连接该第二输入端，第三端子 连接该第 N+1级栅极扫描线；
周期性方波自该第一输入端输入，栅极扫描信号自该第二输入端输 入，该周期性方波的周期为该栅极扫描信号的扫描周期的 2倍；
当该第一电路模块的第一端子的输入电压等于该周期性方波的第一幅 值电压时，其第二端子和第三端子之间截止；当该第一电路模块的第一端 子的输入电压等于该周期性方波的第二幅值电压时，其第二端子和第三端 子之间导通； 当该第二电路模块的第一端子的输入电压等于该周期性方波的第一幅 值电压时，其第二端子和第三端子之间截止；当该第二电路模块的第一端 子的输入电压等于该周期性方波的第二幅值电压时，其第二端子和第三端 子之间导通；
当该第三电路模块的第一端子的输入电压等于该周期性方波的第一幅 值电压时，其第二端子和第三端子之间截止；当该第三电路模块的第一端 子的输入电压等于该周期性方波的第二幅值电压时，其第二端子和第三端 子之间导通。
2、 如权利要求 1 所述的栅极侧扇出区域电路结构，其中，该第一晶 体管为 NMOS晶体管。
3、 如权利要求 1 所述的栅极侧扇出区域电路结构，其中，该第一电 路模块，第二电路模块及第三电路模块的电路结构相同。
4、 如权利要求 1 所述的栅极侧扇出区域电路结构，其中，该第一电 路模块包括第二 NMOS晶体管和第三 NMOS晶体管；该第二 NMOS晶体 管的栅极作为该第一电路模块的第一端子，源极和漏极分别输入该第一幅 值电压和第二幅值电压；该第三 NMOS 晶体管的栅极输入该第一幅值电 压，源极和漏极分别作为该第一电路模块的第二端子和第三端子。
5、 如权利要求 1 所述的栅极侧扇出区域电路结构，其中，该第二电 路模块包括第二 NMOS晶体管和第三 NMOS晶体管；该第二 NMOS晶体 管的栅极作为该第二电路模块的第一端子，源极和漏极分别输入该第一幅 值电压和第二幅值电压；该第三 NMOS 晶体管的栅极输入该第一幅值电 压，源极和漏极分别作为该第二电路模块的第二端子和第三端子。
6、 如权利要求 1 所述的栅极侧扇出区域电路结构，其中，该第三电 路模块包括第二 NMOS晶体管和第三 NMOS晶体管；该第二 NMOS晶体 管的栅极作为该第三电路模块的第一端子，源极和漏极分别输入该第一幅 值电压和第二幅值电压；该第三 NMOS 晶体管的栅极输入该第一幅值电 压，源极和漏极分别作为该第三电路模块的第二端子和第三端子。
7、 如权利要求 1 所述的栅极侧扇出区域电路结构，其中，该第一幅 值电压为 3.3V。
8、 如权利要求 1 所述的栅极侧扇出区域电路结构，其中，该第二幅 值电压为 -7V。
9、 如权利要求 1 所述的栅极侧扇出区域电路结构，其中，所述栅极 扫描信号来自 G-COF芯片。
10、 如权利要求 1所述的栅极侧扇出区域电路结构，其中，所述栅极 扫描信号来自栅极驱动电路。
11、 一种栅极侧扇出区域电路结构，包括：第一电路模块，第二电路 模块，第三电路模块，以及第一晶体管；
该第一晶体管的栅极连接第一输入端，漏极和源极分别连接第二输入 端和第 N级栅极扫描线， N为自然数；
该第一电路模块的第一端子连接该第一输入端，第二端子连接该第二 输入端，第三端子连接第 N+1级栅极扫描线；
该第二电路模块的第一端子和第二端子连接该第二输入端，第三端子 连接该第 N级栅极扫描线；
该第三电路模块的第一端子和第二端子连接该第二输入端，第三端子 连接该第 N+1级栅极扫描线；
周期性方波自该第一输入端输入，栅极扫描信号自该第二输入端输 入，该周期性方波的周期为该栅极扫描信号的扫描周期的 2倍；
当该第一电路模块的第一端子的输入电压等于该周期性方波的第一幅 值电压时，其第二端子和第三端子之间截止；当该第一电路模块的第一端 子的输入电压等于该周期性方波的第二幅值电压时，其第二端子和第三端 子之间导通； 当该第二电路模块的第一端子的输入电压等于该周期性方波的第一幅 值电压时，其第二端子和第三端子之间截止；当该第二电路模块的第一端 子的输入电压等于该周期性方波的第二幅值电压时，其第二端子和第三端 子之间导通；
当该第三电路模块的第一端子的输入电压等于该周期性方波的第一幅 值电压时，其第二端子和第三端子之间截止；当该第三电路模块的第一端 子的输入电压等于该周期性方波的第二幅值电压时，其第二端子和第三端 子之间导通；
其中，该第一晶体管为 NMOS晶体管；
其中，该第一电路模块，第二电路模块及第三电路模块的电路结构相 同；
其中，该第一电路模块包括第二 NMOS 晶体管和第三 NMOS 晶体 管；该第二 NMOS晶体管的栅极作为该第一电路模块的第一端子，源极和 漏极分别输入该第一幅值电压和第二幅值电压；该第三 NMOS晶体管的栅 极输入该第一幅值电压，源极和漏极分别作为该第一电路模块的第二端子 禾口第三端子；
其中，该第二电路模块包括第二 NMOS 晶体管和第三 NMOS 晶体 管；该第二 NMOS晶体管的栅极作为该第二电路模块的第一端子，源极和 漏极分别输入该第一幅值电压和第二幅值电压；该第三 NMOS晶体管的栅 极输入该第一幅值电压，源极和漏极分别作为该第二电路模块的第二端子 禾口第三端子；
其中，该第三电路模块包括第二 NMOS 晶体管和第三 NMOS 晶体 管；该第二 NMOS晶体管的栅极作为该第三电路模块的第一端子，源极和 漏极分别输入该第一幅值电压和第二幅值电压；该第三 NMOS晶体管的栅 极输入该第一幅值电压，源极和漏极分别作为该第三电路模块的第二端子 禾口第三端子。
12、 如权利要求 11 所述的栅极侧扇出区域电路结构，其中，该第一 幅值电压为 3.3V0
13、 如权利要求 11 所述的栅极侧扇出区域电路结构，其中，该第二 幅值电压为 -7V。
14、 如权利要求 11 所述的栅极侧扇出区域电路结构，其中，所述栅 极扫描信号来自 G-COF芯片。
15、 如权利要求 11 所述的栅极侧扇出区域电路结构，其中，所述栅 极扫描信号来自栅极驱动电路。
PCT/CN2014/078673 2014-05-12 2014-05-28 栅极侧扇出区域电路结构 Ceased WO2015172406A1 (zh)

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