WO2015168370A1 - Structure et procédé permettant de préparer un boîtier pour accepter un composant d'une carte de circuit imprimé à composant incorporé - Google Patents

Structure et procédé permettant de préparer un boîtier pour accepter un composant d'une carte de circuit imprimé à composant incorporé Download PDF

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Publication number
WO2015168370A1
WO2015168370A1 PCT/US2015/028453 US2015028453W WO2015168370A1 WO 2015168370 A1 WO2015168370 A1 WO 2015168370A1 US 2015028453 W US2015028453 W US 2015028453W WO 2015168370 A1 WO2015168370 A1 WO 2015168370A1
Authority
WO
WIPO (PCT)
Prior art keywords
printed circuit
circuit board
subassembly
foil
vias
Prior art date
Application number
PCT/US2015/028453
Other languages
English (en)
Inventor
Dhanonjaya TURPUSEEMA
Thomas P. Warwick
Thomas Smith
James V. Russell
Original Assignee
R&D Circuits, Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by R&D Circuits, Inc filed Critical R&D Circuits, Inc
Publication of WO2015168370A1 publication Critical patent/WO2015168370A1/fr

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Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
    • H05K1/185—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit
    • H05K1/188—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit manufactured by mounting on or attaching to a structure having a conductive layer, e.g. a metal foil, such that the terminals of the component are connected to or adjacent to the conductive layer before embedding, and by using the conductive layer, which is patterned after embedding, at least partially for connecting the component
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/14—Structural association of two or more printed circuits
    • H05K1/144—Stacked arrangements of planar printed circuit boards
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
    • H05K1/183—Components mounted in and supported by recessed areas of the printed circuit board
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0011—Working of insulating substrates or insulating layers
    • H05K3/0017—Etching of the substrate by chemical or physical means
    • H05K3/0026—Etching of the substrate by chemical or physical means by laser ablation
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0094—Filling or covering plated through-holes or blind plated vias, e.g. for masking or for mechanical reinforcement
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/321—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by conductive adhesives
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/36—Assembling printed circuits with other printed circuits
    • H05K3/366—Assembling printed circuits with other printed circuits substantially perpendicularly to each other
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H05K3/4652—Adding a circuit layer by laminating a metal foil or a preformed metal foil pattern
    • H05K3/4655—Adding a circuit layer by laminating a metal foil or a preformed metal foil pattern by using a laminate characterized by the insulating layer
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H05K3/4679—Aligning added circuit layers or via connections relative to previous circuit layers
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
    • H05K1/185—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit
    • H05K1/186—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit manufactured by mounting on or connecting to patterned circuits before or during embedding
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/03—Conductive materials
    • H05K2201/032—Materials
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/03—Conductive materials
    • H05K2201/0332—Structure of the conductor
    • H05K2201/0335—Layered conductors or foils
    • H05K2201/0355—Metal foils
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/04—Assemblies of printed circuits
    • H05K2201/042—Stacked spaced PCBs; Planar parts of folded flexible circuits having mounted components in between or spaced from each other
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/095—Conductive through-holes or vias
    • H05K2201/09509—Blind vias, i.e. vias having one side closed
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/095—Conductive through-holes or vias
    • H05K2201/09536—Buried plated through-holes, i.e. plated through-holes formed in a core before lamination
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/095—Conductive through-holes or vias
    • H05K2201/09545—Plated through-holes or blind vias without lands
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/095—Conductive through-holes or vias
    • H05K2201/09572—Solder filled plated through-hole in the final product
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/04—Soldering or other types of metallurgic bonding
    • H05K2203/0485—Tacky flux, e.g. for adhering components during mounting
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/06—Lamination
    • H05K2203/063—Lamination of preperforated insulating layer
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/11—Treatments characterised by their effect, e.g. heating, cooling, roughening
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49128—Assembling formed circuit to base
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.
    • Y10T29/49139—Assembling to base an electrical component, e.g., capacitor, etc. by inserting component lead or terminal into base aperture
    • Y10T29/4914—Assembling to base an electrical component, e.g., capacitor, etc. by inserting component lead or terminal into base aperture with deforming of lead or terminal

Definitions

  • the present application relates to a structure and a method for preparing a housing to accept a component for an embedded printed circuit board and for an inter-level interconnect system.
  • the present invention in particular provides for a structure for an electrical interconnect for an embedded printed circuit board or for an embedded multilayered printed circuit board.
  • the present invention provides a mechanism for improving printed circuit board embedded component performance, ease of manufacture and the use of vertical space required for embedding components.
  • Embedded component technology places commercially available components, such as surface mount ceramic capacitors, surface mount resistors, and surface mount inductors inside the printed circuit board and in close proximity to connecting integrated circuits or other components. This provides greater circuit density and better electrical performance due to the shorter electrical lengths.
  • Prior art for embedded components require that the material surrounding the components be non-circuit layers. This creates three electrical and mechanical concerns:
  • the wasted vertical space drives large line widths for signal traces within the pc board that connect to the embedded component. This impedes routing and signal fidelity for escapes through a via field with a tight pitch (such as a large BGA device mounted above the embedded component).
  • the present invention provides a structure and a method for an electrical interconnect structure for a single or multilayered printed circuit board to create a reliable high performance connection between signal traces and power/ground plane or planes that occupy the same vertical space as an embedded component such as a capacitor or a resistor.
  • the present invention provides for a sub-lamination containing the embedded component that may have a number of metallic and non-conductive layers, as required by the application while easing the orientation and securing the component through the manufacturing process. This is a critical difference between this disclosure and prior art.
  • the component terminals connect to these layers electrically through plating, micro- machining, and the use of conductive materials.
  • FIG. 1 is a first embodiment of the present invention for a single layer, two sided or subassembly of an embedded printed circuit board (PCB);
  • FIG. 2 is the first embodiment shown in FIG. 1 with lamination and cure of the embedded PCB or subassembly;
  • FIG. 3 is a second embodiment of the present invention with unclad dielectric carrier built-up on a single, or multilayer PCB;
  • FIG. 4 is a third embodiment of the present invention wherein internal or external layers of the carrier are connected to end points or terminals of embedded components of either a single or multilayer PCBs;
  • FIG. 5 is a fourth embodiment of the present invention wherein instead of having internal or external layers connected to end points or terminals of embedded components of either a single or multilayer PCBs as in FIG. 4, adjacent vias are provided to bring the internal layer connections to the top or bottom of the dielectric material for solder, conductive paste or sinter paste bridging between the adjacent vias pad and the end point or terminals of the embedded component;
  • FIGS.1-2 describe a first
  • a lamination adhesive or prepreg 2 is applied to a conductive foil 3 preferably a copper foil with the adhesive being partially cured as to provide adhesion to the foil but also allow it to flow again through additional lamination steps.
  • This partial cure time, pressure and temperature will be dependent on the types of adhesive and vary from application to application but for purposes of a non- limiting example an Issola FR408 1080 prepreg requires approximately 125 pounds per square inch pressure, at 155 degrees Fahrenheit for 30 minutes.
  • Vias 9 are formed through the adhesive 2 to expose the copper foil 3. It is understood that these vias may be formed with laser drilling, mechanically drilling, plasma etching, use of photo definable liquid dialectic or any other methods known in the art.
  • the vias 9 are filled with conductive epoxy, sintering paste or solder paste 4.
  • An unclad dielectric material 1 with cut outs 6 of an approximate shape, preferably slightly larger (1 to 3 mils), than the intended embedded component or components 5, with the proper orientation is/are tack bonded or laminated as shown in figure 2.
  • the approximate shapes and sizes of the cut outs 6 for the present invention can vary and be any shape or preferred geometric shape including preferably but not limited to rectangular shapes.
  • This partial cure time, pressure and temperature will be dependent on the types of adhesive and will vary with the type and thickness of the particular prepeg chosen based on the known manufacturing specifications for that chosen prepeg but by way of a non-limiting illustrative example the present invention can use but is not limited to using an Issola FR408 1080 prepreg that requires approximately 75 pounds per square inch pressure, at 150 degrees
  • the said cuts outs in the said unclad material as well as the said unclad material when bonded is/are oriented in order to locate the end points or terminals of the intended embedded components 5 to the vias 9 that are filled with paste
  • the unclad dielectric material 1 with cutouts 6 are populated with components 5 using the cutouts 6 as a guide and a protective housing to keep the components 5 in place for the next operation.
  • another copper foil 3 is prepared similar to the first foil with conductive paste, sintering paste or solder 4 in the vias 9.
  • the second foil is then laminated to the top of the unclad material 1 through a curing process.
  • This final cure time, temperature and pressure will be dependent on the types of adhesive but for purposes of a non-limiting example an Issola FR408 1080 prepreg requires approximately 200 PSI, at 376F for 90 minutes.
  • either or both of the foils described could be replaced with single or multilayered printed circuit boards or subassemblies. These subassemblies pads and or vias would be aligned to the end points or terminals of the embedded components 5 to provide electrical connection through the subassembly circuits and the embedded components 5.
  • the unclad dielectric material 1 could be a single or multilayered printed circuit board with internal and/or external, power, ground and signal layers and optionally through blind or buried vias. Further, these internal and or external layers may be connected to the end points or terminals of the embedded components through selective metal plating the side walls 1 1 of the cutouts 6 that house the embedded components 5.
  • adjacent viasl 2 can be provided that bring the internal layer connections to the top or bottom of the dielectric material 1 for solder, conductive paste or sinter paste 4 bridging between the adjacent vias or pads 12 and the end point or terminals of the embedded components 5.
  • the cavities or cutouts 6 for the embedded components 5 are micro-machined prior to plating.
  • the entire cut out 6 is thus plated and completes the normal printed circuit board process for the sub- lamination. This electrically shorts all connecting points for component 5 terminals together.
  • a micro-machining step cuts away electrically conductive metal plating between the terminal connections in the printed circuit board. This electrically isolates each pad appropriately.
  • the component 5 is then inserted into the cavity 6 and pressed flat.
  • the sub-lamination booklet is then completed with build-up layers - first non- conductive layers, followed by a metallic pad layer, and then heat pressed and cured.
  • the non-conductive layer was first micro-machined with openings or vias, followed by a conductive attach material being placed into these openings or vias.
  • the component 5 thus attaches to the plated side-walls 1 1 and/or to outer plating (metallic pads) during the curing process of the booklet/sub-lamination whereby the conductive attached material 4 (i.e. conductive epoxies, sintered pastes, solder paste) bridge the plated side wall and end points of the component 5.
  • the conductive attached material 4 i.e. conductive epoxies, sintered pastes, solder paste
  • the single or multilayer PCB1 A. aligns the embedded component or components to the paste or solder 4.
  • the structure of the embodiment of FIG. 4 of the present invention uses a printed circuit board sub-lamination created to be approximately the same thickness or slightly thinner by -.001 as the targeted commercially available component.
  • FIG. 4 shows an alternate embodiment in which the structure is nearly identical to the process for the structure in FIG. 5.
  • the sub-lamination contains any number of metallic and non-conductive layers, as required by the application.
  • drilled and plated through vias or blind vias exist.
  • a precision micro-drilling mechanism cuts an appropriate opening the size and shape of the component 5 to be embedded.
  • the micro-machining method may cut in approximately half or castellate the via, leaving one-half of it intact.
  • the cut out end points can come into close proximity to the vias then the commercially available component 5 is inserted into the cavity 6 and pressed flat.
  • the sub-lamination booklet is then completed with surface build-up layers - first non-conductive layers, followed by a metallic pad layer, and then heated, pressed and cured.
  • the non-conductive layer was first micro-machined with openings, followed by a conductive attach material being placed into these openings.
  • the embedded component 5 thus attaches to the cut out or castellated vias 6 or to the outer plating (metallic pads) during the curing process of the booklet/sub-lamination whereby the conductive adhesive (i.e. conductive epoxies, sintered pastes, solder paste) bridge the pads and or half vias and end points of the component 5 .

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

L'invention concerne un procédé et une structure d'interconnexion électrique interne à une carte de circuit imprimé dans le but de créer un procédé de connexion fiable et à haut rendement entre des bornes de composant incorporé, des tracés de signal et/ou des plans d'alimentation/de masse qui peuvent occuper le même espace vertical que les composants incorporés, tels qu'un condensateur ou une résistance. L'invention a pour objectif de faciliter l'assemblage et d'augmenter la fiabilité pendant le processus de fabrication desdites structures de composant incorporé. Selon une structure, des trous d'interconnexion crénelés, percés et plaqués raccordent le tracé ou le plan de la carte de circuit imprimé aux bornes électriques du composant incorporé à l'aide d'un matériau de fixation permanent hautement conducteur. Selon une autre structure, le tracé ou le plan est connecté par placage sélectif de paroi latérale, qui entoure la borne électrique du composant. Cette structure utilise également un matériau de fixation permanent et hautement conducteur pour raccorder électriquement le composant terminal à la paroi latérale plaquée et, selon un dernier mode de réalisation, les bornes sont raccordées au moyen d'un matériau de fixation conducteur à travers un trou d'interconnexion dans l'axe z à un plot conducteur.
PCT/US2015/028453 2014-05-02 2015-04-30 Structure et procédé permettant de préparer un boîtier pour accepter un composant d'une carte de circuit imprimé à composant incorporé WO2015168370A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US201461987585P 2014-05-02 2014-05-02
US61/987,585 2014-05-02

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US (1) US20150319863A1 (fr)
TW (1) TW201545614A (fr)
WO (1) WO2015168370A1 (fr)

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