WO2015143902A1 - 一种多量子阱结构及采用该结构的发光二极管 - Google Patents

一种多量子阱结构及采用该结构的发光二极管 Download PDF

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WO2015143902A1
WO2015143902A1 PCT/CN2014/094873 CN2014094873W WO2015143902A1 WO 2015143902 A1 WO2015143902 A1 WO 2015143902A1 CN 2014094873 W CN2014094873 W CN 2014094873W WO 2015143902 A1 WO2015143902 A1 WO 2015143902A1
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layer
quantum well
well structure
structure according
multiple quantum
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PCT/CN2014/094873
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English (en)
French (fr)
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刘志彬
陈沙沙
张东炎
刘晓峰
王笃祥
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厦门市三安光电科技有限公司
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Publication of WO2015143902A1 publication Critical patent/WO2015143902A1/zh
Priority to US15/175,528 priority Critical patent/US9997665B2/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/04—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction
    • H01L33/06—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction within the light emitting region, e.g. quantum confinement structure or tunnel barrier
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0062—Processes for devices with an active region comprising only III-V compounds
    • H01L33/0075—Processes for devices with an active region comprising only III-V compounds comprising nitride compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/04—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/26—Materials of the light emitting region
    • H01L33/30—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table
    • H01L33/32—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table containing nitrogen
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/26—Materials of the light emitting region
    • H01L33/30—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table
    • H01L33/32—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table containing nitrogen
    • H01L33/325—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table containing nitrogen characterised by the doping materials

Definitions

  • This invention relates to microelectronic devices and, more particularly, to structures that can be used in Group III nitride semiconductor devices, such as light emitting diodes.
  • LEDs Light-emitting diodes
  • the GaN-based epitaxial wafer grown on the substrate is the core component of the LED and determines the performance of the LED product.
  • an LED epitaxial wafer mainly includes a substrate, an N-type conductive layer, a stress releasing layer, a light emitting layer, an electron blocking layer, a P-type conductive layer, and a P-type contact layer.
  • the structure of the light-emitting layer and the quality of the crystal play a decisive role in the photoelectric performance of the semiconductor device.
  • the III-nitride-based semiconductor device since the material and composition of the quantum well layer are different from those of the N-type conductive layer and the quantum barrier layer, stress is generated in the quantum well layer, so that quantum wells and quantum are present. Polarized charges are generated at the interface of the barrier to form a polarization field.
  • the polarization field causes a quantum Stark effect in the quantum well layer, which separates the electron from the hole wave function, reducing its photoelectric conversion efficiency, thereby reducing the light extraction efficiency.
  • a Chinese patent application CN102760808A discloses a structure of a light-emitting region, which mainly divides a quantum barrier layer into three layers, a GaN material on both sides and an AlInGaN material on the intermediate layer for releasing stress in the quantum well layer.
  • the stress release in the quantum well is not complete.
  • a method of growing a Group III nitride film on a non-polar or semi-polar plane to reduce the polarization charge in a quantum well is disclosed in Chinese Patent Application No. CN 102449737A.
  • the quantum wells in the non-polar or semi-polar plane have little polarization charge, the polarization field is small, and the quantum well band is weakened.
  • the light emitting diode structure of the present invention may include, in order from bottom to top, a substrate, a buffer layer, an N-type conductive layer, a stress relief layer, a light-emitting region, an electron blocking layer, a P-type conductive layer, and a P-type contact layer.
  • the N-type conductive layer is made of an n-type doped Group III nitride; the P-type conductive layer is made of a P-type doped Group III nitride.
  • the light emitting region has at least one quantum well structure including: a first protective layer based on a group III nitride, a first transition layer based on a group III nitride on the first protective layer, on the first transition layer a III-nitride-based well layer, a III-nitride-based second transition layer on the quantum well layer, a III-nitride-based second protective layer on the second transition layer, and a second protective layer A group III nitride based barrier layer.
  • inserting a temperature-growth III-nitride-based transition layer between the well layer and the low temperature protective layer can effectively reduce the polarization charge of the quantum well layer, weaken the quantum Stark effect, and improve the device quantum. effectiveness.
  • the transition layer can eliminate the additional barrier caused by the doping of the quantum barrier layer, lower the operating voltage, and improve the photoelectric conversion efficiency.
  • the light emitting region of the light emitting diode comprises 2 to 20 repetitions of the quantum well structure described above, wherein the growth conditions of each of the repeated quantum well structures may be the same or different.
  • the periodic thickness of the first 10 pairs of quantum well structures may be smaller than the periodic thickness of the last 10 pairs of quantum well structures, and the growth temperature may also be smaller than the last 10 pairs of quantum well structures.
  • the first protective layer is composed of Al a In b Ga 1-ab N (where 0 ⁇ a ⁇ 1, 0 ⁇ b ⁇ 1, 0 ⁇ a + b ⁇ 1),
  • the strip width should be greater than the forbidden band width of the quantum well constituent material, and the material composition of the layer can be set according to the material composition of the well layer to minimize the polarization field of the quantum well layer.
  • the layer has a thickness of 0 to 5 nm and the growth environment is pure N 2 or H 2 or a combination of the foregoing.
  • the growth temperature of the layer is not lower than the well layer temperature, and is preferably not higher than the well layer temperature by 100 degrees.
  • the first transition layer is composed of Al p In q Ga 1-pq N (where 0 ⁇ p ⁇ 1, 0 ⁇ q ⁇ 1, 0 ⁇ p + q ⁇ 1), the group thereof
  • the gradual change in the growth process, the forbidden band width is not greater than the forbidden band width of the first protective layer, not less than the forbidden band width of the quantum well layer, and gradually decreases during the growth process.
  • the layer has a thickness of 0 to 5 nm and the growth environment is pure N 2 H 2 or a combination of the foregoing.
  • the growth temperature is lowered from the growth temperature of the first protective layer to the temperature of the quantum well layer, and a corresponding cooling mode, such as linear cooling, quadratic cooling, etc., can be adopted according to the obtained component distribution.
  • the sub-well layer is composed of Al x In y Ga 1-xy N (where 0 ⁇ x ⁇ 1, 0 ⁇ y ⁇ 1, 0 ⁇ x+y ⁇ 1), of the layer
  • the components may remain unchanged or may vary, and the preferred embodiment is to maintain the components and their energy bands unchanged.
  • the quantum well layer has a thickness of 0 to 5 nm, and the growth environment is pure N 2 , H 2 or a combination thereof.
  • the growth temperature of this layer is 700-900 ° C, and the temperature can be changed or kept constant during the growth process. In order to facilitate control of the luminescent wavelength of the device, it is preferred that the growth temperature remains constant in the layer.
  • the second transition layer is composed of Al p In q Ga 1-pq N (where 0 ⁇ p ⁇ 1, 0 ⁇ q ⁇ 1, 0 ⁇ p + q ⁇ 1).
  • the composition distribution of the layer may be the same as or different from the first transition layer.
  • the forbidden band width is not greater than the forbidden band width of the first protective layer, not less than the forbidden band width of the well layer, and gradually increases during the growth process.
  • the second transition layer has a thickness of 0 to 5 nm, and the growth environment is pure N 2 , H 2 or a combination of the foregoing.
  • the growth temperature increases from the growth temperature of the quantum well layer to the second protective layer, and the composition of the layer can be calculated according to the composition distribution, and the corresponding heating mode, such as linearity, is adopted according to the distribution of the obtained components. Heating, quadratic heating, etc.
  • the second protective layer is composed of Al a In b Ga 1-ab N (where 0 ⁇ a ⁇ 1, 0 ⁇ b ⁇ 1, 0 ⁇ a + b ⁇ 1),
  • the strip width should be greater than the forbidden band width of the quantum well constituent material.
  • the layer can set the material composition of the layer according to the material composition of the quantum well layer such that the polarization field of the quantum well layer is minimized.
  • the layer has a thickness of 0 to 5 nm and the growth environment is pure N 2 , H 2 or a combination of the foregoing.
  • the growth temperature of the layer is not lower than the quantum well layer temperature, preferably not higher than the quantum well temperature by 100 °C.
  • the composition distribution, thickness, and growth temperature of the layer may be the same as or different from the first protective layer.
  • the barrier layer is composed of Al c In d Ga 1-cd N (0 ⁇ c ⁇ 1, 0 ⁇ d ⁇ 1, 0 ⁇ c+d ⁇ 1), and the forbidden band width should be Greater than the forbidden band width of the well layer.
  • the composition distribution of the constituent materials of the barrier layer may or may not be changed.
  • the energy band can be varied or unchanged.
  • the thickness of the layer is 0-50 nm, the growth temperature should not be lower than the temperature of the second protective layer, the growth environment may be N 2 or H 2 or the combination of the foregoing; if it is a H 2 /N 2 mixed gas, it preferably passes into the H 2
  • the amount should vary with the growth temperature.
  • the quantum barrier may be doped without doping, or may be doped n-type when grown to the layer thickness D (D ⁇ 0), and stop the silicon doping before the end of growth or at the end of growth.
  • the doping concentration is not more than 5 ⁇ 10 19 cm - 3 .
  • the doping level can be an actual doping level or an average doping level.
  • a preferred embodiment is to start doping after 5 nm of growth, and to stop doping at 5 nm before the end of growth, with a doping concentration of 2 ⁇ 10 18 cm -3 .
  • the barrier layer adopts a method of not doping silicon at the well barrier interface, effectively reducing the additional resistance at the well barrier interface and reducing silicon impurities in the quantum barrier while reducing the barrier layer resistance. Diffusion into the quantum well layer reduces the compressive stress introduced by silicon impurities.
  • FIG. 1 is a schematic view of Embodiment 1 of the present invention.
  • Fig. 2 is an enlarged plan view showing the structure of the light-emitting region 5 in the first embodiment of the present invention.
  • Fig. 3 is a modification 1 of the quantum well structure in the first embodiment of the present invention.
  • Fig. 4 is a modification 2 of the quantum well structure in the first embodiment of the present invention.
  • Fig. 5 is a modification 3 of the quantum well structure in the first embodiment of the present invention.
  • Figure 6 is a schematic view of Embodiment 2 of the present invention.
  • Fig. 7 is an enlarged plan view showing the structure of the light-emitting region 15 in the second embodiment of the present invention.
  • Embodiment 1 of the present invention will be described below with reference to Figs.
  • a light emitting diode (LED) structure may sequentially include a substrate 1, a buffer layer 2, an N-type conductive layer 3, a stress relief layer 4, a light-emitting region 5, an electron blocking layer 6, a P-type conductive layer 7, and a P-type.
  • Contact layer 8 the substrate 1 may be a sapphire substrate, a gallium nitride substrate or a silicon substrate;
  • the buffer layer 2 material is preferably a gallium nitride, an aluminum nitride material, an aluminum gallium nitride material, etc., and the thickness may be 30 nm;
  • the layer 3 is preferably gallium nitride, and an aluminum gallium nitride material may be used.
  • the silicon doping preferably has a concentration of 2 ⁇ 10 19 cm ⁇ 3 ;
  • the stress releasing layer 4 is preferably a superlattice structure in which InGaN/GaN is alternately grown, and the growth temperature is 750 ° C, grown in a pure N 2 environment, to increase the V-pits of the light-emitting region 5 and partially release the stress in the quantum well layer;
  • a current expansion can be inserted between the N-type conductive layer 3 and the stress-relieving layer 4 Layer 9
  • the layer is preferably an aluminum gallium nitride material, and the electrons are laterally expanded in the layer through the N-type conductive layer 3 and then flow into the light-emitting region to increase the light-emitting area;
  • the light-emitting region 5 has at least one quantum well structure 10, It is preferably a repeating structure having 15 quantum wells, the specific structure of which will be described in detail below with reference to FIG.
  • the P-type electron blocking layer 6 is preferably made of an aluminum gallium nitride material, and has a growth temperature of 750 to 950 ° C, preferably a growth temperature of 800 ° C. , thickness 50 ⁇ 200nm, preferably Degree of 150nm, the electron blocking layer into the P-type layer recombine with holes, it can be grown aluminum component gradual manner; doping concentration of the P-type conductive layer 7 and the P-type contact layer 8 are respectively preferably 1 ⁇ 10 20 cm -3 and 1 x 10 21 cm -3 .
  • the quantum well structure 10 includes a first protective layer 10a, a first transition layer 10b, a well layer 10c, a second transition layer 10d, a second protective layer 10e, and a barrier layer 10f.
  • the first protective layer 10a and the second protective layer 10e are composed of Al a In b Ga 1-ab N (0 ⁇ a ⁇ 1, 0 ⁇ b ⁇ 1, 0 ⁇ a + b ⁇ 1), and have a thickness of 0 to 5 nm.
  • the growth environment is pure N 2 .
  • the growth temperature of the two layers should be not lower than the temperature of the quantum well layer, not higher than the quantum well temperature of 100 ° C, and the growth temperature is preferably 800 ° C. This layer mainly protects the quantum well layer and the In composition of the transition layer from being pyrolyzed.
  • the first transition layer 10b and the second transition layer 10d are composed of Al p In q Ga 1-pq N (where 0 ⁇ p ⁇ 1 , 0 ⁇ q ⁇ 1, 0 ⁇ p + q ⁇ 1), and the thickness is 0 to 5 nm. Preferably, both are 2 nm, and the growth environment is pure N 2 .
  • the forbidden band width of the first transition layer 10b is not greater than the forbidden band width of the first protective layer 10a, not less than the forbidden band width of the well layer 10c, and gradually decreases during the growth process; the forbidden band of the second transition layer 10d
  • the width is not greater than the forbidden band width of the second protective layer 10e, not less than the forbidden band width of the well layer, and gradually increases during the growth process.
  • the first transition layer 10b is gradually changed from the energy band distribution of the first protective layer 10a to the energy band distribution of the well layer 10c during the growth process
  • the second transition layer 10d is gradually changed from the energy band distribution of the well layer 10c to the second. The energy band distribution of the protective layer 10e.
  • the growth temperature of the first transition layer 10b is lowered from the growth temperature of the first protective layer 10a to the growth temperature of the well layer 10c, and the growth temperature of the second transition layer 10d is raised from the growth temperature of the well layer to the second protection.
  • the growth temperature of the layer can be any cooling/warming mode, such as linear cooling/warming.
  • the two layers can calculate the composition of the layer according to the energy band distribution of the quantum well layer and the first and second protective layers, so that the polarization charge in the quantum well layer is minimized, thereby reducing the polarization field of the quantum well layer. , improve light extraction efficiency and reduce the droop effect.
  • the well layer 10c is composed of Al x In y Ga 1-xy N (where 0 ⁇ x ⁇ 1, 0 ⁇ y ⁇ 1, 0 ⁇ x + y ⁇ 1), and has a thickness of 0 to 5 nm, preferably 2 nm, and the growth environment is Pure N 2 has a growth temperature of 700 to 900 ° C, preferably a temperature of 750 ° C and is kept constant.
  • the barrier layer 10f is composed of Al c In d Ga 1-cd N (where 0 ⁇ c ⁇ 1 , 0 ⁇ d ⁇ 1 , 0 ⁇ c + d ⁇ 1 ), and has a thickness of 0 to 50 nm, preferably 20 nm, and the growth temperature is not Below the temperature of the second protective layer 10e, the growth temperature is preferably 850 °C.
  • the growth environment may be a H 2 /N 2 mixed gas, the ratio of H 2 and N 2 is 0 ⁇ H 2 /N 2 ⁇ 1, preferably the amount of H 2 is 10L, and the crystal of the quantum barrier layer can be increased by introducing H 2 . Quality, reduce dislocations and defects.
  • the barrier layer 10f may be doped without doping, or may be n-doped while growing to the layer thickness D (D ⁇ 0), and stop the silicon doping before the end of growth or at the end of the growth, and the doping concentration is not More than 5 ⁇ 10 19 cm -3 , the doping level may be an actual doping level or an average doping level.
  • the preferred embodiment provided by this embodiment starts doping after growing 5 nm, and stops doping at 5 nm before the end of growth, and the doping concentration is 2 ⁇ 10 18 cm ⁇ 3 .
  • the main function is to reduce the barrier resistance while effectively eliminating the additional resistance at the well barrier interface and reducing the diffusion of silicon impurities into the quantum well layer in the quantum barrier, reducing the compressive stress introduced by the silicon impurities.
  • the quantum well 40 structure shown in FIG. 3 can also be employed in the light-emitting region 5 of the foregoing light-emitting diode.
  • the quantum well 40 includes a first protective layer 40a, a well layer 40c, a second transition layer 40d, a second protective layer 40e, and a barrier layer 40f, that is, a well layer 40c is formed directly on the first protective layer 40a.
  • the first protective layer 40a is composed of Al a In b Ga 1-ab N (0 ⁇ a ⁇ 1, 0 ⁇ b ⁇ 1, 0 ⁇ a + b ⁇ 1), and the thickness D a is 0 ⁇ D a ⁇ 5 nm.
  • the growth temperature of the two layers should be not lower than the temperature of the quantum well layer, not higher than the quantum well temperature of 100 ° C, and the growth temperature is preferably 750 ° C. This layer mainly protects the quantum well layer and the In composition of the transition layer from being pyrolyzed.
  • the well layer 40c is composed of Al x In y Ga 1-xy N (0 ⁇ x ⁇ 1 , 0 ⁇ y ⁇ 1, 0 ⁇ x + y ⁇ 1), and the thickness D c is 0 ⁇ D c ⁇ 5 nm, preferably 2 nm
  • the growth environment is pure N 2 , the growth temperature is 700 to 900 ° C, preferably the temperature is 750 ° C and is kept constant.
  • a quantum well 50 structure as shown in FIG. 4 can also be employed in the light-emitting region 5 of the foregoing light-emitting diode.
  • the quantum well 50 includes a first protective layer 50a, a first transition layer 50b, a well layer 50c, a second protective layer 50e, and a barrier layer 50f, that is, a second protective layer 50e is formed directly on the well layer 50c.
  • the well layer 50c is composed of Al x InyGa 1-xy N (0 ⁇ x ⁇ 1 , 0 ⁇ y ⁇ 1, 0 ⁇ x + y ⁇ 1), and the thickness D c is 0 ⁇ D c ⁇ 5 nm, preferably 2 nm, growth
  • the environment is pure N 2 , the growth temperature is 700 to 900 ° C, preferably the temperature is 750 ° C and is kept constant.
  • the second protective layer 50e is composed of Al a In b Ga 1-ab N (0 ⁇ a ⁇ 1, 0 ⁇ b ⁇ 1, 0 ⁇ a + b ⁇ 1), and the thickness D e is 0 ⁇ D e ⁇ 5 nm.
  • the growth environment is pure N 2 .
  • the growth temperature of this layer should not be lower than the temperature of the quantum well layer, not higher than the quantum well temperature of 100 ° C, and the growth temperature is preferably 750 ° C. This layer mainly protects the quantum well layer and the In composition of the transition layer from being pyrolyzed.
  • a quantum well 60 structure as shown in FIG. 5 can also be employed in the light-emitting region 5 of the foregoing light-emitting diode.
  • the quantum well 60 includes a first protective layer 60a, a first transition layer 60b, a second transition layer 60d, a second protective layer 60e, and a barrier layer 60f, that is, the well layer has a thickness of zero.
  • the first transition layer 60b and the second transition layer 60d are composed of Al p In q Ga 1-pq N (0 ⁇ p ⁇ 1 , 0 ⁇ q ⁇ 1, 0 ⁇ p + q ⁇ 1), and the thickness D is 0 ⁇ D ⁇ 5 nm, preferably 3 nm, and the growth environment is pure N 2 .
  • the forbidden band width of the first transition layer 60b is not greater than the forbidden band width of the first protective layer 60a, and is gradually reduced during the growth process; the forbidden band width of the second transition layer 60d is not greater than the forbidden band of the second protective layer 60e.
  • the tape width is gradually increased during the growth process.
  • the first transition layer 60b is gradually changed from the energy band distribution of the first protective layer 60a to the set distribution during the growth process
  • the second transition layer 60d is gradually changed from the set distribution to the energy band distribution of the second protective layer 60e.
  • This setting distribution is derived from the set illumination wavelength.
  • the growth temperature of the first transition layer 60b is lowered from the growth temperature of the first protective layer 60a to the set temperature
  • the growth temperature of the second transition layer 60d is raised from the set temperature to the growth temperature of the second protective layer.
  • the set temperature is derived from the set illuminating wavelength, and any cooling/warming mode, such as linear cooling/warming, can be used.
  • the two layers can calculate the composition of the layer according to the set illuminating wavelength and the energy band distribution of the first and second protective layers, so that the polarization charge in the quantum well layer is minimized, thereby reducing the pole of the quantum well layer.
  • the field is reduced, the light extraction efficiency is improved, and the droop effect is reduced.
  • the light emitting diode (LED) structure of FIG. 6 includes a substrate 11, a buffer layer 12 on the substrate 11, and an N-type conductive layer 13 on the buffer layer 12.
  • the stress relief layer 14 on the N-type conductive layer 13 has a light-emitting region 15 on the stress relief layer, and the light-emitting region 15 is divided into two portions 15a and 15b.
  • a P-type electron blocking layer 16 on the light-emitting region 15 a P-type conductive layer 17 on the electron blocking layer 16, and a P-type contact layer 18 on the P-type conductive layer 17.
  • other layer structures and fabrication methods can be referred to in Embodiment 1.
  • the first portion 15a of the light-emitting region 15 includes a periodic repeating structure having nine pairs of quantum well structures 20 and quantum well structures 30.
  • the quantum well structure 20 in the light-emitting region 15 includes a first protective layer 20a, a first transition layer 20b, a well layer 20c, a second transition layer 20d, a second protective layer 20e, and a barrier layer 20f.
  • a second portion 15b of the light-emitting region is provided on the first portion 15a of the light-emitting region, having a repeating structure of ten quantum well structures 30.
  • the quantum well structure 30 in the light-emitting region 15 includes a first protective layer 30a, a first transition layer 30b, a well layer 30c, a second transition layer 30d, a second protective layer 30e, and a barrier layer 30f.
  • the growth parameters of each layer in the quantum well structure 30 can be referred to the growth parameters of the layers in the quantum well structure in Example 1.
  • the quantum well structure 20 has the same growth conditions as the quantum well 30.
  • the growth conditions include growth pressure, growth gas flow, growth temperature, MO source used for growth, and dopant source.
  • the thickness of each layer in the quantum well structure 20 is not equal to the thickness of the corresponding layer in the quantum well structure 30.
  • the preferred embodiment provided by this embodiment is that the thickness of each layer in the quantum well structure 20 is equal to 1/3 of the thickness of the corresponding layer in the quantum well structure 30.
  • the dominant wavelength of light emitted by the quantum well structure 20 is about 400 nm, and the luminous efficiency is much smaller than that of the quantum well structure 30.
  • the quantum well structure 20 acts primarily to release the stress of the quantum well layer in the quantum well structure 30, reducing its polarization field and improving luminous efficiency.

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Abstract

本发明提供了一种多量子阱结构及采用该结构的发光二极管，所述发光二极管的发光区具有至少一个量子阱结构，其结构包括第一保护层、在第一保护层上的第一过渡层、在第一过渡层上的量子阱层、在量子阱层上的第二过渡层、在第二过渡层上的第二保护层、以及在第二保护层上的量子垒层。

Description

一种多量子阱结构及采用该结构的发光二极管
本申请要求于2014年3月24日提交中国专利局、申请号为201410110224.8、发明名称为“一种多量子阱结构及采用该结构的发光二极管”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本发明涉及微电子器件，更详细地说，涉及可用于Ⅲ族氮化物半导体器件(如发光二极管)的结构。
背景技术
发光二极管(LED)具有亮度高，节能环保等优点，已被公认为第三代照明光源，在近几年得到大力发展。在衬底上生长的GaN基外延片，是LED的核心组成部分，决定着LED产品的性能。
一般来说，LED外延片主要包括衬底，N型导电层，应力释放层，发光层，电子阻挡层，P型导电层以及P型接触层。其中发光层结构及晶体质量对半导体器件的光电性能起决定性作用。而以Ⅲ族氮化物为基础的半导体器件中，由于量子阱层的材料与组分多数与N型导电层及量子垒层不同，因此会在量子阱层中产生应力，使得在量子阱及量子垒的交界面处产生极化电荷形成极化场。该极化场会引起量子阱层中的量子斯塔克效应，使得电子与空穴波函数相分离，减小其光电转换效率，从而降低出光效率。
目前，量子阱的发光效率已成为提高Ⅲ族半导体器件性能的瓶颈，因此减小量子阱中的极化电荷，减弱量子阱中的量子斯塔克效应及提高器件的出光效率成为目前技术研究热点。中国专利申请案CN1552104A中提及一种减少量子阱中的极化电荷的方法，即在量子阱生长之前插入一层InxGa1-xN/InyGa1-yN超晶格结构，其作用在于释放量子阱中的应力，以减小量子阱中的极化电荷并提高出光效率。中国专利申请案CN102760808A中公开了一种发光区结构，主要是将量子垒层分为三层，两边采用GaN材料而中间层采用AlInGaN材料，用以释放量子阱层中的应力。但上述技术方案中对量子阱中的应力释放并不完全。中国专利申请案CN 102449737A中公开了一种在非极性面或半极性面上生长Ⅲ族氮化物薄膜的方法，来减小量子阱中的极化电荷。但该方法中在非极性面或半极性面中的量子阱极化电荷很少，其极化场较小，量子阱能带倾斜减弱，因此要达到相同波长，需要含有更多的In组分，而在 非极性面和半极性面上In组分并入效率较低，因此需要更低的生长温度，如此会恶化量子阱的晶体质量。因此有必要进一步减少量子阱层中极化电荷。
发明内容
本发明的目的在于：提供一种具有减少量子阱层中极化电荷作用的基于Ⅲ族氮化物的发光区的发光二极管结构及其制造方法。
本发明的发光二极管结构，由下而上可以依次包括：衬底、缓冲层、N型导电层、应力释放层、发光区、电子阻挡层、P型导电层和P型接触层。N型导电层由n型掺杂的Ⅲ族氮化物制成；P型导电层由P型掺杂的Ⅲ族氮化物制成。所述发光区具有至少一个量子阱结构，其包括：基于Ⅲ族氮化物的第一保护层，在第一保护层上的基于Ⅲ族氮化物的第一过渡层，在第一过渡层上的基于Ⅲ族氮化物的阱层，在量子阱层上的基于Ⅲ族氮化物的第二过渡层，在第二过渡层上的基于Ⅲ族氮化物的第二保护层，以及在第二保护层上的基于Ⅲ族氮化物的垒层。
前述量子阱结构中，在阱层与低温保护层之间插入变温生长的基于Ⅲ族氮化物的过渡层，可以有效地减少量子阱层的极化电荷，减弱量子斯塔克效应，提高器件量子效率。这种过渡层可消除因量子垒层掺硅引起的附加势垒，降低工作电压，提高光电转换效率。
在本发明的一些实施例中，发光二极管的发光区包括前述量子阱结构的2～20次的重复，其中每一次重复的量子阱结构的生长条件可以相同也可以不同。例如20对量子阱结构中，前10对量子阱结构的周期厚度可以小于后10对量子阱结构的周期厚度，生长温度也可小于后10对量子阱结构。
在本发明的实施例中，所述第一保护层由AlaInbGa1-a-bN组成(其中0≤a≤1，0≤b≤1，0≤a+b≤1)，其禁带宽度应大于量子阱组成材料的禁带宽度，可以根据阱层的材料组分设定该层的材料组分，使得量子阱层的极化场达到最小。该层厚度为0～5nm，生长环境为纯净N2或H2或前述组合。该层的生长温度不低于阱层温度，且较佳地不高于阱层温度100度。
在本发明的实施例中，所述第一过渡层由AlpInqGa1-p-qN组成(其中0≤p≤1，0≤q≤1，0≤p+q≤1)，其组分在生长过程中渐变，禁带宽度不大于第一保护层的禁带宽度、不小于量子阱层的禁带宽度，并且在生长过程中逐渐减小。该层的厚度为0～5nm，生长环境为纯净N2H2或前述组合。在生长过程中，其生长温度从第一保护层的生长温度降低到量子阱层温度，可以根据得到的组分分布采用相应的降温方式，如线性降温、二次曲线降温等。
在本发明的实施例中，所述子阱层由AlxInyGa1-x-yN组成(其中0≤x≤1，0≤y≤1，0≤x+y≤1)，该层的组分可以保持不变，也可以变化，较优方案为保持组分以及其能带不变化。该量子阱层厚度为0～5nm，生长环境为纯净N2、H2或前述组合。此层生长温度为700～900℃，在生长过程中温度可以变化也可保持不变。为了便于控制该器件的发光波长，优选方案为在该层中生长温度保持恒定。
在本发明的实施例中，所述第二过渡层由AlpInqGa1-p-qN组成(其中0≤p≤1，0≤q≤1，0≤p+q≤1)。该层的组分分布可以与第一过渡层保持一致，也可不同。其禁带宽度不大于第一保护层的禁带宽度、不小于阱层的禁带宽度，并且在生长过程中逐渐增大。该第二过渡层厚度为0～5nm，生长环境为纯净N2、H2或前述组合。在生长过程中，其生长温度从量子阱层的生长温度升高到第二保护层，可以根据组分分布计算该层的组分，并根据得到的组分分布采用相应的升温方式，如线性升温、二次曲线升温等。
在本发明的实施例中，所述第二保护层由AlaInbGa1-a-bN组成(其中0≤a≤1，0≤b≤1，0≤a+b≤1)，其禁带宽度应大于量子阱组成材料的禁带宽度。该层可以根据量子阱层的材料组分设定该层的材料组分，使得量子阱层的极化场达到最小。该层厚度为0～5nm，生长环境为纯净N2、H2或前述组合。该层的生长温度不低于量子阱层温度、较佳的不高于量子阱温度100℃。该层的组分分布、厚度、生长温度可以与第一保护层相同，也可不同。
在本发明的实施例中，所述垒层由AlcIndGa1-c-dN组成(0≤c≤1，0≤d≤1，0≤c+d≤1)，其禁带宽度应大于阱层的禁带宽度。该垒层的组成材料的组分分布是可以变化的，也可以不变。其能带可以是变化的，也可以不变。该层厚度为0～50nm，生长温度应不低于第二保护层的温度，生长环境可以为N2或H2或前述组合；若为H2/N2混合气体，其优选通入H2量应随着生长温度不同而变化。
在本发明的实施例中，量子垒可以不进行掺杂，也可以在生长至该层厚度D(D≥0)时进行n型掺杂，并且在生长结束之前或生长结束时停止硅掺杂，其掺杂浓度不大于5×1019cm- 3。所述掺杂级可以是实际掺杂级也可以是平均掺杂级。优选实施例为在生长5nm后开始进行掺杂，而在生长结束前5nm时停止掺杂，掺杂浓度为2×1018cm-3。
在本发明的一些实施例中，所述垒层采用在阱垒交界面处不掺硅的方法，在降低垒层电阻的同时有效地消除阱垒界面处的附加电阻并减少量子垒中硅杂质扩散到量子阱层中，减少硅杂质引入的压应力。
附图说明
为了更清楚地说明本发明实施例中的技术方案，下面将对实施例描述中所需要的附图作简单的介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例。但本发明可以用许多不同形式体现，不应认为仅限于此文提出的实施例。提供这些实施例是为了使所公开的内容更彻底完整地向本专业的技术人员充分传达本发明的范围。在附图中，为了清晰起见，层和区的厚度都放大了。在所用的图中，相同的符号代表相同的元件。在本发明中，当提到一个元件(如一层，区或衬底)是在另一个元件“上”或者延伸到另一元件“上”，可以是直接在另一个元件“上”或者直接延伸到另一个元件“上”，或者也可有插入元件存在。若提到一个元件直接在另一个元件“上”或直接眼神到另一个元件“上”，表明没有插入元件存在。
图1是本发明实施例1的示意图。
图2是本发明实施例1中发光区5的结构放大图。
图3是本发明实施例1中量子阱结构的变形1。
图4是本发明实施例1中量子阱结构的变形2。
图5是本发明实施例1中量子阱结构的变形3。
图6是本发明实施例2的示意图。
图7是本发明实施例2中的发光区15的结构放大图。
具体实施方式
下面将结合附图和实施例对本发明所述的多量子阱结构及采用该结构的发光二极管进行详细说明。
实施例1
下面将参考图1～2说明本发明的实施例1。
请参看图1，发光二极管(LED)结构可以依次包括衬底1、缓冲层2、N型导电层3、应力释放层4、发光区5、电子阻挡层6、P型导电层7以及P型接触层8。具体的，衬底1可以选用蓝宝石衬底、氮化镓衬底或硅衬底；缓冲层2材料优选采用氮化镓、氮化铝材料、铝镓氮材料等，厚度可取30nm；N型导电层3优选为氮化镓，也可采用铝镓氮材料，硅掺杂优选浓度为2×1019cm-3；应力释放层4优选为InGaN/GaN交替生长的超晶格结构，生长温度为750℃，在纯净N2环境中生长，起到增加发光区5的V-pits以及部分释放量子阱层中应力的作用；在N型导电层3与应力释放层4之间还可以插入电流扩展层9，该层优选铝镓氮材料，电子经过N型导电层3后进行在该层横向扩展并随后流入发光区，起到增加发光 面积的作用；发光区5具有至少一个量子阱结构10，优选为具有15个量子阱的重复结构，其具体结构下面将结合图2进行详细说明；P型电子阻挡层6优选采用铝镓氮材料，生长温度为750～950℃，优选生长温度为800℃，厚度50～200nm，优选厚度为150nm，该层阻挡电子进入P型层与空穴复合，可采用铝组分渐变的方式生长；P型导电层7和P型接触层8的掺杂浓度优选分别为1×1020cm-3和1×1021cm-3。
请参看图2，量子阱结构10包括第一保护层10a、第一过渡层10b、阱层10c、第二过渡层10d第二保护层10e以及垒层10f。
第一保护层10a及第二保护层10e由AlaInbGa1-a-bN组成(0≤a≤1，0≤b≤1，0≤a+b≤1)，厚度为0～5nm。优选的，GaN材料(即a＝b＝0)，厚度为2nm，生长环境为纯净N2。此两层的生长温度应不低于量子阱层温度，不高于量子阱温度100℃，优选生长温度为800℃。该层主要保护量子阱层及过渡层的In组分不被高温分解。
第一过渡层10b及第二过渡层10d由AlpInqGa1-p-qN组成(其中0≤p≤1，0≤q≤1，0≤p+q≤1)，厚度为0～5nm，优选均取2nm，生长环境为纯净N2。其中，第一过渡层10b的禁带宽度不大于第一保护层10a的禁带宽度，不小于阱层10c的禁带宽度，并且在生长过程中逐渐减小；第二过渡层10d的禁带宽度不大于第二保护层10e的禁带宽度，不小于阱层的禁带宽度，并且在生长过程中逐渐增大。较佳的，第一过渡层10b在生长过程中由第一保护层10a的能带分布渐变到阱层10c的能带分布，第二过渡层10d由阱层10c的能带分布渐变到第二保护层10e的能带分布。在外延生长过程中，第一过渡层10b的生长温度从第一保护层10a的生长温度降低到阱层10c的生长温度，第二过渡层10d的生长温度从阱层生长温度升温至第二保护层的生长温度，可以采用任何降温/升温方式，如线性降温/升温。该两层可以根据量子阱层和第一、第二保护层的能带分布来计算该层的组分，使得量子阱层中的极化电荷达到最小，从而减小量子阱层的极化场，提高出光效率，并且减少droop效应。
阱层10c由AlxInyGa1-x-yN组成(其中0≤x≤1，0≤y≤1，0≤x+y≤1)，厚度为0～5nm，优选为2nm，生长环境为纯净N2，生长温度为700～900℃，优选温度为750℃并且保持恒定。
垒层10f由AlcIndGa1-c-dN组成(其中0≤c≤1，0≤d≤1，0≤c+d≤1)，厚度为0～50nm，优选为20nm，生长温度不低于第二保护层10e的温度，优选生长温度为850℃。生长环境可以为H2/N2混合气体，H2和N2比例为0<H2/N2≤1，优选通入H2量为10L，通入H2可以提高该量子垒层的晶格质量，减少位错及缺陷。垒层10f可以不进行掺杂，也可以在生长至该层厚度D(D≥0)进时进行n型掺杂，并且在生长结束之前或生长结束时停 止硅掺杂，其掺杂浓度不大于5×1019cm-3，掺杂级可以是实际掺杂级也可以是平均掺杂级。本实施例提供的优选方案为在生长5nm后开始进行掺杂，而在生长结束前5nm时停止掺杂，掺杂浓度为2×1018cm-3。主要作用为降低垒层电阻的同时有效消除阱垒界面处的附加电阻并减少量子垒中硅杂质扩散到量子阱层中，减少硅杂质引入的压应力。
变形1
在前述发光二极管的发光区5还可以采用图3所示的量子阱40结构。在本结构中，量子阱40包括：第一保护层40a、阱层40c、第二过渡层40d、第二保护层40e以及垒层40f，即直接在第一保护层40a上形成阱层40c。
第一保护层40a由AlaInbGa1-a-bN组成(0≤a≤1，0≤b≤1，0≤a+b≤1)，厚度Da为0＜Da≤5nm。优选的，GaN材料(即a＝b＝0)，厚度为1nm，生长环境为纯净N2。此两层的生长温度应不低于量子阱层温度，不高于量子阱温度100℃，优选生长温度为750℃。该层主要保护量子阱层及过渡层的In组分不被高温分解。
阱层40c由AlxInyGa1-x-yN组成(0≤x≤1，0≤y≤1，0≤x+y≤1)，厚度Dc为0＜Dc≤5nm，优选为2nm，生长环境为纯净N2，生长温度为700～900℃，优选温度为750℃并且保持恒定。
变形2
在前述发光二极管的发光区5还可以采用图4所示的量子阱50结构。在本结构中，量子阱50包括：第一保护层50a、第一过渡层50b、阱层50c、第二保护层50e以及垒层50f，即直接在阱层50c上形成第二保护层50e。
阱层50c由AlxInyGa1-x-yN组成(0≤x≤1，0≤y≤1，0≤x+y≤1)，厚度Dc为0＜Dc≤5nm，优选为2nm，生长环境为纯净N2，生长温度为700～900℃，优选温度为750℃并且保持恒定。
第二保护层50e由AlaInbGa1-a-bN组成(0≤a≤1，0≤b≤1，0≤a+b≤1)，厚度De为0＜De≤5nm。优选的，GaN材料(即a＝b＝0)，厚度为2nm，生长环境为纯净N2。此层的生长温度应不低于量子阱层温度，不高于量子阱温度100℃，优选生长温度为750℃。该层主要保护量子阱层及过渡层的In组分不被高温分解。
变形3
在前述发光二极管的发光区5还可以采用图5所示的量子阱60结构。在本结构中，量子阱60包括：第一保护层60a、第一过渡层60b、第二过渡层60d、第二保护层60e以及垒层60f，即阱层的厚度为0。
第一过渡层60b及第二过渡层60d由AlpInqGa1-p-qN组成(0≤p≤1，0≤q≤1，0≤p+q≤1)，厚度D为0＜D≤5nm，优选均取3nm，生长环境为纯净N2。其中，第一过渡层60b的禁带宽度不大于第一保护层60a的禁带宽度，并且在生长过程中逐渐减小；第二过渡层60d的禁带宽度不大于第二保护层60e的禁带宽度，并且在生长过程中逐渐增大。较佳的，第一过渡层60b在生长过程中由第一保护层60a的能带分布渐变到设定分布，第二过渡层60d由设定分布渐变到第二保护层60e的能带分布，此设定分布由设定发光波长得出。在外延生长过程中，第一过渡层60b的生长温度从第一保护层60a的生长温度降低到设定温度，第二过渡层60d的生长温度从设定温度升温至第二保护层的生长温度，此设定温度由设定的发光波长得出，可以采用任何降温/升温方式，如线性降温/升温。该两层可以根据设定的发光波长和第一、第二保护层的能带分布来计算该层的组分，使得量子阱层中的极化电荷达到最小，从而减小量子阱层的极化场，提高出光效率，并且减少droop效应。
实施例2
下面将参考图6说明本发明的实施例2，图6中所述发光二极管(LED)结构包括衬底11，在衬底11上的缓冲层12，在缓冲层12上的N型导电层13，在N型导电层13上的应力释放层14，在应力释放层上发光区15，发光区15分为15a和15b两部分。还包括在发光区15上的P型电子阻挡层16，在电子阻挡层16上的P型导电层17，以及在P型导电层17上的P型接触层18。上述结构中，除发光区15以外，其它各层结构及制作方法可以参考实施例1中描述。
发光区15中第一部分15a包括具有9对量子阱结构20、量子阱结构30的周期重复结构。发光区15中的量子阱结构20如图7所示，包括第一保护层20a、第一过渡层20b、阱层20c、第二过渡层20d、第二保护层20e以及垒层20f。
在发光区第一部分15a上有发光区第二部分15b，具有10个量子阱结构30的重复结构。发光区15中的量子阱结构30如图7所示，包括第一保护层30a、第一过渡层30b、阱层30c、第二过渡层30d、第二保护层30e以及垒层30f。量子阱结构30中各层生长参数可参照实施例1中量子阱结构中各层的生长参数。
在本实施例中，量子阱结构20的生长条件与量子阱30相同，该生长条件包括生长压力，生长气流，生长温度，生长所使用的MO源及掺杂源。但量子阱结构20中各层的厚度不等于量子阱结构30中相对应层的厚度。本实施例提供的优选方案是量子阱结构20中各层的厚度等于量子阱结构30中相对应层的厚度的1/3。量子阱结构20发出的光的主波长约400nm，且发光效率远小于量子阱结构30的发光效率。量子阱结构20主要作用为释放量子 阱结构30中量子阱层的应力，减小其极化场并提高发光效率。量子阱结构20中垒层20f的厚度越小，在量子阱结构30中垒层30f的硅掺杂可以越高，优选掺杂浓度为1×1019cm-3。
在附图和说明书中，公开了本发明的典型优选实施例，虽然使用了具体术语，但这些术语的使用仅仅为了具体说明本发明，而不是为了起限制作用，本发明的范围在以上权利要求中阐述。

Claims (17)

  1. 一种多量子阱结构，其中至少一个量子阱结构包括：基于Ⅲ族氮化物的第一保护层、在第一保护层上的基于Ⅲ族氮化物的第一过渡层，在第一过渡层上的基于Ⅲ族氮化物的阱层，在量子阱层上的基于Ⅲ族氮化物的第二过渡层，在第二过渡层上的基于Ⅲ族氮化物的第二保护层，以及在第二保护层上的基于Ⅲ族氮化物的垒层。
  2. 根据权利要求1所述的一种多量子阱结构，其特征在于：所述第一保护层或第二保护层由AlaInbGa1-a-bN组成，其中0≤a≤1，0≤b≤1，0≤a+b≤1。
  3. 根据权利要求1所述的一种多量子阱结构，其特征在于：所述第一保护层、第二保护层厚度为n、m，其中0＜n≤5nm、0＜m≤5nm。
  4. 根据权利要求1所述的一种多量子阱结构，其特征在于：所述第一保护层禁带宽度不小于第一过渡层中组成材料的禁带宽度。
  5. 根据权利要求1所述的一种多量子阱结构，其特征在于：所述第二保护层禁带宽度不小于第二过渡层中组成材料的禁带宽度。
  6. 根据权利要求1所述的一种多量子阱结构，其特征在于：所述第一过渡层或第二过渡层由AlpInqGa1-p-qN组成，其中0≤p≤1，0≤q≤1，0≤p+q≤1。
  7. 根据权利要求1所述的一种多量子阱结构，其特征在于：所述第一过渡层或第二过渡层厚度为i、j，其中0≤i≤5nm、0≤j≤5nm，且i、j不同时为0。
  8. 根据权利要求1所述的一种多量子阱结构，其特征在于：所述第一过渡层在生长过程中，其生长温度从第一保护层生长温度降低到阱层生长温度，采用单调下降的方式降温。
  9. 根据权利要求1所述的一种多量子阱结构，其特征在于：所述第二过渡层在生长过程中，其生长温度从阱层生长温度升高到第二保护层生长温度，采用单调上升的方式升温。
  10. 根据权利要求1所述的一种多量子阱结构，其特征在于：所述第一过渡层的禁带宽度不大于第一保护层的禁带宽度且不小于阱层的禁带宽度，并且在生长过程中逐渐减小。
  11. 根据权利要求1所述的一种多量子阱结构，其特征在于：所述第二过渡层的禁带宽度不 大于第二保护层的禁带宽度且不小于阱层的禁带宽度，并且在生长过程中逐渐增大。
  12. 根据权利要求1所述的一种多量子阱结构，其特征在于：所述阱层由AlxInyGa1-x-yN组成，其中0≤x≤1，0≤y≤1，0≤x+y≤1。
  13. 根据权利要求1所述的一种多量子阱结构，其特征在于：所述阱层厚度为0～5nm。
  14. 根据权利要求1所述的一种多量子阱结构，其特征在于：所述垒层由AlcIndGa1-c-dN组成，其中0≤c≤1，0≤d≤1，0≤c+d≤1。
  15. 根据权利要求1所述的一种多量子阱结构，其特征在于：所述垒层厚度为0～50nm。
  16. 根据权利要求1所述的一种多量子阱结构，其特征在于：所述垒层为全部掺杂或部分掺杂，其掺杂浓度不大于5×1019cm-3。
  17. 一种发光二极管，包括：N型导电层、P型导电层及夹在两者之间的发光区，其特征在于：所述发光层包含权利要求1至16中任一权利要求所述的多量子阱结构。
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