WO2015137337A1 - 半導体装置およびその製造方法 - Google Patents
半導体装置およびその製造方法 Download PDFInfo
- Publication number
- WO2015137337A1 WO2015137337A1 PCT/JP2015/057009 JP2015057009W WO2015137337A1 WO 2015137337 A1 WO2015137337 A1 WO 2015137337A1 JP 2015057009 W JP2015057009 W JP 2015057009W WO 2015137337 A1 WO2015137337 A1 WO 2015137337A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- oxide semiconductor
- semiconductor layer
- layer
- tft
- electrode
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 200
- 238000000034 method Methods 0.000 title description 30
- 238000004519 manufacturing process Methods 0.000 title description 9
- 239000010410 layer Substances 0.000 claims abstract description 197
- 239000010409 thin film Substances 0.000 claims abstract description 46
- 239000000758 substrate Substances 0.000 claims abstract description 40
- 239000011241 protective layer Substances 0.000 claims abstract description 30
- 229910052751 metal Inorganic materials 0.000 claims description 9
- 239000002184 metal Substances 0.000 claims description 9
- 229910052733 gallium Inorganic materials 0.000 claims description 5
- 229910052738 indium Inorganic materials 0.000 claims description 5
- 229910052725 zinc Inorganic materials 0.000 claims description 5
- 239000010408 film Substances 0.000 description 89
- 238000005530 etching Methods 0.000 description 19
- 229910007541 Zn O Inorganic materials 0.000 description 17
- 239000010936 titanium Substances 0.000 description 15
- 239000011159 matrix material Substances 0.000 description 12
- 229910021417 amorphous silicon Inorganic materials 0.000 description 9
- 239000011229 interlayer Substances 0.000 description 8
- 239000011701 zinc Substances 0.000 description 8
- 230000000052 comparative effect Effects 0.000 description 7
- 239000010949 copper Substances 0.000 description 7
- 230000007423 decrease Effects 0.000 description 7
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 6
- 229910052760 oxygen Inorganic materials 0.000 description 6
- 239000001301 oxygen Substances 0.000 description 6
- 229910004298 SiO 2 Inorganic materials 0.000 description 5
- 238000005401 electroluminescence Methods 0.000 description 5
- 239000000463 material Substances 0.000 description 5
- 238000000059 patterning Methods 0.000 description 5
- 230000015572 biosynthetic process Effects 0.000 description 4
- 239000011651 chromium Substances 0.000 description 4
- 238000001312 dry etching Methods 0.000 description 4
- 239000004973 liquid crystal related substance Substances 0.000 description 4
- 238000000206 photolithography Methods 0.000 description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- 229910052719 titanium Inorganic materials 0.000 description 4
- 229910052782 aluminium Inorganic materials 0.000 description 3
- 229910052802 copper Inorganic materials 0.000 description 3
- 229910052750 molybdenum Inorganic materials 0.000 description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- 238000004544 sputter deposition Methods 0.000 description 3
- 229910052721 tungsten Inorganic materials 0.000 description 3
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 229910052804 chromium Inorganic materials 0.000 description 2
- 238000005259 measurement Methods 0.000 description 2
- 239000011733 molybdenum Substances 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 238000006722 reduction reaction Methods 0.000 description 2
- 239000003870 refractory metal Substances 0.000 description 2
- 238000004904 shortening Methods 0.000 description 2
- 229910052715 tantalum Inorganic materials 0.000 description 2
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 1
- 229910004205 SiNX Inorganic materials 0.000 description 1
- 229910020923 Sn-O Inorganic materials 0.000 description 1
- 229910006404 SnO 2 Inorganic materials 0.000 description 1
- 229910003077 Ti−O Inorganic materials 0.000 description 1
- HCHKCACWOHOZIP-UHFFFAOYSA-N Zinc Chemical compound [Zn] HCHKCACWOHOZIP-UHFFFAOYSA-N 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000003384 imaging method Methods 0.000 description 1
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 1
- 238000011835 investigation Methods 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 238000006479 redox reaction Methods 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 238000002834 transmittance Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41733—Source or drain electrodes for field effect devices for thin film transistors with insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
Definitions
- the present invention relates to a semiconductor device including a thin film transistor and a manufacturing method thereof.
- An active matrix substrate used for a liquid crystal display device or the like includes a switching element such as a thin film transistor (hereinafter, “TFT”) for each pixel.
- a switching element such as a thin film transistor (hereinafter, “TFT”) for each pixel.
- TFT thin film transistor
- amorphous silicon TFT a TFT having an amorphous silicon film as an active layer
- polycrystalline silicon TFT a TFT having a polycrystalline silicon film as an active layer
- oxide semiconductor TFT in place of amorphous silicon or polycrystalline silicon as a material for the active layer of a TFT.
- a TFT is referred to as an “oxide semiconductor TFT”.
- An oxide semiconductor has higher mobility than amorphous silicon. For this reason, the oxide semiconductor TFT can operate at a higher speed than the amorphous silicon TFT.
- the oxide semiconductor film is formed by a simpler process than the polycrystalline silicon film, the oxide semiconductor film can be applied to a device that requires a large area.
- a TFT having a bottom gate structure having source and drain electrodes (top contact) on an oxide semiconductor layer has been proposed.
- the source and drain electrodes are formed by etching a conductive film formed over the oxide semiconductor layer.
- a structure in which the surface portion of the oxide semiconductor layer is also etched by this etching is called a channel etching type.
- a structure in which an insulating film (etch stop film) functioning as an etch stop is formed on the channel of the oxide semiconductor layer so that the channel is not etched in the etching process for forming the source and drain electrodes is proposed.
- the structure in which the etch stop film is provided on the channel is called an etch stop type.
- a channel etching type TFT is abbreviated as “CE type TFT”
- an etching stop type TFT is abbreviated as “ES type TFT”.
- Patent Documents 1 and 2 disclose ES type TFTs.
- Patent Document 1 discloses that an oxide semiconductor layer and an etch stop film are formed by patterning using the same mask. The etch stop film is provided with a source opening and a drain opening for connecting the source and drain electrodes and the oxide semiconductor layer, respectively.
- Patent Document 2 discloses that an interlayer insulating film (etch stop film) is formed so as to cover an oxide semiconductor layer, and a source opening and a drain opening are formed in the etch stop film.
- FIG. 8 is a cross-sectional view showing an ES-type TFT disclosed in Patent Document 2.
- the ES type TFT includes a substrate 1, a gate electrode 3 provided on the substrate 1, a gate insulating layer 5 covering the gate electrode 3, an oxide semiconductor layer 7 formed on the gate insulating layer 5, and an oxidation
- An interlayer insulating film (etch stop film) 90 covering the physical semiconductor layer 7 and a source electrode 11 and a drain electrode 13 provided on the oxide semiconductor layer 7 are provided.
- the source electrode 11 and the drain electrode 13 are electrically connected to the oxide semiconductor layer 7 in the source opening 91 and the drain opening 92 provided in the etch stop film 90, respectively.
- the conventional CE TFT has a problem that the off-characteristic of the TFT decreases as the channel length decreases (that is, the distance between the source electrode and the drain electrode decreases). I found. This is considered to be due to the oxide semiconductor layer underneath being damaged in the etching process when forming the source electrode and the drain electrode. As a result of further studies by the present inventor, it has been found that the decrease in off-characteristics is caused mainly by damage to the edge portion of the oxide semiconductor layer. Details will be described later.
- the edge portion (including the side surface) of the oxide semiconductor layer is exposed from the etch stop film, so that the oxide semiconductor layer receives during the process. Damage may not be reduced sufficiently.
- the distance between the channel region and the side surface of the oxide semiconductor layer is increased in order to suppress variation in characteristics of the oxide semiconductor TFT caused by oxygen intrusion or the like on the side surface of the oxide semiconductor layer. It has been proposed. However, with such a structure, damage to the oxide semiconductor layer may not be sufficiently suppressed. There is also a problem that the size of the TFT increases.
- the side surface of the oxide semiconductor layer 7 is also protected by the etch stop film 90 as shown in FIG. 7 can be prevented from being damaged.
- the channel length is larger than that of the CE TFT.
- the channel length is determined by the distance between the source electrode and the drain electrode.
- the substantial channel length CL is defined by the distance between the source opening 91 and the drain opening 92, and is larger than the distance L between the source electrode 11 and the drain electrode 13. Because it grows. For this reason, it is difficult to shorten the channel length CL.
- One embodiment of the present invention has been made to solve the above-described problems, and its main purpose is to provide a novel oxidation capable of suppressing process damage to the oxide semiconductor layer and shortening the channel length.
- An object of the present invention is to provide a semiconductor device including a physical semiconductor TFT.
- a semiconductor device is a semiconductor device including a thin film transistor, and the thin film transistor includes a substrate, a gate electrode provided on the substrate, and a gate insulating layer formed on the gate electrode. And an island-shaped oxide semiconductor layer formed on the gate insulating layer, and an upper surface and the entire side surface of the oxide semiconductor layer, and a part of the upper surface of the oxide semiconductor layer. And a protective layer having a single opening that exposes the oxide semiconductor layer, and a source electrode and a drain electrode that are in contact with the oxide semiconductor layer in the single opening, respectively.
- At least a part of the channel region of the oxide semiconductor layer is exposed by the single opening.
- a channel length CL of the thin film transistor is equal to an interval L between the source electrode and the drain electrode on the upper surface of the oxide semiconductor layer.
- a width along the channel width direction of the oxide semiconductor layer is larger than a width along the channel width direction of the opening, and a width along the channel width direction of the source electrode and the drain electrode. Smaller than.
- the entire oxide semiconductor layer overlaps the gate electrode when viewed from the normal direction of the surface of the substrate.
- the single opening is rectangular when viewed from the normal direction of the surface of the substrate.
- the single opening is elliptical when viewed from the normal direction of the surface of the substrate.
- the oxide semiconductor layer contains at least one metal element of In, Ga, and Zn.
- the oxide semiconductor layer includes a crystalline part.
- a method for manufacturing a semiconductor device includes: (A) a step of forming a gate electrode on a substrate; and (B) a step of forming a gate insulating layer so as to cover the upper surface and side surfaces of the gate electrode. (C) forming an island-shaped oxide semiconductor layer on the gate insulating layer; and (D) protecting the oxide semiconductor layer on the oxide semiconductor layer so as to cover an upper surface and side surfaces of the oxide semiconductor layer. Forming a layer; (E) forming a single opening in the protective layer that exposes only a portion of the top surface of the oxide semiconductor layer; and (F) within the single opening. Forming a source electrode and a drain electrode in contact with the oxide semiconductor layer.
- a semiconductor device including a novel oxide semiconductor TFT capable of improving reliability by suppressing process damage to an oxide semiconductor layer and shortening a channel length.
- FIGS. 5A and 5B are a plan view illustrating another thin film transistor 101 in the semiconductor device of the embodiment and a cross-sectional view along the channel length direction, respectively.
- FIGS. 5A and 5B are a plan view illustrating another thin film transistor 101 in the semiconductor device of the embodiment and a cross-sectional view along the channel length direction, respectively.
- FIGS. 4A to 4D are process cross-sectional views for explaining a method for manufacturing the thin film transistor 101.
- FIG. (A) And (b) is the top view and sectional drawing which show a part of active matrix substrate provided with the thin-film transistor 101, respectively.
- (A) is a top view which shows TFT of an Example
- (b) is a figure which shows the result of having measured the threshold voltage of TFT of an Example and a comparative example.
- 10 is a cross-sectional view showing an etch stop type TFT disclosed in Patent Document 2.
- the present inventor has found that the off-characteristics of the conventional CE type TFT are lowered as the channel length CL is reduced. Further, the present inventors have found that this problem is caused by damage mainly received at the edge portion of the oxide semiconductor layer in the etching step when forming the source electrode and the drain electrode. Specifically, oxygen defects are formed mainly on the side surfaces of the oxide semiconductor layer 7 by an oxidation-reduction reaction during a manufacturing process such as an etching process. As a result, it is considered that the edge portion of the oxide semiconductor layer is reduced in resistance and the off-leakage current is increased. Note that the “edge portion” includes a side surface of the oxide semiconductor layer and a portion located in the vicinity of the outer edge of the top surface of the oxide semiconductor layer.
- the oxide semiconductor layer other than the edge portion (for example, the channel region of the oxide semiconductor layer) undergoes process damage when forming the source and drain electrodes, the characteristic variation of the TFT due to the process damage is It was also found that the edge was much smaller than when the damage was taken. Since portions other than the edge portion of the oxide semiconductor layer are protected by the resist when the oxide semiconductor film is patterned, the oxide semiconductor layer is not damaged by the patterning of the oxide semiconductor film as compared with the edge portion. For this reason, even if the subsequent process (for example, the etching process when forming the source and drain electrodes) is damaged, the change in characteristics due to the damage is suppressed to be smaller than when the edge part is damaged. It is done.
- the subsequent process for example, the etching process when forming the source and drain electrodes
- the present inventor has sufficiently reduced the OFF characteristics of the TFT due to process damage as long as the side surface is protected even if the top surface of the oxide semiconductor layer is exposed in the etching process.
- Embodiments of the present invention have been made on the basis of the above-described knowledge, and have a protective layer that can suppress process damage to the oxide semiconductor layer, and are capable of reducing the channel length.
- a semiconductor device including an oxide semiconductor TFT is provided.
- a semiconductor device includes a thin film transistor (oxide semiconductor TFT) having an active layer made of an oxide semiconductor.
- the semiconductor device of the present embodiment only needs to include at least one oxide semiconductor TFT, and widely includes a substrate including such a TFT, an active matrix substrate, various display devices, electronic devices, and the like.
- FIG. 1 is a diagram schematically showing a thin film transistor 100 according to this embodiment.
- 1A is a plan view of the thin film transistor 100
- FIGS. 1B and 1C are cross-sectional views taken along lines AA ′ and BB ′ shown in FIG. 1A, respectively. It is.
- the thin film transistor 100 includes a substrate 1, a gate electrode 3 provided on the substrate 1, a gate insulating layer 5 covering the gate electrode 3, and an island-shaped oxide semiconductor layer 7 formed on the gate insulating layer 5.
- a protective layer 9 provided so as to cover the entire upper surface 7u and side surface 7e of the oxide semiconductor layer 7, and a source electrode 11 provided on the oxide semiconductor layer 7 and electrically connected to the oxide semiconductor layer 7.
- a drain electrode 13 At least a part of the oxide semiconductor layer 7 overlaps the gate electrode 3 with the gate insulating layer 5 interposed therebetween. As illustrated, the entire oxide semiconductor layer 7 may overlap with the gate electrode (gate wiring) 3.
- the protective layer 9 has a single opening 9p exposing only a part of the upper surface 7u of the oxide semiconductor layer 7.
- the source electrode 11 and the drain electrode 13 are in contact with the upper surface 7u of the oxide semiconductor layer 7 in the opening 9p.
- the region 7 s in contact with the source electrode 11 in the oxide semiconductor layer 7 is referred to as a “first contact region”
- the region 7 d in contact with the drain electrode 13 is referred to as a “second contact region”.
- a region 7 c of the oxide semiconductor layer 7 that overlaps with the gate electrode 3 and is located between the first contact region and the second contact region is referred to as a “channel region”.
- the semiconductor device of this embodiment includes the thin film transistor 100 having the above-described configuration, it has the following merits.
- the channel length CL of the thin film transistor 100 is equal to the distance L between the source electrode 11 and the drain electrode 13 on the upper surface 7 u of the oxide semiconductor layer 7. Therefore, the channel length CL can be reduced to a minimum value (for example, 3 ⁇ m) determined by the photoresist formation accuracy. Accordingly, it is possible to reduce the size and capacity of the TFT.
- a minimum value for example, 3 ⁇ m
- FIGS. 2A and 2B are plan views showing TFTs of reference examples.
- FIG. 2A shows a CE TFT 400 of a reference example that does not have an etch stop film or a protective layer.
- FIG. 2B shows an ES TFT 500 of a reference example provided with an etch stop film having two openings.
- the channel length CL is equal to the distance L between the source and drain electrodes 11 and 13. Therefore, the channel length CL can be reduced to the minimum etching width (for example, 3 ⁇ m) determined by the photoresist formation accuracy in the etching process for separating the source electrode 11 and the drain electrode 13.
- the minimum etching width for example, 3 ⁇ m
- the side surfaces of the oxide semiconductor layer 7 are mainly damaged in the etching process for forming the source and drain electrodes 11 and 13. There is a risk of receiving. For this reason, desired TFT characteristics may not be obtained.
- the threshold voltage may shift.
- the source and drain electrodes 11 and 13 are respectively connected to the oxide semiconductor layer 7 through the openings 91 and 92 provided in the etch stop film. Electrically connected.
- the oxide semiconductor layer 7 is protected by the etch stop film, variation in TFT characteristics due to process damage can be suppressed.
- the distance CL between the opening 91 and the opening 92 is the channel length.
- the channel length CL is larger than the distance L between the source electrode 11 and the drain electrode 13.
- the channel length CL when viewed from the normal direction of the substrate 1, is a distance L1, a distance l1 between the edge of the opening 91 and the edge of the source electrode 11, and an edge of the opening 92 and the drain electrode.
- the distance (L + l1 + l2) is obtained by adding the distance l2 to the 13 edges, which is larger than the minimum etching width (for example, 3 ⁇ m) determined by the photoresist formation accuracy.
- the channel length CL is large, it is difficult to increase the on-current. In addition, it is difficult to reduce the TFT size and capacitance, which may reduce the visible light transmittance in each pixel.
- the side surface 7e of the oxide semiconductor layer 7 is protected when the source and drain electrodes 11 and 13 are formed. Therefore, similar to the ES type TFT 500 of the reference example, Variations in TFT characteristics are suppressed.
- the protective layer 9 is provided with one common opening 9 p for contact with the source and drain electrodes 11 and 13. For this reason, the thin film transistor 100 can be made finer than the ES type TFT 500 (FIG. 2B) of the reference example in which openings for the contact of the source electrode 11 and the contact of the drain electrode 13 are separately provided in the protective layer 9.
- the channel length CL can be made smaller than that of the ES TFT 500.
- the channel length CL is not particularly limited, but is, for example, 5 ⁇ m or less, preferably 4 ⁇ m or less.
- the opening 9p of the protective layer 9 is arranged so as to expose a part of the channel region 7c of the oxide semiconductor layer 7, but the arrangement of the opening 9p is not limited to this.
- the opening 9p may be arranged so as to expose only a part of the upper surface 7u of the oxide semiconductor layer 7 and not the side surface 7e.
- the opening 9p may be arranged so as to expose a part or the whole of the channel region 7c.
- the length of the opening 9p in the channel width direction and the channel length direction may be smaller than the length of the oxide semiconductor layer 7 in the channel width direction and the channel length direction, respectively. Thereby, the part of the upper surface 7u of the oxide semiconductor layer 7 in the vicinity of the side surface 7e (near the outer edge) can also be protected. Accordingly, it is possible to more effectively suppress a decrease in off characteristics due to damage at the edge portion of the oxide semiconductor layer 7.
- the width along the channel width direction of the source electrode 11 and the drain electrode 13 may be larger than the width along the channel width direction of the oxide semiconductor layer 7. Further, when viewed from the normal direction of the surface of the substrate 1, the entire oxide semiconductor layer 7 may overlap with the gate electrode 3. As a result, light from the substrate 1 side toward the oxide semiconductor layer 7 can be blocked by the gate electrode 3, so that characteristic variation due to light incident on the oxide semiconductor layer 7 can be suppressed.
- the oxide semiconductor layer 7 in this embodiment may include at least one metal element of In, Ga, and Zn.
- an In—Ga—Zn—O-based semiconductor (hereinafter abbreviated as “In—Ga—Zn—O-based semiconductor”) may be included.
- a TFT having an In—Ga—Zn—O-based semiconductor layer has high mobility (more than 20 times that of an a-Si TFT) and low leakage current (less than one hundredth of that of an a-Si TFT). It is suitably used as a drive TFT and a pixel TFT.
- the In—Ga—Zn—O-based semiconductor may be amorphous, may include a crystalline portion, and may have crystallinity.
- a crystalline In—Ga—Zn—O-based semiconductor in which the c-axis is oriented substantially perpendicular to the layer surface is preferable.
- Such a crystal structure of an In—Ga—Zn—O-based semiconductor is disclosed in, for example, Japanese Patent Laid-Open No. 2012-134475. For reference, the entire disclosure of Japanese Patent Application Laid-Open No. 2012-134475 is incorporated herein by reference.
- a TFT having an In—Ga—Zn—O-based semiconductor layer has high mobility (more than 20 times that of an a-Si TFT) and low leakage current (less than one hundredth of that of an a-Si TFT). It is suitably used as a drive TFT and a pixel TFT.
- the oxide semiconductor layer 7 may include another oxide semiconductor instead of the In—Ga—Zn—O-based semiconductor.
- Zn—O based semiconductor ZnO
- In—Zn—O based semiconductor IZO (registered trademark)
- Zn—Ti—O based semiconductor ZTO
- Cd—Ge—O based semiconductor Cd—Pb—O based A semiconductor
- an In—Sn—Zn—O based semiconductor eg, In 2 O 3 —SnO 2 —ZnO
- an In—Ga—Sn—O based semiconductor or the like may be included.
- the protective layer 9 may be an insulating layer.
- an oxide film may be used as the protective layer 9.
- the oxide film when oxygen vacancies are generated in the oxide semiconductor layer 7, the oxygen vacancies can be recovered by oxygen contained in the oxide film. It can reduce more effectively.
- a SiO film or a SiO 2 film may be used as the oxide film.
- the thickness of the protective layer 9 is preferably 50 nm or more and 400 nm.
- the thickness is 50 nm or more, the side surface 7e of the oxide semiconductor layer 7 can be more reliably protected in the patterning process of the source / drain electrodes.
- it exceeds 400 nm a larger step is generated in the source electrode 11 and the drain electrode 13, which may cause disconnection.
- the source and drain electrodes 11 and 13 may be formed of the same conductive film.
- a material of the conductive film for example, a metal such as aluminum (Al), tungsten (W), molybdenum (Mo), tantalum (Ta), copper (Cu), chromium (Cr), titanium (Ti), or an alloy thereof, Alternatively, a film containing the metal nitride can be used as appropriate.
- the conductive film may be a single layer film or a laminated film. When the stacked film is used, a refractory metal film such as Ti, W, or Mo may be used as the lowermost layer in contact with the oxide semiconductor layer 7.
- the oxide semiconductor layer 7 Since Ti and Mo are less likely to act (diffuse etc.) on the oxide semiconductor than other metals (Al, Cu, etc.), it is possible to suppress degradation of TFT characteristics due to the metal acting on the oxide semiconductor layer 7.
- an Al film or a Cu film may be used as the upper layer. Al films and Cu films have the advantages of relatively low resistance and excellent workability.
- the stacked film may have, for example, a two-layer structure having a Ti film and an Al film in this order from the oxide semiconductor layer 7 side, or a three-layer structure having a Ti film, an Al film, and a Ti film in this order.
- the source electrode 11 may be formed integrally with the source wiring.
- 3A and 3B are a plan view and a cross-sectional view of another thin film transistor 101 in the present embodiment, respectively.
- the source and drain electrodes 11 and 13 are formed from the same laminated film.
- the source electrode 11 is formed integrally with the source line S.
- the source electrode 11 and the source wiring S (these may be collectively referred to as source wiring) have a two-layer structure in which, for example, a Ti film is a lower layer 11L and an Al film is an upper layer 11U.
- the drain electrode 13 has a two-layer structure in which the Ti film is the lower layer 13L and the Al film is the upper layer 13U.
- Other structures are similar to those of the thin film transistor 100 shown in FIG.
- FIGS. 4A and 4B are a plan view and a cross-sectional view, respectively, of still another thin film transistor 102 in the present embodiment.
- This example is different from the thin film transistor 101 shown in FIG. 3 in that the shape of the opening 9p of the protective layer 9 is an ellipse.
- the opening 9p is provided so that only a part of the upper surface of the oxide semiconductor layer 7 is exposed and a sufficient connection area between the exposed portion and the source and drain electrodes 11 and 13 can be secured.
- the shape is not limited to a rectangle (FIGS. 1 and 3) or an ellipse (FIG. 4).
- 5A to 5D are process cross-sectional views for explaining a method of manufacturing the thin film transistor 101.
- a manufacturing method of the thin film transistor 101 illustrated in FIG. 3 will be described as an example, but the thin film transistors 100 and 102 illustrated in FIGS. 1 and 4 may be manufactured in a similar manner.
- a gate electrode (gate wiring) 3 and a gate insulating layer 5 are provided in this order on a substrate 1 such as a glass substrate. Thereafter, an island-shaped oxide semiconductor layer 7 is formed over the gate insulating layer 5.
- the gate electrode 3 can be formed by forming a conductive film on the substrate 1 by sputtering or the like and then patterning the conductive film (thickness: for example, 100 nm or more and 500 nm or less) by photolithography.
- a conductive film for example, a film containing a metal such as aluminum (Al), tungsten (W), molybdenum (Mo), tantalum (Ta), chromium (Cr), titanium (Ti), copper (Cu), or an alloy thereof. It can be used as appropriate.
- the gate electrode 3 may be formed integrally with the gate wiring.
- the gate insulating layer 5 is formed so as to cover the gate electrode 3.
- the gate insulating layer 5 can be formed using, for example, a CVD method.
- a SiO 2 film having a thickness of 200 nm or more and 500 nm or less or a laminated film of a SiNx film and a SiO 2 film is formed.
- the oxide semiconductor layer 7 can be formed as follows. First, an In—Ga—Zn—O-based semiconductor film with a thickness of 40 nm to 100 nm, for example, is formed on the gate insulating layer 5 by sputtering. After that, a resist mask that covers a predetermined region of the In—Ga—Zn—O-based semiconductor film is formed by photolithography. Next, a portion of the In—Ga—Zn—O-based semiconductor film that is not covered with the resist mask is removed by wet etching. Thereafter, the resist mask is peeled off. In this way, an island-shaped oxide semiconductor layer 7 is obtained. Note that the oxide semiconductor layer 7 may be formed using another oxide semiconductor film instead of the In—Ga—Zn—O-based semiconductor film.
- the protective layer 9 that covers the entire side surface and a part of the upper surface of the oxide semiconductor layer 7 is formed.
- an oxide film for example, SiO 2 film
- an opening 9p exposing only a part of the upper surface of the oxide semiconductor layer 7 is formed in the oxide film by known photolithography.
- the protective layer 9 is obtained.
- only one opening 9 p is provided on one island-shaped oxide semiconductor layer 7.
- the conductive film 10 is formed in the opening 9p and on the protective layer 9 by sputtering, for example.
- the conductive film 10 for example, a laminated film having a Ti film as a lower layer 10L and an Al film as an upper layer 10U is used.
- the lower layer 10L has a thickness of, for example, 20 nm to 150 nm
- the upper layer 10U has a thickness of, for example, 100 nm to 500 nm.
- the conductive film 10 may be a laminated film having a refractory metal film such as a Ti film as a lowermost layer, and may have a laminated structure of three or more layers.
- the conductive film 10 is etched to form the source electrode 11 and the drain electrode 13.
- the source electrode 11 and the drain electrode 13 are disposed so as to be in contact with regions located on both sides of the region to be the channel region in the oxide semiconductor layer 7 in the opening 9p, respectively.
- a metal film (in this case, the upper layer 10U) above the Ti film as the lower layer 10L is first patterned by wet etching.
- the etching conditions can be set so that the lower layer 10L is not etched.
- the Ti film of the lower layer 10L is patterned by dry etching.
- the side surface of the oxide semiconductor layer 7 is protected by the protective layer 9, so that damage to the side surface is reduced. Note that as shown in the drawing, not only the side surface of the oxide semiconductor layer 7 but also the portion of the upper surface located in the vicinity of the side surface is protected, damage can be reduced more reliably.
- the lower layer 10L is made of a material having a lower etching rate when etching the upper layer 10U than the material of the upper layer 10U, only the upper layer 10U can be easily patterned.
- the lower layer 10L is thinner than the upper layer 10U, damage to the oxide semiconductor layer 7 during dry etching of the lower layer 10L can be further reduced.
- part of the surface of the oxide semiconductor layer 7 exposed by the opening 9p is also etched (channel etch). Therefore, a portion of the upper surface of the oxide semiconductor layer 7 exposed through the opening 9p and not in contact with any of the source electrode 11 and the drain electrode 13 is lower than the other portions.
- the channel length CL of the thin film transistor 101 is equal to the distance L between the source electrode 11 and the drain electrode 13 on the oxide semiconductor layer 7.
- the channel length CL is, for example, 5 ⁇ m or less, preferably 3 ⁇ m or more and 4 ⁇ m or less.
- the thin film transistor 101 can be used as a switching element of an active matrix substrate of a liquid crystal display device, for example.
- a pixel electrode that is electrically connected to the drain electrode 13 of the thin film transistor 101 is formed as described below.
- FIGS. 6A and 6B are a plan view and a cross-sectional view showing an example of an active matrix substrate including the thin film transistor 101.
- FIG. 6A is a plan view and a cross-sectional view showing an example of an active matrix substrate including the thin film transistor 101.
- an interlayer insulating layer 15 is formed so as to cover the thin film transistor 101.
- the interlayer insulating layer 15 has an opening 15 p reaching the drain electrode 13.
- a pixel electrode 19 is provided on the interlayer insulating layer 15.
- the pixel electrode 19 is in contact with the drain electrode 13 in the opening 15 p of the interlayer insulating layer 15.
- the interlayer insulating layer 15 is a laminated film having, for example, a SiO 2 film as a lower layer and an organic insulating film as an upper layer.
- the pixel electrode 19 is made of, for example, an ITO film (thickness: 50 to 200 nm).
- the active matrix substrate usually has a plurality of pixels arranged two-dimensionally, and the pixel electrode 19 and the thin film transistor 101 are disposed in each of the plurality of pixels.
- the side surface 7e of the oxide semiconductor layer 7 is protected by the protective layer 9 during patterning for forming the source electrode 11 and the drain electrode 13 or when the interlayer insulating layer 15 is formed. For this reason, process damage to the side surface 7e of the oxide semiconductor layer 7 can be suppressed. Accordingly, resistance reduction due to generation of carriers due to generation of oxygen vacancies in the oxide semiconductor layer 7 can be suppressed. As a result, the off-leakage current of the thin film transistor 101 can be reduced, and the hysteresis of the TFT characteristics can be reduced. Further, since the distance L between the source and drain electrodes 11 and 13 becomes equal to the channel length CL, the channel length CL can be reduced to a minimum value considering the alignment accuracy. Thus, the thin film transistor 101 can be reduced in size and capacity. In addition, when the thin film transistor 101 is applied to an active matrix substrate, the pixel aperture ratio can be increased.
- the protective layer 9 may not cover substantially the entire substrate.
- the protective layer 9 may have an island pattern having an opening 9p in the TFT formation region on the substrate.
- TFTs oxide semiconductor TFTs of Examples and Comparative Examples
- TFTs The oxide semiconductor TFTs of Examples and Comparative Examples (hereinafter simply referred to as “TFTs”) were fabricated, and changes in characteristics were measured when the channel length CL was varied. The method and results will be described.
- a TFT having an opening 9 p in which the protective layer 9 exposes a part of the upper surface of the oxide semiconductor layer 7 was produced.
- the shape of the opening 9p was an ellipse.
- a comparative example TFT a conventional CE type oxide semiconductor TFT having no protective layer 9 was fabricated.
- the TFT of the comparative example has the same configuration (material, thickness, size, etc. of each layer) as the TFT of the example except that the protective layer 9 is not provided.
- the change of the threshold voltage Vth was investigated by changing the channel length CL by changing the distance L between the source and drain electrodes 11 and 13 in the TFTs of the example and the comparative example.
- the gate voltage Vgs was set to ⁇ 20V to + 35V. The measurement results are shown in FIG.
- the threshold voltage Vth decreases as the channel length CL decreases (for example, less than 5 ⁇ m).
- the threshold voltage Vth is substantially constant even if the channel length CL is reduced. From this result, it was found that by providing the protective layer 9, the threshold shift accompanying the reduction of the channel length CL can be reduced. Therefore, it was confirmed that the configuration of the present embodiment can reduce the channel length CL to the same extent as that of the CE TFT while suppressing the threshold shift caused by process damage.
- This embodiment is preferably applied to an active matrix substrate using an oxide semiconductor TFT.
- the active matrix substrate can be used in various display devices such as a liquid crystal display device, an organic EL display device, and an inorganic EL display device, and an electronic device including the display device.
- the thin film transistors 100, 101, and 102 illustrated in FIG. 1, FIG. 3, FIG. 4 and the like are not only used as switching elements provided in each pixel, but also as circuit elements for peripheral circuits such as drivers. It can also be used (monolithic).
- the oxide semiconductor TFT according to this embodiment uses an oxide semiconductor layer having a high mobility (for example, 10 cm 2 / Vs or more) as an active layer, and thus is suitably used as a circuit element. .
- Embodiments of the present invention include a circuit board such as an active matrix substrate, a liquid crystal display device, a display device such as an organic electroluminescence (EL) display device and an inorganic electroluminescence display device, an imaging device such as an image sensor device, and an image input
- a circuit board such as an active matrix substrate, a liquid crystal display device, a display device such as an organic electroluminescence (EL) display device and an inorganic electroluminescence display device, an imaging device such as an image sensor device, and an image input
- EL organic electroluminescence
- an imaging device such as an image sensor device
- image input an image input
- the present invention can be widely applied to devices including thin film transistors, such as electronic devices such as devices and fingerprint readers.
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Thin Film Transistor (AREA)
Abstract
Description
実施例および比較例の酸化物半導体TFT(以下、単に「TFT」という。)を作製し、チャネル長CLを異ならせた場合の特性の変化を測定したので、その方法および結果を説明する。
3 ゲート電極
5 ゲート絶縁層
7 酸化物半導体層
7s 第1コンタクト領域
7d 第2コンタクト領域
7c チャネル領域
7e 酸化物半導体層の側面
7u 酸化物半導体層の上面
9 保護層
9p 開口部
11 ソース電極
13 ドレイン電極
100、101、102 薄膜トランジスタ
Claims (10)
- 薄膜トランジスタを備える半導体装置であって、前記薄膜トランジスタは、
基板と、
前記基板上に設けられたゲート電極と、
前記ゲート電極上に形成されたゲート絶縁層と、
前記ゲート絶縁層上に形成された島状の酸化物半導体層と、
前記酸化物半導体層の上面および側面全体を覆うように設けられ、かつ、前記酸化物半導体層の前記上面の一部のみを露出する単一の開口部を有する保護層と
それぞれが前記単一の開口部内で前記酸化物半導体層と接するソース電極およびドレイン電極と
を備える半導体装置。 - 前記酸化物半導体層のチャネル領域の少なくとも一部は、前記単一の開口部によって露出されている請求項1に記載の半導体装置。
- 前記薄膜トランジスタのチャネル長CLは、前記酸化物半導体層の前記上面における前記ソース電極と前記ドレイン電極との間隔Lと等しい請求項1または2に記載の半導体装置。
- 前記酸化物半導体層のチャネル幅方向に沿った幅は、前記開口部のチャネル幅方向に沿った幅よりも大きく、前記ソース電極および前記ドレイン電極のチャネル幅方向に沿った幅よりも小さい請求項1から3のいずれかに記載の半導体装置。
- 前記基板の表面の法線方向から見たとき、前記酸化物半導体層の全体は、前記ゲート電極と重なっている請求項1から4のいずれかに記載の半導体装置。
- 前記基板の表面の法線方向から見たとき、前記単一の開口部は矩形である請求項1から5のいずれかに記載の半導体装置。
- 前記基板の表面の法線方向から見たとき、前記単一の開口部は楕円形である請求項1から5のいずれかに記載の半導体装置。
- 前記酸化物半導体層は、In、GaおよびZnのうち少なくとも1種の金属元素を含む請求項1から7のいずれかに記載の半導体装置。
- 前記酸化物半導体層は結晶質部分を含む、請求項8に記載の半導体装置。
- (A)基板上にゲート電極を形成する工程と、
(B)前記ゲート電極の上面および側面を覆うようにゲート絶縁層を形成する工程と、
(C)前記ゲート絶縁層上に、島状の酸化物半導体層を形成する工程と、
(D)前記酸化物半導体層の上に、前記酸化物半導体層の上面および側面を覆うように保護層を形成する工程と、
(E)前記保護層に、前記酸化物半導体層の上面の一部のみを露出する単一の開口部を形成する工程と、
(F)前記単一の開口部内で前記酸化物半導体層と接するソース電極およびドレイン電極をそれぞれ形成する工程と
を包含する半導体装置の製造方法。
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US15/124,385 US9716183B2 (en) | 2014-03-11 | 2015-03-10 | Semiconductor device and method of manufacturing same |
JP2016507761A JP6218923B2 (ja) | 2014-03-11 | 2015-03-10 | 半導体装置およびその製造方法 |
CN201580013007.XA CN106104810A (zh) | 2014-03-11 | 2015-03-10 | 半导体器件及其制造方法 |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2014-047608 | 2014-03-11 | ||
JP2014047608 | 2014-03-11 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2015137337A1 true WO2015137337A1 (ja) | 2015-09-17 |
Family
ID=54071780
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/JP2015/057009 WO2015137337A1 (ja) | 2014-03-11 | 2015-03-10 | 半導体装置およびその製造方法 |
Country Status (4)
Country | Link |
---|---|
US (1) | US9716183B2 (ja) |
JP (1) | JP6218923B2 (ja) |
CN (1) | CN106104810A (ja) |
WO (1) | WO2015137337A1 (ja) |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10263090B2 (en) * | 2017-04-24 | 2019-04-16 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device and manufacturing method thereof |
CN107369715A (zh) * | 2017-07-13 | 2017-11-21 | 南京中电熊猫平板显示科技有限公司 | 一种薄膜晶体管的制造方法 |
CN107564966B (zh) * | 2017-08-07 | 2020-05-05 | 武汉华星光电半导体显示技术有限公司 | 薄膜晶体管及薄膜晶体管的制造方法、液晶显示面板 |
CN110233109A (zh) * | 2019-06-24 | 2019-09-13 | 京东方科技集团股份有限公司 | 晶体管及其制备方法、阵列基板及其制备方法和显示面板 |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2001194659A (ja) * | 1999-03-26 | 2001-07-19 | Fuji Xerox Co Ltd | 薄膜トランジスタ一体型カラーフィルターの製造方法 |
JP2010161373A (ja) * | 2009-01-12 | 2010-07-22 | Samsung Mobile Display Co Ltd | 薄膜トランジスタ及びその製造方法、並びに薄膜トランジスタを備える平板表示装置 |
JP2013016612A (ja) * | 2011-07-04 | 2013-01-24 | Sony Corp | 半導体装置及びその製造方法、画像表示装置、並びに、画像表示装置を構成する基板 |
JP2013051421A (ja) * | 2009-12-09 | 2013-03-14 | Sharp Corp | 半導体装置 |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6503772B1 (en) * | 1999-03-26 | 2003-01-07 | Fuji Xerox Co., Ltd. | Method of manufacturing a thin film transistor-integrated color filter |
JP5303119B2 (ja) * | 2007-06-05 | 2013-10-02 | 株式会社ジャパンディスプレイ | 半導体装置 |
JPWO2009034953A1 (ja) | 2007-09-10 | 2010-12-24 | 出光興産株式会社 | 薄膜トランジスタ |
JP5561899B2 (ja) * | 2007-10-19 | 2014-07-30 | キヤノン株式会社 | 表示装置の製造方法 |
JP2011009393A (ja) | 2009-06-25 | 2011-01-13 | Sony Corp | 薄膜トランジスタ、薄膜トランジスタの製造方法、および表示装置 |
KR101995082B1 (ko) | 2010-12-03 | 2019-07-02 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | 산화물 반도체막 및 반도체 장치 |
-
2015
- 2015-03-10 JP JP2016507761A patent/JP6218923B2/ja not_active Expired - Fee Related
- 2015-03-10 CN CN201580013007.XA patent/CN106104810A/zh active Pending
- 2015-03-10 WO PCT/JP2015/057009 patent/WO2015137337A1/ja active Application Filing
- 2015-03-10 US US15/124,385 patent/US9716183B2/en active Active
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2001194659A (ja) * | 1999-03-26 | 2001-07-19 | Fuji Xerox Co Ltd | 薄膜トランジスタ一体型カラーフィルターの製造方法 |
JP2010161373A (ja) * | 2009-01-12 | 2010-07-22 | Samsung Mobile Display Co Ltd | 薄膜トランジスタ及びその製造方法、並びに薄膜トランジスタを備える平板表示装置 |
JP2013051421A (ja) * | 2009-12-09 | 2013-03-14 | Sharp Corp | 半導体装置 |
JP2013016612A (ja) * | 2011-07-04 | 2013-01-24 | Sony Corp | 半導体装置及びその製造方法、画像表示装置、並びに、画像表示装置を構成する基板 |
Also Published As
Publication number | Publication date |
---|---|
JP6218923B2 (ja) | 2017-10-25 |
US9716183B2 (en) | 2017-07-25 |
CN106104810A (zh) | 2016-11-09 |
US20170018646A1 (en) | 2017-01-19 |
JPWO2015137337A1 (ja) | 2017-04-06 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US8685803B2 (en) | Semiconductor device and method for producing same | |
CN108140675B (zh) | 半导体装置及其制造方法 | |
TWI538222B (zh) | 半導體裝置 | |
JP5209146B2 (ja) | 半導体装置およびその製造方法 | |
TWI600165B (zh) | 半導體裝置及其製造方法 | |
US20120199891A1 (en) | Semiconductor device and method for manufacturing same | |
US11302718B2 (en) | Active matrix substrate and production method therefor | |
US11637132B2 (en) | Active matrix substrate and method for manufacturing same | |
US11721704B2 (en) | Active matrix substrate | |
CN107851668B (zh) | 半导体装置及其制造方法 | |
WO2016104216A1 (ja) | 半導体装置、表示装置および半導体装置の製造方法 | |
JP6218923B2 (ja) | 半導体装置およびその製造方法 | |
US20210013238A1 (en) | Active matrix substrate and method for manufacturing same | |
JP7471075B2 (ja) | アクティブマトリクス基板およびその製造方法 | |
US9831352B2 (en) | Semiconductor device and method for manufacturing same | |
US11502115B2 (en) | Active matrix substrate and method for manufacturing same | |
JP2022191755A (ja) | 半導体装置 | |
US12034010B2 (en) | Active matrix substrate | |
JP7437359B2 (ja) | アクティブマトリクス基板およびその製造方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
121 | Ep: the epo has been informed by wipo that ep was designated in this application |
Ref document number: 15761976 Country of ref document: EP Kind code of ref document: A1 |
|
ENP | Entry into the national phase |
Ref document number: 2016507761 Country of ref document: JP Kind code of ref document: A |
|
WWE | Wipo information: entry into national phase |
Ref document number: 15124385 Country of ref document: US |
|
NENP | Non-entry into the national phase |
Ref country code: DE |
|
122 | Ep: pct application non-entry in european phase |
Ref document number: 15761976 Country of ref document: EP Kind code of ref document: A1 |