WO2015136659A1 - 位相同期ループ回路及び注入同期型分周器の周波数調整方法 - Google Patents
位相同期ループ回路及び注入同期型分周器の周波数調整方法 Download PDFInfo
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
- H03L7/183—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K23/00—Pulse counters comprising counting chains; Frequency dividers comprising counting chains
- H03K23/58—Gating or clocking signals not applied to all stages, i.e. asynchronous counters
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/089—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
- H03L7/0891—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses the up-down pulses controlling source and sink current generators, e.g. a charge pump
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/095—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using a lock detector
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/10—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range
- H03L7/107—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range using a variable transfer function for the loop, e.g. low pass filter having a variable bandwidth
- H03L7/1075—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range using a variable transfer function for the loop, e.g. low pass filter having a variable bandwidth by changing characteristics of the loop filter, e.g. changing the gain, changing the bandwidth
Definitions
- the present invention relates to a PLL (Phase Locked Loop) circuit, and more particularly to a frequency adjustment technology of an injection locked frequency divider (ILFD).
- PLL Phase Locked Loop
- ILFD injection locked frequency divider
- the ILFD may be used as a prescaler that divides an output of a voltage controlled oscillator (VCO).
- VCO voltage controlled oscillator
- the ILFD is based on the phenomenon of injection locking in which when an external signal is input to an oscillator having a free run frequency, the oscillator outputs a signal in synchronization with a frequency equal to an integral fraction of the input signal.
- ILFD has the advantage of improving operating frequency and reducing current consumption, compared to Emitter Coupled Logic (ECL) and Current Mode Logic (CML) dividers that have been conventionally used as prescalers. ing.
- ECL Emitter Coupled Logic
- CML Current Mode Logic
- ILFD has the property that it can operate only near the free run frequency. For this reason, for example, there is a problem that the division operation may become impossible if the characteristic of the element varies depending on the manufacturing conditions, the temperature and the power supply voltage and the free run frequency of the divider deviates from the desired operating frequency. Have.
- An object of the present invention is to realize adjustment of a free run frequency of an ILFD with a simple configuration.
- the phase locked loop circuit of the present invention is An oscillator that outputs an oscillation signal having a frequency; A first injection locked frequency divider to which an oscillation signal having a frequency output from the oscillator is input; A filter for outputting a voltage to the oscillator; An output voltage supply unit that takes in an output voltage that the filter outputs to the oscillator, performs supply and disconnection of the taken output voltage to the injection-locked frequency divider, holds an output voltage of the filter, and outputs the output voltage And a supply unit having a holding voltage supply unit that supplies the held output voltage to the injection-locked frequency divider when the output voltage is shut off by the voltage supply unit.
- the present invention it is possible to adjust the frequency of the ILFD with a simple circuit configuration without the need for the frequency measurement means, the calculation means, and the like. Therefore, stable frequency dividing operation can be secured with a simple configuration.
- FIG. 2 is a diagram of the first embodiment and is a block diagram of a PLL circuit 1001.
- FIG. 7 is a diagram of Embodiment 1, which is a flowchart of operation of a PLL circuit 1001.
- FIG. FIG. 2 is a diagram of the first embodiment and is a block diagram of a PLL circuit 1002.
- FIG. 17 is a diagram of the first embodiment and is a block diagram of a PLL circuit 1003.
- FIG. 2 is a block diagram showing an analog-to-digital converter and a digital-to-analog converter used in a sample and hold circuit in the diagram of Embodiment 1;
- FIG. 17 is a diagram of the second embodiment and is a block diagram of a PLL circuit 2000.
- FIG. 17 is a diagram of the third embodiment and is a block diagram of a PLL circuit 3000.
- FIG. 21 is a diagram of the fourth embodiment and is a block diagram of a PLL circuit 4000.
- FIG. 18 is a diagram of the fourth embodiment and is a block diagram illustrating an example of a lock detection unit 95.
- FIG. 21 is a diagram of the fifth embodiment and is a block diagram of a PLL circuit 5000.
- FIG. 1 is a block diagram showing a PLL circuit 1001 according to the first embodiment.
- FIG. 2 is a flowchart showing the operation of the PLL circuit 1001.
- the PLL circuit 1001 inputs an oscillator control voltage output from the loop filter into an injection locked frequency divider (ILFD), forms a loop using the ILFD as an oscillator to form a PLL, and adjusts the free-running frequency of the ILFD. To realize.
- ILFD injection locked frequency divider
- the PLL circuit 1001 includes n (n is an integer of 1 or more) injection-locked frequency divider 10, frequency divider 20, phase comparator 30, charge pump 40, and loop filter connected in series. 50 (filter), n switches 60, n switches 61, n sample and hold circuits 70, a voltage controlled oscillator 100 (oscillator), and a timer circuit 300.
- the n injection locked frequency dividers 10 are described as IFLD 10 (1), IFLD 10 (2),... IFLD 10 (n). When it is not necessary to distinguish, it is described as IFLD10.
- the divider 20 is described as DIV 20.
- the phase comparator 30 is described as PFD 30.
- the charge pump 40 is described as CP40.
- the loop filter 50 is described as LP50.
- the n switches 60 are described as SW 60 (1), SW 60 (2),... SW 60 (n). When it is not necessary to distinguish, it is described as SW60.
- the n sample and hold circuits 70 are described as SH70 (1), SH70 (2),... SH70 (n). When it is not necessary to distinguish, it is described as SH70.
- the n switches 61 are described as SW 61 (1), SW 61 (2),... SW 61 (n). When it is not necessary to distinguish, it is described as SW61.
- IFLDs 10 (1) to IFLDs 10 (n) are connected in series.
- IFLDs 10 (1) to IFLD 10 (n) connected in series receive the output frequency of voltage controlled oscillator 100 (hereinafter referred to as VCO 100) whose oscillation frequency changes according to the input voltage from the frequency control terminal.
- VCO 100 voltage controlled oscillator 100
- Divide the output frequency by the division ratio of The VCO 100 outputs an oscillation signal having a frequency corresponding to the input voltage from the frequency control terminal.
- the DIV 20 divides the output frequency of the ILFD 10 (n) by a predetermined dividing ratio.
- the PFD 30 detects the phase difference between the division result signal (denoted as CKDIV) output from the DIV 20 and the reference clock (denoted as CKREF).
- the CP 40 receives the output of the PFD 30 and outputs a current or voltage.
- the LPF 50 smoothes the output of the CP 40 and outputs the frequency control voltage Vtune.
- the SW 60 (1) to the SW 60 (n) select whether to supply the control voltage Vtune to the ILFD 10 (1) to the ILFD 10 (n).
- SH70 (1) to SH70 (n) sample and hold control voltages of ILFD 10 (1) to ILFD 10 (n).
- the switches SW61 (1) to SW61 (n) select whether to supply the output voltages of SH70 (1) to SH70 (n) to the ILFDs 10 (1) to IFLD 10 (n), respectively.
- the timer circuit 300 controls the SW 60, the SW 61, the SH 70, the ILFD 10, and the DA 80 and AD 90 described later.
- the supply unit 201 includes SW60 (1) to SW60 (n), SW61 (1) to SW61 (n), and SH70 (1) to SH70 (n).
- the switches SW60 (1) to SW60 (n) take in the output voltage that the LPF 50 outputs to the VCO 100, and supply and shut off the received output voltage to the ILFD 10 (1) to the IFLD 10 (n).
- SW60 (1) to SW60 (n) are output voltage supply units.
- SW61 (1) to SW61 (n) and SH70 (1) to SH70 (n) are IFLD that hold the output voltage when the output voltage is cut off by SW60 (1) to SW60 (n). (1) to IFLD (n).
- SW 61 (1) to SW 61 (n) and SH 70 (1) to SH 70 (n) are holding voltage supply units.
- the timer circuit 300 is the main operation.
- the timer circuit 300 opens all the switches (SW60 (1) to SW60 (n) and SW61 (1) to SW61 (n)) (S30).
- the adjustment is started from the ILFD 10 (n) connected to the DIV 20 with the lowest operating frequency among the ILFDs 10 (1) to IFLD 10 (n) (S40). Therefore, the timer circuit 300 closes the SW 60 (n) connecting the output voltage Vtune of the LPF 50 to the ILFD 10 (n), and uses the ILFD 10 (n) as an oscillator (S50).
- the loop PLL (n) configured of the ILFD 10 (n), the DIV 20, the PFD 30, the CP 40, and the LPF 50 is configured to start the lock operation.
- the output frequency of the ILFD 10 (n) converges to a constant value, and becomes locked (S60).
- S60 it is considered that the lock state is reached when a predetermined time has elapsed.
- the configuration having a lock detection unit for detecting the lock state will be described later in the fourth embodiment.
- the timer circuit 300 After the loop PLL (n) is in the locked state, the timer circuit 300 holds the output voltage Vtune of the LPF 50 at that time with SH70 (n), opens the SW 60 (n), closes the SW 61 (n). Then, the frequency adjustment of the ILFD 10 (n) is completed (S70). Thereafter, in the same procedure, the timer circuit 300 sequentially adjusts the ILFDs 10 (n-1) to the ILFDs 10 (1) (S80, S90).
- the timer circuit 300 configures a PLL composed of the VCO 100, the ILFDs 10 (1) to the ILFDs 10 (n), the DIV 20, the PFD 30, the CP 40, and the LPF 50 and performs locking operation (normal PLL operation) ) Is started (S110).
- the operation S30 in FIG. 2 is a so-called reset (initial) operation, and the state of the ILFD 10 is determined by the adjustment operation after S40. As a result, the reset operation S30 does not affect the PLL normal operation S110. Therefore, the reset operation S30 may be omitted.
- FIG. 3 is a block diagram of the PLL circuit 1002. As shown in FIG. The supply unit 202 is different from FIG. FIG. 3 is a view showing the supply unit 202 having a simpler configuration than the supply unit 201 of FIG.
- the supply unit 202 includes SWs 60 (1) to SW 60 (n) and sampling capacitors C63 (1) to C63 (n).
- the supply unit 201 (sample hold circuit SH70, switches SW60 and SW61) of FIG. 1 is a switch SW60 connected between the output of the LP 50 and the control terminal of the ILFD 10, and a predetermined reference with the control terminal of the ILFD 10. It is comprised by sampling capacitance C63 connected between voltage (for example, ground etc.).
- FIG. 3 shows a configuration of a switch and a sampling capacitor (capacitor).
- the supply unit 202 can be realized by the switches SW60 (1) to SW60 (n) and the sampling capacitors C63 (1) to C63 (n) corresponding to the switches SW60 (1) to SW60 (n). Therefore, the SW 61 (1) to the SW 61 (n) in FIG. 1 are unnecessary.
- SW60 (1) to SW60 (n) are output voltage supply units
- sampling capacitors C63 (1) to C63 (n) are holding voltage supply units.
- the supply unit 202 corresponds to SH70 (1) to SH70 (n) in FIG.
- FIG. 4 is a configuration diagram of the PLL circuit 1003.
- the supply unit 203 is different from FIG. FIG. 4 shows the configuration of the supply unit 203 different from the supply unit 201.
- the SH 70 of FIG. 1 is realized by the n digital-to-analog converters 80 (referred to as DA 80) and one analog-to-digital converter 90 (referred to as AD 90).
- the n DAs 80 are denoted as DA80 (1) to DA80 (n).
- the AD 90 may be provided for each of DA 80 (1) to DA 80 (n).
- the supply unit 203 includes SW60 (1) to SW60 (n), SW61 (1) to SW61 (n), DA80 (1) to DA80 (n), and AD90.
- DA80 (1) to DA80 (n) and AD90 correspond to SH70 (1) to SH70 (n) in FIG.
- SW60 (1) to SW60 (n) are output voltage supply units.
- DA80 (1) to DA80 (n), AD90, and SW61 (1) to SW61 (n) are holding voltage supply units.
- FIG. 5 is a diagram showing specific configurations of DA80 (1) to DA80 (n) and AD90.
- DA80 (1) to DA80 (n) are R-2R type DA converters.
- the AD 90 is a voltage comparator and SAR (Successive Approximation Resistor) control logic.
- a sample-and-hold operation can be realized by the SAR type AD converter performing AD conversion and holding of Vtune.
- the ILFD 10 can be adjusted with a simple configuration of an AD converter, a DA converter, and a switch.
- FIG. 6 is a block diagram showing a PLL circuit 2000 according to the second embodiment.
- the LPF 50 receives control to switch the cutoff frequency between the normal time and the ILFD adjustment time.
- the convergence time and stability of the PLL depend on the cut-off frequency of the loop filter. Therefore, by switching the cut-off frequency of the loop filter, for example, the cut-off frequency is set low in normal times to reduce phase noise, and the cut-off frequency is set higher in normal times to adjust convergence time during adjustment. Shorten. As described above, since the cutoff frequency of the LPF 50 can be changed, it is possible to properly maintain the response characteristics of the PLL at the normal time and at the adjustment time.
- FIG. 7 is a block diagram showing a PLL circuit 3000 of the third embodiment. Here, only the difference from the PLL circuit 1001 of the first embodiment will be described.
- the CP 40 switches the output current level between the normal time and the ILFD adjustment time.
- the convergence time and stability of the PLL depend on the CP40 output current. Therefore, by switching the output current of the CP 40, for example, the output current of the CP 40 is set low in order to reduce phase noise in normal times, and the output current of the CP 40 is increased in order to shorten the convergence time during adjustment. Such switching makes it possible to properly maintain the response characteristics of the PLL circuit 3000 at the normal time and at the adjustment time.
- FIG. 8 is a block diagram showing a PLL circuit 4000 of the fourth embodiment.
- a lock detection unit 95 hereinafter referred to as an LD 95
- the LD 95 determines whether the PLL is in a locked state by determining whether the phase difference between CKREF and CKDIV is within a predetermined range.
- FIG. 9 shows a configuration example of the LD 95.
- the LD 95 can be realized by frequency counters 95-1A and 95-1B to which CKREF and CKDIV are input, and a lock determination unit 95-2 comparing the count value of each frequency counter.
- FIG. 10 is a block diagram showing a PLL circuit 5000 of the fifth embodiment.
- a switch 101 (1) for selecting whether or not to input a signal from the VCO 100 to the ILFD 10 (1) is added to the PLL circuit 1001 of FIG.
- the timer circuit 300 turns off the switch 101 (1) and the output of the VCO 100 is not input to the ILFD 10 (1).
- the VCO 100 in the case of the ILFD 10 (1)
- the possibility that the ILFD 10 (k) is synchronized with the signal of the previous stage and can not be adjusted to the free run state due to the input of the signal of (1) can be eliminated.
- the number of ILFDs 10 may be one.
- the operation of the PLL circuit has been described for the PLL circuit, but it is apparent that the operation of the PLL circuit can be understood as a method of adjusting the free run frequency of the ILFD.
- IFLD injection locked frequency divider
- DIV frequency divider
- PFD phase comparator
- 40 CP charge pump
- 50 LFP loop filter
- 60, 61, 101 SW switch
- 70 SH sample and hold circuit
- 80 DA converter digital analog converter
- 90 AD converter analog digital converter
- 95 LD lock detection unit
- 100 VCO voltage controlled oscillator
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Abstract
Description
周波数を有する発振信号を出力する発振器と、
前記発振器が出力する周波数を有する発振信号が入力される第1の注入同期型分周器と、
前記発振器へ電圧を出力するフィルタと、
前記フィルタが前記発振器へ出力する出力電圧を取り込み、取り込んだ出力電圧の前記注入同期型分周器への供給と遮断とを行う出力電圧供給部と、前記フィルタの出力電圧を保持し、前記出力電圧供給部により出力電圧の遮断が行われた場合に、保持された出力電圧を前記注入同期型分周器に供給する保持電圧供給部とを有する供給部と
を備えたことを特徴とする。
図1は、実施の形態1によるPLL回路1001を示すブロック図である。
図2は、PLL回路1001の動作を示すフローチャートである。PLL回路1001は、ループフィルタから出力される発振器制御電圧を注入同期型分周器(ILFD)に入力し、ILFDを発振器とするループを形成してPLLを構成し、ILFDのフリーラン周波数調整を実現する。
(1)n個の注入同期型分周器10は、IFLD10(1)、IFLD10(2)、・・・IFLD10(n)のように記す。区別する必要が無い場合はIFLD10と記す。
(2)分周器20は、DIV20と記す。
(3)位相比較器30はPFD30と記す。
(4)チャージポンプ40は、CP40と記す。
(5)ループフィルタ50は、LP50と記す。
(6)n個のスイッチ60は、SW60(1)、SW60(2)、・・・SW60(n)のように記す。区別する必要が無い場合はSW60と記す。
(7)n個のサンプルホールド回路70は、SH70(1)、SH70(2)、・・・SH70(n)のように記す。区別する必要が無い場合はSH70と記す。
(8)n個のスイッチ61は、SW61(1)、SW61(2)、・・・SW61(n)のように記す。区別する必要が無い場合はSW61と記す。
(2)DIV20は、ILFD10(n)の出力周波数を、所定の分周比で分周する。
(3)PFD30は、DIV20から出力される分周結果信号(CKDIVと記す)と、基準クロック(CKREFと記す)の位相差を検出する。
(4)CP40は、PFD30の出力を受けて電流もしくは電圧を出力する。
(5)LPF50は、CP40の出力を平滑化して周波数制御電圧Vtuneを出力する。
(6)SW60(1)~SW60(n)は、制御電圧VtuneをILFD10(1)~ILFD10(n)に供給するか否かを選択する。
(7)SH70(1)~SH70(n)は、ILFD10(1)~ILFD10(n)の制御電圧をサンプル及びホールドする。
(8)SW61(1)~SW61(n)は、SH70(1)~SH70(n)の出力電圧をILFD10(1)~IFLD10(n)にそれぞれ供給するか否かを選択する。
(9)タイマー回路300は、SW60,SW61、SH70、ILFD10や後述のDA80,AD90を制御する。
ここで、図2における動作S30はいわゆるリセット(初期)動作であり、ILFD10の状態はS40以降の調整動作により決定され、結果としてこのリセット動作S30がPLL通常動作S110には影響しない。このため、リセット動作S30は省略して構わない。
図6は、実施の形態2によるPLL回路2000を示すブロック図である。ここでは、実施の形態1のPLL回路1001との差分のみを説明する。実施の形態2のPLL回路2000では、LPF50が、制御を受けることにより、カットオフ周波数が、通常時とILFD調整時とで切り替わる。
図7は、実施の形態3のPLL回路3000を示すブロック図である。ここでは、実施の形態1のPLL回路1001との差分のみを説明する。実施の形態3のPLL回路3000では、CP40は、制御を受けることで、出力電流レベルが通常時とILFD調整時とで切り替わる。
図8は、実施の形態4のPLL回路4000を示すブロック図である。ここでは、実施の形態1のPLL回路1001との差分のみを説明する。実施の形態4のPLL回路4000では、図1のPLL回路1001に対してロック検出部95(以下、LD95と記す)が追加された。LD95は、CKREFとCKDIVの位相差が一定範囲内にあるか判定をすることで、PLLがロック状態にあるか否かを検出する。LD95がロック状態を検出したところで、タイマー回路300はILFD10(k)(k=1,2、・・・n)の調整完了と判断できる。
図9は、LD95の構成例を示す。LD95は、例えば図9のように、CKREFとCKDIVが入力される周波数カウンタ95-1A、95-1Bと、各周波数カウンタのカウント値を比較するロック判定部95-2とによって実現ができる。
図10は、実施の形態5のPLL回路5000を示すブロック図である。ここでは、実施の形態1のPLL回路1001との差分にのみを説明する。実施の形態5のPLL回路5000では、図1のPLL回路1001に対して、VCO100からILFD10(1)に、信号を入力するか否かを選択するスイッチ101(1)が追加された。ILFD10(1)の調整中には、タイマー回路300がスイッチ101(1)をオフにし、VCO100の出力がILFD10(1)に入力されない。また、同様に、ILFD10(2)~ILFD10(n)にも、入力箇所に、タイマー回路300によって制御されるスイッチ101(1)~101(n)を設けた。これにより、ILFD10(k)(k=1,2,3、・・・n)の調整中に、タイマー回路300がスイッチ101(k)をオフにし、ILFD10(k)に、前段の出力信号が入力されないようにする。
Claims (14)
- 周波数を有する発振信号を出力する発振器と、
前記発振器が出力する周波数を有する発振信号が入力される第1の注入同期型分周器と、
前記発振器へ電圧を出力するフィルタと、
前記フィルタが前記発振器へ出力する出力電圧を取り込み、取り込んだ出力電圧の前記注入同期型分周器への供給と遮断とを行う出力電圧供給部と、前記フィルタの出力電圧を保持し、前記出力電圧供給部により出力電圧の遮断が行われた場合に、保持された出力電圧を前記注入同期型分周器に供給する保持電圧供給部とを有する供給部と
を備えたことを特徴とする位相同期ループ回路。 - 前記位相同期ループ回路は、
直列に接続された複数の注入同期型分周器あって、直列の最初の注入同期型分周器が前記第1の注入同期型分周器である複数の注入同期型分周器を備え、
前記供給部は、
前記出力電圧供給部が、取り込んだ出力電圧の各注入同期型分周器への供給と遮断とを行い、
前記保持電圧供給部が、前記フィルタの出力電圧を保持し、前記出力電圧供給部により出力電圧の遮断が行われた場合に、保持された出力電圧を出力電圧が遮断された前記注入同期型分周器に供給することを特徴とする請求項1記載の位相同期ループ回路。 - 前記供給部は、
前記フィルタの出力電圧の前記注入同期型分周器への供給と、
前記フィルタの出力電圧の保持と、
出力電圧の前記注入同期型分周器への供給の遮断と、
出力電圧の遮断後の保持された出力電圧の前記注入同期型分周器への供給と
の一連の処理を、
前記注入同期型分周器ごとに、順番に行うことを特徴とする請求項2記載の位相同期ループ回路。 - 前記出力電圧供給部は、
前記注入同期型分周器ごとに設けられ、前記フィルタの出力電圧の前記注入同期型分周器への供給と遮断とを行うスイッチを有し、
前記保持電圧供給部は、
前記注入同期型分周器ごとに設けられ、前記フィルタの出力電圧を保持するサンプルホールド回路と、前記注入同期型分周器ごとに設けられ、前記サンプルホールド回路の出力の前記注入同期型分周器への供給と遮断とを行うスイッチとを
有することを特徴とする請求項2または3に記載の位相同期ループ回路。 - 前記出力電圧供給部は、
前記注入同期型分周器ごとに設けられ、前記フィルタの出力電圧の前記注入同期型分周器への供給と遮断とを行うスイッチを有し、
前記保持電圧供給部は、
前記注入同期型分周器ごとに設けられ、前記注入同期型分周器と前記スイッチとの間に配置されたコンデンサを有することを特徴とする請求項2または3に記載の位相同期ループ回路。 - 前記出力電圧供給部は、
前記注入同期型分周器ごとに設けられ、前記フィルタの出力電圧の前記注入同期型分周器への供給と遮断とを行うスイッチを有し、
前記保持電圧供給部は、
前記フィルタの出力電圧を取り込むアナログディジタルコンバータと、
前記注入同期型分周器ごとに設けられ、前記アナログディジタルコンバータの出力を取り込むディジタルアナログコンバータと、
前記ディジタルアナログコンバータごとに設けられ、前記ディジタルアナログコンバータと前記注入同期型分周器との間に配置され、前記ディジタルアナログコンバータの出力信号の前記注入同期型分周器への供給と遮断とを行うスイッチと
を有することを特徴とする請求項2または3に記載の位相同期ループ回路。 - 前記アナログディジタルコンバータは、
前記注入同期型分周器ごとに設けられたことを特徴とする請求項6記載の位相同期ループ回路。 - 前記フィルタは、
制御を受けることで、カットオフ周波数が切り替わることを特徴とする請求項1~7のいずれかに記載の位相同期ループ回路。 - 前記位相同期ループ回路は、
前記フィルタに電流を出力するチャージポンプであって、出力する電流のレベルが、制御を受けることで切り替わるチャージポンプを備えたことを特徴とする請求項1~8のいずれかに記載の位相同期ループ回路。 - 前記位相同期ループ回路は、
前記出力電圧供給部によって前記出力電圧が供給されている前記注入同期型分周器が、前記注入同期型分周器の出力信号と、基準となる基準信号との位相差に基づき定まるロック状態にあるかどうかを検出するロック検出部を備えたことを特徴とする請求項1~9のいずれかに記載の位相同期ループ回路。 - 前記位相同期ループ回路は、
前記発振器と前記第1の注入同期型分周器との間と、前記注入同期型分周器どうしの間とに、制御によってオンとオフとが切り替わるスイッチを備えたことを特徴とする請求項2~7のいずれかに記載の位相同期ループ回路。 - 供給部と注入同期型分周器とを備えた位相同期ループ回路の前記注入同期型分周器のフリーラン周波数の調整方法において、
前記供給部が、
フィルタが発振器に出力する出力電圧を取り込み、取り込んだ出力電圧の第1の注入同期型分周器への供給を開始し、
出力電圧の供給の開始時点から時間が経過した時点の前記フィルタの出力電圧を保持し、かつ、出力電圧の前記第1の注入同期型分周器への供給の遮断を実行し、
出力電圧の前記第1の注入同期型分周器への供給の遮断後に、保持された出力電圧を前記第1の注入同期型分周器に供給することを特徴とするフリーラン周波数の調整方法。 - 前記位相同期ループ回路は、
直列に接続された複数の注入同期型分周器あって、直列の最初の注入同期型分周器が前記第1の注入同期型分周器である複数の注入同期型分周器を備え、
前記供給部は、
前記フィルタの出力電圧の前記注入同期型分周器への供給開始と、
前記フィルタの出力電圧の保持と、
出力電圧の前記注入同期型分周器への供給の遮断と、
出力電圧の遮断後の保持された出力電圧の前記注入同期型分周器への供給と
の一連の処理を、
注入同期型分周器ごとに、順番に行うことを特徴とする請求項12記載のフリーラン周波数の調整方法。 - 前記複数の注入同期型分周器は、
前記発振器に接続する前記第1の注入同期型分周器と、前記第1の注入同期型分周器に直列に接続する1以上の注入同期型分周器とによって直列接続を作り、
前記供給部は、
前記直列に接続された複数の注入同期型分周器のうち、直列接続において前記発振器に対して遠い注入同期型分周器から、前記一連の処理を実行することを特徴とする請求項13記載のフリーラン周波数の調整方法。
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US15/111,701 US9847785B2 (en) | 2014-03-13 | 2014-03-13 | Phase locked loop circuit and method of frequency adjustment of injection locked frequency divider |
PCT/JP2014/056623 WO2015136659A1 (ja) | 2014-03-13 | 2014-03-13 | 位相同期ループ回路及び注入同期型分周器の周波数調整方法 |
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US10862423B2 (en) | 2018-01-25 | 2020-12-08 | University College Dublin | Multi-stage sub-THz frequency generator incorporating injection locking |
US10771296B1 (en) * | 2019-06-25 | 2020-09-08 | Realtek Semiconductor Corp. | 2.4GHz ISM band zero-IF transceiver and method thereof |
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