WO2015115266A1 - 窒化物半導体素子 - Google Patents
窒化物半導体素子 Download PDFInfo
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- WO2015115266A1 WO2015115266A1 PCT/JP2015/051480 JP2015051480W WO2015115266A1 WO 2015115266 A1 WO2015115266 A1 WO 2015115266A1 JP 2015051480 W JP2015051480 W JP 2015051480W WO 2015115266 A1 WO2015115266 A1 WO 2015115266A1
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- 150000004767 nitrides Chemical class 0.000 title claims abstract description 83
- 239000004065 semiconductor Substances 0.000 title claims abstract description 81
- 239000000758 substrate Substances 0.000 claims abstract description 59
- 239000010410 layer Substances 0.000 claims description 152
- 239000002346 layers by function Substances 0.000 claims description 13
- 229910002704 AlGaN Inorganic materials 0.000 description 13
- 238000000034 method Methods 0.000 description 11
- 229910052594 sapphire Inorganic materials 0.000 description 11
- 239000010980 sapphire Substances 0.000 description 11
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 10
- 239000013078 crystal Substances 0.000 description 10
- 238000000605 extraction Methods 0.000 description 10
- 230000000694 effects Effects 0.000 description 9
- 230000005684 electric field Effects 0.000 description 7
- 238000001878 scanning electron micrograph Methods 0.000 description 7
- 230000004888 barrier function Effects 0.000 description 6
- 239000012159 carrier gas Substances 0.000 description 6
- 230000007423 decrease Effects 0.000 description 6
- 239000001257 hydrogen Substances 0.000 description 6
- 229910052739 hydrogen Inorganic materials 0.000 description 6
- 238000005259 measurement Methods 0.000 description 6
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 5
- 229910052757 nitrogen Inorganic materials 0.000 description 5
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 4
- 238000009792 diffusion process Methods 0.000 description 4
- 229910004298 SiO 2 Inorganic materials 0.000 description 3
- 230000007547 defect Effects 0.000 description 3
- 239000002019 doping agent Substances 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 230000006870 function Effects 0.000 description 3
- 230000006872 improvement Effects 0.000 description 3
- 230000008569 process Effects 0.000 description 3
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 3
- 229910010271 silicon carbide Inorganic materials 0.000 description 3
- 230000005428 wave function Effects 0.000 description 3
- 230000004913 activation Effects 0.000 description 2
- 238000005452 bending Methods 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 239000003086 colorant Substances 0.000 description 2
- 238000000295 emission spectrum Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 230000005012 migration Effects 0.000 description 2
- 238000013508 migration Methods 0.000 description 2
- 230000006798 recombination Effects 0.000 description 2
- 238000005215 recombination Methods 0.000 description 2
- 238000000851 scanning transmission electron micrograph Methods 0.000 description 2
- 239000000243 solution Substances 0.000 description 2
- 229910002601 GaN Inorganic materials 0.000 description 1
- 238000010521 absorption reaction Methods 0.000 description 1
- 125000004429 atom Chemical group 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 230000000994 depressogenic effect Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005401 electroluminescence Methods 0.000 description 1
- 238000011156 evaluation Methods 0.000 description 1
- 230000005284 excitation Effects 0.000 description 1
- 150000002431 hydrogen Chemical class 0.000 description 1
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 230000031700 light absorption Effects 0.000 description 1
- 238000004020 luminiscence type Methods 0.000 description 1
- 238000013507 mapping Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000002488 metal-organic chemical vapour deposition Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 230000000737 periodic effect Effects 0.000 description 1
- 238000005424 photoluminescence Methods 0.000 description 1
- 230000000704 physical effect Effects 0.000 description 1
- 230000010287 polarization Effects 0.000 description 1
- 230000008092 positive effect Effects 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 238000002310 reflectometry Methods 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 229910052596 spinel Inorganic materials 0.000 description 1
- 239000011029 spinel Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 239000004094 surface-active agent Substances 0.000 description 1
- 238000002834 transmittance Methods 0.000 description 1
- 230000005641 tunneling Effects 0.000 description 1
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/20—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate
- H01L33/24—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate of the light emitting region, e.g. non-planar junction
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02367—Substrates
- H01L21/0237—Materials
- H01L21/0242—Crystalline insulating materials
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02367—Substrates
- H01L21/02428—Structure
- H01L21/0243—Surface structure
-
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- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02367—Substrates
- H01L21/02433—Crystal orientation
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02436—Intermediate layers between substrates and deposited layers
- H01L21/02439—Materials
- H01L21/02455—Group 13/15 materials
- H01L21/02458—Nitrides
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- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02436—Intermediate layers between substrates and deposited layers
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- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02436—Intermediate layers between substrates and deposited layers
- H01L21/02494—Structure
- H01L21/02496—Layer structure
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- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
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- H01L21/02538—Group 13/15 materials
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- H01L33/26—Materials of the light emitting region
- H01L33/30—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table
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- H01L33/40—Materials therefor
- H01L33/42—Transparent materials
Definitions
- the present invention relates to a nitride semiconductor device.
- the lattice constant in the a-axis direction changes depending on the composition of the group 3 element, so that a piezoelectric field is generated when heterojunction is performed.
- the matrix element which is one element that determines the luminescence recombination lifetime, becomes smaller, so that the luminous efficiency is theoretically lowered. Therefore, semipolar and nonpolar techniques with small or no polarization have been proposed.
- Non-Patent Document 1 an attempt is made to cut a GaN substrate into a semipolar surface and grow on the surface.
- Non-patent Document 2 there is a method of obtaining a nonpolar surface by growing an R surface on a sapphire substrate (Non-patent Document 2) or growing from an uneven sidewall.
- Non-Patent Document 4 a trapezoidal n-GaN array having an inclined surface is formed in a stripe shape on the C-plane (0001) of an n-GaN layer in which a stripe-like SiO 2 mask is partially arranged. Then, a method of forming an InGaN / GaN multiple quantum well (MQW) light emitting layer so as to cover the n-GaN array is disclosed.
- MQW InGaN / GaN multiple quantum well
- problems when using the GaN substrate disclosed in Non-Patent Document 1 include difficulty in large diameter and high cost.
- Non-Patent Document 2 epitaxially grown on an R-plane sapphire substrate has a large half-value width of XRD of 700 arcsec in the c-axis direction and 1200 arcsec (main surface) in the m-axis direction, and has a high dislocation density.
- high-quality crystal growth has not been established.
- surface faults stacking faults propagate upward at a high density, which greatly affects crystallinity.
- a protective film needs to be laminated, and the process becomes complicated. Also, the growth from the uneven sidewall is difficult to control.
- Non-Patent Document 4 since the LED described in Non-Patent Document 4 emits two colors, it is difficult to obtain a high-efficiency LED with monochromatic emission, and the emission volume is reduced because it is formed by arranging a striped SiO 2 mask. It cannot be raised enough. Furthermore, there is a problem that a step of disposing a SiO 2 mask is required.
- the embodiment disclosed herein includes a substrate having an uneven surface, a nitride semiconductor underlayer on the substrate, and a nitride semiconductor functional layer on the nitride semiconductor underlayer, and the nitride semiconductor underlayer includes C
- the nitride semiconductor underlayer includes C
- a nitride semiconductor including a concavo-convex surface comprising an inclined surface inclined at an angle of 50 ° or more and 65 ° or less with respect to the surface, and the nitride semiconductor functional layer is provided on the concavo-convex surface of the nitride semiconductor underlayer It is an element.
- a piezo electric field using a substrate made of sapphire, spinel, SiC (silicon carbide), Si (silicon), etc. which has been subjected to unevenness processing, even if it is not an R-plane or N-plane GaN substrate. Therefore, the light emission efficiency of the light emitting element can be improved. Furthermore, the light extraction efficiency can be increased by exposing the uneven surface. Further, the operating voltage can be lowered by increasing the contact area. Sapphire can be used because of its low absorption coefficient even in the ultraviolet region. Further, since the growth is performed while obtaining stable C-plane kinetics, the crystallinity can be grown so high that it does not differ from the C-plane.
- the concavo-convex surface is formed so that at least one of the R surface and the N surface is exposed.
- the exposure means that at least one of the R surface and the N surface of the concavo-convex surface is exposed in a layer (nitride semiconductor underlayer) below the nitride semiconductor functional layer that functions as a light emitting layer, a light receiving layer, or the like.
- a nitride semiconductor functional layer such as a light emitting layer or a light receiving layer is laminated on at least one of the surface and the N surface. Therefore, the nitride semiconductor functional layer such as the light emitting layer or the light receiving layer is formed along the inclined surface (oblique facet surface) of the uneven surface.
- the nitride semiconductor functional layer such as the light emitting layer or the light receiving layer may be embedded by a layer stacked thereon.
- a structure in which a nitride semiconductor functional layer such as a light emitting layer or a light receiving layer is not embedded is preferable.
- the R plane and the N plane exposed by facet growth in this specification are respectively surrounded by an ideal R plane (a plane surrounded by a solid line in FIG. 16) and an ideal N plane (a solid line in FIG. 17).
- an inclined surface inclined at an angle of 50 ° to 65 ° with respect to the C surface and preferably inclined at an angle of 50 ° to 65 ° with respect to the C surface.
- the nitride semiconductor functional layer is a nitride semiconductor layer capable of expressing some function such as a light emitting layer or a light receiving layer.
- the nitride semiconductor underlayer is a nitride semiconductor layer located on the lower side (substrate side) of the nitride semiconductor functional layer.
- the nitride semiconductor layer is a nitride semiconductor crystal represented by the formula In ⁇ Al ⁇ Ga ⁇ N (0 ⁇ ⁇ ⁇ 1, 0 ⁇ ⁇ ⁇ 1, 0 ⁇ ⁇ ⁇ 1, ( ⁇ + ⁇ + ⁇ )> 0).
- the nitride semiconductor crystal layer may be doped with an n-type dopant and / or a p-type dopant, or may be undoped.
- the concave portion of the uneven surface may be located above the convex portion of the uneven surface of the substrate.
- the substrate 11 has dot-shaped protrusions 12, and the unevenness that exposes at least one of the R plane and the N plane by facet growth on the dot-shaped protrusions 12.
- the convex portion 13a of the concave and convex surface 13 forms a hexagonal side in the top view of the concave and convex surface 13, and a plurality of hexagons are arranged side by side so as to contact each other. It is preferable. There are cases where two main surfaces are mixed and dodecagons are arranged side by side. In fact, as shown in FIG. 3, when observed closely, the N plane may be exposed, so that it may not be a hexagon.
- the substrate 11 has a stripe-shaped convex portion 12, and at least one of the R plane and the N plane is exposed on the stripe-shaped convex portion 12 by facet growth.
- the uneven surface 13 to be formed can also be formed.
- the R surface and the N surface are mixedly exposed on the uneven surface. Details are unknown, but when the R and N surfaces are exposed on the uneven surface, the R and N surfaces can be controlled by changing the growth conditions, and a wider design Is possible. Further, in the top view of the uneven surface, it is preferable that the hexagon is a dodecagon because the surface area is increased. Further, if the ratio of the R plane and the N plane changes during growth depending on the growth conditions, it means that the growth rate of each plane of growth changes, and the behavior of threading dislocations also changes. It is also possible to bend the dislocation in the process of changing the exposed surface.
- the inclined surface (oblique facet surface) of the uneven surface is preferably an Al x Ga 1-x N (0 ⁇ x ⁇ 1) layer.
- a material other than Al x Ga 1-x N (0 ⁇ x ⁇ 1) can be used for the uppermost layer or the intermediate layer.
- an AlGaN (0 ⁇ x ⁇ 1) layer In may be included, but the quaternary mixed crystal is difficult to control and is not suitable for obtaining a layer thickness sufficient to form a facet. If it is included, there is an electron doping effect such as a surfactant effect, which may be preferable.),
- the growth rate of the C plane is high, and the R plane and the N plane tend to be exposed. Therefore, it is preferable because the degree of freedom of growth conditions (for example, growth temperature, growth rate, V / III ratio, etc.) for obtaining facets is increased.
- FIG. 2 There may be a cavity above the protrusion on the uneven surface of the substrate.
- FIG. 2 it can be seen that there is a slightly elongated cavity in the right part above the convex part of the uneven surface of the substrate. This is due to the fact that when facet growth is continued, the grains fit perfectly and leave a slight gap without meeting. For example, this can be expected to have effects such as relaxation of strain and warpage, and effective termination for threading dislocations (see FIG. 20).
- a cavity may exist on the slope of the uneven surface of the substrate.
- this is a cavity formed when a nitride layer having a surface in which grains (crystal grain boundaries) abnormally grown on the protrusions on the uneven surface of the substrate are aligned is associated.
- This is an effect unique to facet growth, and is a characteristic seen in many cases of this structure with continued facet growth. For example, this can be expected to have effects such as relaxation of distortion, warpage, and effective termination for threading dislocations.
- a depression may exist at the bottom of the concave portion of the uneven surface. This is the same as described above, and occurs because the grains including the facet surfaces have gaps. This may be an essential part of realizing this structure. Effects such as prevention of dislocation propagation are conceivable.
- FIG. 2 is a SEM (Scanning Electron Microscope) image of a cross section of a low-temperature Al 0.1 Ga 0.9 N fourth layer produced in Example 1.
- FIG. 2 is a SEM image of a cross section of a low-temperature Al 0.1 Ga 0.9 N fourth layer produced in Example 1.
- FIG. 3 is a SEM image of the low-temperature Al 0.1 Ga 0.9 N fourth layer produced in Example 1 as viewed from above. 2 is a SEM image of a flat portion of the nitride semiconductor LED wafer of Example 1.
- FIG. 4 is a SEM image of a cross section of an end portion of a Si-doped n-type Al 0.1 Ga 0.9 N third layer produced in Example 1.
- FIG. 4 is a SEM image of a cross section of an end portion of a Si-doped n-type Al 0.1 Ga 0.9 N third layer produced in Example 1.
- FIG. 4 is a SEM image of the end of the Si-doped n-type Al 0.1 Ga 0.9 N third layer produced in Example 1 as viewed from above.
- 2 is a PL emission spectrum of a flat portion of a wafer produced in Example 1.
- FIG. 2 is a PL emission spectrum of a concavo-convex portion at an end portion of a wafer manufactured in Example 1.
- FIG. It is PL wavelength distribution obtained by PL (photoluminescence) measurement. It is PL peak intensity distribution obtained by PL measurement. It is PL integral intensity distribution obtained by PL measurement.
- FIG. 4 is a STEM (Scanning transmission electron microscope) image of an end portion of the nitride semiconductor LED wafer of Example 2.
- FIG. 4 is a STEM image of an end portion of a nitride semiconductor LED wafer of Example 2.
- FIG. 6 is a schematic cross-sectional view of a nitride semiconductor LED chip of Example 3.
- the present invention forms a base by performing facet growth on a substrate having an uneven surface (for example, Si, SiC, sapphire, GaN, etc.) and maintaining its shape or changing the exposed surface during the growth process.
- a nitride semiconductor layer such as a light emitting layer or a light receiving layer is grown from a surface different from the main surface of the substrate.
- the selectivity of the growth surface is significantly increased.
- the volume of the light emitting layer or the light receiving layer per substrate unit plane can be increased, and the light emitting volume or the light receiving volume can be increased.
- the substrate is grown in a pattern in which the convex portion has a hexagonal polka dot pattern when viewed from above.
- an oblique facet surface having a depression above the convex portion of the concavo-convex surface of the substrate can be formed, so that the shape of the light emitting layer when completely grown in the R plane or N plane is viewed from above.
- the shape is an inverted hexagonal pyramid. Then, when the R plane grows with an inclination of about 60 ° with respect to the C plane, the area is about 1.5 times that of the plane.
- FIG. 15 shows the relationship between the tilt angle [°] with respect to the C plane of In 0.2 Ga 0.8 N on GaN and the discontinuity [C / m 2 ] of total polarity (see Non-Patent Document 3).
- the white circles in FIG. 15 correspond to the R plane and the N plane. According to this, the piezo electric field is approximately 1/5 or less compared with the case where it grows on the C plane. This theory holds true even for the AlGaN / GaN interface.
- the overlap integral of the wave function is increased, the light emission recombination lifetime can be shortened, and the light emission efficiency is improved as a result. Furthermore, it is not easy to make a good quality base crystal by growing the R plane and the N plane in the nitride having strong c-axis orientation.
- the quality is the same as that of growing a C plane nitride layer on the C plane. (Value width, threading dislocation, point defect, surface defect, etc.).
- non-polarity is a serious problem because surface faults propagate in the growth direction. In the present invention, this can be avoided.
- facet growth is possible with GaN and AlGaN, and this structure can then be realized by growing “without embedding”.
- AlGaN has a stronger three-dimensional growth element than GaN, and has a large tolerance for growth of facet growth having hexagonal to dodecagonal shapes (the case where the R and N planes are mixed in hexagons or more) in this natural formation.
- the facets having the light emitting layer or the light receiving layer are spatially fitted to each other, that is, in a state where there are few flat surfaces (2A in FIG. 6 and 3A in FIG. 7) generated between the facets.
- the important point of light extraction efficiency is how to increase the area of the oblique facet surface, because the area of the oblique facet surface is reduced by increasing the flat portion.
- the wavelength is changed, and the light emission efficiency may be reduced by using two wavelengths.
- AlGaN tends to have an N surface (11-21) when facet grown in the region of 1000 ° C. or higher, when the substrate 11 has dot-like convex portions 12 as shown in FIG.
- the convex portions 13a are arranged so as to form hexagonal sides, and the hexagonal sides formed by the convex portions 13a of the concavo-convex surface 13 are irregularities on the surface of a nitride semiconductor layer such as a light emitting layer or a light receiving layer.
- the flat surface showing the C surface is preferably small.
- the dot-like convex portions 12 of the substrate 11 are the most in the m-axis direction of a nitride semiconductor layer such as a light emitting layer or a light receiving layer stacked on the substrate 11. It is preferable to arrange so that the period is short.
- the plane can be switched from the N plane to the R plane. This switching may significantly change the behavior of dislocations or change physical properties, for example.
- low-temperature AlGaN can form V-shaped pits that can reduce the influence of dislocations on carriers in the light-emitting layer or light-receiving layer. Is also considered as a preferred example.
- the quantum well structure there is a portion formed so as to trace a hexagon to a dodecagon in the nano order near the bottom of the facet where it exists.
- this structure it is possible to alleviate warpage and distortion of the substrate and to prevent cracks.
- cracks are caused by doping and compositional changes in the case of an AlGaN layer.
- cracks occur because tensile stress is applied to the bonding with the GaN layer.
- the a-axis direction to which stress is applied meanders due to facets, the total strain and stress are alleviated. Therefore, cracks are unlikely to occur.
- the light extraction efficiency can be increased. Since damage due to etching can be reduced, oxidation due to etching at the time of contact can be prevented, and contact with an electrode (for example, a transparent conductive oxide film) can be performed without changing the surface state as compared with etching.
- an electrode for example, a transparent conductive oxide film
- light extraction efficiency is a major issue. This is because a transparent conductive oxide film having a high transmittance is difficult in principle. If the band gap is large, the bond energy is usually large, so that it is difficult to replace atoms with dopants.
- the present invention can control the facet shape (size, etc.) by changing the height and period of the protrusions on the uneven surface of the substrate, for example, in terms of light extraction efficiency, the appropriate unevenness depends on the wavelength. The period is different. Therefore, this variable feature has great merit.
- the present invention can be applied to, for example, an LED, a solar cell, a photodiode, or an electronic device.
- LED In LED, it can be used from deep ultraviolet to infrared region (200 nm to 2000 nm). Cracks are a major problem in the ultraviolet region (200 nm to 405 nm). As described above, since the direction of strain meanders due to the unevenness of the surface of the substrate, and the surface area per unit area of the substrate is increased, warping, strain and cracks are alleviated.
- the extraction efficiency becomes a big problem in the ultraviolet region. It is mentioned that there is no metal with high reflectivity and that there is no transparent conductive film satisfying transparency and high conductivity. Then, since the unevenness of the substrate and the unevenness of the surface are maintained by the uneven structure of the present invention, the impact on the extraction efficiency is considerably large.
- Carrier confinement is also a problem in the ultraviolet region. This is because a carrier block layer having a high band gap cannot be stacked. In such a case, a barrier layer having a large band offset with respect to the light emitting layer is one solution, but the piezo electric field is usually increased in the case of a polar surface. Thereby, the overlap of the wave function of the conduction band and the valence band is reduced, and the light emission efficiency is lowered.
- this structure is semipolar and the piezoelectric field is small, the demerit when the band offset is high is small, and the influence of the merit of carrier confinement is large, which is preferable.
- the present invention in which the piezoelectric field is small has a great merit in this wavelength region.
- red and infrared regions (480 nm to 2000 nm), as described in the explanation of the blue region, when a GaN barrier layer is used, the band offset with the light emitting layer increases, so the effect of reducing the piezo electric field is achieved. Becomes larger. Other advantages are approximately the same as the blue region.
- the contents described above also apply to light receiving elements such as solar cells and photodiodes.
- the efficiency of photoelectric conversion is increased by a decrease in the piezoelectric field.
- the light receiving area is also increased, so the yield is considered to increase.
- the contact resistance between the drain and gate electrodes and the nitride semiconductor layer is considered to be lowered from the viewpoint of contact area.
- a sapphire substrate 1 whose principal surface having a concavo-convex surface with a diameter of 4 inches is a C-plane (pitch P of the convex portion 1 a: 2 ⁇ m, width W of the convex portion 1 a: 1.
- the AlN buffer layer 8 was grown on 3 ⁇ m and the height H of the convex portion 1a: 0.6 ⁇ m).
- the temperature (growth temperature) of the sapphire substrate 1 is increased to 1255 ° C., and Al 0.1 Ga 0.9 N is formed on the AlN buffer layer 8 by using a carrier gas containing 47% nitrogen and 53% hydrogen in a molar flow rate ratio.
- the first layer 2 was grown to a thickness of 36.5 ⁇ m at a growth rate of 1.5 ⁇ m / h. Thereby, the facet layer with an uneven surface having a slant facets (Al 0.1 Ga 0.9 N first layer 2) is formed.
- the molar flow ratio of 90% nitrogen, with reference to a carrier gas containing 10% of hydrogen, Al 0.1 Ga 0.9 N thickness of 1.5 ⁇ m the Al 0.1 Ga 0.9 N second layer 3 on the first layer 2 To grow.
- the center portion of the wafer was filled with the Al 0.1 Ga 0.9 N layer 3 and the facet layer disappeared, but the facet layer having an uneven surface having an oblique facet surface was maintained at the edge of the wafer.
- the Si-doped n-type Al 0.1 Ga 0.9 N third layer 4 is formed on the Al 0.1 Ga 0.9 N second layer 3 under the same conditions as the Al 0.1 Ga 0.9 N second layer 3 except that SiH 4 is introduced. (Carrier concentration: 5 ⁇ 10 18 / cm 3 ) was grown. At this point, the growth of the nitride semiconductor layer was stopped and the end portion of the Si-doped n-type Al 0.1 Ga 0.9 N third layer 4 was observed by SEM. As a result, the N surface was mixed and exposed on the main R surface. Facets (oblique facet plane 4a) were observed. 5 to 7 show SEM observation results of the end portion of the Si-doped n-type Al 0.1 Ga 0.9 N third layer 4.
- the temperature of the sapphire substrate 1 is lowered to 930 ° C., and a carrier gas containing 97% nitrogen and 3% hydrogen is used on the Si-doped n-type Al 0.1 Ga 0.9 N third layer 4 with a molar flow ratio.
- a low-temperature Al 0.1 Ga 0.9 N fourth layer 5 (nitride semiconductor underlayer) having a thickness of 500 nm was formed.
- switching between the N plane and the R plane occurs, and the ratio of the R plane increases.
- 1 to 3 show the SEM observation results of the end portion of the low-temperature Al 0.1 Ga 0.9 N fourth layer 5.
- a light emitting layer 6 (nitride semiconductor functional layer) having a multiple quantum well structure was formed on the low temperature Al 0.1 Ga 0.9 N fourth layer 5.
- the light emitting layer 6 has a 20 nm thick barrier layer made of Al 0.1 Ga 0.9 N using a carrier gas containing 97% nitrogen and 3% hydrogen at a molar flow ratio, and 90% nitrogen at a molar flow ratio.
- a 13-nm-thick well layer made of GaN was alternately formed for five periods one by one using a carrier gas containing 10% hydrogen.
- the surface of the light emitting layer 6 also has an uneven shape, and the N face and the R face remain mixedly exposed on the oblique facet surface 6a of the light emitting layer 6.
- the temperature of the sapphire substrate 1 is increased to 1260 ° C., and Mg-doped p-type AlGaN, undoped AlGaN, and Mg A p-type layer 7 was formed by stacking doped p-type GaN in this order.
- the nitride semiconductor LED wafer of Example 1 was produced.
- the wafer having a diameter of 4 inches has an in-plane distribution due to the variation in the growth temperature, and the inside of the wafer is completely filled with the film and the outside is as in the present invention. It was. Therefore, it is considered that the growth temperature is an important factor in maintaining the facet.
- 10 to 13 show the results of PL measurement (excitation with a YAG laser beam having a wavelength of 266 nm). 10 shows the PL wavelength distribution, FIG. 11 shows the PL peak intensity distribution, FIG. 12 shows the PL integrated intensity distribution, and FIG. 13 shows the PL half-value width distribution.
- the PL peak intensity is about 1 (au) in the flat portion at the center of the nitride semiconductor LED wafer of Example 1 shown in FIG. Is 7 (au) and 7 times as large as the remaining portion (uneven portion). This is a remarkably high value.
- the PL peak wavelength at the central flat portion was 358 nm (FIG. 8), and the PL peak wavelength of the uneven portion at the end was 355 nm (FIG. 9). Since the PL peak wavelength is shortened at the oblique facet surface of the uneven portion at the end, the piezoelectric field may be lowered at the uneven portion at the end as described above.
- the PL half-value width of the central flat portion was 21.4 nm, whereas the PL half-value width of the uneven portion at the end portion was 14.1 nm.
- the PL half-value width was overwhelmingly smaller in the uneven portion at the end than in the central flat portion. Therefore, it was confirmed that the concavo-convex portion at the end has better crystallinity. This may be due to factors such as small band bending. In the band bending, when the luminescent layer is stacked as thick as 13 nm as in Example 1 in a state where a piezo electric field is applied, the curve is S-curved. As a result, the quantum level changes with respect to the growth direction, which may lead to uneven emission wavelengths. This also suggests that the piezoelectric field may have dropped.
- the X-ray half width of the central flat portion is (0004) (004) 102 arcsec, (1-102) (102) 417 arcsec at the central flat portion, and the uneven portion at the end having the oblique facet surface is (0004) ( 004) 122 arcsec, (1-102) (102) 363 arcsec, which were almost inferior.
- the R plane (10-11) is depressed. There is a possibility that the light extraction efficiency is improved due to the step on the N-plane (11-21).
- crystal plane orientation (0004) indicated by the four variables can be expressed by converting it into three variables (004) and (1-102) as three variables (102).
- nitride semiconductor LED wafer of Example 2 was fabricated in the same manner as in Example 1 except that it hardly entered.
- the PL peak wavelength of the concavo-convex portion at the end of the nitride semiconductor LED wafer of Example 2 is 362 nm, and is similar to the nitride semiconductor LED wafer of Example 1 in the flat portion at the center.
- the PL strength of the uneven portion having the oblique facet surface at the end portion was remarkably improved (the flat portion 1.3 [au] at the center, the uneven portion 5.4 [au] at the end portion).
- FIG. 20 and 21 show STEM images of the end portions of the nitride semiconductor LED wafer of Example 2.
- FIG. FIG. 20 shows that threading dislocations bend in the lateral direction and terminate in a cavity above the protrusion on the uneven surface of the substrate.
- FIG. 21 also shows that the periodic structure of the multiple quantum well structure of the light emitting layer is formed in parallel to the oblique facet plane.
- FIG. 22 is a schematic cross-sectional view of the nitride semiconductor LED chip of Example 3.
- a transparent conductive layer 20 made of ITO was formed on the p-type layer 7 to a thickness of 80 nm by sputtering at a temperature of 300 ° C.
- the transparent conductive layer 20, the p-type layer 7, the light emitting layer 6, and the low-temperature Al 0.1 Ga 0.9 N fourth layer 5 are patterned by ICP. did.
- a p-side pad electrode 21 made of Ti / Al for wire connection is formed on the transparent conductive layer 20, and the n-side pad electrode 22 is exposed on the Si-doped n-type Al 0.1 Ga 0.9 N third layer 4.
- the nitride semiconductor LED wafer of Example 3 was fabricated by forming the above.
- the substrate 1 of the nitride semiconductor LED wafer of Example 3 was divided by a laser scribing method to produce a nitride semiconductor LED chip of Example 3.
- the surface of the transparent conductive layer 20 was not flattened when the nitride semiconductor LED chip of Example 3 was manufactured, and the surfaces along the R plane and the N plane of the low-temperature Al 0.1 Ga 0.9 N fourth layer remained. .
- the PL intensity was higher than that obtained by growing the light emitting layer on the polar surface, so that it is expected that the EL (electroluminescence) also becomes high. Further, in the nitride semiconductor LED chip of Example 3, it is expected that the light emission efficiency does not easily decrease even in a large current density region (reduction of the drop phenomenon).
- the nitride semiconductor element of the present invention can be applied to, for example, electronic devices, light emitting diodes, semiconductor lasers, solar cells, photodiodes, and the like.
- 1 Sapphire substrate 2 Al 0.1 Ga 0.9 N first layer, 3 Al 0.1 Ga 0.9 N second layer, 3a oblique facet plane, 4 Si-doped n-type Al 0.1 Ga 0.9 N third layer, 5 low temperature Al 0.1 Ga 0.9 N 4th layer, 6 light emitting layer, 4a, 6a oblique facet surface, 7 p-type layer, 8 AlN buffer layer, 11 substrate, 12, 13a convex portion, 13 uneven surface, 20 transparent conductive layer, 21 p-side pad electrode, 22 n-side pad electrode.
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Abstract
Description
Claims (11)
- 凹凸表面を有する基板と、
前記基板上の窒化物半導体下地層と、
前記窒化物半導体下地層上の窒化物半導体機能層と、を含み、
前記窒化物半導体下地層は、C面に対して50°以上65°以下の角度で傾斜する傾斜面からなる凹凸面を表面として含み、
前記窒化物半導体機能層は、前記窒化物半導体下地層の前記凹凸面上に設けられている、窒化物半導体素子。 - 前記傾斜面は、a軸に対して50°以上65°以下の角度で傾斜する、請求項1に記載の窒化物半導体素子。
- 前記凹凸面は、前記傾斜面として、R面およびN面の少なくとも一方を含む、請求項1または請求項2に記載の窒化物半導体素子。
- 前記凹凸面の上面視において、前記凹凸面の凸部が6角形の辺を構成しており、前記6角形の複数が互いに接するように配置されている、請求項1~請求項3のいずれか1項に記載の窒化物半導体素子。
- 前記基板の前記凹凸表面の凸部の上方に前記凹凸面の凹部が位置している、請求項1~請求項4のいずれか1項に記載の窒化物半導体素子。
- 前記基板の前記凹凸表面の前記凸部がドット状に配置されている、請求項5に記載の窒化物半導体素子。
- 前記基板の前記凹凸表面の前記凸部の上方に空洞が存在する、請求項5または請求項6に記載の窒化物半導体素子。
- 前記窒化物半導体機能層は発光層を含み、
前記発光層が前記傾斜面上に設けられている、請求項1~請求項7のいずれか1項に記載の窒化物半導体素子。 - 前記発光層が前記傾斜面としてのR面およびN面の少なくとも一方の上に設けられている、請求項8に記載の窒化物半導体素子。
- 前記発光層上の透明導電層をさらに含み、
前記発光層および前記透明導電層によってR面およびN面の少なくとも一方が覆われていない箇所を含む、請求項8または請求項9に記載の窒化物半導体素子。 - 前記発光層は、GaNおよびInGaNの少なくとも一方を含む、請求項1~請求項10のいずれか1項に記載の窒化物半導体素子。
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JPWO2017038961A1 (ja) * | 2015-09-03 | 2017-09-07 | 丸文株式会社 | 深紫外led及びその製造方法 |
JP2022082182A (ja) * | 2020-11-20 | 2022-06-01 | 日機装株式会社 | 窒化物半導体発光素子及び窒化物半導体発光素子の製造方法 |
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WO2018221752A1 (ko) * | 2017-05-29 | 2018-12-06 | 이석헌 | 3차원 장파장 발광다이오드 및 그 제조 방법 |
JP2021057443A (ja) * | 2019-09-30 | 2021-04-08 | セイコーエプソン株式会社 | 発光装置、および、プロジェクター |
US20210366703A1 (en) * | 2020-05-20 | 2021-11-25 | Asahi Kasei Kabushiki Kaisha | Nitride semiconductor element |
US20230130445A1 (en) * | 2021-10-25 | 2023-04-27 | Meta Platforms Technologies, Llc | Semipolar micro-led |
CN114016018B (zh) * | 2021-11-05 | 2023-07-04 | 江苏徐工工程机械研究院有限公司 | 具有复合涂层的工件及其制造方法 |
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