WO2015110028A1 - 存储电容、像素单元及存储电容的制造方法 - Google Patents

存储电容、像素单元及存储电容的制造方法 Download PDF

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Publication number
WO2015110028A1
WO2015110028A1 PCT/CN2015/071294 CN2015071294W WO2015110028A1 WO 2015110028 A1 WO2015110028 A1 WO 2015110028A1 CN 2015071294 W CN2015071294 W CN 2015071294W WO 2015110028 A1 WO2015110028 A1 WO 2015110028A1
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layer
electrode
storage capacitor
metal layer
insulating layer
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PCT/CN2015/071294
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English (en)
French (fr)
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姚晓慧
许哲豪
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深圳市华星光电技术有限公司
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Priority to US14/782,188 priority Critical patent/US20170192323A1/en
Publication of WO2015110028A1 publication Critical patent/WO2015110028A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136213—Storage capacitors associated with the pixel electrode
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/133345—Insulating layers
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/13439—Electrodes characterised by their electrical, optical, physical properties; materials therefor; method of making
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1255—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs integrated with passive devices, e.g. auxiliary capacitors
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/133302—Rigid substrates, e.g. inorganic substrates
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/12—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode
    • G02F2201/123—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode pixel
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/40—Arrangements for improving the aperture ratio
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2202/00—Materials and properties
    • G02F2202/10—Materials and properties semiconductor

Definitions

  • the present invention relates to the field of semiconductor manufacturing, and in particular, to a storage capacitor, a pixel unit having the storage capacitor, and a method of manufacturing the storage capacitor.
  • Thin Film Transistor Array is an important display component that is indispensable for Liquid Crystal Display (LCD).
  • the thin film transistor matrix is mainly composed of a plurality of pixel units and a plurality of scanning lines. Scan line) and a number of data lines.
  • the pixel units are electrically connected to the scan lines and the data lines, and each of the pixel units has a thin film transistor, a liquid crystal capacitor (CLC), and a storage capacitor (CS).
  • CLC liquid crystal capacitor
  • CS storage capacitor
  • the thin film transistor charges the liquid crystal capacitor to drive the liquid crystal molecules in the liquid crystal layer, thereby causing the liquid crystal display to display an image, and at the same time, the thin film transistor charges the storage capacitor, and the storage capacitor maintains the voltage across the liquid crystal capacitor at a certain value, that is, The voltage across the liquid crystal capacitor is maintained by the storage capacitor before the data is updated.
  • the storage capacitor includes a first metal layer/insulator-metal (MIM) structure and a first metal layer/insulation layer/indium-oxide metal oxide (Metal-Insulator-ITO, MII) Two architectures.
  • MIM metal layer/insulator-metal
  • MII metal-Insulator-ITO
  • the capacitance of the MIM architecture changes when the positive and negative turns, and the unstable storage capacitor causes the display panel to have no display characteristics. stable.
  • the semiconductor layer since the semiconductor layer is wider than the second metal layer electrically connected to the thin film transistor, that is, the semiconductor layer may leak out of the second metal layer, electrons may be released, which also affects the display characteristics of the display panel.
  • the gap between the storage capacitors of the MII architecture is large. Since the capacitance is inversely proportional to the distance, if a larger storage capacitor value is to be obtained, the area of the storage capacitor needs to be increased, which reduces the aperture ratio of the liquid crystal panel.
  • an embodiment of the present invention provides a storage capacitor including a base and a bit.
  • a first electrode formed on the substrate and formed of a first metal layer, a first insulating layer formed on the substrate and the first electrode, and a semiconductor layer formed on the first insulating layer, formed on the semiconductor layer a second metal layer, a second insulating layer formed on the first insulating layer, the semiconductor layer and the second metal layer, and formed on the second insulating layer and the second metal layer as a second electrode
  • the pixel electrode A contact window is opened on the second insulating layer to expose the second metal layer.
  • the pixel electrode is electrically connected to the exposed second metal layer via the contact window.
  • the substrate is made of glass or plastic.
  • the first electrode is a molybdenum layer, an aluminum layer, a titanium layer or a copper layer, or a stack of any two layers.
  • the first electrode includes a shared line.
  • the first electrode comprises a scan line.
  • the first insulating layer is a silicon nitride layer
  • the second insulating layer is a silicon oxide or silicon nitride layer.
  • the pixel electrode is a transparent conductive layer made of indium tin metal oxide material.
  • an embodiment of the present invention further provides a pixel unit including a storage capacitor and a thin film transistor.
  • the storage capacitor includes a substrate, a first electrode formed on the substrate and formed of a first metal layer, a first insulating layer formed on the substrate and the first electrode, and a semiconductor layer formed on the first insulating layer, a second metal layer formed on the semiconductor layer, a second insulating layer formed on the first insulating layer, the semiconductor layer and the second metal layer, and a second insulating layer and the second metal layer formed on the second insulating layer
  • a pixel electrode that serves as a second electrode A contact window is opened on the second insulating layer to expose the second metal layer.
  • the pixel electrode is electrically connected to the exposed second metal layer via the contact window.
  • the thin film transistor is electrically connected to the pixel electrode.
  • the substrate is made of glass or plastic.
  • the first electrode is a molybdenum layer, an aluminum layer, a titanium layer or a copper layer, or a stack of any two layers.
  • the first electrode includes a shared line.
  • the first electrode comprises a scan line.
  • the first insulating layer is a silicon nitride layer
  • the second insulating layer is a silicon oxide or silicon nitride layer.
  • the pixel electrode is a transparent conductive layer made of indium tin metal oxide material.
  • an embodiment of the present invention further provides a method for manufacturing a storage capacitor, comprising the steps of: providing a substrate; forming a first metal layer on the substrate, patterning the first metal layer to form a a first electrode; a first insulating layer is formed on the substrate and the first electrode; a semiconductor layer and a second metal layer are sequentially formed on the first insulating layer; and the first insulating layer is Forming a second insulating layer on the semiconductor layer and the second metal layer, and exposing a portion of the second metal layer; and forming a pixel as the second electrode on the second insulating layer and the exposed second metal layer An electrode to electrically contact the pixel electrode with the second metal layer.
  • the storage capacitor provided by the present invention, the method for manufacturing the storage capacitor, and the second metal layer in the pixel unit are used as part of the storage capacitor only for adjusting the capacitance, and the pixel electrode connected to the thin film transistor is used as the second electrode, and is disposed under the second electrode.
  • the second insulating layer prevents the second metal layer in the storage capacitor of the MIM architecture from accompanying the semiconductor layer, thereby ensuring that the capacitance of the storage capacitor is stable even when the positive and negative turns are turned over, and the semiconductor layer can be prevented from releasing electrons. Ensure the display characteristics of the display panel.
  • a contact window is opened on the second insulating layer to expose the second metal layer, and the pixel electrode is electrically connected to the exposed second metal layer via the contact window, thereby reducing the relationship between the storage capacitors.
  • the gap increases the aperture ratio of the liquid crystal panel having the storage capacitor.
  • FIG. 1 to FIG. 6 are schematic diagrams showing a method of manufacturing a storage capacitor according to a preferred embodiment of the present invention.
  • FIG. 7 is a schematic plan view of a pixel unit according to another preferred embodiment of the present invention.
  • a method for manufacturing a storage capacitor according to a first embodiment of the present invention includes the following steps:
  • a substrate 10 is provided which is made of glass or plastic.
  • the substrate 10 is made of glass.
  • a first metal layer is formed on the substrate 10, and the first metal layer is patterned to form a first electrode 20.
  • the first metal layer is a molybdenum layer, an aluminum layer, a titanium layer or a copper layer, or a stack of any two layers, the first metal layer is formed on the substrate 10 by a sputtering process, and patterned The first metal layer is formed by the first metal layer by a photomask process.
  • the mask process includes steps of exposure, development, and etching. Specifically, first, a layer of a photo-resistance is applied over the first metal layer. The light is then applied to the photoresist layer through a gray scale mask or a half gray mask to expose the photoresist layer.
  • the gray-scale mask or the half-gray mask has a pattern corresponding to the first electrode 20, and the exposure of the photoresist layer is selective, and the pattern on the gray-scale mask or the half-gray mask is complete. Transfer onto the photoresist layer. A portion of the photoresist layer is then removed using a suitable developer such that the remaining photoresist layer exhibits the desired pattern, i.e., exhibits a pattern corresponding to the first electrode 20.
  • the first metal layer not covered by the remaining photoresist layer is removed by an etching process, where the etching process may be selected by dry etching, wet etching, or a combination of the two. Finally, the remaining photoresist layer is removed to obtain a first electrode 20 forming a predetermined pattern.
  • a first insulating layer 30 is formed on the substrate 10 and the first electrode 20.
  • the first insulating layer 30 is generally a SiNx layer formed on the substrate 10 and the first electrode 20 by chemical vapor deposition (CVD).
  • a semiconductor layer 40 and a second metal layer 50 are sequentially formed on the first insulating layer 30.
  • This step is implemented in a similar manner to the second step and is also made using a photomask process.
  • a second insulating layer 60 is formed on the first insulating layer 30, the semiconductor layer 40, and the second metal layer 50, and a portion of the second metal layer 50 is exposed.
  • a silicon oxide or a silicon nitride layer is deposited on the first insulating layer 30, the semiconductor layer 40, and the second metal layer 50 by chemical vapor deposition, and the second insulating layer 60 is formed by a photomask process. To expose the second metal layer 50 to form the contact window 52.
  • a pixel electrode 70 as a second electrode is formed on the second insulating layer 60 and the exposed second metal layer 50, and the pixel electrode 70 and the second metal layer 50 are electrically connected.
  • Sexual contact forms a storage capacitor 100.
  • ITO indium tin metal oxide
  • a storage capacitor 100 includes a substrate 10, a first electrode 20 on the substrate 10 and formed of a first metal layer, and is formed on the substrate 10 and the first electrode 20. a first insulating layer 30, a semiconductor layer 40 formed on the first insulating layer 30, a second metal layer 50 formed on the semiconductor layer 40, a first insulating layer 30, the semiconductor layer 40, and the a second insulating layer 60 on the second metal layer 50 and a pixel electrode 70 formed on the second insulating layer 60 and the second metal layer 50 as a second electrode.
  • the substrate 10 is made of glass or plastic. In this embodiment, the substrate 10 is made of glass.
  • the first electrode 20 is a molybdenum layer, an aluminum layer, a titanium layer or a copper layer, or a stack of any two layers.
  • the first insulating layer 30 is typically a SiNx layer.
  • the second insulating layer 60 is a silicon oxide or silicon nitride layer.
  • a contact window 52 is opened on the second insulating layer 60 to expose the second metal layer 50.
  • the pixel electrode 70 is electrically connected to the exposed second metal layer 50 via the contact window 52.
  • the pixel electrode 70 is a transparent conductive layer made of an indium tin metal oxide (ITO) material.
  • ITO indium tin metal oxide
  • the first electrode 20 includes a shared line 205. In other embodiments, the first electrode 20 includes a scan line 202.
  • a pixel unit 200 is defined by two adjacent scan lines 202 and two adjacent data lines 204.
  • the pixel unit 200 includes a thin film transistor 206 and a storage capacitor 100 as in the first embodiment.
  • the gate of the thin film transistor 206 is electrically connected to the scan line 202
  • the source is electrically connected to the data line 204
  • the drain is electrically connected to the pixel electrode 70 in the storage capacitor 100 .
  • the scan line 202 provides a scan voltage to the thin film transistor 206 to turn on the thin film transistor 206.
  • the data line 204 supplies a data voltage to the thin film transistor 206 such that the pixel electrode 70 displays a gray scale corresponding to the data voltage, and the storage capacitor 100 stores the display voltage of the pixel electrode 70 during the closing of the thin film transistor 206, that is, The voltage of the pixel electrode 70 is maintained by the storage capacitor 100 before the data update is performed.
  • the storage capacitor 100 provided by the present invention, the method of manufacturing the storage capacitor 100, and the second metal layer 50 in the pixel unit 200 are used as a part of the storage capacitor 100 and are only used to adjust the capacitance, and the pixel electrode 70 connected to the thin film transistor 206 is It is a second electrode, and the second metal layer in the storage capacitor of the MIM structure is not accompanied by the semiconductor layer, but the second insulating layer 60 is disposed, thereby ensuring that the capacitance value of the storage capacitor 100 can be maintained even when the storage capacitor 100 is turned over and over. Stable, at the same time, it is possible to prevent the semiconductor layer 40 from releasing electrons, thereby ensuring the display characteristics of the display panel.
  • a contact window is opened on the second insulating layer 60. 52 to expose the second metal layer 50, and the pixel electrode 70 is electrically connected to the exposed second metal layer 50 via the contact window 52, thereby reducing the gap between the storage capacitors 100, due to the capacitance value and the distance
  • the area of the storage capacitor 100 is smaller than the area of the storage capacitor of the MII architecture, and thus the aperture ratio of the liquid crystal panel having the storage capacitor 100 is high.

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  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Optics & Photonics (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Chemical & Material Sciences (AREA)
  • Mathematical Physics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
  • Geometry (AREA)
  • Liquid Crystal (AREA)
  • Thin Film Transistor (AREA)

Abstract

一种存储电容(100)，包括基底(10)，位于该基底(10)上且由第一金属层形成的第一电极(20)，形成在该基底(10)及该第一电极(20)上的第一绝缘层(30)，形成在该第一绝缘层(30)上的半导体层(40)，形成在该半导体层(40)上的第二金属层(50)，形成在该第一绝缘层(30)、该半导体层(40)及该第二金属层(50)上的第二绝缘层(60)，以及形成在该第二绝缘层(60)及该第二金属层(50)上并作为第二电极的像素电极(70)。该第二绝缘层(60)上开设有一个接触窗(52)以暴露第二金属层(50)。该像素电极(70)经由该接触窗(52)与该暴露的第二金属层(50)电性连接，由此减小了存储电容之间的间隙，提高了具有该存储电容的液晶面板的开口率。还公开了一种具有该存储电容(100)的像素单元(200)及一种该存储电容(100)的制造方法。

Description

存储电容、像素单元及存储电容的制造方法 技术领域
本发明涉及半导体制造领域，尤其涉及一种存储电容、一种具有该存储电容的像素单元以及一种该存储电容的制造方法。
背景技术
薄膜晶体管矩阵(Thin Film Transistor Array，TFT Array)是液晶显示器(Liquid Crystal Display，LCD)不可获缺的重要显示组件，薄膜晶体管矩阵主要是由多个像素单元(pixel unit)、多条扫描线(scan line)以及多条数据线(data line)组成。这些像素单元电性连接扫描线与数据线，每个像素单元具有薄膜晶体管、液晶电容(liquid crystal capacitor，CLC)以及存储电容(storage capacitor，CS)。其中，薄膜晶体管对液晶电容进行充电以驱动液晶层内的液晶分子，从而使液晶显示器显示影像，同时，薄膜晶体管对存储电容进行充电，该存储电容使液晶电容两端的电压维持在一定值，即，在未进行数据更新之前，液晶电容两端电压通过存储电容维持住。
目前，存储电容包括第一金属层/绝缘层/第二金属层(Metal-Insulator-Metal，MIM)架构及第一金属层/绝缘层/铟锡金属氧化物(Metal-Insulator-ITO，MII)架构两种。其中，由于与薄膜晶体管电性连接的第二金属层下方伴随著半导体层，MIM架构的存储电容在正负翻周时电容值会变化，不稳定的存储电容会使得显示面板的显示特性也不稳定。另外，由于半导体层较与薄膜晶体管电性连接的第二金属层宽，即半导体层会相对第二金属层外漏一部分，可能会释放电子，同样也会影响显示面板的显示特性。而MII架构的存储电容之间的间隙较大，由于电容与距离成反比，若要想获得较大的存储电容值，则需要增大存储电容的面积，如此会降低液晶面板的开口率。
因此，有必要提供能够解决上述问题的存储电容、像素单元及存储电容的制造方法。
发明内容
为了解决上述技术问题，本发明实施例提供一种存储电容，包括基底，位 于该基底上且由第一金属层形成的第一电极，形成在该基底及该第一电极上的第一绝缘层，形成在该第一绝缘层上的半导体层，形成在该半导体层上的第二金属层，形成在该第一绝缘层、该半导体层及该第二金属层上的第二绝缘层，以及形成在该第二绝缘层及该第二金属层上并作为第二电极的像素电极。该第二绝缘层上开设有一个接触窗以暴露第二金属层。该像素电极经由该接触窗与该暴露的第二金属层电性连接。
其中，该基底由玻璃或者塑胶制成。
其中，该第一电极为钼层、铝层、钛层或铜层，或者是任意两层的堆叠。
其中，该第一电极包括一共享线。
其中，该第一电极包括一扫描线。
其中，该第一绝缘层为氮化硅层，该第二绝缘层为氧化硅或氮化硅层。
其中，该像素电极为铟锡金属氧化物材料制成的透明导电层。
为了解决上述技术问题，本发明实施例还提供了一种像素单元，包括存储电容及薄膜晶体管。该存储电容包括基底，位于该基底上且由第一金属层形成的第一电极，形成在该基底及该第一电极上的第一绝缘层，形成在该第一绝缘层上的半导体层，形成在该半导体层上的第二金属层，形成在该第一绝缘层、该半导体层及该第二金属层上的第二绝缘层，以及形成在该第二绝缘层及该第二金属层上并作为第二电极的像素电极。该第二绝缘层上开设有一个接触窗以暴露第二金属层。该像素电极经由该接触窗与该暴露的第二金属层电性连接。该薄膜晶体管与该像素电极电性连接。
其中，该基底由玻璃或者塑胶制成。
其中，该第一电极为钼层、铝层、钛层或铜层，或者是任意两层的堆叠。
其中，该第一电极包括一共享线。
其中，该第一电极包括一扫描线。
其中，该第一绝缘层为氮化硅层，该第二绝缘层为氧化硅或氮化硅层。
其中，该像素电极为铟锡金属氧化物材料制成的透明导电层。
为了解决上述技术问题，本发明实施例还提供了一种存储电容的制造方法，包括以下步骤：提供一个基底；在该基底上形成一个第一金属层，图案化该第一金属层以形成一个第一电极；在该基底及该第一电极上形成一个第一绝缘层；在该第一绝缘层上依次形成一个半导体层及一个第二金属层；在该第一绝缘层、 该半导体层及该第二金属层上形成一个第二绝缘层，并暴露一部分的第二金属层；及在该第二绝缘层及该暴露的第二金属层上形成一作为第二电极的像素电极，以使该像素电极与该第二金属层电性接触。
本发明提供的存储电容、制造该存储电容的方法及像素单元中的第二金属层作为存储电容的一部分仅用于调整电容，而与薄膜晶体管连接的像素电极作为第二电极，其下方设置的是第二绝缘层，避免如MIM架构的存储电容中的第二金属层伴随半导体层，由此保证存储电容在正负翻周时电容值也能够保持稳定，同时能够避免半导体层释放电子，从而保证显示面板的显示特性。另外，由于该第二绝缘层上开设有一个接触窗以暴露第二金属层，且像素电极经由该接触窗与该暴露的第二金属层电性连接，由此减小了存储电容之间的间隙，提高了具有该存储电容的液晶面板的开口率。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动性的前提下，还可以根据这些附图获得其他的附图。
图1至图6是本发明一较佳实施例提供的存储电容的制造方法的示意图。
图7是本发明另一较佳实施例提供的像素单元的平面示意图。
具体实施例
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
实施例一
请参阅图1至图6，本发明第一实施例提供的一种存储电容的制造方法，包括以下步骤：
第一步，请参阅图1，提供一个基底10，该基底10由玻璃或者塑胶制成。本实施例中，该基底10由玻璃制成。
第二步，请参阅图2，在该基底10上形成一个第一金属层，图案化该第一金属层以形成一个第一电极20。其中，该第一金属层为钼层、铝层、钛层或铜层，或者是任意两层的堆叠，该第一金属层通过溅射(sputtering)工艺形成在该基底10上，而图案化该第一金属层而形成该第一电极20则是采用光罩制程。
其中，光罩制程包括曝光、显影及蚀刻等步骤。具体地，首先，在第一金属层上覆上一层光致抗蚀剂(photo-resistance)层。接着，光线通过灰阶掩膜或半灰阶掩膜照射在该光致抗蚀剂层上以将该光致抗蚀剂层曝光。灰阶掩膜或半灰阶掩膜上具有与该第一电极20对应的图案，且该光致抗蚀剂层的曝光具有选择性，灰阶掩膜或半灰阶掩膜上的图案完整转印到该光致抗蚀剂层上。然后，利用合适的显影液(developer)除去部分光致抗蚀剂层，使得剩余的光致抗蚀剂层呈现出需要的图案，即呈现出与该第一电极20对应的图案。接着，通过蚀刻工艺将未被该剩余的光致抗蚀剂层遮盖的第一金属层去除，在此，蚀刻工艺可选用干式蚀刻、湿式蚀刻或者二者结合。最后，去除该剩余的光致抗蚀剂层，得到形成预定图案的第一电极20。
第三步，请参阅图3，在该基底10及该第一电极20上形成一个第一绝缘层30。该第一绝缘层30一般为SiNx层，其通过化学气相沉积(chemical vapor deposition，CVD)形成在该基底10及该第一电极20上。
第四步，请参阅图4，在该第一绝缘层30上依次形成一个半导体层40及一个第二金属层50。此步骤的实现方法与第二步类似，也是采用光罩制程制得。
第五步，请参阅图5，在该第一绝缘层30、该半导体层40及该第二金属层50上形成一个第二绝缘层60，并暴露一部分的第二金属层50。例如通过化学气相沉积的方式沉积氧化硅或氮化硅层在该第一绝缘层30、该半导体层40及该第二金属层50上，并且以光罩制程的方式形成该第二绝缘层60，以暴露第二金属层50形成接触窗52。
第六步，请参阅图6，在该第二绝缘层60及该暴露的第二金属层50上形成一作为第二电极的像素电极70，使该像素电极70与该第二金属层50电性接触，从而形成一个存储电容100。例如，沉积铟锡金属氧化物(ITO)在该第二绝缘层60及该暴露的第二金属层50上，使该像素电极70与该第二金属层50经由该接触窗52电性接触。
实施例二
请参阅图6，本发明第二实施例提供的存储电容100包括基底10、位于该基底10上并由第一金属层形成的第一电极20、形成在该基底10及该第一电极20上的第一绝缘层30、形成在该第一绝缘层30上的半导体层40、形成在该半导体层40上的第二金属层50、形成在该第一绝缘层30、该半导体层40及该第二金属层50上的第二绝缘层60以及形成在该第二绝缘层60及该第二金属层50上并作为第二电极的像素电极70。
该基底10由玻璃或者塑胶制成。本实施例中，该基底10由玻璃制成。该第一电极20为钼层、铝层、钛层或铜层，或者是任意两层的堆叠。该第一绝缘层30一般为SiNx层。该第二绝缘层60为氧化硅或氮化硅层。该第二绝缘层60上开设有一个接触窗52以暴露第二金属层50。该像素电极70经由该接触窗52与该暴露的第二金属层50电性连接。该像素电极70为铟锡金属氧化物(ITO)材料制成的透明导电层。
请结合图7，在本实施例中，该第一电极20包括一共享线205。在其他实施例中，该第一电极20包括一扫描线202。
实施例三
请参见图7，本发明第三实施例提供的像素单元200由两条相邻的扫描线202及两条相邻的数据线204共同定义。该像素单元200包括薄膜晶体管206以及如第一实施例中的存储电容100。其中，该薄膜晶体管206的栅极电性连接扫描线202，源极电性连接数据线204，漏极电性连接该存储电容100中的像素电极70。该扫描线202为该薄膜晶体管206提供扫描电压以使该薄膜晶体管206导通。该数据线204为该薄膜晶体管206提供数据电压，使得该像素电极70显示相应于该数据电压的灰阶，该存储电容100在该薄膜晶体管206关闭期间存储该像素电极70的显示电压，即在未进行数据更新之前，该像素电极70的电压由存储电容100维持住。
本发明提供的存储电容100、制造该存储电容100的方法及像素单元200中的第二金属层50作为存储电容100的一部分并仅用于调整电容，而与薄膜晶体管206连接的像素电极70才是第二电极，其下方并非如MIM架构的存储电容中的第二金属层伴随半导体层，而是设置第二绝缘层60，由此保证存储电容100在正负翻周时电容值也能够保持稳定，同时能够避免半导体层40释放电子，从而保证显示面板的显示特性。另外，由于该第二绝缘层60上开设有一个接触窗 52以暴露第二金属层50，且像素电极70经由该接触窗52与该暴露的第二金属层50电性连接，由此减小了存储电容100之间的间隙，由于电容值与距离成反比，在存储电容值相同的前提下，该存储电容100的面积较MII架构的存储电容的面积小，由此具有该存储电容100的液晶面板的开口率较高。
以上所揭露的仅为本发明较佳实施例而已，当然不能以此来限定本发明之权利范围，因此依本发明权利要求所作的等同变化，仍属本发明所涵盖的范围。

Claims (15)

  1. 一种存储电容，其中，该存储电容包括基底，位于该基底上且由第一金属层形成的第一电极，形成在该基底该第一电极上的第一绝缘层，形成在该第一绝缘层上的半导体层，形成在该半导体层上的第二金属层，形成在该第一绝缘层、该半导体层及该第二金属层上的第二绝缘层，以及形成在该第二绝缘层及该第二金属层上并作为第二电极的像素电极，该第二绝缘层上开设有一个接触窗以暴露第二金属层，该像素电极经由该接触窗与该暴露的第二金属层电性连接。
  2. 如权利要求1所述的存储电容，其中，该基底由玻璃或者塑胶制成。
  3. 如权利要求1所述的存储电容，其中，该第一电极为钼层、铝层、钛层或铜层，或者是任意两层的堆叠。
  4. 如权利要求1所述的存储电容，其中，该第一电极包括一共享线。
  5. 如权利要求1所述的存储电容，其中，该第一电极包括一扫描线。
  6. 如权利要求1所述的存储电容，其中，该第一绝缘层为氮化硅层，该第二绝缘层为氧化硅或氮化硅层。
  7. 如权利要求1所述的存储电容，其中，该像素电极为铟锡金属氧化物材料制成的透明导电层。
  8. 一种像素单元，包括存储电容及薄膜晶体管，其中，该存储电容包括基底，位于该基底上且由第一金属层形成的第一电极，形成在该基底及该第一电极上的第一绝缘层，形成在该第一绝缘层上的半导体层，形成在该半导体层上的第二金属层，形成在该第一绝缘层、该半导体层及该第二金属层上的第二绝缘层，以及形成在该第二绝缘层及该第二金属层上并作为第二电极的像素电极，该第二绝缘层上开设有一个接触窗以暴露第二金属层，该像素电极经由该接触窗与该暴露的第二金属层电性连接，该薄膜晶体管与该像素电极电性连接。
  9. 如权利要求8所述的像素单元，其中，该基底由玻璃或者塑胶制成。
  10. 如权利要求8所述的像素单元，其中，该第一电极为钼层、铝层、钛层或铜层，或者是任意两层的堆叠。
  11. 如权利要求8所述的像素单元，其中，该第一电极包括一共享线。
  12. 如权利要求8所述的像素单元，其中，该第一电极包括一扫描线。
  13. 如权利要求8所述的像素单元，其中，该第一绝缘层为氮化硅层，该第 二绝缘层为氧化硅或氮化硅层。
  14. 如权利要求8所述的像素单元，其中，该像素电极为铟锡金属氧化物材料制成的透明导电层。
  15. 一种存储电容的制造方法，包括以下步骤：
    提供一个基底；
    在该基底上形成一个第一金属层，图案化该第一金属层以形成一个第一电极；
    在该基底及该第一电极上形成一个第一绝缘层；
    在该第一绝缘层上依次形成一个半导体层及一个第二金属层；
    在该第一绝缘层、该半导体层及该第二金属层上形成一个第二绝缘层，并暴露一部分的第二金属层；及
    在该第二绝缘层及该暴露的第二金属层上形成一作为第二电极的像素电极，以使该像素电极与该第二金属层电性接触。
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