WO2013131390A1 - Tft阵列基板及其制造方法和显示装置 - Google Patents

Tft阵列基板及其制造方法和显示装置 Download PDF

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Publication number
WO2013131390A1
WO2013131390A1 PCT/CN2012/086216 CN2012086216W WO2013131390A1 WO 2013131390 A1 WO2013131390 A1 WO 2013131390A1 CN 2012086216 W CN2012086216 W CN 2012086216W WO 2013131390 A1 WO2013131390 A1 WO 2013131390A1
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Prior art keywords
insulating layer
metal layer
drain
gate
layer
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PCT/CN2012/086216
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English (en)
French (fr)
Inventor
盖翠丽
张卓
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京东方科技集团股份有限公司
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Priority to US14/126,653 priority Critical patent/US9276015B2/en
Publication of WO2013131390A1 publication Critical patent/WO2013131390A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41733—Source or drain electrodes for field effect devices for thin film transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4908—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET for thin film semiconductor, e.g. gate of TFT

Definitions

  • TFT array substrate manufacturing method thereof and display device
  • Embodiments of the present invention relate to a TFT array substrate, a TFT array substrate manufacturing method, and a display device. Background technique
  • LCD Liquid Crystal Display
  • TFT Thin Film Transistor
  • a coupling capacitor is usually generated between the pixel electrode and the source.
  • the area of overlap between the pixel electrode and the source is generally reduced by reducing the area of the pixel electrode, so that the coupling capacitance between the source and the pixel electrode is reduced. Small, but this also reduces the aperture ratio of the pixel unit, thereby affecting the contrast of the electronic display device driven by the TFT array substrate.
  • An embodiment of the present invention provides a TFT array substrate, including: a substrate, a gate line, a gate, a gate insulating layer, a semiconductor active layer, a data line, a source/drain, and a pixel electrode formed on the substrate.
  • the data line is connected to the source, and the drain is connected to the pixel electrode, wherein a first insulating layer, a metal layer and a second insulating are sequentially formed between the source/drain and the pixel electrode.
  • a layer, the metal layer being connected to the stable voltage signal line through the metal layer lead via.
  • Another embodiment of the present invention provides a method of fabricating a TFT array substrate, including: forming a gate line, a gate, a gate insulating layer, a semiconductor active layer, a data line, a source/drain, and a pixel electrode on the substrate, The method further includes: sequentially forming a first insulating layer, a metal layer, and a second insulating layer between the source/drain and the pixel electrode.
  • Yet another embodiment of the present invention provides a display device including any of the embodiments of the present invention.
  • TFT array substrate TFT array substrate.
  • FIG. 1 is a cross-sectional view of a TFT array substrate along a parallel grid line direction of a TFT region according to an embodiment of the present invention. detailed description
  • the embodiment of the invention provides a TFT array substrate, as shown in FIG. 1 is a cross-sectional view of a TFT array substrate along a TFT region parallel to a gate line direction, wherein the data lines and gate lines in FIG. 1 are not shown.
  • a twisted nematic (TN) type TFT array substrate will be specifically described as an example.
  • the array substrate includes: a substrate 10, a gate line formed on the substrate 10, and a gate electrode 12.
  • a gate insulating layer 17 is formed on the substrate on which the gate line and the gate electrode 12 are formed, and a corresponding TFT region is formed on the gate insulating layer 17.
  • the semiconductor active layer 18 has a data line, a source electrode 14, a drain electrode 15, and a pixel electrode 16 formed on a substrate on which the gate line, the gate electrode 12, the gate insulating layer 17, and the semiconductor active layer 18 are formed.
  • a metal layer 20 is formed between the source electrode 14, the drain electrode 15, and the pixel electrode 16.
  • a first insulating layer 19 is formed between the source electrode 14, the drain electrode 15 and the metal layer 20.
  • a second insulating layer 21 is formed between the metal layer 20 and the pixel electrode 16.
  • the data line is connected to the source 14, and the pixel electrode 16 is connected to the drain 15 through the via 22.
  • the via 22 penetrates through the first insulating layer 19, the metal layer 20, and the second insulating layer 21, and is located above the drain 15, so that the pixel electrode 16 can be connected to the drain.
  • the pixel electrode 16 and the metal layer may be formed on the sidewall of the via 22 20 insulation layers insulated from each other.
  • the gate line and the gate are formed by patterning the gate metal layer, and the source/drain and the data line are formed by patterning the source/drain metal layer, and therefore, the gate line and the gate are on the same layer, and The source/drain and the data line are on the same layer.
  • the metal layer 20 may be connected to the stable voltage signal source through the metal layer lead via 23, such that the pixel electrode 16 The voltage is stable, thereby ensuring that the coupling capacitance between the pixel electrode 16 and the metal layer 20 cannot be charged and discharged, so that the coupling capacitance between the pixel electrode 16 and the metal layer 20 cannot be The voltage of the pixel electrode 16 has an effect.
  • the metal layer 20 may be connected to the ground through a metal layer lead via 23.
  • the metal layer lead via 23 is shown to penetrate the second insulating layer 21 and the metal layer 20.
  • the via 23 may penetrate only the second insulating layer 21 as long as the metal layer 20 can be exposed.
  • any suitable form can be taken.
  • the metal layer 20 may be a transparent metal layer such as indium tin oxide or indium oxide, and the TFT array substrate using a transparent metal layer may be used for a transmissive electronic display device such as a TFT LCD display.
  • the metal layer 20 may also be a non-transparent metal layer, and specifically may be any of non-transparent metals such as molybdenum, aluminum, aluminum-nickel alloy, molybdenum-tungsten alloy, chromium, or copper.
  • a TFT array substrate using a non-transparent metal layer can be used for a reflective electronic display device such as a display device for active electronic paper.
  • a non-transparent metal layer is formed on the source 14 and the drain 15 of the TFT array substrate, the TFT channel region between the source 14 and the drain 15 is also covered, and the TFT channel is not exposed to the outside. The light generates leakage current and affects the image display of the active electronic paper, thereby enhancing the light reflectivity of the active electronic paper and improving the display effect.
  • a thin film transistor consisting of a gate electrode, a semiconductor active layer, a source/drain
  • a gate insulating layer may be interposed between the gate electrode and the semiconductor active layer, and the semiconductor active layer is sandwiched between the source/drain and the gate insulating layer.
  • the TN type TFT array substrate is taken as an example.
  • the present invention is also applicable to other types of array substrates, such as FFS type and IPS type TFT array substrates.
  • the TFT array substrate provided by the embodiment of the invention can reduce the influence of the coupling capacitance on the TFT array substrate on the pixel electrode voltage, and can also increase the aperture ratio of the pixel unit.
  • Embodiments of the present invention provide a method of fabricating a TFT array substrate.
  • the following is a detailed description of the four mask processes of the TN type TFT array substrate, including:
  • a 1000A to 7000 person gate metal film is deposited on the substrate by a magnetron sputtering process, and the metal material can usually be made of molybdenum, aluminum, aluminum-nickel alloy, molybdenum-tungsten alloy, chromium, or copper. A combination of the above several materials is used. Then, a plurality of parallel gate lines and gates connected to the gate lines are formed on the substrate by a masking process by exposure, development, etching, and stripping using a mask. The above process of forming the gate lines and the gates is the first mask process.
  • a gate insulating layer film, a semiconductor active layer film, and a data metal layer film are formed on the substrate on which the gate line and the gate are formed, and the gate insulating layer, the semiconductor active layer, and the source/drain are formed by a patterning process.
  • a gate insulating layer is used to deposit a gate insulating layer having a thickness of 1000 A to 6000 on the gate line 11 and the gate electrode 12.
  • the material of the gate insulating layer is usually silicon nitride, or Silicon oxide, silicon oxynitride or the like is used.
  • a metal oxide film having a thickness of 50 to 1000 A can be continuously deposited as a semiconductor active layer film by a sputtering method.
  • a layer of 1000 to 7,000 data metal film can be deposited by magnetron sputtering.
  • Forming a photoresist on the substrate forming the gate insulating film, the semiconductor active layer film, and the data metal layer film, exposing the photoresist by using a gray tone mask or a semi-transparent mask, and forming a photolithography after development The fully retained area of the glue, the semi-reserved area of the photoresist, and the completely removed area of the photoresist.
  • a photoresist completely reserved area corresponds to a data line
  • a source/drain corresponds to a channel area between the source and the drain
  • the photoresist completely removes regions corresponding to the photoresist completely remaining regions in the pixel unit and the photoresist semi-reserved regions.
  • the source layer film is removed by a plasma ashing process to remove the photoresist in the semi-reserved region of the photoresist, exposing the data metal layer film in the semi-reserved region of the photoresist, and etching away the semi-reserved region of the photoresist by an etching process.
  • the data metal layer film and a portion of the semiconductor active layer film form a TFT channel; then the photoresist in the completely remaining region of the photoresist is stripped to form a data line, a source/drain.
  • the above process of forming the gate insulating layer, the semiconductor active layer, and the source/drain is a second mask process.
  • a photoresist is formed on the substrate on which the first insulating layer film, the metal layer film, and the second insulating layer film are formed, and then the photoresist is exposed and developed to form a photoresist completely reserved region and a photoresist completely removed region.
  • the photoresist completely removed region includes: a drain and a pixel electrode connected via and a metal layer connected to the external stable signal source of the metal layer lead via; the photoresist completely reserved region includes a pixel unit composed of the gate line and the data line The area outside the area where the photoresist is completely removed.
  • the photoresist completely removed region is etched, and after the etching is completed, the photoresist in the completely remaining region of the photoresist is stripped, thereby forming a via connecting the drain and the pixel electrode (through the first insulating layer, the metal layer, and the first Two insulating layers), metal layer lead vias, a first insulating layer, a metal layer, and a second insulating layer.
  • the above process of forming the via and the pixel electrode connection via, the metal layer via via, the first insulating layer, the metal layer, and the second insulating layer is a third mask process.
  • the above metal layer may specifically be a transparent metal layer such as indium tin oxide or indium oxide, and the TFT array substrate using a transparent metal layer may be used for a transmissive electronic display device such as a TFT LCD display.
  • the metal layer may also be a non-transparent metal layer, specifically any of non-transparent metals such as molybdenum, aluminum, aluminum-nickel alloy, molybdenum-tungsten alloy, chromium, or copper, and a TFT array substrate using a non-transparent metal layer may be used.
  • a reflective electronic display device such as a display device for active electronic paper.
  • the TFT channel region between the source and the drain is also covered, and the TFT channel does not generate leakage current due to external light. The image display of the active electronic paper is affected, thereby enhancing the light reflectivity of the active electronic paper and improving the display effect.
  • the metal layer may be specifically connected to a stable voltage signal through a metal layer lead via, such as a +5 volt voltage.
  • a metal layer lead via such as a +5 volt voltage.
  • the metal layer can be directly connected to the ground through the metal layer lead via.
  • the method includes: forming a pixel electrode on the second insulating layer, and the specific material of the pixel electrode may be indium tin oxide or indium oxide.
  • the pixel electrode is then formed by a process such as exposure of a pixel electrode mask, exposure development, etching, and stripping of a photoresist.
  • the above process of forming the pixel electrode is a fourth mask process.
  • the above-mentioned patterning process specifically includes: a process of coating a photoresist, exposing, developing, etching, and stripping a photoresist.
  • the pixel electrode is connected to the drain through a via above the drain, and the metal layer via via may be formed at a position not covered by the pixel electrode.
  • the embodiment of the method for fabricating the TFT array substrate is specifically described by taking four mask processes as an example. Of course, it is also achievable for the five mask processes, and the same is needed in the process of forming vias connecting the drain and the pixel electrode.
  • a first insulating layer, a metal layer and a second metal layer, and a metal layer lead via are formed in the process.
  • the first insulating layer, the metal layer, the second metal layer, and the metal layer lead via may be formed by a single mask process between the source/drain and the pixel electrode.
  • the invention is not specifically limited herein.
  • the TN type TFT array substrate is taken as an example.
  • the present invention is also applicable to other types of array substrates, such as FFS type and IPS type TFT array substrates.
  • the above TFT array substrate can be applied not only to a liquid crystal display or an electronic paper device but also to a display requiring active driving such as an organic light emitting display (OLED).
  • OLED organic light emitting display
  • a first insulating layer, a metal layer and a second insulating layer are formed between the pixel electrode and the source/drain, and the metal layer can pass through the metal layer via via Stable voltage signal line connection. Due to the TFT array substrate formed by the above-described manufacturing method of the TFT array substrate, a metal layer connected to the stable voltage source is provided between the source and the pixel electrode, so that there is no charge between the coupling capacitance of the pixel electrode and the metal layer. The process of discharging, such that the coupling capacitance of the pixel electrode and the metal layer does not affect the voltage of the pixel electrode.
  • the TFT array substrate provided by the embodiment of the invention can reduce the influence of the coupling capacitance on the TFT array substrate on the pixel electrode voltage, and can also increase the aperture ratio of the pixel unit.
  • An embodiment of the present invention further provides a display device including the above TFT array substrate, the display
  • the device may be a TFT liquid crystal display device, a reflective active electronic paper display device, an OLED, etc., and the specific structure will not be described herein.

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Abstract

一种TFT阵列基板及其制造方法和显示装置。所述TFT阵列基板包括：基板（10），形成于基板（10）上的栅线、栅极（12）、栅绝缘层（17）、半导体有源层（18）、数据线、源极（14）/漏极（15）、像素电极（16），所述数据线与所述源极（14）相连，所述漏极（15）与所述像素电极（16）相连，其中所述源极（14）/漏极（15）和所述像素电极（16）之间依次形成有第一绝缘层（19）、金属层（20）、第二绝缘层（21），所述金属层（20）通过金属层引线过孔（23）与稳定电压信号线连接，从而减小了TFT阵列基板上的耦合电容对像素电极电压的影响，同时增大了像素单元的开口率。

Description

TFT阵列基板及其制造方法和显示装置 技术领域
本发明的实施例涉及一种 TFT阵列基板、 TFT阵列基板制造方法及显示 装置。 背景技术
随着信息和网络的发展，电子显示技术已经作为一种被广泛应用的技术。 目前应用广泛的有 LCD ( Liquid Crystal Display )显示设备， 还有作为人们阅 读纸张的一种替代品一一电子纸也迅速发展起来。 技术， 如 TFT ( Thin Film Transistor ) 阵列基板驱动的方式。
在实现 TFT 阵列基板的过程， 通常像素电极和源极之间会产生耦合电 容。 为了减小像素电极和源极之间的耦合电容， 一般会通过减小像素电极的 面积来减小了像素电极与源极之间的重叠面积， 使得源极与像素电极之间的 耦合电容减小， 但是这样同时也降低了像素单元的开口率， 从而影响 TFT阵 列基板驱动的电子显示设备的对比度。 发明内容
本发明的一个实施例提供一种 TFT阵列基板， 包括： 基板， 形成于基板 上的栅线、 栅极、栅绝缘层、 半导体有源层、 数据线、 源极 /漏极、像素电极， 所述数据线与所述源极相连， 所述漏极与所述像素电极相连， 其中所述源极 / 漏极和所述像素电极之间依次形成有第一绝缘层、 金属层、 第二绝缘层， 所 述金属层通过金属层引线过孔与稳定电压信号线连接。
本发明的另一个实施例提供一种 TFT阵列基板的制造方法， 包括： 在基 板上形成栅线、 栅极、 栅绝缘层、 半导体有源层、 数据线、 源极 /漏极、 像素 电极， 其中， 所述方法还包括： 在所述源极 /漏极和所述像素电极之间依次形 成有第一绝缘层、 金属层和第二绝缘层。
本发明的再一个实施例提供一种显示装置， 包括根据本发明任一实施例 的 TFT阵列基板。 附图说明
为了更清楚地说明本发明实施例的技术方案， 下面将对实施例的附图作 简单地介绍，显而易见地，下面描述中的附图仅仅涉及本发明的一些实施例， 而非对本发明的限制。
图 1为本发明实施例提供的 TFT阵列基板沿 TFT区域平行栅线方向的 剖视图。 具体实施方式
为使本发明实施例的目的、 技术方案和优点更加清楚， 下面将结合本发 明实施例的附图，对本发明实施例的技术方案进行清楚、 完整地描述。显然， 所描述的实施例是本发明的一部分实施例， 而不是全部的实施例。 基于所描 述的本发明的实施例， 本领域普通技术人员在无需创造性劳动的前提下所获 得的所有其他实施例， 都属于本发明保护的范围。
本发明实施例提供了一种 TFT阵列基板， 如图 1所示。 图 1为 TFT阵 列基板沿 TFT区域平行于栅线方向的剖视图， 其中图 1中数据线、栅线未示 出。 下面以扭转向列 （TN )型 TFT阵列基板为例具体说明。 该阵列基板包 括： 基板 10, 形成于基板 10上的栅线、 栅极 12, 在形成有栅线、 栅极 12 的基板上形成有栅绝缘层 17, 在栅绝缘层 17上对应 TFT区域形成有半导体 有源层 18,在形成有栅线、栅极 12、栅绝缘层 17和半导体有源层 18的基板 上形成有数据线、 源极 14、 漏极 15、 像素电极 16。 所述源极 14、 漏极 15 和像素电极 16之间形成有金属层 20。为了保证所述源极 14、漏极 15和所述 金属层 20绝缘， 所述源极 14、 漏极 15和所述金属层 20之间形成有第一绝 缘层 19。 为了保证所述金属层 20和所述像素电极 16绝缘， 所述金属层 20 和所述像素电极 16之间形成第二绝缘层 21。所述数据线与所述源极 14相连， 所述像素电极 16通过过孔 22与漏极 15相连。
从图 1中可以看到， 上述过孔 22贯穿第一绝缘层 19、 金属层 20和第二 绝缘层 21 ,并且位于漏极 15的上方， 因此，可以使像素电极 16与漏极相连。 另外， 虽然未示出， 过孔 22的侧壁上还可以形成有使像素电极 16和金属层 20彼此绝缘的绝缘层。
例如， 栅线和栅极是通过对栅极金属层进行构图形成的， 源极 /漏极和数 据线是通过对源漏金属层构图形成的， 因此， 栅线和栅极位于同一层， 且源 极 /漏极以及所述数据线位于同一层。
为了在增大开口率的情况下，同时减小耦合电容对所述像素电极 16电压 的影响，所述金属层 20可以通过金属层引线过孔 23与稳定电压信号源连接， 这样由于像素电极 16的电压稳定不变， 从而保证了所述像素电极 16和所述 金属层 20之间的耦合电容无法产生充放电的过程， 这样像素电极 16和所述 金属层 20之间的耦合电容也无法对像素电极 16的电压产生影响。
在一个实施例中， 所述金属层 20可以通过金属层引线过孔 23连接到地 线。 在图 1中示出了金属层引线过孔 23贯穿第二绝缘层 21和金属层 20, 然 而， 该过孔 23也可以仅贯穿第二绝缘层 21 , 只要能够露出金属层 20而使其 能够与稳定电压信号线连接， 可以釆取任何合适的形式。
金属层 20可以是透明金属层，如氧化铟锡或氧化铟辞，釆用透明金属层 的 TFT 阵列基板可用于透射式的电子显示装置， 如 TFT LCD显示器。
当然， 金属层 20也可以是非透明金属层， 具体可以钼、 铝、 铝镍合金、 钼钨合金、 铬、 或铜等非透明金属的任一种。 釆用非透明金属层的 TFT阵列 基板可用于反射式的电子显示装置， 如有源电子纸的显示装置。 进一步的， 由于在 TFT阵列基板的源极 14、 漏极 15上形成有非透明金属层， 源极 14 和漏极 15之间的 TFT沟道区域也被遮盖， TFT沟道不会因为外界的光线产 生漏电流而影响有源电子纸的图像显示，从而增强了有源电子纸的光反射率， 提高显示效果。
另外， 以上实施例仅仅以底栅结构为例进行了描述， 然而根据本发明的 阵列基板并不限制于此。 例如， 阵列基板上的薄膜晶体管 （由栅极、 半导体 有源层、 源极 /漏极组成）也可以为顶栅极结构。 无论为底栅结构还是顶栅结 构， 都可以是栅绝缘层夹设在栅极和半导体有源层之间， 且半导体有源层夹 设在源极 /漏极与栅极绝缘层之间。
上述实施例中以 TN型 TFT阵列基板为例， 当然， 本发明也适用于其他 类型阵列基板， 如 FFS型、 IPS型 TFT阵列基板。
在基板上形成的像素电极和源极 /漏极之间形成有第一绝缘层、 金属层、 第二绝缘层， 所述金属层与稳定电压信号线连接。 由于像素电极和金属层之 间的电压稳定， 像素电极和金属层的耦合电容之间不会有充放电的过程， 这 样像素电极和金属层的耦合电容不会对像素电极的电压产生影响。 因此， 避 免了现有技术中由于需要减小源极和像素电极之间的耦合电容需要缩小像素 电极面积的问题。 本发明实施例提供的 TFT阵列基板可以减小 TFT阵列基 板上的耦合电容对像素电极电压的影响， 也可以增大像素单元开口率。
本发明实施例提供一种 TFT阵列基板的制造方法。下面以 TN型 TFT阵 列基板的四次掩模工艺为例进行具体说明， 包括：
5201、 在基板上依次形成栅金属层薄膜， 通过构图工艺， 形成栅线、 栅 极。
例如，在基板上利用磁控溅射工艺沉积一层 1000A至 7000人栅金属层薄 膜， 金属材料通常可以釆用钼、 铝、 铝镍合金、 钼钨合金、 铬、 或铜等金属， 也可以使用上述几种材料薄膜的组合结构。 然后， 釆用掩模板通过曝光、 显 影、 刻蚀、 剥离的构图工艺处理， 在基板上形成多条平行的栅线和与栅线相 连的栅极。 上述形成栅线、 栅极的过程为第一次掩模工艺。
5202、 然后在形成有栅线、 栅极的基板上形成栅绝缘层薄膜、 半导体有 源层薄膜、 数据金属层薄膜， 通过构图工艺形成栅绝缘层、 半导体有源层和 源极 /漏极。
例如， 利用化学汽相沉积法（Chemical Vapor Deposition, CVD )在栅线 11、 栅极 12上沉积厚度为 1000A至 6000人的栅极绝缘层， 栅绝缘层的材料 通常是氮化硅， 也可以使用氧化硅和氮氧化硅等。 然后， 可以通过溅射方法 连续沉积厚度为 50 ~ 1000 A金属氧化物薄膜作为半导体有源层薄膜。最后可 以釆用磁控溅射工艺沉积一层 1000人至 7000人数据金属层薄膜。
在形成栅绝缘层薄膜、 半导体有源层薄膜、 数据金属层薄膜的基板上形 成光刻胶， 利用灰色调掩摸板或半透式掩摸板对光刻胶进行曝光， 显影后形 成光刻胶完全保留区域、 光刻胶半保留区域和光刻胶完全去除区域。 在由栅 线和数据线围成的一个像素单元中， 光刻胶完全保留区域对应数据线、 源极 / 漏极， 光刻胶半保留区域对应源极和漏极之间的沟道区域， 光刻胶完全去除 区域对应像素单元中的光刻胶完全保留区域和光刻胶半保留区域之外的区 域。 利用刻蚀工艺刻蚀掉光刻胶完全去除区域的数据金属层薄膜和半导体有 源层薄膜； 利用等离子灰化工艺再去除掉光刻胶半保留区域的光刻胶， 露出 光刻胶半保留区域的数据金属层薄膜， 利用刻蚀工艺刻蚀掉光刻胶半保留区 域的数据金属层薄膜和部分半导体有源层薄膜， 形成 TFT沟道； 然后剥离光 刻胶完全保留区域的光刻胶， 形成数据线， 源极 /漏极。 上述形成栅绝缘层、 半导体有源层和源极 /漏极的过程为第二次掩模工艺。
S203、在形成上述源极 /漏极的基板上依次形成第一绝缘层薄膜、金属层 薄膜、 第二绝缘层薄膜， 通过构图工艺， 形成第一绝缘层、 金属层、 第二绝 缘层和金属层引线过孔。
例如， 在形成第一绝缘层薄膜、 金属层薄膜、 第二绝缘层薄膜的基板上 形成光刻胶， 然后对光刻胶曝光显影后形成光刻胶完全保留区域和光刻胶完 全去除区域， 光刻胶完全去除区域包括： 漏极和像素电极连接的过孔和金属 层连接到外部稳定信号源的金属层引线过孔； 光刻胶完全保留区域包括由栅 线和数据线组成的像素单元内除光刻胶完全去除区域之外的区域。 然后对光 刻胶完全去除区域进行刻蚀，刻蚀完成后剥离光刻胶完全保留区域的光刻胶， 从而形成漏极和像素电极连接的过孔（贯穿第一绝缘层、 金属层和第二绝缘 层） 、 金属层引线过孔、 第一绝缘层、 金属层、 第二绝缘层。 上述形成漏极 和像素电极连接的过孔、 金属层引线过孔、 第一绝缘层、 金属层、 第二绝缘 层的过程为第三次掩模工艺。
上述的金属层具体可以是透明金属层， 如氧化铟锡或氧化铟辞， 釆用透 明金属层的 TFT 阵列基板可用于透射式的电子显示装置， 如 TFT LCD显示 器。
当然， 金属层也可以是非透明金属层， 具体可以钼、 铝、 铝镍合金、 钼 钨合金、 铬、 或铜等非透明金属的任一种， 釆用非透明金属层的 TFT阵列基 板可用于反射式的电子显示装置， 如有源电子纸的显示装置。 进一步的， 由 于在 TFT 阵列基板的源极 /漏极上形成有非透明金属层， 源极和漏极之间的 TFT沟道区域也被遮盖， TFT沟道不会因为外界的光线产生漏电流而影响有 源电子纸的图像显示，从而可以增强有源电子纸的光反射率，提高显示效果。
所述金属层具体可以通过金属层引线过孔与某一稳定电压信号连接， 如 +5v电压。 在一个实例中，金属层可以通过金属层引线过孔直接与地线连接。
S204、 在第二绝缘层上形成像素电极层薄膜， 通过构图工艺， 形成像素 电极。
具体包括： 在第二绝缘层上形成像素电极， 像素电极具体材料可以是氧 化铟锡或氧化铟辞。 然后通过像素电极掩模板， 曝光显影、 刻蚀和剥离光刻 胶等工艺形成像素电极。 上述形成像素电极的过程为第四次掩模工艺。
上述的构图工艺， 具体包括有： 涂布光刻胶， 曝光、 显影、 刻蚀和剥离 光刻胶等工艺。
例如， 像素电极通过漏极上方的过孔与漏极连接， 金属层引线过孔可以 形成在未被像素电极覆盖的位置。
本 TFT 阵列基板的制造方法实施例是以四次掩模工艺为例进行具体说 明的， 当然对于五次掩模工艺也是可以实现的， 同样是需要在形成连接漏极 和像素电极过孔的工艺过程中形成第一绝缘层、 金属层和第二金属层及金属 层引线过孔。 对于其他的掩模工艺， 当然也需要在实现形成连接漏极和像素 电极过孔的工艺过程中形成第一绝缘层、 金属层和第二金属层及金属层 )线 过孔。或者也可以单独在源极 /漏极和像素电极之间釆用一次掩模工艺形成第 一绝缘层、 金属层、 第二金属层及金属层引线过孔。 本发明在此不作具体限 定。
上述实施例中以 TN型 TFT阵列基板为例， 当然， 本发明也适用于其他 类型阵列基板， 如 FFS型、 IPS型 TFT阵列基板。 上述 TFT阵列基板除了可 以应用于液晶显示器、电子纸器件外，还可以应用于有机发光显示器（ OLED ) 等需要有源驱动的显示器中。
本发明实施例提供的 TFT 阵列基板的制造方法， 在像素电极和源极 /漏 极之间形成第一绝缘层、 金属层和第二绝缘层， 所述金属层可以通过金属层 引线过孔与稳定电压信号线连接。由于通过上述的 TFT阵列基板的制造方法 形成的 TFT阵列基板，源极和像素电极之间设有一层连接到稳定电压源的金 属层， 这样像素电极和金属层的耦合电容之间不会有充放电的过程， 这样像 素电极和金属层的耦合电容不会对像素电极的电压产生影响。 因此， 避免了 现有技术中由于需要减小源极和像素电极之间的耦合电容需要缩小像素电极 面积的问题。 本发明实施例提供的 TFT阵列基板可以减小 TFT阵列基板上 的耦合电容对像素电极电压的影响， 也可以增大像素单元开口率。
本发明实施例还提供了一种包括上述 TFT阵列基板的显示装置，该显示 装置具体可以使 TFT 液晶显示装置， 也可以是反射式的有源电子纸显示装 置、 OLED等， 具体的结构在此不再赘述。
以上所述仅是本发明的示范性实施方式， 而非用于限制本发明的保护范 围， 本发明的保护范围由所附的权利要求确定。

Claims

权利要求书
1、 一种 TFT阵列基板， 包括：
基板，
形成于基板上的栅线、 栅极、 栅绝缘层、 半导体有源层、 数据线、 源极 / 漏极、 像素电极， 所述数据线与所述源极相连， 所述漏极与所述像素电极相 连，
其中所述源极 /漏极和所述像素电极之间依次形成有第一绝缘层、 金属 层、 第二绝缘层， 所述金属层通过金属层引线过孔与稳定电压信号线连接。
2、根据权利要求 1所述的基板，其中所述金属层为透明金属层或非透明 金属层。
3、 根据权利要求 1或 2所述的基板， 其中所述稳定电压信号线为地线。
4、根据权利要求 1-3中任一项所述的基板， 其中所述栅线和所述栅极位 于同一层， 且所述源极 /漏极以及所述数据线位于同一层。
5、根据权利要求 1-4中任一项所述的基板， 其中所述栅绝缘层夹设在所 述栅极和所述半导体有源层之间，且所述半导体有源层夹设在所述源极 /漏极 与所述栅极绝缘层之间。
6、根据权利要求 1-5中任一项所述的基板， 其中所述像素电极通过位于 所述漏极上方且贯穿所述第一绝缘层、 所述金属层和所述第二绝缘层的过孔 与所述漏极连接。
7、根据权利要求 6所述的基板，其中所述像素电极与所述金属层通过所 述漏极上方所述过孔的侧壁上的绝缘层而彼此绝缘。
8、 一种 TFT阵列基板的制造方法， 包括： 在基板上形成栅线、 栅极、 栅绝缘层、 半导体有源层、 数据线、 源极 /漏极、 像素电极，
其中， 所述方法还包括： 在所述源极 /漏极和所述像素电极之间依次形成 有第一绝缘层、 金属层和第二绝缘层。
9、 根据权利要求 8所述的方法， 其中， 所述在所述源极 /漏极和像素电 极之间形成有第一绝缘层、 金属层和第二绝缘层包括：
在形成有栅线、 栅极、 栅绝缘层、 半导体有源层、 数据线、 源极 /漏极的 基板上，通过构图工艺形成所述第一绝缘层、 所述金属层、所述第二绝缘层， 并在所述漏极上方形成贯穿所述第一绝缘层、 所述金属层和所述第二绝缘层 的过孔、 以及露出所述金属层的金属层引线过孔。
10、 根据权利要求 9所述的方法， 包括：
在所述基板上形成栅金属层薄膜， 通过构图工艺形成所述栅线和所述栅 极；
在形成有所述栅线和所述栅极的基板上形成栅绝缘层薄膜、 半导体有源 层薄膜和数据金属层薄膜， 通过构图工艺形成所述栅绝缘层、 所述半导体有 源层和所述源极 /漏极；
在形成上述所述源极 /漏极的基板上依次形成第一绝缘层薄膜、金属层薄 膜、 第二绝缘层薄膜， 通过构图工艺形成所述第一绝缘层、 所述金属层和所 述第二绝缘层， 以及所述漏极上方的过孔和所述金属引线过孔； 以及
在第二绝缘层上形成像素电极层薄膜， 通过构图工艺形成像素电极， 所 述像素电极通过所述漏极上方的过孔与所述漏极连接。
11、根据权利要求 10所述的方法，其中所述金属层引线过孔形成在未被 所述像素电极覆盖的位置。
12、 一种显示装置， 包括权利要求 1-7中任一项所述的 TFT阵列基板。
13、根据权利要求 12所述的显示装置，其中所述显示装置为液晶显示装 置、 反射式电子纸显示装置或有机发光显示器装置。
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US20020050599A1 (en) * 2000-10-28 2002-05-02 Lg.Philips Lcd Co., Ltd. Array substrate for liquid crystal display device and method for manufacturing the same
CN101114087A (zh) * 2006-07-25 2008-01-30 奇美电子股份有限公司 薄膜晶体管基板及其制造方法以及在液晶显示面板中的应用
KR20110069378A (ko) * 2009-12-17 2011-06-23 엘지디스플레이 주식회사 횡전계 방식 액정표시장치 및 그 제조 방법
CN102654702A (zh) * 2012-03-06 2012-09-05 京东方科技集团股份有限公司 Tft阵列基板、tft阵列基板制造方法及显示装置

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