WO2015107875A1 - シリコン単結晶ウェーハの熱処理方法 - Google Patents
シリコン単結晶ウェーハの熱処理方法 Download PDFInfo
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- WO2015107875A1 WO2015107875A1 PCT/JP2015/000058 JP2015000058W WO2015107875A1 WO 2015107875 A1 WO2015107875 A1 WO 2015107875A1 JP 2015000058 W JP2015000058 W JP 2015000058W WO 2015107875 A1 WO2015107875 A1 WO 2015107875A1
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- 238000010438 heat treatment Methods 0.000 title claims abstract description 183
- 238000000034 method Methods 0.000 title claims abstract description 71
- 229910021421 monocrystalline silicon Inorganic materials 0.000 title abstract 7
- 239000011800 void material Substances 0.000 claims abstract description 103
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 72
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/322—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections
- H01L21/3221—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections of silicon bodies, e.g. for gettering
-
- C—CHEMISTRY; METALLURGY
- C30—CRYSTAL GROWTH
- C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
- C30B29/00—Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
- C30B29/02—Elements
- C30B29/06—Silicon
-
- C—CHEMISTRY; METALLURGY
- C30—CRYSTAL GROWTH
- C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
- C30B33/00—After-treatment of single crystals or homogeneous polycrystalline material with defined structure
- C30B33/02—Heat treatment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02587—Structure
- H01L21/0259—Microstructure
- H01L21/02598—Microstructure monocrystalline
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/30—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by physical imperfections; having polished or roughened surface
- H01L29/32—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by physical imperfections; having polished or roughened surface the imperfections being within the semiconductor body
Definitions
- the present invention relates to a heat treatment method for a silicon single crystal wafer in an oxidizing atmosphere.
- high quality means that there is no defect in the region where the device operates.
- the Grown-in defect is expressed as a vacancy type void defect in which Si atoms at lattice points are missing, and Interstitial-Si (interstitial Si, hereinafter referred to as I-Si) in which Si atoms enter between lattices. It is known that there are two types of dislocation cluster defects. The formation state of the grown-in defect varies depending on the growth rate of the single crystal and the cooling conditions of the single crystal pulled from the silicon melt.
- the hollow defects in which the vacancy is aggregated and gathered are called void defects, and the names differ depending on how they are detected. And so on. If these defects are taken into an oxide film formed on a silicon substrate, for example, it is considered that the electrical characteristics deteriorate, such as causing a breakdown voltage failure of the oxide film.
- defect-free crystals for example, a method by controlling the furnace temperature and growth rate as shown in Patent Document 1 has been proposed. However, since defect-free crystals generally have a slow growth rate, there is a problem that productivity is relatively low.
- the defect-free region in the CZ crystal there are various means for determining the defect-free region in the CZ crystal, and one of them is an oxygen precipitate.
- oxygen present in the CZ silicon crystal forms oxygen precipitates (SiO 2 ) when heat treatment is applied. Since this oxygen precipitation reaction has a characteristic that it easily proceeds in the presence of vacancy, the defect region is determined by utilizing the fact that the generation state of oxygen precipitates differs depending on the defect region.
- the demand for low-oxygen products is increasing in various devices such as memory and logic, including power devices and RF devices. This means that if oxygen is present, the resistivity will change due to low-temperature heat treatment, and the device process will be clean, so that oxygen precipitates will be formed inside the conventional wafer to getter heavy metal impurities. This is because technology is becoming unnecessary.
- by reducing the oxygen concentration it becomes difficult to evaluate defects due to the oxygen precipitates described above, and it is difficult to determine a defect-free region.
- One means for solving the problems in defect-free crystals as described above is to grow crystals in a vacancy-rich region where the growth rate can be increased.
- a void defect in which vacancy is aggregated occurs in this region. Therefore, techniques for eliminating these void defects have been disclosed in the past.
- Patent Documents 2 and 3 disclose techniques for eliminating void defects by non-oxidative heat treatment + oxidation heat treatment.
- a non-oxidizing heat treatment is performed to diffuse oxygen in the vicinity of the wafer surface layer outward and dissolve the inner wall oxide film existing on the inner wall of the void-like void defect.
- an oxidation heat treatment is performed, and I-Si is injected from the oxide film formed on the surface into the wafer to fill the void defect.
- Patent Document 4 discloses a technique of oxidation heat treatment + non-oxidation heat treatment in which the order of treatment is reversed. Although these techniques can eliminate void defects, these techniques require two-step heat treatment and are expensive.
- Patent Document 5 discloses a method of performing an oxidation heat treatment at 1,300 ° C. Although this is a single-stage heat treatment, it is highly difficult because of the high temperature of 1,300 ° C., and there are problems of wafer contamination and occurrence of slip dislocations.
- Patent Literature 6 discloses the effect of the oxygen concentration. This is a technology that makes it easier to disappear by heat treatment by increasing the number of connected forms of void defects.
- non-oxidizing heat treatment is performed, and the direction is different from the oxidation heat treatment described below, and the direction in which the oxygen concentration is increased or the cooling rate is decreased is better.
- Patent Document 7 discloses that, in the case of an oxidation heat treatment, if the oxygen concentration is low, the void defect disappears only by a relatively low temperature treatment of 1,200 ° C. or lower, which is a known technique. This is about 8 ppma-JEIDA when the oxygen solid solubility limit (equilibrium concentration) in the silicon crystal is, for example, 1200 ° C., and when the oxygen concentration is lower than this, the inner wall oxide film of Void is the above-mentioned Patent Document 2, This is considered to be due to dissolution without performing non-oxidizing heat treatment as in 3. At the same time, since an oxide film is formed on the surface and I-Si is implanted, the void can be extinguished only by performing an oxidation heat treatment without requiring a special process.
- Patent Document 8 discloses a technique in which this technique is applied to oxidize heat treatment on a low oxygen silicon wafer to eliminate void defects.
- Patent Document 8 has no description regarding the size of the void defect.
- Patent Document 9 discloses a similar technique, which describes the void size, but is as large as 100 nm and does not mention size dependency.
- the void size is large, the void defects are not completely eliminated even if the oxidation heat treatment is performed. Therefore, there is a problem that these techniques cannot completely eliminate the void defects.
- Both of these techniques are for neutron-irradiated products, and the heat treatment temperature is high and the treatment time is long because it also serves as a recovery heat treatment. Therefore, there is a problem in terms of cost reduction, and there are also problems in terms of wafer contamination and slip dislocation generation.
- Japanese Patent Laid-Open No. 11-157996 Japanese Patent Laid-Open No. 11-260677 WO2000 / 012786 JP 2013-87983 A WO2003 / 056221 JP 2000-272996 A WO2004 / 073057 JP 2006-344823 A JP 2010-265143 A
- the present invention has been made in order to solve the above-described problems.
- An object of the present invention is to provide a heat treatment method for a silicon single crystal wafer to be extinguished.
- the present invention is a method of performing a heat treatment in an oxidizing atmosphere on a silicon single crystal wafer, It is obtained from the three-way correlation of the heat treatment temperature at the time of performing the heat treatment, the oxygen concentration in the silicon single crystal wafer before the heat treatment, and the void size in the silicon single crystal wafer before the heat treatment.
- a heat treatment method for a silicon single crystal wafer that performs heat treatment based on conditions.
- the void defects and minute oxygen precipitation nuclei of the silicon single crystal wafer can be eliminated efficiently and reliably at low cost by the heat treatment in an oxidizing atmosphere.
- T heat treatment temperature (° C.)
- [Oi] oxygen concentration (ppma-JEIDA) in the silicon single crystal wafer before heat treatment
- Lvoid void size in the silicon single crystal wafer before heat treatment (Nm).
- the heat treatment temperature is preferably 900 ° C. or more and 1,200 ° C. or less, and the heat treatment time is preferably 1 minute or more and 180 minutes or less.
- the silicon single crystal wafer having an oxygen concentration of 8 ppma-JEIDA or less it is preferable to use the silicon single crystal wafer having an oxygen concentration of 8 ppma-JEIDA or less.
- the heat treatment temperature necessary to eliminate void defects can be lowered, so that the cost can be reduced and the occurrence of slip dislocation during the heat treatment, which tends to occur at higher temperatures, can be suppressed. Can do.
- a silicon single crystal wafer that is not doped with nitrogen or is cut from a silicon single crystal doped with nitrogen of 5 ⁇ 10 15 atoms / cm 3 or less.
- the void defect disappears if the above conditions are satisfied.
- the resistance to slip dislocation can be improved and the void size can be reduced.
- a silicon single crystal wafer having a thickness of 0.1 mm to 20 mm.
- the shape of the wafer can be easily maintained, and the heat treatment time does not become too long, so that an increase in cost can be suppressed.
- the void size obtained from the simulation can be applied as the void size.
- the silicon single crystal wafer heat treatment method of the present invention the silicon single crystal can be efficiently and surely suppressed while suppressing the occurrence of slip dislocation by heat treatment in an oxidizing atmosphere. Waid defects and minute oxygen precipitation nuclei of the wafer can be eliminated.
- a defect-free silicon single crystal wafer that does not include defects due to both Void and I-Si can be obtained.
- Such a wafer is particularly suitable as a defect-free wafer used as a substrate for a semiconductor device such as a memory, CPU, or power device.
- Patent Document 7 It is known from Patent Document 7 that whether or not void defects disappear due to the oxidation heat treatment is related to the heat treatment temperature and the oxygen concentration of the wafer. There was a problem that the defects did not disappear completely. As a result of intensive investigations, the present inventors have focused on this point, and as a result of oxidation heat treatment conditions that can eliminate void defects, not only the heat treatment temperature and the oxygen concentration of the wafer, but also the void size in the wafer are included. As a result, the present inventors have found that the above-mentioned problems can be achieved by performing heat treatment based on the conditions obtained from the correlation between these three factors, and have completed the present invention.
- the present invention is a method for performing a heat treatment in an oxidizing atmosphere on a silicon single crystal wafer, It is obtained from the three-way correlation of the heat treatment temperature at the time of performing the heat treatment, the oxygen concentration in the silicon single crystal wafer before the heat treatment, and the void size in the silicon single crystal wafer before the heat treatment.
- This is a heat treatment method for a silicon single crystal wafer in which heat treatment is performed based on conditions.
- oxygen concentration when simply referred to as “oxygen concentration”, this indicates “oxygen concentration in a silicon single crystal wafer before heat treatment”, and when simply referred to as “Void size”, this means “silicon before heat treatment”. “Void size in a single crystal wafer”.
- the above formula (1) is a heat treatment in which the heat treatment temperature is set higher than the temperature obtained from the oxygen concentration and the void size
- the oxygen concentration is controlled to be equal to or lower than the concentration obtained from the heat treatment temperature and the void size
- the void size is controlled to be equal to or smaller than the size obtained from the heat treatment temperature and the oxygen concentration
- the void defects can be surely eliminated by setting the heat treatment temperature, oxygen concentration, and void size satisfying these conditions. Furthermore, if this relationship is applied, for example, the heat treatment temperature can be lowered by controlling the oxygen concentration to be lower and the void size to be smaller. If the heat treatment temperature can be lowered, the cost can be reduced and the occurrence of slip dislocation during heat treatment, which is likely to occur as the temperature becomes higher, can be suppressed.
- the void defect can be eliminated by the heat treatment method of the present invention, the defect caused by I-Si cannot be eliminated. Therefore, it is preferable to use a silicon single crystal wafer cut from a silicon single crystal that does not include defects due to I-Si.
- the single crystal there is a region where OSF nuclei are generated (OSF region) on the slow growth side from the region where void defects are generated, and there is a defect-free region on the low speed side.
- the defect-free region includes a region containing a lot of vacancy (Nv region) and a region containing a lot of I-Si (Ni region), and the Nv region includes a portion containing nuclei of minute oxygen precipitates.
- Nv region a region containing a lot of vacancy
- I-Si I-Si
- the silicon single crystal to which the heat treatment method of the present invention is effectively applied is targeted for the void defect occurrence region, the OSF region, the Nv region, and the Ni region, excluding the above-described I-rich region.
- the heat treatment method of the present invention not only improves the void defect occurrence region, but also can be expected to improve the OSF region and the Nv region. Therefore, the heat treatment method of the present invention is effective in all regions where there are no defects due to I-Si.
- the heat treatment temperature is preferably 900 ° C. or more and 1,200 ° C. or less.
- the heat treatment temperature is 900 ° C. or higher, void defects having a size that affects electrical characteristics can be eliminated.
- the cost can be suppressed and the occurrence of slip dislocation can be suppressed.
- it is 1,150 degrees C or less, since generation
- the heat treatment time is preferably 1 minute or more and 180 minutes or less, although it depends on the thickness of the wafer used. As described above, the diffusion of I-Si is relatively fast, and a diffusion distance with a normal wafer thickness of less than 1 mm can be obtained in 1 minute. Therefore, a heat treatment time of about 1 minute is sufficient. On the other hand, if the heat treatment time becomes longer, the cost increases, so that a treatment time exceeding 180 minutes is not necessary.
- a silicon single crystal wafer having an oxygen concentration of 8 ppma-JEIDA or less it is preferable to use a silicon single crystal wafer having an oxygen concentration of 8 ppma-JEIDA or less.
- the oxygen solid solubility limit of 1,200 ° C. which is the above-mentioned preferable heat treatment temperature, is about 8 ppma-JEIDA, and treatment at a higher temperature is required when the oxygen concentration exceeds this.
- the heat treatment method of the present invention can be used not only for wafers cut from CZ crystals but also for wafers cut from crystals containing almost no oxygen such as FZ crystals.
- the silicon single crystal wafer used in the heat treatment method of the present invention is preferably not a crystal intentionally doped with impurities except a dopant for controlling resistivity, and is cut from a general crystal. . This is because even if it is a general crystal, the void defect disappears if the oxygen concentration satisfies the above conditions.
- doping nitrogen is known to improve resistance to slip dislocations. Further, when nitrogen is doped, the defect formation temperature zone is lowered and the void size tends to be reduced. Therefore, in the heat treatment method of the present invention, it is also preferable to use a silicon single crystal wafer cut out from a crystal intentionally doped with nitrogen in addition to a dopant for controlling resistivity. At this time, the doping amount of nitrogen is preferably 5 ⁇ 10 15 atoms / cm 3 or less. Since the solid solubility limit of nitrogen in a silicon crystal is said to be in the 15th power range, by setting it to the above concentration or less, there is no possibility that the crystal is dislocated due to high concentration doping of nitrogen. On the other hand, a lower nitrogen concentration may be used. This is because the heat treatment method of the present invention can be used without any problem even when nitrogen is not doped.
- the heat treatment method of the present invention it is preferable to use a silicon single crystal wafer having a thickness of 0.1 mm to 20 mm.
- the heat treatment is preferably performed at 1,200 ° C. or less and 180 minutes or less from the viewpoint of cost.
- the diffusion distance of I-Si after heat treatment at 1,200 ° C. for 180 minutes is about 10 mm.
- the oxide film is formed on both the front surface and the back surface, and I-Si is supplied therefrom.
- the surface state of the silicon single crystal wafer used for the heat treatment method of the present invention is a surface state within the range used in the silicon wafer manufacturing process, such as a polished surface, an etched surface, a lapping surface, a ground surface, and a sliced surface, for example. Good.
- the heat treatment method of the present invention it is only necessary to form an oxide film, so there is no need to worry about the surface condition. Cleaning or the like is necessary to enter the heat treatment furnace, but no other special surface treatment is necessary, and heat treatment can be performed anywhere in the wafer manufacturing process. Therefore, the heat treatment may be performed in any surface state used in the silicon wafer manufacturing process.
- the void size is ideally obtained by directly observing with a TEM or SEM, for example.
- the void size obtained from the simulation may be applied as the void size. As a result, it is possible to save the trouble of actually measuring the void size and more easily obtain the heat treatment conditions.
- the void sizes obtained from the respective simulations do not always match. Therefore, when using the simulation, it is preferable to correct the void size obtained from the simulation with the void size (measured value) obtained by observation with a TEM, SEM, or the like. In this way, the actual void size can be reflected more accurately, and even if the simulation method is different, comparison is possible if the calculation is appropriate.
- the heat treatment method of the present invention is a method performed in an oxidizing atmosphere, and any oxygen-containing atmosphere may be used, and the oxygen flow rate at this time is not particularly limited.
- the silicon single crystal wafer heat treatment method of the present invention the silicon single crystal can be efficiently and surely suppressed while suppressing the occurrence of slip dislocation by heat treatment in an oxidizing atmosphere. Waid defects and minute oxygen precipitation nuclei of the wafer can be eliminated.
- a defect-free silicon single crystal wafer that does not include defects due to both Void and I-Si can be obtained.
- Such a wafer is particularly suitable as a defect-free wafer used as a substrate for a semiconductor device such as a memory, CPU, or power device.
- a silicon single crystal having a diameter slightly exceeding 200 mm or 300 mm was grown.
- the crystal was grown by varying the oxygen concentration and the void size.
- the oxygen concentration was controlled by changing the rotation speed of the crystal, the rotation speed of the crucible, the pressure in the furnace, the flow rate of Ar gas flowing for purging, and the like.
- the void size was changed by controlling the structure and growth rate of the in-furnace parts in addition to the presence or absence of nitrogen doping. At this time, crystal growth conditions were adjusted so as not to include defects caused by I-Si.
- This crystal was cylindrically ground and processed into a cylindrical block having a desired thickness, and then a wafer-like sample having a thickness of about 1.2 mm was cut out from the block.
- three samples were cut out at positions adjacent to each other, and one of them was a sample for measuring the oxygen concentration before heat treatment, presence of FPD / LEP / LSTD, and void size (hereinafter referred to as measurement).
- the other two sheets were actually subjected to heat treatment as described later, and were samples (hereinafter referred to as heat treatment samples) for measuring FPD / LSTD after the heat treatment.
- 35 levels of samples were prepared including in-plane distribution within the wafer. Of these, 5 levels were doped with nitrogen, and the concentration was 4 to 12 ⁇ 10 13 atoms / cm 3 .
- the sample for measurement was surface-ground with high brightness, and then the oxygen concentration was determined by the FT-IR method. At this time, the oxygen concentration of the measurement sample was between 0.4 and 12.2 ppma-JEIDA (0.3 to 9.8 ⁇ 10 17 atoms / cm 3 -ASTM'79). Further, the sample for measurement was mirror-etched with a mixed acid composed of hydrofluoric acid, nitric acid and acetic acid. Next, selective etching was performed by leaving the measurement sample in a selective etching solution composed of hydrofluoric acid, nitric acid, acetic acid, and water without shaking. Although FPD was observed in these measurement samples, LEP was not observed, and it was confirmed that there were no defects due to I-Si.
- Infrared scattering tomographs can detect defects up to a size of 20 nm by increasing the sensitivity of the optical system.
- the intensity scattered from the defect is proportional to the square of the defect volume and the sixth power of the defect size. By utilizing this feature, it is possible to determine the defect size.
- the scattered light intensity is proportional to the sixth power of the defect size, the dynamic range between the case of viewing a small defect and the case of viewing a large defect is too large, and it is difficult to compare and evaluate the size over all sizes.
- the void size fluctuated from 21 nm to 111 nm.
- required by simulation was calculated
- the oxygen concentration and the void size before the heat treatment of the 35 level measurement samples including the in-plane distribution in the wafer were measured.
- heat treatment was actually performed using the above heat treatment sample.
- two heat treatment samples were subjected to high-intensity surface grinding, and each was divided into four and mirror-etched with the above mixed acid. After the etching, the heat treatment sample was heat treated in an oxidizing atmosphere of dry oxygen 3 L / min.
- the heat-treated sample had an oxide film formed on the surface, it was removed with hydrofluoric acid. Thereafter, like the measurement sample, the surface was mirror-etched with a mixed acid, and then selective etching was performed to observe the FPD. Some FPDs disappeared compared to the measurement samples that were not heat-treated. Next, this sample was cleaved, and the presence or absence of LSTD was confirmed by MO441. Here again, it was confirmed that the LSTD disappeared compared to the measurement sample that was not heat-treated. Although the surface state was an etched surface, the defects disappeared by oxidation treatment without any particular problem. The case where the FPD disappeared and the case where the LSTD disappeared basically had the same tendency. However, there was a tendency for FPD to disappear easily.
- Example 2 Using a crystal pulling apparatus having a crucible outer diameter of approximately 660 mm, a crystal having a diameter of approximately 200 mm was grown by the MCZ method. This crystal was doped with nitrogen. Two wafers having a thickness of 1.2 mm were cut from adjacent positions of the crystal. The nitrogen concentration at the position where the wafer was cut out was 8 ⁇ 10 13 atoms / cm 3 . One of the cut wafers was ground on both sides, and the oxygen concentration was measured by FT-IR. As a result, it was 2.8 ppma-JEIDA.
- the silicon single crystal wafer heat treatment method of the present invention enables efficient and reliable low-cost, silicon crystal crystal void defects and minute oxygen precipitation by heat treatment in an oxidizing atmosphere. It became clear that the nucleus could be extinguished.
- the present invention is not limited to the above embodiment.
- the above-described embodiment is an exemplification, and the present invention has any configuration that has substantially the same configuration as the technical idea described in the claims of the present invention and that exhibits the same effects. Are included in the technical scope.
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Abstract
Description
一方で成長速度を比較的低速に設定して単結晶を育成した場合には、I-Siが優勢になることが知られている。このI-Siが凝集して集まると、転位ループなどがクラスタリングしたと考えられるLEP(Large Etch Pit=転位クラスタ欠陥)が検出される。この転位クラスタ欠陥が生じる領域にデバイスを形成すると、電流リークなど重大な不良を起こすと言われている。
近年パワーデバイスやRFデバイスをはじめとして、メモリーやロジックなど様々なデバイスで低酸素品の需要が高まってきている。これは酸素があると低温熱処理でドナー化してしまい抵抗率が変化してしまうこと、デバイスプロセスが綺麗になったため従来行ってきたウェーハ内部に酸素析出物を形成して重金属不純物をゲッタリングするという技術が不要になってきていること、などのためである。一方、低酸素濃度化することにより、前述の酸素析出物による欠陥評価が難しくなり、無欠陥領域の判定が難しくなってきているという問題点もある。
これらの技術によってVoid欠陥を消滅させることは可能であるが、これらの技術では2段階の熱処理が必要であり高コストである。また表層近傍のVoid欠陥しか消すことができないという問題点がある。
また特許文献5では、1,300℃で酸化熱処理する方法が開示されている。これは単段の熱処理ではあるが、1,300℃という高温のため、難易度が高く、ウェーハ汚染やスリップ転位発生の問題もある。
前記熱処理を行う際の熱処理温度、前記熱処理を行う前の前記シリコン単結晶ウェーハ中の酸素濃度、及び前記熱処理を行う前の前記シリコン単結晶ウェーハ中のVoidサイズの3者の相関関係から求められる条件に基づいて熱処理を行うシリコン単結晶ウェーハの熱処理方法を提供する。
T≧37.5[Oi]+1.74Lvoid+890
(ここで、T:熱処理温度(℃)、[Oi]:熱処理を行う前のシリコン単結晶ウェーハ中の酸素濃度(ppma-JEIDA)、Lvoid:熱処理を行う前のシリコン単結晶ウェーハ中のVoidサイズ(nm)である。)
また、このような熱処理時間であれば、Void欠陥を消滅させるのに十分であり、コストの増加を抑制することができる。
また、I-Siに起因する欠陥を含まないウェーハを用いることで、Void、I-Siの両方に起因する欠陥を含まない無欠陥のシリコン単結晶ウェーハを得ることができる。このようなウェーハであれば、特に、メモリー・CPU・パワーデバイスなど半導体デバイスの基板として用いられる無欠陥ウェーハとして好適である。
本発明者らはこの点に着目し、鋭意検討を重ねた結果、Void欠陥を消滅させることができる酸化熱処理の条件には、熱処理温度とウェーハの酸素濃度だけではなく、ウェーハ中のVoidサイズも関係していることに想到し、これら3者の相関関係から求められる条件に基づいて熱処理を行うことで上記課題を達成できることを見出し、本発明を完成させた。
前記熱処理を行う際の熱処理温度、前記熱処理を行う前の前記シリコン単結晶ウェーハ中の酸素濃度、及び前記熱処理を行う前の前記シリコン単結晶ウェーハ中のVoidサイズの3者の相関関係から求められる条件に基づいて熱処理を行うシリコン単結晶ウェーハの熱処理方法である。
なお、本明細書中、単に「酸素濃度」と言う場合、これは「熱処理前のシリコン単結晶ウェーハ中の酸素濃度」を示し、単に「Voidサイズ」と言う場合、これは「熱処理前のシリコン単結晶ウェーハ中のVoidサイズ」を示す。
また上記の実験から、Void欠陥は、熱処理温度が高ければ消滅しやすく、酸素濃度が低いほど、またはVoidサイズが小さいほど消滅しやすいことが判った。一方で、熱処理時間には大きく影響されることは無かった。これはI-Siの拡散係数が比較的大きいので、数分程度でI-Siがウェーハの内部まで拡散するためと考えられる。従って、熱処理温度、酸素濃度、Voidサイズの3者の相関関係から求められる条件に基づいて熱処理を行うことが非常に有効である。
T≧37.5[Oi]+1.74Lvoid+890 (1)
また、この式を[Oi]、Lvoidを表す式に変形すると、以下の式となる。
[Oi]≦0.0267T-0.0464Lvoid-23.7 (2)
Lvoid≦0.575T-21.5[Oi]-510 (3)
ここで、Tは熱処理温度(℃)であり、[Oi]は熱処理を行う前のシリコン単結晶ウェーハ中の酸素濃度(ppma-JEIDA)であり、Lvoidは熱処理を行う前のシリコン単結晶ウェーハ中のVoidサイズ(nm)である。
上記式(2)は、酸素濃度を、熱処理温度とVoidサイズから求められる濃度以下に制御すること、
上記式(3)は、Voidサイズを、熱処理温度と酸素濃度から求められるサイズ以下に制御すること、
をそれぞれ意味しており、本発明の熱処理方法は、具体的には、これらのいずれかを満たす熱処理もしくは制御を行えばよい。
本発明の熱処理方法では、OSF核や微小酸素析出核も消滅可能と考えられる。従って、本発明の熱処理方法が有効に適用されるシリコン単結晶は、上述したI-rich領域を除く、Void欠陥発生領域、OSF領域、Nv領域、Ni領域が対象の領域である。
つまり、本発明の熱処理方法ではVoid欠陥発生領域の改善はもちろんであるが、OSF領域やNv領域の改善効果も期待できる。従ってI-Siに起因する欠陥が無い領域では、全ての領域で本発明の熱処理方法が有効である。
このとき、窒素をドープする量としては、5×1015atoms/cm3以下であることが好ましい。シリコン結晶における窒素の固溶限が15乗台と言われているため、上記の濃度以下とすることで、窒素の高濃度ドープによって結晶が有転位化する恐れがない。一方で窒素濃度が低い方は、いくら低くてもよい。なぜなら窒素ドープしない場合であっても問題なく本発明の熱処理方法を用いることができるからである。
一方で、前述のようにコストなどの面から熱処理は1,200℃以下、180分以下で行うのが好ましい。1,200℃、180分の熱処理でのI-Siの拡散距離は10mm程度である。酸化膜は表面と裏面との両面に形成され、そこからI-Siが供給されるので、1,200℃、180分の熱処理を行っても20mm程度のウェーハ厚さまでしか改質ができない。従って、前述の熱処理温度、熱処理時間内でウェーハ全体のVoid欠陥を消滅させるためには、ウェーハの厚さが20mm以下のものを用いることが好ましい。
そこで、Voidサイズとして、シミュレーションから求められたVoidサイズを適用してもよい。これにより、実際にVoidサイズを測定する手間を省き、より簡便に熱処理の条件を求めることができる。
そこで、シミュレーションを用いる場合は、シミュレーションから求められたVoidサイズを、TEMやSEM等による観察で得られたVoidサイズ(実測値)で補正して用いることが好ましい。このようにすれば、現実のVoidサイズをより正確に反映することができ、またシミュレーションの方法が違っていても、計算が妥当であれば、比較が可能となる。
また、I-Siに起因する欠陥を含まないウェーハを用いることで、Void、I-Siの両方に起因する欠陥を含まない無欠陥のシリコン単結晶ウェーハを得ることができる。このようなウェーハであれば、特に、メモリー・CPU・パワーデバイスなど半導体デバイスの基板として用いられる無欠陥ウェーハとして好適である。
CZ法もしくは磁場印加CZ(MCZ)法を用いて、直径が200mmもしくは300mmを少し超える太さのシリコン単結晶を育成した。このとき酸素濃度及びVoidサイズを振って結晶を育成した。酸素濃度は結晶の回転数、ルツボの回転数、炉内の圧力、パージのために流しているArガスの流量などを変えて制御した。一方でVoidサイズは、窒素ドープの有無に加え、炉内部品の構造や成長速度を制御して変化させた。このときI-Siに起因する欠陥が含まれないように結晶成長条件を調整した。
以上のようにして、ウェーハ内での面内分布も含めて35水準の測定用サンプルの熱処理前の酸素濃度及びVoidサイズを測定した。
まず、熱処理の前処理として、2枚の熱処理用サンプルを高輝度平面研削した後、それぞれ4分割し上述の混酸によりミラーエッチングした。エッチング後、熱処理用サンプルをドライ酸素3L/minの酸化性雰囲気で熱処理した。このとき、熱処理温度及び熱処理時間は、(a)1,150℃で30分又は60分、(b)1,100℃で30分又は60分、(c)1,050℃で60分又は120分、(d)1,000℃で60分又は120分、の4×2=8パターンとした。
その後、測定用サンプルと同様に、表面を混酸にてミラーエッチングした後、選択エッチングを行いFPDの観察を行った。熱処理をしていない測定用サンプルに比較して、FPDが消えているものがあった。次に、このサンプルを劈開し、MO441でLSTDの有無を確認した。ここでも熱処理をしていない測定用サンプルに比較して、LSTDが消えているものが確認された。
表面状態はエッチング面であるが、特に問題なく酸化処理で欠陥が消滅した。FPDが消滅しているケースとLSTDが消滅しているケースは基本的に同じ傾向であった。ただ、FPDの方が消滅しやすい傾向が見られた。これは、FPDは表層数十μmを観察しているのに対し、LSTDはウェーハ内部まで観察しているためと考えられる。一方、各熱処理温度で熱処理時間を2水準振っているが、欠陥が消滅するかどうかは熱処理時間にはほとんど依存していなかった。
ここで、Void欠陥が消滅する過程を考えると、はじめに内壁酸化膜が消え、次にI-SiがVoid欠陥を埋める。内壁酸化膜が消えるかどうかは、先に述べたように、酸素濃度が熱処理温度での酸素固溶限より下回っているかどうかである。つまり消滅するかどうかの温度依存性は、酸素固溶限によって決まると考えられる。
上述の実験で用意したブロックのうち、直径が300mm、酸素濃度が3.2ppma-JEIDA、Voidサイズが38nmである窒素をドープしていないブロックの部分からウェーハを切り出し、厚さが775μmのポリッシュドウェーハ(PW=研磨面)を作製した。測定した酸素濃度[Oi]及びVoidサイズLvoidを関係式に代入して必要な熱処理温度を求めると、
T≧37.5×3.2+1.74×38+890=1,076
となった。この求めた熱処理温度に基づいて、ウェーハにドライ酸素3L/minの酸化性雰囲気下、1,150℃にて、30分熱処理を行った。
熱処理後に酸化膜を除去した後、このウェーハをMO441で欠陥観察した結果、LSTDは検出されなかった。
ルツボの外径が概略660mmである結晶引上げ装置を用いて、直径が概略200mmの結晶をMCZ法により育成した。この結晶には窒素をドープした。この結晶の隣接する位置から1.2mm厚さのウェーハを2枚切り出した。ウェーハを切り出した位置での窒素濃度は8×1013atoms/cm3であった。切り出したウェーハのうち1枚を両面研削した後、FT-IRにて酸素濃度を測定したところ、2.8ppma-JEIDAであった。この測定用のウェーハをフッ酸、硝酸、酢酸からなる混酸にてミラーエッチングした後、劈開してMO441にて観察しところ、LSTDが検出されそのサイズは40nmであった。測定した酸素濃度[Oi]及びVoidサイズLvoidを関係式に代入して必要な熱処理温度を求めると、
T≧37.5×2.8+1.74×40+890=1,065
となった。切り出したウェーハのうちもう1枚を平面研削した後、ミラーエッチングし、上記のようにして求めた熱処理温度に基づいて、このウェーハにドライ酸素3L/minの酸化性雰囲気下、1,100℃にて、30分熱処理を行った。
熱処理後に酸化膜を除去した後、このウェーハをMO441で欠陥観察した結果、LSTDは検出されなかった。
ルツボの外径が概略660mmである結晶引上げ装置を用いて、直径が概略200mmの結晶をMCZ法により育成した。この結晶には窒素をドープした。この結晶の隣接する位置から1.2mm厚さのウェーハを2枚切り出した。ウェーハを切り出した位置での窒素濃度は7×1013atoms/cm3であった。切り出したウェーハのうち1枚を平面研削した後、ミラーエッチングし、酸素濃度及びVoidサイズの測定を行わず、ドライ酸素3L/minの酸化性雰囲気下、1,150℃にて、30分熱処理を行った。
熱処理後に酸化膜を除去した後、このウェーハをMO441で欠陥観察した結果、LSTDが検出された。
T≧37.5×11.2+1.74×22+890=1,348
であり、熱処理温度を1,150℃とした熱処理でLSTDが消えなかったのは、相関関係から求められる熱処理温度を満たさなかったためであることが示唆された。
Claims (8)
- シリコン単結晶ウェーハに酸化性雰囲気下で熱処理を行う方法であって、
前記熱処理を行う際の熱処理温度、前記熱処理を行う前の前記シリコン単結晶ウェーハ中の酸素濃度、及び前記熱処理を行う前の前記シリコン単結晶ウェーハ中のVoidサイズの3者の相関関係から求められる条件に基づいて熱処理を行うことを特徴とするシリコン単結晶ウェーハの熱処理方法。 - 前記3者の相関関係が、下記の関係式で表されることを特徴とする請求項1に記載のシリコン単結晶ウェーハの熱処理方法。
T≧37.5[Oi]+1.74Lvoid+890
(ここで、T:熱処理温度(℃)、[Oi]:熱処理を行う前のシリコン単結晶ウェーハ中の酸素濃度(ppma-JEIDA)、Lvoid:熱処理を行う前のシリコン単結晶ウェーハ中のVoidサイズ(nm)である。) - 前記シリコン単結晶ウェーハとして、Interstitial-Siに起因する欠陥を含まないシリコン単結晶から切り出されたものを用いることを特徴とする請求項1又は請求項2に記載のシリコン単結晶ウェーハの熱処理方法。
- 前記熱処理温度は900℃以上1,200℃以下であり、熱処理時間は1分以上180分以下であることを特徴とする請求項1から請求項3のいずれか一項に記載のシリコン単結晶ウェーハの熱処理方法。
- 前記シリコン単結晶ウェーハとして、前記酸素濃度が8ppma-JEIDA以下のものを用いることを特徴とする請求項1から請求項4のいずれか一項に記載のシリコン単結晶ウェーハの熱処理方法。
- 前記シリコン単結晶ウェーハとして、窒素がドープされていないか、もしくは5×1015atoms/cm3以下の窒素がドープされたシリコン単結晶から切り出されたものを用いることを特徴とする請求項1から請求項5のいずれか一項に記載のシリコン単結晶ウェーハの熱処理方法。
- 前記シリコン単結晶ウェーハとして、厚さが0.1mm以上20mm以下のものを用いることを特徴とする請求項1から請求項6のいずれか一項に記載のシリコン単結晶ウェーハの熱処理方法。
- 前記Voidサイズとして、シミュレーションから求められたVoidサイズを適用することを特徴とする請求項1から請求項7のいずれか一項に記載のシリコン単結晶ウェーハの熱処理方法。
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JP2008135773A (ja) * | 2002-02-07 | 2008-06-12 | Siltronic Ag | シリコンウェーハの熱処理方法及び該方法で処理したシリコンウェーハ |
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KR102192287B1 (ko) | 2020-12-17 |
JP6052188B2 (ja) | 2016-12-27 |
CN105900220B (zh) | 2018-09-25 |
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