WO2015096320A1 - 低温多晶硅薄膜及其制备方法、薄膜晶体管和显示装置 - Google Patents
低温多晶硅薄膜及其制备方法、薄膜晶体管和显示装置 Download PDFInfo
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- WO2015096320A1 WO2015096320A1 PCT/CN2014/076046 CN2014076046W WO2015096320A1 WO 2015096320 A1 WO2015096320 A1 WO 2015096320A1 CN 2014076046 W CN2014076046 W CN 2014076046W WO 2015096320 A1 WO2015096320 A1 WO 2015096320A1
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- 229910021420 polycrystalline silicon Inorganic materials 0.000 title claims abstract description 74
- 239000010409 thin film Substances 0.000 title claims abstract description 49
- 238000002360 preparation method Methods 0.000 title abstract description 26
- 229910021417 amorphous silicon Inorganic materials 0.000 claims abstract description 155
- 239000000758 substrate Substances 0.000 claims abstract description 74
- 238000000034 method Methods 0.000 claims abstract description 69
- 238000007715 excimer laser crystallization Methods 0.000 claims abstract description 28
- 238000000059 patterning Methods 0.000 claims abstract description 22
- 238000005530 etching Methods 0.000 claims abstract description 9
- 239000010410 layer Substances 0.000 claims description 233
- 239000010408 film Substances 0.000 claims description 108
- 229920005591 polysilicon Polymers 0.000 claims description 60
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 14
- 229910004205 SiNX Inorganic materials 0.000 claims description 12
- 238000009413 insulation Methods 0.000 claims description 11
- 238000004519 manufacturing process Methods 0.000 claims description 11
- 239000002131 composite material Substances 0.000 claims description 8
- 235000012239 silicon dioxide Nutrition 0.000 claims description 8
- 239000002356 single layer Substances 0.000 claims description 7
- 239000000377 silicon dioxide Substances 0.000 claims description 6
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 4
- 229910052681 coesite Inorganic materials 0.000 claims 2
- 229910052906 cristobalite Inorganic materials 0.000 claims 2
- 229910052682 stishovite Inorganic materials 0.000 claims 2
- 229910052905 tridymite Inorganic materials 0.000 claims 2
- 238000005516 engineering process Methods 0.000 abstract description 6
- 238000002425 crystallisation Methods 0.000 description 14
- 230000008025 crystallization Effects 0.000 description 14
- 239000013078 crystal Substances 0.000 description 10
- 238000000151 deposition Methods 0.000 description 10
- 239000004973 liquid crystal related substance Substances 0.000 description 8
- 230000006911 nucleation Effects 0.000 description 8
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 8
- 238000009827 uniform distribution Methods 0.000 description 8
- 229920002120 photoresistant polymer Polymers 0.000 description 7
- 239000011521 glass Substances 0.000 description 6
- 238000010899 nucleation Methods 0.000 description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 229910052710 silicon Inorganic materials 0.000 description 5
- 239000010703 silicon Substances 0.000 description 5
- 238000005229 chemical vapour deposition Methods 0.000 description 4
- 238000009826 distribution Methods 0.000 description 4
- 229910004298 SiO 2 Inorganic materials 0.000 description 3
- 229910021419 crystalline silicon Inorganic materials 0.000 description 3
- 238000005401 electroluminescence Methods 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 230000008018 melting Effects 0.000 description 3
- 238000002844 melting Methods 0.000 description 3
- 229920001621 AMOLED Polymers 0.000 description 2
- 210000002858 crystal cell Anatomy 0.000 description 2
- 230000017525 heat dissipation Effects 0.000 description 2
- 238000005224 laser annealing Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 239000010453 quartz Substances 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 230000004927 fusion Effects 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000007641 inkjet printing Methods 0.000 description 1
- 230000031700 light absorption Effects 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 238000012827 research and development Methods 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 238000007650 screen-printing Methods 0.000 description 1
- 239000002210 silicon-based material Substances 0.000 description 1
- 239000007790 solid phase Substances 0.000 description 1
- 238000012876 topography Methods 0.000 description 1
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- H—ELECTRICITY
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/04—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02367—Substrates
- H01L21/0237—Materials
- H01L21/02422—Non-crystalline insulating materials, e.g. glass, polymers
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02436—Intermediate layers between substrates and deposited layers
- H01L21/02439—Materials
- H01L21/02488—Insulating materials
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02436—Intermediate layers between substrates and deposited layers
- H01L21/02494—Structure
- H01L21/02496—Layer structure
- H01L21/02502—Layer structure consisting of two layers
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02524—Group 14 semiconducting materials
- H01L21/02532—Silicon, silicon germanium, germanium
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02656—Special treatments
- H01L21/02664—Aftertreatments
- H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
- H01L21/02675—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth using laser beams
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02656—Special treatments
- H01L21/02664—Aftertreatments
- H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
- H01L21/02675—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth using laser beams
- H01L21/02686—Pulsed laser beam
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- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
- H01L27/1274—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement using crystallisation of amorphous semiconductor or recrystallisation of crystalline semiconductor
- H01L27/1281—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement using crystallisation of amorphous semiconductor or recrystallisation of crystalline semiconductor by using structural features to control crystal growth, e.g. placement of grain filters
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- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
- H01L27/1274—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement using crystallisation of amorphous semiconductor or recrystallisation of crystalline semiconductor
- H01L27/1285—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement using crystallisation of amorphous semiconductor or recrystallisation of crystalline semiconductor using control of the annealing or irradiation parameters, e.g. using different scanning direction or intensity for different transistors
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
- H01L29/6675—Amorphous silicon or polysilicon transistors
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78651—Silicon transistors
- H01L29/7866—Non-monocrystalline silicon transistors
- H01L29/78672—Polycrystalline or microcrystalline silicon transistor
Definitions
- Embodiments of the present invention relate to a low temperature polysilicon film and a method of fabricating the same, and a thin film transistor and display device using the low temperature polysilicon film. Background technique
- a thin film transistor In a flat display device such as a liquid crystal display (LCD), an organic electroluminescence display, or an inorganic electroluminescence display, a thin film transistor (TFT) is generally used as a switching element to control a pixel or as a driving element to drive Pixel.
- Thin film transistors are generally classified into amorphous silicon (a-Si) and polycrystalline (Poly-Si) thin film transistors according to the silicon thin film shield used as the active layer. Compared with amorphous silicon thin film transistors, polysilicon thin film transistors have higher electron mobility and lower leakage current characteristics, so displays made using polysilicon thin film transistors have higher resolution and faster response speed.
- the preparation process of polysilicon film can be divided into two categories.
- One type is a high temperature process, the temperature during the preparation is higher than 600 ° C, the substrate uses expensive quartz, and the other is a low temperature process.
- the entire processing temperature is lower than 600 ° C, and inexpensive glass can be used as the substrate. Therefore, low temperature polysilicon (LTPS) technology has gradually replaced amorphous silicon technology into the mainstream of thin film transistor research and development.
- LTPS low temperature polysilicon
- the crystallization of polycrystalline silicon has been the focus of research in the field of low temperature polysilicon.
- ELC Excimer Laser Crystallization
- the surface of the a-Si film is brought to a molten state at a high temperature of 1000 ° C or higher, and after cooling of the laser pulse, the amorphous silicon in the molten state is cooled to become polycrystalline silicon.
- the polycrystalline silicon film prepared by ELC has large crystal grains, good spatial selectivity, high doping efficiency, few intragranular defects, and good electrical characteristics.
- the high mobility is the best low-temperature polysilicon film at present.
- the polysilicon film prepared by ELC also has its own disadvantages, that is, the grain size is sensitive to the laser power, and the uniformity of the prepared polysilicon film is poor, so that the performance of products prepared by the polysilicon film (such as thin film transistors) is different. Larger.
- the polysilicon film currently prepared by the ELC technology has poor uniformity, thereby affecting the performance of the product prepared from the polysilicon film.
- At least one embodiment of the present invention provides a low temperature polysilicon film and a method of fabricating the same, a thin film transistor and a display device for solving the problem of poor uniformity of a polycrystalline silicon film prepared by the ELC technique.
- At least one embodiment of the present invention provides a method for preparing a low temperature polysilicon film, comprising: forming a pattern of an amorphous silicon layer on a substrate by a patterning process, wherein the amorphous silicon layer includes a plurality of raised structures and An etched region in which a portion of the plurality of the raised structures is etched away; excimer laser crystallization of the amorphous silicon layer to obtain a low temperature polysilicon film.
- the convex structures serve as nucleation centers in the subsequent crystallization process, and can be used for uniform nucleation, thereby ensuring polysilicon.
- the uniform distribution of grains increases the size of the grains.
- a buffer layer is formed on the substrate, and then the amorphous silicon layer is formed on a buffer layer on the substrate.
- forming a pattern of the amorphous silicon layer on the substrate by a patterning process may include: depositing an amorphous silicon film on the substrate; and selectively selecting the amorphous silicon film Etching, the etched region of the amorphous silicon film forms an etched region of the amorphous silicon layer, and the unetched region of the amorphous silicon film forms a plurality of the amorphous germanium layer Raised structure.
- a plurality of the raised structures are equally spaced apart from the amorphous silicon layer.
- the method may further include: An insulating layer for preventing heat loss on the upper surface of the amorphous silicon layer is deposited on the amorphous silicon layer to further increase the size of the polycrystalline silicon crystal grains.
- the insulating layer is made of a silicon dioxide (Si0 2 ) or a silicon nitride (SiNx) single layer film. Or a composite film of Si0 2 and SiNx.
- At least one embodiment of the present invention also provides a low temperature polysilicon film which is prepared by any of the above methods, wherein the low temperature polysilicon film has a uniform grain distribution and a large size.
- At least one embodiment of the present invention also provides a thin film transistor using the above low temperature polysilicon film, which can be used as an active layer of a thin film transistor.
- At least one embodiment of the present invention also provides a method of fabricating a thin film transistor, which may include: preparing an active layer of the thin film transistor, and preparing the active layer comprises: forming amorphous silicon on a substrate by a patterning process a pattern of a layer, wherein the amorphous silicon layer includes a plurality of raised structures and an etched region where portions of the plurality of the raised structures are etched away; and the amorphous silicon layer is subjected to an excimer laser Crystallization, obtaining a low temperature polysilicon film; forming a pattern of the active layer by the patterning process on the low temperature polysilicon film.
- the method may further include: forming a buffer layer on the substrate; or forming a pattern of the gate on the substrate by a patterning process, and forming the gate On the substrate, a buffer layer is formed.
- a pattern of an amorphous silicon layer on a substrate by a patterning process comprising: depositing an amorphous silicon film on the substrate; selectively etching the amorphous silicon film, the amorphous The etched region of the silicon film forms an etched region of the amorphous silicon layer, and the unetched region of the amorphous silicon film forms a plurality of raised structures of the amorphous silicon layer.
- a plurality of the raised structures are equally spaced apart from the amorphous silicon layer.
- the method may further include: depositing a layer on the amorphous silicon layer
- the layer is an insulating layer for preventing heat loss on the upper surface of the amorphous silicon layer.
- the method may further include: removing the insulating layer on the low temperature polysilicon film.
- At least one embodiment of the present invention also provides a display device including the above thin film transistor.
- the thin film transistor can be used as a switching element to control a pixel or as a driving element to drive a pixel.
- FIG. 1 is a schematic view showing a preparation method of a low-temperature polysilicon film according to an embodiment of the present invention
- FIG. 2 is a schematic view showing a preparation process of an embodiment of the present invention
- FIG. 3 is a schematic cross-sectional structural view of a buffer layer after depositing a layer according to an embodiment of the present invention
- FIG. 4 is a schematic cross-sectional structural view of an amorphous silicon film deposited in an embodiment of the present invention.
- 5A is a schematic cross-sectional structural view of an amorphous silicon layer formed in an embodiment of the present invention.
- 5B is a schematic top plan view of an amorphous silicon layer formed in an embodiment of the present invention.
- FIG. 6 is a schematic cross-sectional structural view of the embodiment of the present invention after depositing an insulating layer. detailed description
- the amorphous silicon layer formed on the substrate includes a plurality of raised structures, and the plurality of raised structures may serve as a nucleation center during the crystallization of the amorphous silicon layer.
- the plurality of raised structures may serve as a nucleation center during the crystallization of the amorphous silicon layer.
- At least one embodiment of the present invention provides a method of preparing a low temperature polysilicon film, the method comprising the steps of:
- Step 11 Form a buffer layer on the substrate to prevent impurities on the substrate from entering the amorphous silicon layer and affecting the performance of the amorphous silicon layer.
- a buffer film may be deposited on the substrate by chemical vapor deposition (CVD) to form a buffer layer.
- CVD chemical vapor deposition
- a buffer layer film is deposited on the substrate by a Plasma Enhanced Chemical Vapor Deposition (PECVD) method to form a buffer layer.
- PECVD Plasma Enhanced Chemical Vapor Deposition
- the buffer layer may be a single layer film using silicon dioxide (Si ⁇ 2 ) or silicon nitride (SiNx ), or a composite layer film of Si 2 2 and SiN 2 .
- the buffer layer formed in this step has a thickness of 2000 ⁇ to 4000 ⁇ .
- the thickness of the buffer layer can also be set to other values according to actual preparation requirements.
- the buffer layer may comprise at least one layer, for example a composite layer which may be composed of layers of different materials.
- the substrate may be cleaned beforehand to keep the substrate clean.
- a substrate such as an alkali-free glass substrate, a resin substrate, or a quartz substrate can be used as the substrate.
- a buffer layer is not formed on the substrate, but a subsequent step of forming an amorphous silicon layer is performed directly on the substrate.
- Step 12 forming an amorphous silicon layer on the buffer layer of the substrate by a patterning process, the amorphous silicon layer comprising a plurality of convex structures and an etched region where portions of the plurality of raised structures are etched away .
- an amorphous silicon layer is formed on the buffer layer of the substrate by a patterning process, and the formed amorphous silicon layer includes a plurality of convex structures and portions of the plurality of raised structures are etched away Etched area.
- a photolithographic method may be used to protect an amorphous silicon thin film region that needs to form a convex structure, and other regions are etched (ie, an etched region), and finally the protected region forms a plurality of convex structures uniformly distributed.
- These raised structures act as nucleation centers in the subsequent crystallization process and can be used for uniform nucleation, thereby ensuring uniform distribution of polycrystalline silicon grains.
- the plurality of convex structures formed are equally spaced so that the amorphous silicon layer exhibits a uniform distribution of hill topography, and further Ensure uniform distribution of crystal grains.
- the patterning process is, for example, a photolithographic patterning process, comprising: coating a photoresist layer, exposing the photoresist layer using a mask, and developing the exposed photoresist layer to A photoresist pattern is obtained, the structure layer is etched using a photoresist pattern, and then the photoresist pattern is optionally removed.
- the process for forming the photoresist pattern may also be a screen printing, an inkjet printing method, or the like.
- Step 13 Perform an excimer laser crystallization on the amorphous silicon layer formed in the step 12 to obtain a low temperature polysilicon film.
- the size of the crystal grains of the low-temperature polysilicon film obtained by the manufacturing method known to the inventors is generally about 400 nm, and the size of the crystal grains obtained by using the low-temperature polysilicon film of at least one embodiment of the present invention can at least reach 600 nm ⁇ 1000 nm, increasing the size of the grains.
- the amorphous silicon layer when the formed amorphous silicon layer is subjected to excimer laser crystallization, the amorphous silicon layer may be selected once, twice or twice according to characteristics such as thickness and material of the amorphous silicon layer. More excimer laser annealing is performed to form a polysilicon film.
- the amorphous silicon layer formed is subjected to one-time excimer laser annealing, and the process parameters include: the laser pulse frequency is 500 Hz, and the laser energy density used is 350-450 mJ/cm 2 .
- an example of forming an amorphous silicon layer on a buffer layer of a substrate by a patterning process includes: depositing an amorphous silicon (a-Si) film on a buffer layer of the substrate; and on amorphous silicon The film is selectively etched.
- the etched region of the amorphous silicon film forms an etched region of the amorphous silicon layer, and the unetched region of the amorphous silicon film forms a plurality of raised structures of the amorphous silicon layer.
- a thin film of amorphous silicon is deposited on the buffer layer of the substrate by CVD.
- a layer of amorphous silicon film is deposited on the buffer layer of the substrate by PECVD.
- the thickness of the amorphous silicon film deposited on the buffer layer of the substrate is 400 ⁇ to 800 ⁇ .
- the thickness of the amorphous silicon film can also be set to other values depending on the actual preparation needs (e.g., the thickness of the active layer of the thin film transistor to be prepared).
- the partially etched etched region has a thickness of 200 angstroms to 600 angstroms, and the unetched regions form a plurality of raised structures, each of which The height of the raised structures relative to the partially etched regions is from 100 angstroms to 200 angstroms, and the spacing between any adjacent two raised structures is from 1000 nanometers to 2,000 nanometers.
- the thickness of the etched region, the height of the raised structure, and the pitch of the adjacent two raised structures may also be set to other values according to actual fabrication requirements (such as the size of the grain of the low temperature polysilicon film to be prepared).
- the number of raised structures in the polysilicon layer can be determined based on the size of the substrate and the spacing between any adjacent two raised structures that are set.
- the shape of the raised structure formed by the amorphous silicon layer is not limited.
- the convex structure formed by the amorphous silicon layer of some embodiments of the present invention adopts a cylindrical structure, and the convex structure has a diameter of 200 ⁇ to 300 ⁇ .
- the diameter of the raised structure can also be set to other values according to actual preparation requirements.
- the raised features may also utilize other shapes, such as prisms or the like.
- the method of some embodiments of the present invention further includes the following steps: for example, using PECVD, depositing a layer on the amorphous silicon layer of the substrate to prevent the amorphous The heat insulating layer on the upper surface of the silicon layer is dissipated to further increase the grain size of the obtained polycrystalline silicon.
- a thermal insulation layer is deposited on the amorphous silicon layer, and during the crystallization of the amorphous silicon layer, heat dissipation on the upper surface of the amorphous silicon layer can be prevented, thereby reducing the upper and lower layers of the amorphous silicon layer.
- the difference in temperature further increases the grain size of the polysilicon.
- a layer of thermal insulation layer can be deposited on the amorphous silicon layer by PECVD, and the deposited thermal insulation layer has good uniformity and high stability, and can ensure further increase of grain size after crystallization.
- the thickness of the insulating layer may range from 1000 angstroms to 2000 angstroms.
- the thickness of the insulation layer can also be set to other values according to actual preparation requirements.
- the insulating layer may be a Si0 2 or SiNx single-layer film, or a composite film of Si0 2 and SiNx may be used.
- a method of preparing a low temperature polysilicon film will be described in detail below in conjunction with a preferred embodiment.
- a glass substrate is used as the substrate, and the preparation process thereof is shown in FIG. 2, and includes the following steps.
- Step 21 depositing a buffer layer S2 on the glass substrate S1, the cross-sectional structure of which is shown in FIG. 3; the buffer layer S2 is made of a SiO 2 film having a thickness of 2000 to 4000 angstroms (person).
- Step 22 depositing an amorphous silicon (a-Si) film S3 on the buffer layer, and the cross-sectional structure thereof is shown in FIG. 4; the amorphous silicon film has a thickness of 400 to 800 persons.
- a-Si amorphous silicon
- Step 23 selectively etching the amorphous silicon film S3 by a patterning process to form an amorphous silicon layer.
- the cross-sectional structure is shown in FIG. 5A, and the etched region of the amorphous silicon film S3 is formed.
- the thickness of the thicker film layer in the amorphous silicon layer is 400-800, and the thickness of the partially etched etched region S31 after etching is 200-600, which is formed in the etched region S31.
- the columnar convex structure S32 has a diameter of 200 to 300 persons, and the height of the partially etched portion is 100 to 200 persons, and the distribution pitch of any adjacent two convex structures S32 is 1000 to 2000 nm. (nm), its top view structure is shown in Figure 5B.
- the amorphous silicon layer is formed by a selective etching method, and includes a plurality of equally spaced columnar protrusion structures and etched regions around the protrusion structures to realize the protrusion structures. Incomplete melting state during crystallization, thereby achieving uniform nucleation, uniform distribution of prepared polycrystalline silicon grains, and increased grain size.
- Step 24 On the amorphous silicon layer formed after the etching, a layer of the temperature-preserving layer S4 is deposited by PECVD, and the cross-sectional structure thereof is shown in FIG. 6.
- the thickness of the insulating layer S4 is 1000 to 2000. Since the insulating layer S4 can prevent heat loss on the surface of the amorphous silicon layer, the crystal grain size after crystallization can be further increased.
- the insulating layer S4 may be a SiO 2 or SiNx single layer film, or a composite layer film of Si ⁇ 2 and SiNx may be used. In other embodiments of the invention, no insulating layer is formed on the amorphous silicon layer.
- Step 25 performing ELC on the amorphous silicon layer on the glass substrate S1 to obtain a low-temperature polysilicon film; for example, in the case of a laser pulse frequency of 500 Hz, the laser energy density used is 350-450 mJ/cm 2 , for the glass substrate S The amorphous silicon layer on 1 is crystallized.
- Another embodiment of the present invention also provides a low temperature polysilicon film which is prepared by any of the above methods, wherein the low temperature polysilicon film has a uniform grain distribution and a large size.
- Another embodiment of the present invention also provides a thin film transistor using the above low temperature polysilicon film which can be used as an active layer of a thin film transistor.
- the embodiment of the present invention does not limit other structures of the thin film transistor (such as the gate, the gate insulating layer, the source and the drain, etc.), as long as the active layer of the thin film transistor is fabricated by using the low temperature polysilicon film provided by the embodiment of the present invention.
- the thin film transistor of some embodiments of the present invention may be, for example, a top gate type (the gate is above the active layer) or a bottom gate type (the gate is under the active layer, between the active layer and the substrate),
- the gate and the active layer are provided with a gate insulating layer, and the source and drain are in contact with the source and drain regions of the active layer.
- Some embodiments of the present invention also provide a method of fabricating a thin film transistor, the method comprising A gate of a thin film transistor, a gate insulating layer, an active layer, a source and drain, and the like are prepared.
- the method for fabricating an active layer of the thin film transistor includes: forming a pattern of an amorphous silicon layer on a substrate on which a buffer layer is formed by a patterning process, wherein the amorphous silicon layer includes a plurality of convex structures and is located at a plurality An etched region in which a portion of the raised structure is etched away; excimer laser crystallization of the amorphous silicon layer to obtain a low temperature polysilicon film; and forming a active layer by patterning the low temperature polysilicon film Graphics.
- the active layer of the thin film transistor is fabricated by using a low temperature polysilicon film, and the other structures of the thin film transistor are not limited, as long as the active layer uses the low temperature polysilicon provided by the embodiment of the present invention.
- the fabrication method of the thin film fabrication thin film transistor is encompassed in the embodiment of the present invention.
- the buffer layer may be a single layer film using silicon dioxide (sio 2 ) or silicon nitride (Si), or a composite layer film of SiO 2 and SiNx.
- the buffer layer formed on the substrate has a thickness of 2000 ⁇ to 4000 ⁇ .
- the thickness of the buffer layer can also be set to other values according to the actual preparation needs.
- the thin film transistor may be fabricated by first forming an active layer and then forming a gate.
- the method before forming the pattern of the amorphous silicon layer, the method further includes: on the substrate A buffer layer is formed.
- a buffer film can be deposited on the substrate by CVD to form a buffer layer.
- a buffer film is deposited on a substrate by a PECVD method to form a buffer layer.
- the thin film transistor may be fabricated by first forming a gate electrode and then forming an active layer.
- the method before forming the pattern of the amorphous silicon layer, the method further includes: a process of forming a pattern of a gate on a substrate; and forming a buffer layer on the substrate on which the gate is formed. In this manner, the buffer layer is the gate insulating layer of the thin film transistor.
- forming a pattern of the amorphous silicon layer on the substrate on which the buffer layer is formed by a patterning process may include: depositing an amorphous silicon film on the substrate on which the buffer layer is formed; The silicon film is selectively etched, wherein the etched region of the amorphous silicon film forms an etched region of the amorphous silicon layer, and the unetched region of the crystalline silicon film forms the amorphous A plurality of raised structures of the silicon layer.
- a plurality of raised structures are equally spaced apart from the amorphous silicon layer.
- the method may further include: using PECVD, in the non- An insulating layer for preventing heat loss on the upper surface of the amorphous silicon layer is deposited on the crystalline silicon layer.
- a thermal insulation layer is deposited on the amorphous silicon layer, and during the crystallization of the amorphous silicon layer, heat dissipation on the upper surface of the amorphous silicon layer can be prevented, thereby reducing the upper and lower layers of the amorphous silicon layer.
- the difference in temperature further increases the grain size of the polysilicon.
- the thickness of the insulating layer may range from 1000 angstroms to 2000 angstroms.
- the thickness of the insulation layer can also be set to other values according to actual preparation requirements.
- the insulating layer may be a Si0 2 or SiNx single-layer film, or a composite film of Si0 2 and SiNx may be used.
- the method may further include: removing the thermal insulation layer on the low temperature polysilicon film.
- a low temperature polysilicon film is formed, and the insulating layer on the low temperature polysilicon film can be removed by a dry etching process.
- the insulating layer on the low temperature polysilicon film is removed.
- Still another embodiment of the present invention also provides a display device including the above-described thin film transistor.
- the thin film transistor can be used as a switching element to control a pixel or as a driving element to drive a pixel.
- the display device may be: a liquid crystal display panel, an electronic paper, an Organic Light Emitting Diode (OLED) panel, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, and a navigation device. Any product or part that has a display function.
- OLED Organic Light Emitting Diode
- the display device is suitable for various types of displays such as a liquid crystal display, an organic electroluminescence display, an electroless display, an active matrix organic light emitting diode display (AMOLED).
- a liquid crystal display an organic electroluminescence display, an electroless display, an active matrix organic light emitting diode display (AMOLED).
- AMOLED active matrix organic light emitting diode display
- An example of the display device is a liquid crystal display device in which an array substrate and a counter substrate are opposed to each other to form a liquid crystal cell, and the liquid crystal cell is filled with a liquid crystal material.
- the opposite substrate is, for example, a color filter substrate.
- the liquid crystal display device further includes a backlight.
- the array substrate includes a plurality of gate lines and a plurality of data lines, the gate lines and the data lines crossing each other thereby defining pixel units arranged in a matrix,
- Each of the pixel units includes a thin film transistor as a switching element, which is, for example, a thin film transistor of an embodiment of the present invention.
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Abstract
Description
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EP3336897B1 (en) * | 2015-08-03 | 2021-10-06 | BOE Technology Group Co., Ltd. | Method of manufacturing thin film transistor |
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CN103681776B (zh) * | 2013-12-24 | 2017-11-07 | 京东方科技集团股份有限公司 | 低温多晶硅薄膜及其制备方法、薄膜晶体管和显示装置 |
CN104037127A (zh) * | 2014-06-11 | 2014-09-10 | 京东方科技集团股份有限公司 | 一种多晶硅层及显示基板的制备方法、显示基板 |
CN104078621B (zh) * | 2014-06-20 | 2016-09-07 | 京东方科技集团股份有限公司 | 低温多晶硅薄膜晶体管、其制备方法及阵列基板与显示装置 |
CN104064451A (zh) * | 2014-07-10 | 2014-09-24 | 深圳市华星光电技术有限公司 | 低温多晶硅的制作方法及使用该方法的tft基板的制作方法与tft基板结构 |
CN104409510A (zh) * | 2014-10-28 | 2015-03-11 | 京东方科技集团股份有限公司 | 薄膜晶体管及制备方法、阵列基板及制备方法、显示装置 |
CN104658891B (zh) | 2015-03-03 | 2019-03-15 | 京东方科技集团股份有限公司 | 低温多晶硅薄膜的制备方法、薄膜晶体管及显示装置 |
CN104900532B (zh) | 2015-06-15 | 2018-10-02 | 京东方科技集团股份有限公司 | 一种薄膜晶体管及其制备方法、阵列基板、显示装置 |
CN105633076A (zh) * | 2016-01-04 | 2016-06-01 | 京东方科技集团股份有限公司 | 一种显示基板及其制作方法和显示装置 |
CN105957805B (zh) * | 2016-06-29 | 2018-12-18 | 京东方科技集团股份有限公司 | 低温多晶硅薄膜制作方法、薄膜晶体管、阵列基板和显示装置 |
CN107919268B (zh) * | 2017-10-12 | 2020-10-09 | 惠科股份有限公司 | 低温多晶硅薄膜及晶体管的制造方法 |
CN109638174B (zh) * | 2018-11-13 | 2021-02-26 | 武汉华星光电半导体显示技术有限公司 | Oled显示面板及其制作方法 |
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US9559159B2 (en) | 2017-01-31 |
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