WO2015096320A1 - 低温多晶硅薄膜及其制备方法、薄膜晶体管和显示装置 - Google Patents

低温多晶硅薄膜及其制备方法、薄膜晶体管和显示装置 Download PDF

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WO2015096320A1
WO2015096320A1 PCT/CN2014/076046 CN2014076046W WO2015096320A1 WO 2015096320 A1 WO2015096320 A1 WO 2015096320A1 CN 2014076046 W CN2014076046 W CN 2014076046W WO 2015096320 A1 WO2015096320 A1 WO 2015096320A1
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amorphous silicon
layer
silicon layer
substrate
film
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PCT/CN2014/076046
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French (fr)
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张慧娟
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京东方科技集团股份有限公司
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Priority to US14/421,955 priority Critical patent/US9559159B2/en
Publication of WO2015096320A1 publication Critical patent/WO2015096320A1/zh

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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/04—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes
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    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
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    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
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    • H01L21/02494—Structure
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    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
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    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02664—Aftertreatments
    • H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
    • H01L21/02675—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth using laser beams
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    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02664—Aftertreatments
    • H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
    • H01L21/02675—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth using laser beams
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    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
    • H01L27/1274—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement using crystallisation of amorphous semiconductor or recrystallisation of crystalline semiconductor
    • H01L27/1281—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement using crystallisation of amorphous semiconductor or recrystallisation of crystalline semiconductor by using structural features to control crystal growth, e.g. placement of grain filters
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    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
    • H01L27/1274—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement using crystallisation of amorphous semiconductor or recrystallisation of crystalline semiconductor
    • H01L27/1285—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement using crystallisation of amorphous semiconductor or recrystallisation of crystalline semiconductor using control of the annealing or irradiation parameters, e.g. using different scanning direction or intensity for different transistors
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/6675—Amorphous silicon or polysilicon transistors
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651—Silicon transistors
    • H01L29/7866—Non-monocrystalline silicon transistors
    • H01L29/78672—Polycrystalline or microcrystalline silicon transistor

Definitions

  • Embodiments of the present invention relate to a low temperature polysilicon film and a method of fabricating the same, and a thin film transistor and display device using the low temperature polysilicon film. Background technique
  • a thin film transistor In a flat display device such as a liquid crystal display (LCD), an organic electroluminescence display, or an inorganic electroluminescence display, a thin film transistor (TFT) is generally used as a switching element to control a pixel or as a driving element to drive Pixel.
  • Thin film transistors are generally classified into amorphous silicon (a-Si) and polycrystalline (Poly-Si) thin film transistors according to the silicon thin film shield used as the active layer. Compared with amorphous silicon thin film transistors, polysilicon thin film transistors have higher electron mobility and lower leakage current characteristics, so displays made using polysilicon thin film transistors have higher resolution and faster response speed.
  • the preparation process of polysilicon film can be divided into two categories.
  • One type is a high temperature process, the temperature during the preparation is higher than 600 ° C, the substrate uses expensive quartz, and the other is a low temperature process.
  • the entire processing temperature is lower than 600 ° C, and inexpensive glass can be used as the substrate. Therefore, low temperature polysilicon (LTPS) technology has gradually replaced amorphous silicon technology into the mainstream of thin film transistor research and development.
  • LTPS low temperature polysilicon
  • the crystallization of polycrystalline silicon has been the focus of research in the field of low temperature polysilicon.
  • ELC Excimer Laser Crystallization
  • the surface of the a-Si film is brought to a molten state at a high temperature of 1000 ° C or higher, and after cooling of the laser pulse, the amorphous silicon in the molten state is cooled to become polycrystalline silicon.
  • the polycrystalline silicon film prepared by ELC has large crystal grains, good spatial selectivity, high doping efficiency, few intragranular defects, and good electrical characteristics.
  • the high mobility is the best low-temperature polysilicon film at present.
  • the polysilicon film prepared by ELC also has its own disadvantages, that is, the grain size is sensitive to the laser power, and the uniformity of the prepared polysilicon film is poor, so that the performance of products prepared by the polysilicon film (such as thin film transistors) is different. Larger.
  • the polysilicon film currently prepared by the ELC technology has poor uniformity, thereby affecting the performance of the product prepared from the polysilicon film.
  • At least one embodiment of the present invention provides a low temperature polysilicon film and a method of fabricating the same, a thin film transistor and a display device for solving the problem of poor uniformity of a polycrystalline silicon film prepared by the ELC technique.
  • At least one embodiment of the present invention provides a method for preparing a low temperature polysilicon film, comprising: forming a pattern of an amorphous silicon layer on a substrate by a patterning process, wherein the amorphous silicon layer includes a plurality of raised structures and An etched region in which a portion of the plurality of the raised structures is etched away; excimer laser crystallization of the amorphous silicon layer to obtain a low temperature polysilicon film.
  • the convex structures serve as nucleation centers in the subsequent crystallization process, and can be used for uniform nucleation, thereby ensuring polysilicon.
  • the uniform distribution of grains increases the size of the grains.
  • a buffer layer is formed on the substrate, and then the amorphous silicon layer is formed on a buffer layer on the substrate.
  • forming a pattern of the amorphous silicon layer on the substrate by a patterning process may include: depositing an amorphous silicon film on the substrate; and selectively selecting the amorphous silicon film Etching, the etched region of the amorphous silicon film forms an etched region of the amorphous silicon layer, and the unetched region of the amorphous silicon film forms a plurality of the amorphous germanium layer Raised structure.
  • a plurality of the raised structures are equally spaced apart from the amorphous silicon layer.
  • the method may further include: An insulating layer for preventing heat loss on the upper surface of the amorphous silicon layer is deposited on the amorphous silicon layer to further increase the size of the polycrystalline silicon crystal grains.
  • the insulating layer is made of a silicon dioxide (Si0 2 ) or a silicon nitride (SiNx) single layer film. Or a composite film of Si0 2 and SiNx.
  • At least one embodiment of the present invention also provides a low temperature polysilicon film which is prepared by any of the above methods, wherein the low temperature polysilicon film has a uniform grain distribution and a large size.
  • At least one embodiment of the present invention also provides a thin film transistor using the above low temperature polysilicon film, which can be used as an active layer of a thin film transistor.
  • At least one embodiment of the present invention also provides a method of fabricating a thin film transistor, which may include: preparing an active layer of the thin film transistor, and preparing the active layer comprises: forming amorphous silicon on a substrate by a patterning process a pattern of a layer, wherein the amorphous silicon layer includes a plurality of raised structures and an etched region where portions of the plurality of the raised structures are etched away; and the amorphous silicon layer is subjected to an excimer laser Crystallization, obtaining a low temperature polysilicon film; forming a pattern of the active layer by the patterning process on the low temperature polysilicon film.
  • the method may further include: forming a buffer layer on the substrate; or forming a pattern of the gate on the substrate by a patterning process, and forming the gate On the substrate, a buffer layer is formed.
  • a pattern of an amorphous silicon layer on a substrate by a patterning process comprising: depositing an amorphous silicon film on the substrate; selectively etching the amorphous silicon film, the amorphous The etched region of the silicon film forms an etched region of the amorphous silicon layer, and the unetched region of the amorphous silicon film forms a plurality of raised structures of the amorphous silicon layer.
  • a plurality of the raised structures are equally spaced apart from the amorphous silicon layer.
  • the method may further include: depositing a layer on the amorphous silicon layer
  • the layer is an insulating layer for preventing heat loss on the upper surface of the amorphous silicon layer.
  • the method may further include: removing the insulating layer on the low temperature polysilicon film.
  • At least one embodiment of the present invention also provides a display device including the above thin film transistor.
  • the thin film transistor can be used as a switching element to control a pixel or as a driving element to drive a pixel.
  • FIG. 1 is a schematic view showing a preparation method of a low-temperature polysilicon film according to an embodiment of the present invention
  • FIG. 2 is a schematic view showing a preparation process of an embodiment of the present invention
  • FIG. 3 is a schematic cross-sectional structural view of a buffer layer after depositing a layer according to an embodiment of the present invention
  • FIG. 4 is a schematic cross-sectional structural view of an amorphous silicon film deposited in an embodiment of the present invention.
  • 5A is a schematic cross-sectional structural view of an amorphous silicon layer formed in an embodiment of the present invention.
  • 5B is a schematic top plan view of an amorphous silicon layer formed in an embodiment of the present invention.
  • FIG. 6 is a schematic cross-sectional structural view of the embodiment of the present invention after depositing an insulating layer. detailed description
  • the amorphous silicon layer formed on the substrate includes a plurality of raised structures, and the plurality of raised structures may serve as a nucleation center during the crystallization of the amorphous silicon layer.
  • the plurality of raised structures may serve as a nucleation center during the crystallization of the amorphous silicon layer.
  • At least one embodiment of the present invention provides a method of preparing a low temperature polysilicon film, the method comprising the steps of:
  • Step 11 Form a buffer layer on the substrate to prevent impurities on the substrate from entering the amorphous silicon layer and affecting the performance of the amorphous silicon layer.
  • a buffer film may be deposited on the substrate by chemical vapor deposition (CVD) to form a buffer layer.
  • CVD chemical vapor deposition
  • a buffer layer film is deposited on the substrate by a Plasma Enhanced Chemical Vapor Deposition (PECVD) method to form a buffer layer.
  • PECVD Plasma Enhanced Chemical Vapor Deposition
  • the buffer layer may be a single layer film using silicon dioxide (Si ⁇ 2 ) or silicon nitride (SiNx ), or a composite layer film of Si 2 2 and SiN 2 .
  • the buffer layer formed in this step has a thickness of 2000 ⁇ to 4000 ⁇ .
  • the thickness of the buffer layer can also be set to other values according to actual preparation requirements.
  • the buffer layer may comprise at least one layer, for example a composite layer which may be composed of layers of different materials.
  • the substrate may be cleaned beforehand to keep the substrate clean.
  • a substrate such as an alkali-free glass substrate, a resin substrate, or a quartz substrate can be used as the substrate.
  • a buffer layer is not formed on the substrate, but a subsequent step of forming an amorphous silicon layer is performed directly on the substrate.
  • Step 12 forming an amorphous silicon layer on the buffer layer of the substrate by a patterning process, the amorphous silicon layer comprising a plurality of convex structures and an etched region where portions of the plurality of raised structures are etched away .
  • an amorphous silicon layer is formed on the buffer layer of the substrate by a patterning process, and the formed amorphous silicon layer includes a plurality of convex structures and portions of the plurality of raised structures are etched away Etched area.
  • a photolithographic method may be used to protect an amorphous silicon thin film region that needs to form a convex structure, and other regions are etched (ie, an etched region), and finally the protected region forms a plurality of convex structures uniformly distributed.
  • These raised structures act as nucleation centers in the subsequent crystallization process and can be used for uniform nucleation, thereby ensuring uniform distribution of polycrystalline silicon grains.
  • the plurality of convex structures formed are equally spaced so that the amorphous silicon layer exhibits a uniform distribution of hill topography, and further Ensure uniform distribution of crystal grains.
  • the patterning process is, for example, a photolithographic patterning process, comprising: coating a photoresist layer, exposing the photoresist layer using a mask, and developing the exposed photoresist layer to A photoresist pattern is obtained, the structure layer is etched using a photoresist pattern, and then the photoresist pattern is optionally removed.
  • the process for forming the photoresist pattern may also be a screen printing, an inkjet printing method, or the like.
  • Step 13 Perform an excimer laser crystallization on the amorphous silicon layer formed in the step 12 to obtain a low temperature polysilicon film.
  • the size of the crystal grains of the low-temperature polysilicon film obtained by the manufacturing method known to the inventors is generally about 400 nm, and the size of the crystal grains obtained by using the low-temperature polysilicon film of at least one embodiment of the present invention can at least reach 600 nm ⁇ 1000 nm, increasing the size of the grains.
  • the amorphous silicon layer when the formed amorphous silicon layer is subjected to excimer laser crystallization, the amorphous silicon layer may be selected once, twice or twice according to characteristics such as thickness and material of the amorphous silicon layer. More excimer laser annealing is performed to form a polysilicon film.
  • the amorphous silicon layer formed is subjected to one-time excimer laser annealing, and the process parameters include: the laser pulse frequency is 500 Hz, and the laser energy density used is 350-450 mJ/cm 2 .
  • an example of forming an amorphous silicon layer on a buffer layer of a substrate by a patterning process includes: depositing an amorphous silicon (a-Si) film on a buffer layer of the substrate; and on amorphous silicon The film is selectively etched.
  • the etched region of the amorphous silicon film forms an etched region of the amorphous silicon layer, and the unetched region of the amorphous silicon film forms a plurality of raised structures of the amorphous silicon layer.
  • a thin film of amorphous silicon is deposited on the buffer layer of the substrate by CVD.
  • a layer of amorphous silicon film is deposited on the buffer layer of the substrate by PECVD.
  • the thickness of the amorphous silicon film deposited on the buffer layer of the substrate is 400 ⁇ to 800 ⁇ .
  • the thickness of the amorphous silicon film can also be set to other values depending on the actual preparation needs (e.g., the thickness of the active layer of the thin film transistor to be prepared).
  • the partially etched etched region has a thickness of 200 angstroms to 600 angstroms, and the unetched regions form a plurality of raised structures, each of which The height of the raised structures relative to the partially etched regions is from 100 angstroms to 200 angstroms, and the spacing between any adjacent two raised structures is from 1000 nanometers to 2,000 nanometers.
  • the thickness of the etched region, the height of the raised structure, and the pitch of the adjacent two raised structures may also be set to other values according to actual fabrication requirements (such as the size of the grain of the low temperature polysilicon film to be prepared).
  • the number of raised structures in the polysilicon layer can be determined based on the size of the substrate and the spacing between any adjacent two raised structures that are set.
  • the shape of the raised structure formed by the amorphous silicon layer is not limited.
  • the convex structure formed by the amorphous silicon layer of some embodiments of the present invention adopts a cylindrical structure, and the convex structure has a diameter of 200 ⁇ to 300 ⁇ .
  • the diameter of the raised structure can also be set to other values according to actual preparation requirements.
  • the raised features may also utilize other shapes, such as prisms or the like.
  • the method of some embodiments of the present invention further includes the following steps: for example, using PECVD, depositing a layer on the amorphous silicon layer of the substrate to prevent the amorphous The heat insulating layer on the upper surface of the silicon layer is dissipated to further increase the grain size of the obtained polycrystalline silicon.
  • a thermal insulation layer is deposited on the amorphous silicon layer, and during the crystallization of the amorphous silicon layer, heat dissipation on the upper surface of the amorphous silicon layer can be prevented, thereby reducing the upper and lower layers of the amorphous silicon layer.
  • the difference in temperature further increases the grain size of the polysilicon.
  • a layer of thermal insulation layer can be deposited on the amorphous silicon layer by PECVD, and the deposited thermal insulation layer has good uniformity and high stability, and can ensure further increase of grain size after crystallization.
  • the thickness of the insulating layer may range from 1000 angstroms to 2000 angstroms.
  • the thickness of the insulation layer can also be set to other values according to actual preparation requirements.
  • the insulating layer may be a Si0 2 or SiNx single-layer film, or a composite film of Si0 2 and SiNx may be used.
  • a method of preparing a low temperature polysilicon film will be described in detail below in conjunction with a preferred embodiment.
  • a glass substrate is used as the substrate, and the preparation process thereof is shown in FIG. 2, and includes the following steps.
  • Step 21 depositing a buffer layer S2 on the glass substrate S1, the cross-sectional structure of which is shown in FIG. 3; the buffer layer S2 is made of a SiO 2 film having a thickness of 2000 to 4000 angstroms (person).
  • Step 22 depositing an amorphous silicon (a-Si) film S3 on the buffer layer, and the cross-sectional structure thereof is shown in FIG. 4; the amorphous silicon film has a thickness of 400 to 800 persons.
  • a-Si amorphous silicon
  • Step 23 selectively etching the amorphous silicon film S3 by a patterning process to form an amorphous silicon layer.
  • the cross-sectional structure is shown in FIG. 5A, and the etched region of the amorphous silicon film S3 is formed.
  • the thickness of the thicker film layer in the amorphous silicon layer is 400-800, and the thickness of the partially etched etched region S31 after etching is 200-600, which is formed in the etched region S31.
  • the columnar convex structure S32 has a diameter of 200 to 300 persons, and the height of the partially etched portion is 100 to 200 persons, and the distribution pitch of any adjacent two convex structures S32 is 1000 to 2000 nm. (nm), its top view structure is shown in Figure 5B.
  • the amorphous silicon layer is formed by a selective etching method, and includes a plurality of equally spaced columnar protrusion structures and etched regions around the protrusion structures to realize the protrusion structures. Incomplete melting state during crystallization, thereby achieving uniform nucleation, uniform distribution of prepared polycrystalline silicon grains, and increased grain size.
  • Step 24 On the amorphous silicon layer formed after the etching, a layer of the temperature-preserving layer S4 is deposited by PECVD, and the cross-sectional structure thereof is shown in FIG. 6.
  • the thickness of the insulating layer S4 is 1000 to 2000. Since the insulating layer S4 can prevent heat loss on the surface of the amorphous silicon layer, the crystal grain size after crystallization can be further increased.
  • the insulating layer S4 may be a SiO 2 or SiNx single layer film, or a composite layer film of Si ⁇ 2 and SiNx may be used. In other embodiments of the invention, no insulating layer is formed on the amorphous silicon layer.
  • Step 25 performing ELC on the amorphous silicon layer on the glass substrate S1 to obtain a low-temperature polysilicon film; for example, in the case of a laser pulse frequency of 500 Hz, the laser energy density used is 350-450 mJ/cm 2 , for the glass substrate S The amorphous silicon layer on 1 is crystallized.
  • Another embodiment of the present invention also provides a low temperature polysilicon film which is prepared by any of the above methods, wherein the low temperature polysilicon film has a uniform grain distribution and a large size.
  • Another embodiment of the present invention also provides a thin film transistor using the above low temperature polysilicon film which can be used as an active layer of a thin film transistor.
  • the embodiment of the present invention does not limit other structures of the thin film transistor (such as the gate, the gate insulating layer, the source and the drain, etc.), as long as the active layer of the thin film transistor is fabricated by using the low temperature polysilicon film provided by the embodiment of the present invention.
  • the thin film transistor of some embodiments of the present invention may be, for example, a top gate type (the gate is above the active layer) or a bottom gate type (the gate is under the active layer, between the active layer and the substrate),
  • the gate and the active layer are provided with a gate insulating layer, and the source and drain are in contact with the source and drain regions of the active layer.
  • Some embodiments of the present invention also provide a method of fabricating a thin film transistor, the method comprising A gate of a thin film transistor, a gate insulating layer, an active layer, a source and drain, and the like are prepared.
  • the method for fabricating an active layer of the thin film transistor includes: forming a pattern of an amorphous silicon layer on a substrate on which a buffer layer is formed by a patterning process, wherein the amorphous silicon layer includes a plurality of convex structures and is located at a plurality An etched region in which a portion of the raised structure is etched away; excimer laser crystallization of the amorphous silicon layer to obtain a low temperature polysilicon film; and forming a active layer by patterning the low temperature polysilicon film Graphics.
  • the active layer of the thin film transistor is fabricated by using a low temperature polysilicon film, and the other structures of the thin film transistor are not limited, as long as the active layer uses the low temperature polysilicon provided by the embodiment of the present invention.
  • the fabrication method of the thin film fabrication thin film transistor is encompassed in the embodiment of the present invention.
  • the buffer layer may be a single layer film using silicon dioxide (sio 2 ) or silicon nitride (Si), or a composite layer film of SiO 2 and SiNx.
  • the buffer layer formed on the substrate has a thickness of 2000 ⁇ to 4000 ⁇ .
  • the thickness of the buffer layer can also be set to other values according to the actual preparation needs.
  • the thin film transistor may be fabricated by first forming an active layer and then forming a gate.
  • the method before forming the pattern of the amorphous silicon layer, the method further includes: on the substrate A buffer layer is formed.
  • a buffer film can be deposited on the substrate by CVD to form a buffer layer.
  • a buffer film is deposited on a substrate by a PECVD method to form a buffer layer.
  • the thin film transistor may be fabricated by first forming a gate electrode and then forming an active layer.
  • the method before forming the pattern of the amorphous silicon layer, the method further includes: a process of forming a pattern of a gate on a substrate; and forming a buffer layer on the substrate on which the gate is formed. In this manner, the buffer layer is the gate insulating layer of the thin film transistor.
  • forming a pattern of the amorphous silicon layer on the substrate on which the buffer layer is formed by a patterning process may include: depositing an amorphous silicon film on the substrate on which the buffer layer is formed; The silicon film is selectively etched, wherein the etched region of the amorphous silicon film forms an etched region of the amorphous silicon layer, and the unetched region of the crystalline silicon film forms the amorphous A plurality of raised structures of the silicon layer.
  • a plurality of raised structures are equally spaced apart from the amorphous silicon layer.
  • the method may further include: using PECVD, in the non- An insulating layer for preventing heat loss on the upper surface of the amorphous silicon layer is deposited on the crystalline silicon layer.
  • a thermal insulation layer is deposited on the amorphous silicon layer, and during the crystallization of the amorphous silicon layer, heat dissipation on the upper surface of the amorphous silicon layer can be prevented, thereby reducing the upper and lower layers of the amorphous silicon layer.
  • the difference in temperature further increases the grain size of the polysilicon.
  • the thickness of the insulating layer may range from 1000 angstroms to 2000 angstroms.
  • the thickness of the insulation layer can also be set to other values according to actual preparation requirements.
  • the insulating layer may be a Si0 2 or SiNx single-layer film, or a composite film of Si0 2 and SiNx may be used.
  • the method may further include: removing the thermal insulation layer on the low temperature polysilicon film.
  • a low temperature polysilicon film is formed, and the insulating layer on the low temperature polysilicon film can be removed by a dry etching process.
  • the insulating layer on the low temperature polysilicon film is removed.
  • Still another embodiment of the present invention also provides a display device including the above-described thin film transistor.
  • the thin film transistor can be used as a switching element to control a pixel or as a driving element to drive a pixel.
  • the display device may be: a liquid crystal display panel, an electronic paper, an Organic Light Emitting Diode (OLED) panel, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, and a navigation device. Any product or part that has a display function.
  • OLED Organic Light Emitting Diode
  • the display device is suitable for various types of displays such as a liquid crystal display, an organic electroluminescence display, an electroless display, an active matrix organic light emitting diode display (AMOLED).
  • a liquid crystal display an organic electroluminescence display, an electroless display, an active matrix organic light emitting diode display (AMOLED).
  • AMOLED active matrix organic light emitting diode display
  • An example of the display device is a liquid crystal display device in which an array substrate and a counter substrate are opposed to each other to form a liquid crystal cell, and the liquid crystal cell is filled with a liquid crystal material.
  • the opposite substrate is, for example, a color filter substrate.
  • the liquid crystal display device further includes a backlight.
  • the array substrate includes a plurality of gate lines and a plurality of data lines, the gate lines and the data lines crossing each other thereby defining pixel units arranged in a matrix,
  • Each of the pixel units includes a thin film transistor as a switching element, which is, for example, a thin film transistor of an embodiment of the present invention.

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Abstract

一种低温多晶硅薄膜的制备方法，包括：通过构图工艺，在基板(S1) 上形成非晶硅层(S3)，该非晶硅层(S3)包括多个凸起结构(S32)以及位于该多个凸起结构四周的部分被刻蚀掉的刻蚀区域(S31)；以及对非晶硅层(S3)进行准分子激光晶化，得到低温多晶硅薄膜。还公开了薄膜晶体管和显示装置，用于解决采用ELC技术制备的多晶硅薄膜均匀性较差的问题。

Description

低温多晶硅薄膜及其制备方法、 薄膜晶体管和显示装置 技术领域
本发明的实施例涉及一种低温多晶硅薄膜及其制备方法， 以及应用该低 温多晶硅薄膜的薄膜晶体管和显示装置。 背景技术
在平面显示装置例如液晶显示器（ Liquid Crystal Display, LCD )、 有机 电致发光显示器或者无机电致发光显示器中， 薄膜晶体管 （TFT ) —般用作 开关元件来控制像素或是用作驱动元件来驱动像素。 薄膜晶体管按照所使用 的作为有源层的硅薄膜性盾通常可分为非晶硅（a-Si )与多晶硅（Poly-Si ) 薄膜晶体管两种。 与非晶硅薄膜晶体管相比， 多晶硅薄膜晶体管有更高的电 子迁移率、 较低的漏电流等特性， 因此利用多晶硅薄膜晶体管制作的显示器 会有较高的分辨率以及较快的反应速度。
多晶硅薄膜的制备工艺可分为两大类。 一类是高温工艺， 制备过程中温 度高于 600°C， 衬底使用昂贵的石英； 另一类是低温工艺， 整个加工工艺温 度低于 600°C， 可用廉价玻璃作衬底。 因此， 低温多晶硅（ Low Temperature Poly Silicon, LTPS )技术已逐渐取代非晶硅技术成为薄膜晶体管研发的主流。 在低温多晶硅的制备中， 多晶硅的晶化问题一直是低温多晶硅领域研究的重 点。
目前业界成熟的低温多晶硅薄膜制备工艺主要有固相晶化（Solid Phase Crystallization， SPC ) 、 金属诱导横向晶化 ( Metal-Induced Lateral Crystallization, MILC )、准分子激光晶化（ Excimer Laser Crystallization, ELC ) 等技术。 ELC技术因其产品具有较高的电子迁移率及产率， 被业界普遍用于 非晶硅的晶化。 ELC是将高功率的激光束作用于待晶化的非晶硅（a-Si )薄 膜表面，由于硅材料极强的紫外光吸收能力，该激光束可在极短的时间内（约 50 ns ~ 150ns )使 a-Si薄膜表面达到 1000 °C以上的高温而变成熔融状态， 在 激光脉沖停止后，熔融状态的非晶硅冷却结晶变为多晶硅。采用 ELC制备的 多晶硅薄膜晶粒大、 空间选择性好， 掺杂效率高、 晶内缺陷少、 电学特性好、 迁移率较高， 是目前综合性能最好的低温多晶硅薄膜。 然而， 采用 ELC制备 的多晶硅薄膜也有自身的缺点， 即晶粒尺寸对激光功率敏感， 制备得到的多 晶硅薄膜的均匀性较差， 从而使得由该多晶硅薄膜制备的产品（如薄膜晶体 管等）性能差异较大。
综上所述， 目前采用 ELC技术制备的多晶硅薄膜均匀性较差，从而影响 由该多晶硅薄膜制备的产品的性能。 发明内容
本发明的至少一个实施例提供了一种低温多晶硅薄膜及其制备方法、 薄 膜晶体管和显示装置，用于解决采用 ELC技术制备的多晶硅薄膜均匀性较差 的问题。
本发明的至少一个实施例提供了一种低温多晶硅薄膜的制备方法，包括： 通过构图工艺， 在基板上形成非晶硅层的图形， 其中， 所述非晶硅层包括多 个凸起结构以及位于多个所述凸起结构四周的部分被刻蚀掉的刻蚀区域； 对 所述非晶硅层进行准分子激光晶化， 得到低温多晶硅薄膜。 本发明的一些实 施例中， 由于形成的非晶硅层中包括多个凸起结构， 该些凸起结构在后续晶 化过程中作为形核中心， 能够用于均匀形核， 从而保证了多晶硅晶粒的均匀 分布， 增大了晶粒的尺寸。
本发明的一些实施例中， 在所述基板上形成緩冲层， 然后在所述基板上 的緩冲层上形成所述非晶硅层。
例如， 在制备过程中， 通过构图工艺， 在所述基板上形成非晶硅层的图 形， 可以包括： 在所述基板上沉积一层非晶硅薄膜； 对所述非晶硅薄膜进行 选择性刻蚀，所述非晶硅薄膜中被刻蚀的区域形成所述非晶硅层的刻蚀区域， 所述非晶硅薄膜中未被刻蚀的区域形成所述非晶珪层的多个凸起结构。
例如， 多个所述凸起结构等间距分布于非晶硅层。
例如， 在制备过程中， 在所述基板上形成非晶硅层的图形之后， 且在对 所述非晶硅层进行准分子激光晶化之前， 所述方法还可以包括： 在所述基板 的非晶硅层上沉积一层用于防止所述非晶硅层上表面热量散失的保温层， 以 进一步增大多晶硅晶粒的尺寸。
例如， 所述保温层釆用二氧化硅（Si02 )或氮化硅（SiNx )单层薄膜， 或 Si02和 SiNx的复合层薄膜。
本发明的至少一个实施例还提供了一种低温多晶硅薄膜， 该低温多晶硅 薄膜由上述任一方法制备而成， 该低温多晶硅薄膜的晶粒分布均匀， 且尺寸 较大。
本发明的至少一个实施例还提供了一种薄膜晶体管， 该薄膜晶体管采用 上述低温多晶硅薄膜， 该低温多晶硅薄膜可作为薄膜晶体管的有源层。
本发明的至少一个实施例还提供了一种薄膜晶体管的制作方法， 可以包 括： 制备所述薄膜晶体管的有源层， 制备所述有源层包括： 通过构图工艺， 在基板上形成非晶硅层的图形， 其中， 所述非晶硅层包括多个凸起结构以及 位于多个所述凸起结构四周的部分被刻蚀掉的刻蚀区域； 对所述非晶硅层进 行准分子激光晶化， 得到低温多晶硅薄膜； 对所述低温多晶硅薄膜通过构图 工艺， 形成有源层的图形。
例如， 在形成非晶硅层的图形之前， 所述方法还可以包括： 在基板上形 成緩冲层； 或者， 通过构图工艺， 在基板上形成栅极的图形， 以及在形成了 所述栅极的基板上， 形成缓冲层。
例如， 通过构图工艺， 在基板上形成非晶硅层的图形， 包括： 在所述基 板上， 沉积一层非晶硅薄膜； 对所述非晶硅薄膜进行选择性刻蚀， 所述非晶 硅薄膜中被刻蚀的区域形成所述非晶硅层的刻蚀区域， 所述非晶硅薄膜中未 被刻蚀的区域形成所述非晶硅层的多个凸起结构。
例如， 多个所述凸起结构等间距分布于非晶硅层。
例如， 在所述基板上形成非晶硅层的图形之后， 且在对所述非晶硅层进 行准分子激光晶化之前， 所述方法还可以包括： 在所述非晶硅层上沉积一层 用于防止所述非晶硅层上表面热量散失的保温层。
例如， 在对所述非晶硅层进行准分子激光晶化之后， 所述方法还可以包 括： 去除所述低温多晶硅薄膜上的保温层。
本发明的至少一个实施例还提供了一种显示装置， 该显示装置包括上述 薄膜晶体管。 该薄膜晶体管可作为开关元件来控制像素， 或是用作驱动元件 来驱动像素。 附图说明 为了更清楚地说明本发明实施例的技术方案， 下面将对实施例的附图作 简单地介绍，显而易见地，下面描述中的附图仅仅涉及本发明的一些实施例， 而非对本发明的限制。
图 1为本发明实施例提供的一种低温多晶硅薄膜的制备方法示意图； 图 2为本发明实施例的制备工艺示意图；
图 3为本发明实施例中沉积缓冲层后的剖面结构示意图；
图 4为本发明实施例中沉积非晶硅薄膜后的剖面结构示意图；
图 5A为本发明实施例中形成的非晶硅层的剖面结构示意图；
图 5B为本发明实施例中形成的非晶硅层的俯视结构示意图；
图 6为本发明实施例中沉积保温层后的剖面结构示意图。 具体实施方式
本发明的至少一个实施例中， 在基板上形成的非晶硅层包括多个凸起结 构， 在对该非晶硅层进行晶化过程中， 该多个凸起结构可以作为形核中心， 从而能够用于均匀形核， 从而保证了形成的多晶硅晶粒的均匀分布。 凸起结 构部分熔融状态下的未熔融部分在后续的结晶过程中作为形核中心。
下面结合说明书附图对本发明实施例作进一步详细描述。
参见图 1所示， 本发明至少一个实施例提供了一种低温多晶硅薄膜的制 备方法， 该方法包括以下步骤：
步骤 11、 在基板上形成緩冲层， 以防止基板上的杂质进入非晶硅层， 而 影响非晶硅层的性能。
本步骤中， 可采用化学气相沉积（Chemical Vapor Deposition, CVD )方 式， 在基板上沉积緩冲层薄膜， 以形成緩冲层。
优选的， 釆用等离子体增强化学气相沉积（Plasma Enhanced Chemical Vapor Deposition, PECVD )方式，在基板上沉积緩冲层薄膜， 以形成緩冲层。
优选的， 緩冲层可采用采用二氧化硅（Si〇2 )或氮化硅 ( SiNx ) 的单层 薄膜， 或 Si02和 SiNx的复合层薄膜。
优选的， 本步骤中形成的緩冲层的厚度为 2000埃〜 4000埃。 当然緩冲层 的厚度也可以根据实际制备需要设置为其他数值。缓沖层可以包括至少一层， 例如可以为不同材料层构成的复合层。 在制备过程中， 执行本步骤之前， 可以预先对基板进行清洗， 以使基板 保持洁净。
本步骤中， 基板可釆用无碱玻璃基板、 树脂基板、 石英基板等常用的基 板。
在本发明的另一些实施例中， 在基板上没有形成緩沖层， 而是直接在基 板上进行后续的形成非晶硅层的步骤。
步骤 12、 通过构图工艺， 在基板的緩冲层上形成非晶硅层， 该非晶硅层 包括多个凸起结构以及位于该多个凸起结构四周的部分被刻蚀掉的刻蚀区 域。
本步骤中， 通过构图工艺， 在基板的緩冲层上形成非晶硅层， 所形成的 非晶硅层包括多个凸起结构以及位于该多个凸起结构四周的部分被刻蚀掉的 刻蚀区域。 例如， 可以采用光刻方法， 将需要形成凸起结构的非晶硅薄膜区 域进行保护， 其他区域进行刻蚀（即刻蚀区域） ， 最终被保护区域形成均匀 分布的多个凸起结构， 而该些凸起结构在后续晶化过程中作为形核中心， 能 够用于均匀形核， 从而保证了多晶硅晶粒的均匀分布。
在制备过程中， 为了进一步保证所形成的低温多晶硅薄膜的晶粒的均匀 分布， 优选的， 形成的多个凸起结构等间距分布， 以使非晶硅层呈现均匀分 布的丘陵形貌， 进一步保证晶粒的均匀分布。
在本发明的一些实施例中， 构图工艺例如为光刻构图工艺， 其包括： 涂 覆光刻胶层， 使用掩膜板对光刻胶层进行曝光， 对曝光的光刻胶层进行显影 以得到光刻胶图案， 使用光刻胶图案对结构层进行蚀刻， 然后可选地去除光 刻胶图案。 在另一些实施例中， 用于形成光刻胶图案的工艺还可以是丝网印 刷、 喷墨打印方法等。
步骤 13、 对步骤 12所形成的非晶硅层进行准分子激光晶化， 得到低温 多晶硅薄膜。
本步骤中， 在对所形成的非晶硅层进行准分子激光晶化过程中， 由于步 骤 12所形成的非晶硅层的厚度呈现均匀分布的起伏，因此厚度不等的非晶硅 层（凸起结构所在区域及刻蚀区域的厚度不等）对应的临界完全熔融能量密 度必然不同。 在厚度较低的刻蚀区域的临界熔融能量密度之上必然存在一个 能量密度区间， 使得在该刻蚀区域之上的厚度较高的凸起结构处于不完全熔 融状态， 从而使这些凸起结构在晶化过程中能够均匀形核， 保证了多晶硅晶 粒的均匀分布， 并增大了晶粒的尺寸。
实验证明， 釆用发明人已知的制作方法得到的低温多晶硅薄膜的晶粒的 大小一般在 400纳米左右， 而采用本发明至少一个实施例的得到的低温多晶 硅薄膜的晶粒的大小能至少达到 600纳米〜 1000纳米， 增大了晶粒的尺寸。
在制备过程中，步骤 13中，对所形成的非晶硅层进行准分子激光晶化时， 可根据非晶硅层的厚度、 材质等特性， 选择对非晶硅层进行一次、 两次或更 多次的准分子激光退火， 以形成多晶硅薄膜。
例如，对所形成的非晶硅层进行一次准分子激光退火，其工艺参数包括： 激光脉冲频率为 500Hz， 使用的激光能量密度为 350~450mJ/cm2。
在制备过程中， 通过构图工艺， 在基板的緩沖层上形成非晶硅层的一个 示例包括： 在基板的緩冲层上沉积一层非晶硅（a-Si )薄膜； 以及对非晶硅 薄膜进行选择性刻蚀。 该非晶硅薄膜中被刻蚀的区域形成非晶硅层的刻蚀区 域， 该非晶硅薄膜中未被刻蚀的区域形成非晶硅层的多个凸起结构。
在制备过程中， 可采用 CVD方式在基板的缓沖层上沉积一层非晶硅薄 膜。
例如， 采用 PECVD方式在基板的緩冲层上沉积一层非晶硅薄膜。
例如， 步骤 12 中， 在基板的緩冲层上沉积的非晶硅薄膜的厚度为 400 埃〜 800埃。 当然非晶硅薄膜的厚度也可以根据实际制备需要 (例如待制备的 薄膜晶体管的有源层的厚度）设置为其他数值。
例如， 步骤 12中， 对非晶硅薄膜进行选择性刻蚀之后，被部分刻蚀掉的 刻蚀区域的厚度为 200埃〜 600埃， 未被刻蚀的区域形成多个凸起结构，每个 凸起结构的相对于被部分蚀刻的区域的高度为 100埃~200埃，且任意相邻两 个凸起结构之间的间距为 1000纳米〜 2000纳米。 当然刻蚀区域的厚度、 凸起 结构的高度、 相邻两个凸起结构的间距， 也可以根据实际制备需要（如所需 制备的低温多晶硅薄膜的晶粒的尺寸 )设置为其他数值。
本发明的一些实施例中， 可根据基板的尺寸、 以及设定的任意相邻两个 凸起结构之间的间距确定多晶硅层中的凸起结构的数量。
本发明的至少一个实施例中， 不对非晶硅层所形成的凸起结构的形状进 行限定。 本发明的一些实施例的非晶硅层所形成的凸起结构采用圆柱体结构， 且 该凸起结构的直径为 200埃〜 300埃。 当然该凸起结构的直径也可以根据实际 制备需要设置为其他数值。 在本发明的另一些实施例中， 凸起结构也可以釆 用其他形状， 例如棱柱体等。
在制备过程中， 步骤 12之后， 且步骤 13之前， 本发明的一些实施例的 方法还包括如下步骤： 例如釆用 PECVD方式， 在基板的非晶硅层上沉积一 层用于防止该非晶硅层上表面热量散失的保温层， 以进一步增大得到的多晶 硅的晶粒尺寸。
本步骤中， 在非晶硅层上沉积一层保温层， 在对该非晶硅层进行晶化过 程中， 能够防止该非晶硅层上表面热量散失， 以缩小非晶硅层上下膜层的温 度差异， 从而进一步增大多晶硅的晶粒尺寸。
本步骤中， 可以采用 PECVD方式在非晶硅层上沉积一层保温层， 沉积 的保温层均匀性好， 稳定性高， 可以保证晶化之后的晶粒尺寸进一步增大。
例如，保温层的厚度可以为 1000埃〜 2000埃。 当然保温层的厚度也可以 根据实际制备需要设置为其他数值。
例如，保温层可以采用 Si02或 SiNx单层薄膜，也可以采用 Si02和 SiNx 的复合层薄膜。
下面结合一个优选的实施例， 对低温多晶硅薄膜的制备方法进行详细说 明。
实施例一
本实施例中以玻璃基板作为基板， 其制备工艺参见图 2所示， 包括如下 步骤。
步骤 21、 在玻璃基板 S1上沉积緩冲层 S2， 其剖面结构参见图 3所示； 緩冲层 S2釆用 Si02薄膜， 其厚度为 2000~4000埃（人） 。
步骤 22、 在该緩冲层之上沉积非晶硅（a-Si )薄膜 S3， 其剖面结构参见 图 4所示； 该非晶硅薄膜的厚度为 400~800人。
步骤 23、 通过构图工艺， 对该非晶硅薄膜 S3进行选择性刻蚀， 以形成 非晶硅层， 其剖面结构参见图 5A所示， 该非晶硅薄膜 S3中被刻蚀的区域形 成非晶硅层的刻蚀区域 S31， 该非晶硅薄膜中未被刻蚀的区域形成非晶硅层 的多个凸起结构 S32。 该非晶硅层中较厚膜层的厚度为原有的 400~800人， 被部分刻蚀掉的刻 蚀区域 S31经蚀刻之后的厚度变为 200~600人， 形成在该刻蚀区域 S31之上 的柱状凸起结构 S32的直径为 200~300人， 其相对于被部分刻蚀的部分的高 度为 100~200人， 任意相邻两个凸起结构 S32的分布间距为 1000~2000纳米 ( nm ) ， 其俯视结构参见图 5B所示。
本步骤釆用选择性刻蚀的方法， 形成的非晶硅层包括了多个等间距分布 的柱状凸起结构以及为该些凸起结构四周的刻蚀区域， 以实现该些凸起结构 在晶化过程中的不完全熔融状态， 从而实现均匀形核， 使制备得到的多晶硅 晶粒分布均匀， 并增大了晶粒尺寸。
步骤 24、 在刻蚀之后形成的非晶硅层上， 采用 PECVD方式沉积一层保 温层 S4, 其剖面结构参见图 6所示。
该保温层 S4的厚度为 1000〜2000入。 由于该保温层 S4能够防止非晶硅 层表面的热量散失， 能够进一步增大晶化后的晶粒尺寸。 优选的， 该保温层 S4可以釆用 SiO2或 SiNx单层薄膜，也可以采用 Si〇2和 SiNx的复合层薄膜。 在本发明的另一些实施例中， 没有在非晶硅层上形成保温层。
步骤 25、对玻璃基板 S1上的非晶硅层进行 ELC，得到低温多晶硅薄膜； 例如， 在激光脉冲频率为 500Hz 的情形下， 使用的激光能量密度为 350-450mJ/cm2, 对玻璃基板 S 1上的非晶硅层进行晶化。
本发明的另一个实施例还提供了一种低温多晶硅薄膜， 该低温多晶硅薄 膜由上述任一方法制备而成， 该低温多晶硅薄膜的晶粒分布均匀， 且尺寸较 大。
本发明的另一个实施例还提供了一种薄膜晶体管， 该薄膜晶体管采用上 述低温多晶硅薄膜， 该低温多晶硅薄膜可作为薄膜晶体管的有源层。
本发明实施例不对薄膜晶体管的其他结构 （如栅极、 栅极绝缘层、 源漏 极等）进行限定， 只要薄膜晶体管的有源层釆用本发明实施例所提供的低温 多晶硅薄膜制作即可。 本发明的一些实施例的薄膜晶体管例如可以为顶栅型 (柵极位于有源层之上）或底栅型 （栅极位于有源层之下， 位于有源层和基 板之间） ， 在栅极和有源层设置有栅绝缘层， 源漏极与有源层的源漏区域接 触。
本发明的一些实施例还提供了一种薄膜晶体管的制作方法， 该方法包括 制备薄膜晶体管的栅极、 栅极绝缘层、 有源层、 源漏极等。 该薄膜晶体管的 有源层的制作方法包括： 通过构图工艺， 在形成了緩冲层的基板上， 形成非 晶硅层的图形， 其中， 该非晶硅层包括多个凸起结构以及位于多个凸起结构 四周的部分被刻蚀掉的刻蚀区域； 对该非晶硅层进行准分子激光晶化， 得到 低温多晶硅薄膜； 以及， 对该低温多晶硅薄膜通过构图工艺， 形成有源层的 图形。
本发明的一些实施例提供的薄膜晶体管的制作方法中， 薄膜晶体管的有 源层采用低温多晶硅薄膜制作， 不对薄膜晶体管的其他结构进行限定， 只要 有源层采用本发明实施例所提供的低温多晶硅薄膜制作薄膜晶体管的制作方 法都涵盖在本发明实施例中。
例如， 緩沖层可采用采用二氧化硅（sio2 )或氮化硅 ( Si )的单层薄 膜， 或 SiO2和 SiNx的复合层薄膜。
例如，基板上形成的緩沖层的厚度为 2000埃〜 4000埃。 当然緩冲层的厚 度也可以根据实际制备需要设置为其他数值。
在本发明的一些实施例中， 薄膜晶体管在制作时， 可以先制作有源层， 再制作栅极， 该制作方式下， 在形成非晶硅层的图形之前， 该方法还包括： 在基板上形成緩冲层。
该方式下， 可采用 CVD方式， 在基板上沉积緩冲层薄膜， 以形成緩冲 层。
例如， 采用 PECVD方式， 在基板上沉积緩冲层薄膜， 以形成緩冲层。 在本发明的另一些实施例中， 薄膜晶体管在制作时， 可以先制作栅极， 再制作有源层， 该制作方式下， 在形成非晶硅层的图形之前， 该方法还包括： 通过构图工艺， 在基板上形成栅极的图形； 以及在形成了栅极的基板上， 形 成緩冲层。 该方式下， 緩冲层即为薄膜晶体管的栅极绝缘层。
在制备中， 通过构图工艺， 在形成了缓冲层的基板上， 形成非晶硅层的 图形， 可以包括： 在形成了緩冲层的基板上， 沉积一层非晶硅薄膜； 对该非 晶硅薄膜进行选择性刻蚀， 其中， 该非晶硅薄膜中被刻蚀的区域形成所述非 晶硅层的刻蚀区域， 且该 晶硅薄膜中未被刻蚀的区域形成所述非晶硅层的 多个凸起结构。
在制备过程中， 为了进一步保证所形成的低温多晶硅薄膜的晶粒的均匀 分布， 优选的， 多个凸起结构等间距分布于非晶硅层。
在制备过程中， 在形成了緩冲层的基板上形成非晶硅层之后， 且在对非 晶硅层进行准分子激光晶化之前， 所述方法还可以包括： 釆用 PECVD方式， 在非晶硅层上沉积一层用于防止该非晶硅层上表面热量散失的保温层。
本步骤中， 在非晶硅层上沉积一层保温层， 在对该非晶硅层进行晶化过 程中， 能够防止该非晶硅层上表面热量散失， 以缩小非晶硅层上下膜层的温 度差异， 从而进一步增大多晶硅的晶粒尺寸。
例如，保温层的厚度可以为 1000埃〜 2000埃。 当然保温层的厚度也可以 根据实际制备需要设置为其他数值。
例如，保温层可以采用 Si02或 SiNx单层薄膜，也可以釆用 Si02和 SiNx 的复合层薄膜。
进一步， 在对非晶硅层进行准分子激光晶化之后， 该方法还可以包括： 去除该低温多晶硅薄膜上的保温层。
例如， 在对非晶硅层进行准分子激光晶化之后， 形成低温多晶硅薄膜， 可以采用干刻工艺去除该低温多晶硅薄膜上的保温层。
例如， 在对非晶硅层进行准分子激光晶化之后， 且在形成有源层的图形 之前， 去除该低温多晶硅薄膜上的保温层。
本发明的再一个实施例还提供了一种显示装置， 该显示装置包括上述薄 膜晶体管。 优选的， 该薄膜晶体管可作为开关元件来控制像素， 或是用作驱 动元件来驱动像素。
本发明至少一个实施例提供的显示装置可以为： 液晶显示面板、电子纸、 有机发光二极管（Organic Light Emitting Diode, OLED )面板、 手机、 平板 电脑、 电视机、 显示器、 笔记本电脑、 数码相框、 导航仪等任何具有显示功 能的产品或部件。
该显示装置适用于液晶显示器、 有机电致发光显示器、 无机电致发光显 示器、 有源矩阵有机发光二极管显示器（AMOLED )等多种类型的显示器。
该显示装置的一个示例为液晶显示装置， 阵列基板与对置基板彼此对置 以形成液晶盒， 在液晶盒中填充有液晶材料。 该对置基板例如为彩膜基板。 在一些示例中， 该液晶显示装置还包括背光源。 阵列基板包括多条栅线和多 条数据线， 这些栅线和数据线彼此交叉由此限定了排列为矩阵的像素单元， 每个像素单元包括作为开关元件的薄膜晶体管， 该薄膜晶体管例如为本发明 实施例的薄膜晶体管。
显然， 本领域的技术人员可以对本发明进行各种改动和变型而不脱离本 发明的精神和范围。 这样， 倘若本发明的这些修改和变型属于本发明权利要 求及其等同技术的范围之内， 则本发明也意图包含这些改动和变型在内。
本申请要求于 2013年 12月 24曰递交的中国专利申请第 201310722877.7 号的优先权， 在此全文引用上述中国专利申请公开的内容以作为本申请的一 部分。

Claims

权利要求书
1、 一种低温多晶硅薄膜的制备方法， 包括：
通过构图工艺， 在基板上形成非晶硅层的图形， 其中， 所述非晶硅层包 括多个凸起结构以及位于多个所述凸起结构四周的部分被刻蚀掉的刻蚀区 域；
对所述非晶硅层进行准分子激光晶化， 得到低温多晶硅薄膜。
2、如权利要求 1所述的方法， 包括： 在所述基板上形成緩沖层， 然后在 所述基板上的緩沖层上形成所述非晶硅层。
3、如权利要求 1或 2所述的方法， 其中， 通过构图工艺在所述基板上形 成非晶硅层的图形， 包括：
在所述基板上沉积一层非晶硅薄膜；
对所述非晶硅薄膜进行选择性刻蚀， 所述非晶硅薄膜中被刻蚀的区域形 成所述非晶硅层的刻蚀区域， 所述非晶硅薄膜中未被刻蚀的区域形成所述非 晶硅层的多个凸起结构。
4、 如权利要求 1-3任一所述的方法， 其中， 多个所述凸起结构等间距分 布于非晶娃层。
5、如权利要求 1-4任一所述的方法， 在所述基板上形成非晶硅层的图形 之后， 且在对所述非晶硅层进行准分子激光晶化之前， 还包括：
在所述基板的非晶硅层上沉积一层用于防止所述非晶硅层上表面热量散 失的保温层。
6、 如权利要求 5所述的方法， 其中， 所述保温层采用二氧化硅 SiO2或 氮化硅 SiNx单层薄膜， 或 Si02和 SiNx的复合层薄膜。
7、 一种低温多晶硅薄膜， 所述低温多晶硅薄膜由权利要求 1-6任一项所 述的方法制备而成。
8、一种薄膜晶体管，采用如权利要求 7所述的低温多晶硅薄膜作为有源 层。
9、 一种薄膜晶体管的制作方法， 包括：
通过构图工艺， 在基板上形成非晶硅层的图形， 其中， 所述非晶硅层包 括多个凸起结构以及位于多个所述凸起结构四周的部分被刻蚀掉的刻蚀区 域；
对所述非晶硅层进行准分子激光晶化， 得到低温多晶硅薄膜； 对所述低温多晶硅薄膜通过构图工艺， 形成有源层的图形。
10、 如权利要求 9所述的方法， 在形成所述非晶硅层的图形之前， 还包 括：
在所述基板上形成緩冲层； 或者，
通过构图工艺， 在基板上形成栅极的图形 , 以及在形成了所述栅极的基 板上， 形成緩沖层。
11、 如权利要求 9或 10所述的方法， 其中， 通过构图工艺， 在所述基板 上形成非晶硅层的图形， 包括：
在所述基板上， 沉积一层非晶硅薄膜；
对所述非晶硅薄膜进行选择性刻蚀， 所述非晶硅薄膜中被刻蚀的区域形 成所述非晶硅层的刻蚀区域， 所述非晶硅薄膜中未被刻蚀的区域形成所述非 晶硅层的多个凸起结构。
12、 如权利要求 9-11任一所述的方法， 其中， 多个所述凸起结构等间距 分布于非晶硅层。
13、如权利要求 9-12任一所述的方法， 在所述基板上形成非晶硅层的图 形之后， 且在对所述非晶硅层进行准分子激光晶化之前， 还包括：
在所述非晶硅层上沉积一层用于防止所述非晶硅层上表面热量散失的保 温层
14、如权利要求 13所述的方法，在对所述非晶硅层进行准分子激光晶化 之后， 还包括：
去除所述低温多晶硅薄膜上的保温层。
15、 一种显示装置， 包括如权利要求 8所述的薄膜晶体管。
PCT/CN2014/076046 2013-12-24 2014-04-23 低温多晶硅薄膜及其制备方法、薄膜晶体管和显示装置 WO2015096320A1 (zh)

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