WO2015070647A1 - 与非门电路、显示器背板、显示器和电子设备 - Google Patents

与非门电路、显示器背板、显示器和电子设备 Download PDF

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WO2015070647A1
WO2015070647A1 PCT/CN2014/083725 CN2014083725W WO2015070647A1 WO 2015070647 A1 WO2015070647 A1 WO 2015070647A1 CN 2014083725 W CN2014083725 W CN 2014083725W WO 2015070647 A1 WO2015070647 A1 WO 2015070647A1
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transistor
level
pull
input
pole
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PCT/CN2014/083725
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English (en)
French (fr)
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吴仲远
宋丹娜
段立业
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京东方科技集团股份有限公司
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Priority to US14/420,880 priority Critical patent/US9325315B2/en
Priority to EP14859294.2A priority patent/EP3070848B1/en
Publication of WO2015070647A1 publication Critical patent/WO2015070647A1/zh

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
    • H03K19/018507—Interface arrangements
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
    • H03K19/0944—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET
    • H03K19/09441—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET of the same canal type
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
    • H03K19/0944—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET
    • H03K19/09441—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET of the same canal type
    • H03K19/09443—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET of the same canal type using a combination of enhancement and depletion transistors
    • H03K19/09445—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET of the same canal type using a combination of enhancement and depletion transistors with active depletion transistors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/20—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits

Definitions

  • the present invention relates to the field of display technologies, and in particular, to a NAND gate circuit, a display backplane, a display, and an electronic device.
  • a-Si (Amorphous Silicon) TFT transistor Thin Film Transistor
  • LTPS Low Temperature Poly-silicon
  • Oxide TFT transistors oxide TFT transistors
  • a-Si TFT transistors have the disadvantages of low mobility and poor stability
  • LTPS TFT transistors are not suitable for the preparation of large-sized panels.
  • the I-V transfer characteristic of the oxide TFT transistor is usually a depletion type, that is, when the gate-source voltage Vgs of the oxide TFT transistor is zero, the oxide TFT transistor is still turned on.
  • the depletion TFT transistor brings great difficulty to the integrated circuit of the backplane.
  • the NAND gate is a commonly used logic circuit in digital circuits. For two input NAND gates, when both input signals are high, the output signal is low, when only one input signal is high, the other input When the signal is low, the output signal is high.
  • the commonly used NAND gate circuit is mainly composed of CMOS (Complementary Metal Oxide Semiconductor) [3 ⁇ 4 channel], two N-type transistors connected to the input signal are connected in series, and the input signal is simultaneously input. The two P-type transistors are connected in parallel with each other.
  • CMOS Complementary Metal Oxide Semiconductor
  • A is the first input signal
  • B is the second input signal
  • Out is the output signal
  • Vdd is high
  • Vss is low.
  • CMOS circuits have the advantages of low leakage and low power consumption. Due to thin film transistor processes such as oxide TFT transistors, there is usually only one type of TFT transistor, such as an N-type TFT transistor, which generates a large leakage current when a logic gate is provided. And static power consumption.
  • Figure 2 is a circuit diagram of a NAND gate using an N-type transistor.
  • the labels T1, ⁇ 2, and ⁇ 3 are the first ⁇ -type transistor, the second ⁇ -type transistor, and the third ⁇ -type transistor, respectively, and ⁇ 2 respectively indicate the first input signal and the second input signal, OUT.
  • Indicates the output signal VDD indicates high level, VSS indicates low level; T3 forms diode connection and acts as pull-up resistor.
  • ⁇ and IN2 are high at the same time, ⁇ and T2 are simultaneously turned on, pulling OUT low; However, since T3 is long-pass, there is a DC path from VDD to VSS.
  • the output low level is determined by the series resistance of T3 and ' ⁇ , ⁇ 2, and cannot reach VSS.
  • T1 and ⁇ 2 are turned off. Since ⁇ 3 is diode-connected, OUT is equal to VDD VTH, and VTH is the threshold voltage of T3. At this time, OUT cannot reach VDD.
  • the conventional NMOS (N- Mental Oxide Semiconductor) structure has the disadvantages of non-track-to-rail output and large leakage current.
  • the main purpose of the present disclosure is to provide a NAND gate circuit, a display backplane, a display, and an electronic device, so that when the input transistor is a depletion TFT transistor, the NAND gate output can be losslessly transmitted, and the NAND gate output rail-to-rail is realized. .
  • the present disclosure provides a NAND gate circuit including at least two input transistors, each of which is connected to an input signal, a first pole and a NAND gate output of the first input transistor. Connecting, the second pole of the last input transistor is connected to the first level; except for the last input transistor, the second pole of each input transistor is connected to the first pole of the next input transistor;
  • the circuit further includes at least two pull-up modules and at least two input control transistors. Each of the input control transistors has a gate connected to the input signal, and a first pole is respectively connected to a control end of the corresponding pull-up module. The second pole is connected to the first level;
  • a first pole of the first input transistor is connected to the second level output terminal through the pull-up module; and the input control transistor is configured to control when the input signal connected to the gate thereof is at a second level
  • the potential of the control terminal of the pull-up module connected to the first pole of the input transistor is a first level;
  • the at least two pull-up modules are configured to disconnect the connection between the second level output end and the NAND gate output when all of the input signals are at a second level, and As all said When the input signals are not all at the second level, the connection between the second level output terminal and the NAND gate output terminal is turned on.
  • the at least two input transistors and the at least two input control transistors are both depletion mode NMOS transistors, wherein the first extreme source, the second extreme drain, and the second The level is high and the first level is low.
  • the at least two input transistors and the at least two input control transistors are both depletion mode PMOS transistors, wherein the first extreme drain, the second extreme source, the second level Is low, the first level is high.
  • the pull-up module includes a first pull-up transistor, a second pull-up transistor, and a storage capacitor, where
  • the gate of the second pull-up transistor is a control end of the pull-up module
  • the first pull-up transistor is connected to the second level output terminal, the first pole is connected to the » pole of the first pull-up transistor, and the second pole is connected to the gate of the second pull-up transistor Pole connection
  • the second pull-up transistor has a first pole connected to the second level output terminal, and a second pole connected to the NAND gate output terminal;
  • the storage capacitor is connected between a gate of the second pull-up transistor and a second pole of the second pull-up transistor.
  • both the first pull-up transistor and the second pull-up transistor are depletion mode NMOS transistors.
  • both the first pull-up transistor and the second pull-up transistor are depletion mode PMOS transistors.
  • the present disclosure also provides a display backplane comprising the NAND gate circuit described above.
  • the present disclosure also provides a display comprising the display backplane described above.
  • the present disclosure also provides an electronic device including the NAND gate circuit described above.
  • the NAND gate circuit, the display backplane, the display and the electronic device of the present disclosure can make the input transistor be a depletion TFT transistor by using an input control transistor and a pull-up module,
  • the non-gate output can also be transmitted without loss, realize the NAND gate output rail-to-rail, and reduce leakage current, improving the stability and speed of the NAND gate circuit.
  • 1 is a circuit diagram of a conventional NAND gate circuit composed of a CMOS circuit;
  • FIG. 2 is a circuit diagram of a NAND gate of a conventional ffi N-type transistor
  • FIG. 3 is a circuit diagram of a NAND gate circuit according to an embodiment of the present disclosure.
  • FIG. 4 is a circuit diagram of a NAND gate circuit according to another embodiment of the present disclosure.
  • the source and drain of the TFT transistor employed in all embodiments of the present disclosure are symmetrical, so that the source and drain are indistinguishable.
  • one of the poles is referred to as a source and the other pole is referred to as a drain.
  • the transistor can be divided into an NMOS transistor (n-type metal-oxide-semiconductor field effect transistor) and a PMOS transistor (p-type metal-oxide-semiconductor field effect transistor).
  • NMOS transistor n-type metal-oxide-semiconductor field effect transistor
  • PMOS transistor p-type metal-oxide-semiconductor field effect transistor
  • the NAND gate circuit of the embodiment of the present disclosure includes at least two input transistors, a gate of each of the input transistors is connected to an input signal, and a first pole of the first input transistor is connected to a NAND gate output, and finally a second pole of an input transistor is coupled to the first level; except for the last input transistor, the second pole of each input transistor is coupled to the first pole of the next input transistor;
  • the NAND circuit further includes at least two pull-up modules and at least two input control transistors.
  • Each of the input control transistors has a gate connected to the input signal, and the first pole and the corresponding pull-up module respectively.
  • the control terminal is connected, and the second pole is connected to the first level;
  • a first pole of the first input transistor is connected to the second level output terminal through the pull-up module; and the input control transistor is configured to control when the input signal connected to the gate thereof is at a second level
  • the potential of the control terminal of the pull-up module connected to the first pole of the input transistor is a first level;
  • the at least two pull-up modules are configured to disconnect the connection between the second level output end and the NAND gate output when all of the input signals are at a second level, and When all of the input signals are not at the second level, the connection between the second level output and the NAND output is turned on.
  • the NAND gate circuit of the embodiment of the present disclosure can make the NAND gate output ffi non-destructively transmit and realize the NAND gate output when the input transistor is a depletion type TTT transistor by using an input control transistor and a pull-up module. Rail-to-rail, and reduce leakage current, improve the stability and speed of NAND gates.
  • the at least two input transistors and the at least two input control transistors are both depletion mode NMOS transistors, in which case the first source is the source, the second source is the drain, and the second level is the high level. Flat, the first level is low.
  • the at least two input transistors and the at least two input control transistors are both depletion mode PMOS transistors, wherein the first extreme drain, the second extreme source, and the second level are low Flat, the first level is high.
  • the first pole of the NMOS transistor may be a source, and the second pole of the NMOS transistor may be a drain.
  • the second level can be a high level and the first level can be a low level. It is conceivable that the implementation using a PMOS transistor is easily conceivable by those skilled in the art without creative efforts and is therefore within the scope of the embodiments of the present disclosure.
  • the NAND circuit includes:
  • a first input transistor Ti a gate connected to the first input signal IN1, a source and a NAND gate output
  • a second input transistor T2 the gate is connected to the second input signal IN2, the source is connected to the drain of the first input transistor T1, and the drain is connected to the low level VSS;
  • the first input control transistor T3 has a gate connected to the first input signal IN1 and a drain connected to a low level VSS;
  • a second input control transistor ⁇ 4 the gate is connected to the second input signal ⁇ 2, and the drain is connected to a low level VSS;
  • the NAND gate circuit further includes a first pull-up module 31 and a second pull-up module 32;
  • the source of the second input control transistor T4 is connected to the control terminal D2 of the second pull-up module 32;
  • the source of the first input transistor T1 is connected to the high-level output terminal of the output high level VDD through the first pull-up module 31;
  • the source of the first input transistor T1 is also connected to the high-level output terminal of the output high level VDD through the second pull-up module 32;
  • the first pull-up module 31 and the second pull-up module 32 are configured to turn off the high-level output when the first input signal IN1 and the second input signal IN2 are both high. a connection between the terminal and the NAND gate output terminal OUT, cutting off a charging current from the high-level output terminal to the NAND gate output terminal OUT, so that an output signal of the NAND gate output terminal OUT can be Reaching the low level output of the low level output
  • the first pull-up module 31 and the second pull-up module 32 are further configured to turn on the high when the first input signal IN1 and the second input signal IN2 are not both high.
  • a connection between the level output terminal and the NAND gate output terminal OUT transmits a lossless high level VDD to the NAND gate output terminal OUT.
  • T1 and T2, ⁇ 3, and ⁇ 4 are both depletion mode NMOS transistors.
  • ⁇ 3 control makes the potential of D1 low.
  • Ping, ⁇ 4 control causes the potential of D2 to be low, thereby disconnecting the high-level output from OUT;
  • T3 controls the potential of D1 to be low, and T4 is turned off, so that the second pull-up module 32 controls to make VDD transmit to OUT without loss;
  • T4 control causes D2 to be low and T3 is turned off, so that the first pull-up module 31 controls VDD to be transmitted to OUT without loss.
  • the pull-up module includes a first pull-up transistor, a second pull-up transistor, and a storage capacitor, and a gate of the second pull-up transistor is a control end of the pull-up module;
  • the first pull-up transistor has a gate connected to the second level output terminal, a first pole connected to a pole of the first pull-up transistor, and a second pole connected to a gate of the second pull-up transistor Pole connection
  • the second pull-up transistor, the first pole is connected to the second level output terminal, and the second pole is connected to the NAND gate output terminal;
  • the storage capacitor is connected between a gate of the second pull-up transistor and a second pole of the second pull-up transistor.
  • both the first pull-up transistor and the second pull-up transistor are depletion mode NMOS transistors.
  • both the first pull-up transistor and the second pull-up transistor are depletion mode PMOS transistors.
  • the NAND gate circuit described in the embodiment of the present disclosure includes:
  • the first input transistor T1 the gate is connected to the first input signal ⁇ , the source and the NAND gate output
  • a second input transistor T2 the gate is connected to the second input signal ⁇ 2, the source is connected to the drain of the first input transistor T1, and the drain is connected to the low level VSS;
  • a second input control transistor ⁇ 4 a gate connected to the second input signal ⁇ 2, and a drain connected to a low level VSS;
  • the first pull-up module 41 has its control terminal D1 connected to the source of the first input control transistor ⁇ 3.
  • the second pull-up module 42 has a control terminal D2 connected to the source of the second input control transistor ⁇ 4;
  • the first pull-up module 41 includes:
  • the first pull-up transistor ⁇ 5, the gate and the source are connected to a high level VDD;
  • a second pull-up transistor ⁇ 6 the drain is connected to the drain of the first pull-up transistor ⁇ 5 of the first pull-up module 41, the source is connected to the high level VDD, and the drain is connected to the NAND gate output terminal OUT And a first storage capacitor C1 connected between the gate of the second pull-up transistor T6 of the first pull-up module 41 and the drain of the second pull-up transistor T6;
  • the end point connected to the gate of the second pull-up transistor T6 is the control terminal D1 of the first pull-up module 41;
  • the second pull-up module 42 includes:
  • the third pull-up transistor T7, the gate and the source are connected to a high level VDD;
  • a fourth pull-up transistor T8 having a gate connected to a drain of the third pull-up transistor ⁇ 7, a source connected to a high level VDD, and a drain connected to the NAND gate output terminal OUT;
  • the end point connected to the gate of the fourth pull-up transistor T8 is the control terminal D2 of the second pull-up module 42;
  • XI ⁇ ⁇ 2, ⁇ 3, ⁇ 4, ⁇ 5, ⁇ , 6, ⁇ 7 and ⁇ ⁇ 8 are depletion type NMOS tubes.
  • T1 and T2 are turned on at the same time, the output signal is pulled low; T3 and T4 are also turned on, and the gate voltages of T6 and T8 are pulled low to make T6 and ⁇ 8 is turned off, and the charging current from the high-level output terminal of the output high level VDD to the NAND gate output terminal OUT is cut off. At this point, the output signal can reach VSS;
  • T1 When IN1 is high and IN2 is low, T1 is turned on, T2 is turned off, and the pull-down path of NAND gate output terminal OUT is cut off by T2, while T3 is turned on and T4 is turned off; diode-connected T7 is turned on, and VDD is turned on. T7 charges C2, so that the gate potential of T8 rises, turns T8 on, and transmits high level to OUT. As the OUT voltage rises, VDD continuously charges C2 through the turned-on T7, so that the gate of T8 The pole potential continues to rise and can reach a positive voltage exceeding (VDD+VTH8).
  • VTH8 is the threshold voltage of T8, making T8 fully conductive, so that VDD can be transmitted from the drain of T8 to the source of T8 without loss (ie OUT) );
  • T5 and T6 can be W/L (transistors with small width and length, which will make T6 gate low when OUT output low level, and leakage of T6 off state) Less than the conduction quiescent current of T3 in Figure 2.
  • the size of the ⁇ 5 is small, the sum of the on-state quiescent currents of ⁇ 5 and ⁇ 6 is much smaller than the on-state quiescent current of ⁇ 3 in Fig. 2, thereby reducing the leakage current.
  • ⁇ 7 and ⁇ 8 are the same as ⁇ 5 and ⁇ 6, and will not be repeated here.
  • the NAND gate circuit of the embodiment of the present disclosure adopts a capacitor bootstrap structure, which is composed of 8 TFT transistors and 2 capacitors, can make the output rail-to-rail, realize full voltage swing, and make the output lossless transmission, and Reduce leakage current and improve the stability and speed of NAND gate circuits.
  • the present disclosure also provides a display backplane comprising the NAND gate circuit described above.
  • the present disclosure also provides a display comprising the display backplane described above.
  • the present disclosure also provides an electronic device including the above NAND gate circuit.

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Abstract

一种与非门电路、显示器背板和显示器，该与非门电路包括至少两输入晶体管（T1，T2）、至少两个上拉模块（31，32）和至少两输入控制晶体管（T3，T4）；每一输入晶体管（T1，Τ2）的第一极通过该上拉模块（31，32）与第二电平输出端连接；输入控制晶体管（Τ3，Τ4）用于当其栅极接入的输入信号为第二电平时，控制使得与该输入晶体管（T1，Τ2）的第一极连接的上拉模块（31，32）的控制端的电位为第一电平；至少两个上拉模块（31，32），用于当所有的输入信号都为第二电平时，断开第二电平输出端与与非门输出端之间的连接，并用于当所有的输入信号不都为第二电平时，导通第二电平输出端与与非门输出端之间的连接。采用耗尽型TFT晶体管时，与非门输出能无损传输，实现与非门输出轨到轨，并降低漏电流，提高与非门电路的稳定性和速度。

Description

与非 η电路、 显示器背板、 显示器和电子设备
本申请 张2013年 11月 15日提交的中国专利申请 No. 201310573352.1 的优先权权益， 其全部内容结合于此作为参考。
本发明涉及显示技术领域， 尤其涉及一种与非门电路、 显示器背板、 显示 器和电子设备。
目前制造显示器件背板的工艺有很多种， 如 a- Si (非晶硅） TFT晶体管 (Thin Film Transistor ，薄膜场效应晶体管)显示器件， LTPS (Low Temperature Poly- silicon, 低温多晶硅） TFT显示器件， Oxide TFT晶体管 （氧化物 TFT 晶体管）显示器件等， a- Si TFT晶体管具有迁移率低和稳定性差的缺点， LTPS TFT晶体管不适于大尺寸面板的制备。 氧化物 TFT晶体管的 I- V转移特性通 常为耗尽型， 即在氧化物 TFT晶体管的栅源电压 Vgs为零时， 氧化物 TFT晶 体管仍然导通。
耗尽型 TFT晶体管给背板集成的电路设 i†带来很大难度。 与非门是数字 电路中常用的逻辑电路， 对于两输入与非门， 当两个输入信号都为高电平时， 输出信号为低电平， 当只有一个输入信号为高电平， 另一个输入信号为低电平 时， 输出信号为高电平。 如图 1 所示， 常用的与非门电路主要由 CMOS ( Complementary Metal Oxide Semiconductor,互补金属氧化物半导体 )【¾路组 成， 接入输入信号的两个 N型晶体管相互串联， 同时接入输入信号的两个 P 型晶体管相互并联。 在图 1中， A为第一输入信号， B为第二输入信号， Out 为输出信号， Vdd标示高电平， Vss标示低电平。 CMOS电路具有漏电小， 低 功耗的优点。 由于如氧化物 TFT晶体管等薄膜晶体管工艺， 通常只有一种类 型的 TFT晶体管， 如 N型 TFT晶体管， 在设†逻辑门时会产生较大的漏电流 和静态功耗。
图 2为釆用 N型晶体管的与非门的电路图。 在图 2中， 标号为 Tl、 Τ2、 Τ3的分别是第一 Ν型晶体管、 第二 Ν型晶体管、 第三 Ν型晶体管， ΙΝ】、 ΙΝ2 分别标示第一输入信号、 第二输入信号， OUT标示输出信号， VDD标示高电 平， VSS标示低电平； T3形成二极管连接， 起到上拉电阻的作用， 当 ΙΝΊ和 IN2同时为高时， ΤΊ和 T2同时导通， 将 OUT拉低； 但由于 T3是长通， 存在 由 VDD到 VSS的直流通路， 同时输出低电平由 T3与' Π、 Τ2的串联电阻分 压决定， 不能达到 VSS; 当 ΙΝ〗 和 ΙΝ2中一个为低或者都为低时， T1和 Τ2 截止， 由于 Τ3为二极管连接， OUT等于 VDD VTH， VTH为 T3的阈值电 压， 此时 OUT 也不能达到 VDD。 由上可知， 传统的 NMOS (N- Mental Oxide Semiconductor, n型金属 -氧化物半导体） 结构的与非门存 在输出不能轨到轨和漏电流大等缺点。
本公开的主要目的在于提供一种与非门电路、显示器背板、显示器和电子 设备， 使得输入晶体管为耗尽型 TFT晶体管时， 与非门输出能无损传输， 实 现与非门输出轨到轨。
为了达到上述目的， 本公开提供了一种与非门电路，包括至少两输入晶体 管， 每个所述输入晶体管的 »极接入一输入信号，第一输入晶体管的第一极和 与非门输出端连接， 最后一输入晶体管的第二极接入第一电平； 除了最后一输 入晶体管之外， 每一输入晶体管的第二极与下一输入晶体管的第一极连接； 所述与非门电路还包括至少两个上拉模块和至少两输入控制晶体管； 每一所述输入控制晶体管， 栅极分别接入一所述输入信号， 第一极分别与 对应的上拉模块的控制端连接， 第二极接入所述第一电平；
所述第一输入晶体管的第一极通过该上拉模块与第二电平输出端连接； 所述输入控制晶体管用于当其栅极接入的输入信号为第二电平时，控制使 得与该输入晶体管的第一极连接的上拉模块的控制端的电位为第一电平；
所述至少两个上拉模块，用于当所有的所述输入信号都为第二电平时， 断 开所述第二电平输出端与所述与非门输出端之间的连接，并 ^于当所有的所述 输入信号不都为第二电平时，导通所述第二电平输出端与所述与非门输出端之 间的连接。
在一个示例中，所述至少两输入晶体管和所述至少两输入控制晶体管都为 耗尽型 NMOS晶体管， 其中， 所述第一极为源极， 所述第二极为漏极， 所述 第二电平为高电平， 所述第一电平为低电平。
在一个示例中，所述至少两输入晶体管和所述至少两输入控制晶体管都为 耗尽型 PMOS 晶体管， 其中所述第一极为漏极， 所述第二极为源极， 所述第 二电平为低电平， 所述第一电平为高电平。
在一个示例中， 所述上拉模块包括第一上拉晶体管、第二上拉晶体管和存 储电容， 其中，
所述第二上拉晶体管的栅极为该上拉模块的控制端；
所述第一上拉晶体管， 櫥极与所述第二电平输出端连接，第一极与所述第 一上拉晶体管的 »极连接， 第二极与所述第二上拉晶体管的栅极连接；
所述第二上拉晶体管，第一极与所述第二电平输出端连接，第二极与所述 与非门输出端连接；
所述存储电容，连接于所述第二上拉晶体管的栅极和所述第二上拉晶体管 的第二极之间。
实施时， 当所述输入晶体管和所述输入控制晶体管为耗尽型 NMOS晶体 管时， 第一上拉晶体管和第二上拉晶体管都为耗尽型 NMOS晶体管。
实施时， 当所述输入晶体管和所述输入控制晶体管为耗尽型 PMOS 晶体 管时， 第一上拉晶体管和第二上拉晶体管都为耗尽型 PMOS晶体管。
本公开还提供了一种显示器背板， 包括上述的与非门电路。
本公开还提供了一种显示器， 包括上述的显示器背板。
本公开还提供了一种电子设备， 包括上述的与非门电路。
与现有技术相比， 本公开所述的与非门电路、 显示器背板、 显示器和电子 设备通过采用输入控制晶体管和上拉模块，可以使得所述输入晶体管为耗尽型 TFT晶体管时， 与非门输出也能无损传输， 实现与非门输出轨到轨， 并降低漏 电流， 提髙与非门电路的稳定性和速度。 图 1是现有的由 CMOS电路组成的与非门电路的电路图；
图 2是现有的采 ffi N型晶体管的与非门的电路图；
图 3是本公开一实施例所述的与非门电路的电路图；
图 4是本公开另一实施例所述的与非门电路的电路图。
下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清 楚、 完整地描述， 显然， 所描述的实施例仅仅是本公开一部分实施例， 而不是 全部的实施例。基于本公开中的实施例， 本领域普通技术人员在没有做出创造 性劳动前提下所获得的所有其他实施例， 都属于本发明保护的范围。
本公开所有实施例中采用的 TFT晶体管的源极和漏极是对称的， 所以其 源极、 漏极是没有区别的。 在本公开实施例中， 为区分 TFT晶体管除欐极之 外的两极， 将其中一极称为源极， 另一极称为漏极。 此外， 按照场效应晶体管 的特性区分可以将晶体管分为 NMOS管（n型金属 -氧化物-半导体场效应晶体 管） 和 PMOS管 （p型金属 -氧化物-半导体场效应晶体管）。 在本公开实施例 提供的 AMOLED像素电路中，所有晶体管均是以 NMOS管为例进行的说明， 可以想到的是采 PMOS 管实现是本领域技术人员可在没有做出创造性劳动 前提下轻易想到的， 因此也是在本公开的实施例保护范围内的。
本公开实施例所述的与非门电路，包括至少两输入晶体管， 每个所述输入 晶体管的栅极接入一输入信号，第一输入晶体管的第一极和与非门输出端连接， 最后一输入晶体管的第二极接入第一电平； 除了最后一输入晶体管之外， 每一 输入晶体管的第二极与下一输入晶体管的第一极连接；
所述与非门电路还包括至少两个上拉模块和至少两输入控制晶体管； 每一所述输入控制晶体管， 栅极分别接入一所述输入信号， 第一极分别与 对应的上拉模块的控制端连接， 第二极接入所述第一电平；
所述第一输入晶体管的第一极通过该上拉模块与第二电平输出端连接； 所述输入控制晶体管用于当其栅极接入的输入信号为第二电平时，控制使 得与该输入晶体管的第一极连接的上拉模块的控制端的电位为第一电平； 所述至少两个上拉模块，用于当所有的所述输入信号都为第二电平时， 断 开所述第二电平输出端与所述与非门输出端之间的连接，并^于当所有的所述 输入信号不都为第二电平时，导通所述第二电平输出端与所述与非门输出端之 间的连接。
本公开实施例所述的与非门电路通过采用输入控制晶体管和上拉模块，可 以使得当所述输入晶体管为耗尽型 TTT晶体管时，与非门输出 ffi能无损传输， 实现与非门输出轨到轨， 并降低漏电流， 提高与非门电路的稳定性和速度。
根据一种具体实施方式，所述至少两输入晶体管和所述至少两输入控制晶 体管都为耗尽型 NMOS晶体管， 此时第一极为源极， 第二极为漏极， 第二电 平为高电平， 第一电平为低电平。
根据一种具体实施方式，所述至少两输入晶体管和所述至少两输入控制晶 体管都为耗尽型 PMOS 晶体管， 此时第一极为漏极， 第二极为源极， 第二电 平为低电平， 第一电平为高电平。
在以下本公开实施例提供的具体的与非门电路中， 所有晶体管均是以 NMOS管为例进行的说明， 其中 NMOS管的第一极可以是源极， NMOS管的 第二极可以是漏极， 第二电平可以为高电平， 第一电平可以为低电平。 可以想 到的是采用 PMOS 管实现是本领域技术人员可在没有做出创造性劳动前提下 轻易想到的， 因此也是在本公开的实施例保护范围内的。
如图 3所示， 在一具体实施例中， 所述与非门电路包括；
第一输入晶体管 Ti , 栅极接入第一输入信号 IN1， 源极和与非门输出端
OUT连接；
第二输入晶体管 T2 , 栅极接入第二输入信号 IN2， 源极与所述第一输入 晶体管 T1的漏极连接， 漏极接入低电平 VSS ;
第一输入控制晶体管 T3， 栅极接入所述第一输入信号 IN1 , 漏极接入低 电平 VSS ;
以及， 第二输入控制晶体管 Τ4， 栅极接入所述第二输入信号 ΙΝ2， 漏极 接入低电平 VSS;
所述与非门电路还包括第一上拉模块 31和第二上拉模块 32 ;
所述第一输入控制晶体管 Τ3的源极与所述第一上拉模块 31的控制端 D1 连接；
所述第二输入控制晶体管 T4的源极与所述第二上拉模块 32的控制端 D2 连接；
所述第一输入晶体管 T1 的源极通过所述第一上拉模块 31 与输出高电平 VDD的高电平输出端连接；
所述第一输入晶体管 T1 的源极也通过所述第二上拉模块 32与所述输出 高电平 VDD的高电平输出端连接；
所述第一上拉模块 31和所述第二上拉模块 32， 用于当所述第一输入信号 IN1和所述第二输入信号 IN2都为高电平时，断开所述高电平输出端与所述与 非门输出端 OUT之间的连接， 截断从所述高电平输出端到所述与非门输出端 OUT的充电电流，使得所述与非门输出端 OUT的输出信号可以达到所述低电 平输出端输出的低电平
所述第一上拉模块 31和所述第二上拉模块 32， 还) ¾于当所述第一输入信 号 IN1和所述第二输入信号 IN2不都为高电平时，导通所述高电平输出端与所 述与非门输出端 OUT之间的连接， 传输无损的高电平 VDD到所述与非门输 出端 OUT。
在本公开该具体实施例所述的与非门电路中， T1和 T2、 Τ3和 Τ4都为耗 尽型 NMOS晶体管， 当 IN1和 ΙΝ2都为高电平时， Τ3控制使得 D1的电位为 低电平， Τ4控制使得 D2的电位为低电平，从而断开所述高电平输出端与 OUT 之间的连接；
当 IN1为高电平而 IN2为低电平时， T3控制使得 D1的电位为低电平， 而 T4关断， 从而第二上拉模块 32控制使得 VDD无损地传输到 OUT;
当 IN2为高电平而 IN1为低电平时， T4控制使得 D2的电位为低电平， 而 T3关断， 从而第一上拉模块 31控制使得 VDD无损地传输到 OUT。
具体的，所述上拉模块包括第一上拉晶体管、第二上拉晶体管和存储电容， 所述第二上拉晶体管的栅极为该上拉模块的控制端；
所述第一上拉晶体管， 栅极与所述第二电平输出端连接，第一极与所述第 一上拉晶体管的極极连接， 第二极与所述第二上拉晶体管的栅极连接； 所述第二上拉晶体管， 第一极与所述第二电平输出端连接， 第二极与所述 与非门输出端连接；
所述存储电容，连接于所述第二上拉晶体管的栅极和所述第二上拉晶体管 的第二极之间。
实施时， 当所述输入晶体管和所述输入控制晶体管为耗尽型 NMOS晶体 管时， 第一上拉晶体管和第二上拉晶体管都为耗尽型 NMOS晶体管。
实施时， 当所述输入晶体管和所述输入控制晶体管为耗尽型 PMOS 晶体 管时， 第一上拉晶体管和第二上拉晶体管都为耗尽型 PMOS晶体管。
如图 4所示， 本公开实施例所述的与非门电路包括：
第一输入晶体管 Tl， 栅极接入第一输入信号 ΙΝΊ， 源极和与非门输出端
OUT连接；
第二输入晶体管 T2， 栅极接入第二输入信号 ΙΝ2， 源极与所述第一输入 晶体管 T1的漏极连接， 漏极接入低电平 VSS ;
第一输入控制晶体管 Τ3， 栅极接入所述第一输入信号 IN1 , 漏极接入低 电平 VSS ;
第二输入控制晶体管 Τ4， 栅极接入所述第二输入信号 ΙΝ2 , 漏极接入低 电平 VSS ;
第一上拉模块 41， 其控制端 D1与所述第一输入控制晶体管 Τ3的源极连 接 *
以及， 第二上拉模块 42， 其控制端 D2与所述第二输入控制晶体管 Τ4的 源极连接；
所述第一上拉模块 41包括：
第一上拉晶体管 Τ5， 栅极和源极接入高电平 VDD;
第二上拉晶体管 Τ6 , 欐极与所述第一上拉模块 41 的第一上拉晶体管 Τ5 的漏极连接， 源极接入高电平 VDD， 漏极与所述与非门输出端 OUT连接； 以及， 第一存储电容 Cl， 连接于所述第一上拉模块 41的第二上拉晶体管 T6的栅极和所述第二上拉晶体管 T6的漏极之间；
与所述第二上拉晶体管 T6的栅极连接的端点为所述第一上拉模块 41 的 控制端 D1 ; 所述第二上拉模块 42包括：
第三上拉晶体管 T7， 栅极和源极接入高电平 VDD;
第四上拉晶体管 T8，栅极与所述第三上拉晶体管 Τ7的漏极连接， 源极接 入高电平 VDD， 漏极与所述与非门输出端 OUT连接；
以及， 第二存储电容 C2，连接于所述第四上拉晶体管 T8的栅极和所述第 四上拉晶体管 T8的漏极之间；
与所述第四上拉晶体管 T8的栅极连接的端点为所述第二上拉模块 42的 控制端 D2;
XI禾 Π Τ2、 Τ3、 Τ4、 Τ5、 Ί，6、 Τ7禾 Π Τ8为耗尽型 NMOS管。
在本公开该实施例所述的与非门电路工作时：
当 IN1和 IN2同时为高电平，此时 T1和 T2同时导通，将输出信号拉低； T3和 T4也导通， 将 T6和 T8的栅极电压拉至低电平， 使 T6禾 Π Τ8关断， 截 断来自输出高电平 VDD的高电平输出端对与非门输出端 OUT的充电电流。 此时输出信号可以达到 VSS;
当 IN1为高， IN2为低时， T1导通， T2截止， 与非门输出端 OUT的下 拉通路被 T2截断， 同时 T3导通， T4截止； 二极管连接的 T7导通， VDD通 过导通的 T7对 C2充电， 使得 T8的栅极电位升高， 使 T8导通， 传输高电平 到 OUT; 随着 OUT电压的上升， VDD通过导通的 T7对 C2持续充电， 丛而 使 T8的栅极电位持续抬升，一直可以达到超过 (VDD+VTH8)的正电压， VTH8 是 T8的阈值电压， 使 T8完全导通， 从而 VDD可以从 T8的漏极无损地传输 到 T8的源极 （即 OUT);
当 INI为低， IN2为高时， Ti截止， T2导通， 与非门输出端的下拉通路 被 T1截断； 同时 T4导通， T3截止； 二极管连接的 T5导通， VDD通过导通 的 T5对 C1充电，使得 T6的栅极电位升高，使 T6导通，传输高电平到 OUT; 随着 OUT的电压的上升， C1使 T6的欐极电位持续抬升， 一直可以达到超过 (VDD+VTH6) 的正电压， VTH6为 T6的阈值电压， 使 T6完全导通， 丛而 VDD可以从 T6的漏极无损地传输到 T6的源极 （即 OUT)。
在图 4中， 与驱动晶体管相比， T5和 T6可以是 W/L (宽长 很小的晶 体管， 这样会在 OUT输出低电平时， T6栅极为低电平， T6的关态的漏电远 小于图 2中 T3的导通静态电流。 另外由于 Τ5的尺寸很小， Τ5和 Τ6的导通 静态电流之和都会远小于图 2中 Τ3的导通静态电流， 从而降低漏电流。 图 4 中 Τ7、 Τ8与 Τ5、 Τ6情况相同， 这里不再复述。
本公开该实施例所述的与非门电路， 采用电容自举结构， 由 8个 TFT晶 体管和 2个电容构成， 可以使输出轨到轨， 实现全电压摆幅， 并使得输出无损 传输， 并降低漏电流， 提高与非门电路的稳定性和速度。
本公开还提供了一种显示器背板， 包括上述的与非门电路。
本公开还提供了一种显示器， 包括上述的显示器背板。
本公开还提供一种电子设备， 包括上述的与非门电路。
以上所述是本发明的优选实施方式， 应当指出，对于本技术领域的普通技 术人员来说，在不脱离本发明所述原理的前提下，还可以作出若干改进和润饰， 这些改进和润饰也应视为本发明的保护范围。

Claims

1 . 一种与非门电路， 包括至少两输入晶体管， 每个所述输入晶体管的栅 极接入一输入信号，第一输入晶体管的第一极和与非门输出端连接， 最后一输 入晶体管的第二极接入第一电平； 除了最后一输入晶体管之外， 每一输入晶体 管的第二极与下一输入晶体管的第一极连接；
其中，所述与非门电路还包括至少两个上拉模块和至少两输入控制晶体管; 每一所述输入控制晶体管， »极分别接入一所述输入信号，第一极分别与 对应的上拉模块的控制端连接， 第二极接入所述第一电平；
所述第一输入晶体管的第一极通过该上拉模块与第二电平输出端连接； 所述输入控制晶体管用于当其栅极接入的输入信号为第二电平时，控制使 得与该输入晶体管的第一极连接的上拉模块的控制端的电位为第一电平；
所述至少两个上拉模块， 用于当所有的所述输入信号都为第二电平时， 断 开所述第二电平输出端与所述与非门输出端之间的连接，并) ¾于当所有的所述 输入信号不都为第二电平时，导通所述第二电平输出端与所述与非门输出端之 间的连接。
2. 如权利要求 1 所述的与非门电路， 其中， 所述至少两输入晶体管和所 述至少两输入控制晶体管都为耗尽型 NMOS晶体管。
3. 根据权利要求 2所述的与非门电路， 其中， 所述第一极为源极， 所述 第二极为漏极， 所述第二电平为高电平， 所述第一电平为低电平。
4. 如权利要求 1 所述的与非门电路， 其中， 所述至少两输入晶体管和所 述至少两输入控制晶体管都为耗尽型 PMOS晶体管。
5. 根据权利要求 4所述的与非门电路， 其中， 所述第一极为漏极， 所述 第二极为源极， 所述第二电平为低电平， 所述第一电平为高电平。
6. 如权利要求 1 所述的与非门电路， 其中， 所述上拉模块包括第一上拉 晶体管、 第二上拉晶体管和存储电容， 其中，
所述第二上拉晶体管的栅极为该上拉模块的控制端；
所述第一上拉晶体管， 栅极与所述第二电平输出端连接，第一极与所述第 一上拉晶体管的極极连接， 第二极与所述第二上拉晶体管的栅极连接； 所述第二上拉晶体管， 第一极与所述第二电平输出端连接， 第二极与所述 与非门输出端连接；
所述存储电容，连接于所述第二上拉晶体管的栅极和所述第二上拉晶体管 的第二极之间。
7, 如权利要求 6所述的与非门电路， 其中， 当所述输入晶体管和所述输 入控制晶体管为耗尽型 NMOS晶体管时， 第一上拉晶体管和第二上拉晶体管 都为耗尽型 NMOS晶体管。
8. 根据权利要求 7所述的与非门电路， 其中， 所述第一极为源极， 所述 第二极为漏极， 所述第二电平为高电平， 所述第一电平为低电平。
9. 如权利要求 6所述的与非门电路， 其中， 当所述输入晶体管和所述输 入控制晶体管为耗尽型 PMOS 晶体管时， 第一上拉晶体管和第二上拉晶体管 都为耗尽型 PMOS晶体管。
10. 根据权利要求 9所述的与非门电路， 其中， 所述第一极为漏极， 所述 第二极为源极， 所述第二电平为低电平， 所述第一电平为高电平。
11. 一种显示器背板， 其特征在于， 包括如权利要求 1 至 10中任一权利 要求所述的与非门电路。
12. —种显示器， 其特征在于， 包括如权利要求 13所述的显示器背板。
13. 一种电子设备， 包括如权利要求 1-10所述的与非门电路。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2017068233A1 (en) * 2015-10-23 2017-04-27 Ari Paasio Low power logic family

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103560782B (zh) 2013-11-15 2015-04-22 京东方科技集团股份有限公司 与非门电路、显示器背板和显示器
CN104575425B (zh) * 2015-01-09 2017-04-12 深圳市华星光电技术有限公司 扫描驱动电路及其与非门逻辑运算电路
CN104883181B (zh) 2015-06-10 2018-03-16 京东方科技集团股份有限公司 或非门电路、移位寄存器、阵列基板及显示装置
US11626875B2 (en) * 2018-04-20 2023-04-11 Texas Instruments Incorporated Stress reduction on stacked transistor circuits
CN108735163B (zh) * 2018-05-30 2020-11-17 京东方科技集团股份有限公司 用于阵列基板行驱动单元的或逻辑运算电路
CN110690889B (zh) * 2019-10-14 2021-08-10 华南理工大学 一种电平移位电路

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6392486B1 (en) * 2001-08-14 2002-05-21 Xilinx, Inc. Low-noise common-gate amplifier for wireless communications
US7061279B1 (en) * 2004-12-30 2006-06-13 Broadcom Corporation System and method for high frequency, high output swing buffers
CN1835402A (zh) * 2005-03-15 2006-09-20 凌阳科技股份有限公司 自偏压式高频逻辑门与应用其的或非门、与非门
CN101354924A (zh) * 2007-07-23 2009-01-28 奇晶光电股份有限公司 移位寄存器电路与其上拉单元
CN101547004A (zh) * 2009-05-12 2009-09-30 威盛电子股份有限公司 与门电路
JP2010098666A (ja) * 2008-10-20 2010-04-30 Seiko Epson Corp 排他的論理和回路および電気光学装置
CN103560782A (zh) * 2013-11-15 2014-02-05 京东方科技集团股份有限公司 与非门电路、显示器背板和显示器

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100498453B1 (ko) * 2002-11-04 2005-07-01 삼성전자주식회사 출력 데이터의 스큐를 감소시킬 수 있는 출력버퍼 회로
US8013633B2 (en) * 2007-06-20 2011-09-06 Hewlett-Packard Development Company, L.P. Thin film transistor logic
US8570066B2 (en) * 2011-03-24 2013-10-29 Electronics And Telecommunications Research Institute Inverter, NAND gate, and NOR gate
TWI488163B (zh) * 2013-01-23 2015-06-11 Au Optronics Corp 移位暫存器、使用該移位暫存器之閘極驅動電路與顯示裝置

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6392486B1 (en) * 2001-08-14 2002-05-21 Xilinx, Inc. Low-noise common-gate amplifier for wireless communications
US7061279B1 (en) * 2004-12-30 2006-06-13 Broadcom Corporation System and method for high frequency, high output swing buffers
CN1835402A (zh) * 2005-03-15 2006-09-20 凌阳科技股份有限公司 自偏压式高频逻辑门与应用其的或非门、与非门
CN101354924A (zh) * 2007-07-23 2009-01-28 奇晶光电股份有限公司 移位寄存器电路与其上拉单元
JP2010098666A (ja) * 2008-10-20 2010-04-30 Seiko Epson Corp 排他的論理和回路および電気光学装置
CN101547004A (zh) * 2009-05-12 2009-09-30 威盛电子股份有限公司 与门电路
CN103560782A (zh) * 2013-11-15 2014-02-05 京东方科技集团股份有限公司 与非门电路、显示器背板和显示器

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2017068233A1 (en) * 2015-10-23 2017-04-27 Ari Paasio Low power logic family

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