WO2015070647A1

WO2015070647A1 - Nand gate circuit, display back panel, display and electronic device

Info

Publication number: WO2015070647A1
Application number: PCT/CN2014/083725
Authority: WO
Inventors: 吴仲远; 宋丹娜; 段立业
Original assignee: 京东方科技集团股份有限公司
Priority date: 2013-11-15
Filing date: 2014-08-05
Publication date: 2015-05-21
Also published as: EP3070848B1; EP3070848A1; CN103560782A; CN103560782B; US9325315B2; US20160028398A1; EP3070848A4

Abstract

A NAND gate circuit, a display back panel and a display. The NAND gate circuit comprises at least two input transistors (T1, T2), at least two pull-up modules (31, 32) and at least two input control transistors (T3, T4), wherein first electrodes of both the input transistors (T1, T2) are connected to an output end of a second level via the pull-up modules (31, 32); the input control transistors (T3, T4) are used for, when input signals which gate electrodes thereof access are at the second level, controlling to enable the electric potential at control ends of the pull-up modules (31, 32) connected to the first electrodes of the input transistors (T1, T2) to be at a first level; and the at least two pull-up modules (31, 32) are used for disconnecting the output end of the second level from an output end of a NAND gate when all input signals are at the second level, and used for connecting the output end of the second level with the output end of the NAND gate when the input signals are not all at the second level. When a depletion type TFT is adopted, the output of the NAND gate can be transmitted without loss, the rail-to-rail output of the NAND gate is realized, and leakage currents are reduced, thereby increasing the stability and speed of a NAND circuit.

Description

And non-η circuits, display backplanes, displays and electronic devices

The priority of Chinese Patent Application No. 201310573352.1, filed on Nov. 15, 2013, is hereby incorporated by reference.

The present invention relates to the field of display technologies, and in particular, to a NAND gate circuit, a display backplane, a display, and an electronic device.

At present, there are many processes for manufacturing display device backplanes, such as a-Si (Amorphous Silicon) TFT transistor (Thin Film Transistor) display device, LTPS (Low Temperature Poly-silicon) TFT display device. , Oxide TFT transistors (oxide TFT transistors) display devices, etc., a-Si TFT transistors have the disadvantages of low mobility and poor stability, and LTPS TFT transistors are not suitable for the preparation of large-sized panels. The I-V transfer characteristic of the oxide TFT transistor is usually a depletion type, that is, when the gate-source voltage Vgs of the oxide TFT transistor is zero, the oxide TFT transistor is still turned on.

The depletion TFT transistor brings great difficulty to the integrated circuit of the backplane. The NAND gate is a commonly used logic circuit in digital circuits. For two input NAND gates, when both input signals are high, the output signal is low, when only one input signal is high, the other input When the signal is low, the output signal is high. As shown in Figure 1, the commonly used NAND gate circuit is mainly composed of CMOS (Complementary Metal Oxide Semiconductor) [3⁄4 channel], two N-type transistors connected to the input signal are connected in series, and the input signal is simultaneously input. The two P-type transistors are connected in parallel with each other. In Figure 1, A is the first input signal, B is the second input signal, Out is the output signal, Vdd is high, and Vss is low. CMOS circuits have the advantages of low leakage and low power consumption. Due to thin film transistor processes such as oxide TFT transistors, there is usually only one type of TFT transistor, such as an N-type TFT transistor, which generates a large leakage current when a logic gate is provided. And static power consumption.

Figure 2 is a circuit diagram of a NAND gate using an N-type transistor. In FIG. 2, the labels T1, Τ2, and Τ3 are the first 晶体管-type transistor, the second Ν-type transistor, and the third Ν-type transistor, respectively, and ΙΝ2 respectively indicate the first input signal and the second input signal, OUT. Indicates the output signal, VDD indicates high level, VSS indicates low level; T3 forms diode connection and acts as pull-up resistor. When both ΙΝΊ and IN2 are high at the same time, ΤΊ and T2 are simultaneously turned on, pulling OUT low; However, since T3 is long-pass, there is a DC path from VDD to VSS. At the same time, the output low level is determined by the series resistance of T3 and 'Π, Τ2, and cannot reach VSS. When ΙΝ and ΙΝ2 are low or both When low, T1 and Τ2 are turned off. Since Τ3 is diode-connected, OUT is equal to VDD VTH, and VTH is the threshold voltage of T3. At this time, OUT cannot reach VDD. As can be seen from the above, the conventional NMOS (N- Mental Oxide Semiconductor) structure has the disadvantages of non-track-to-rail output and large leakage current.

The main purpose of the present disclosure is to provide a NAND gate circuit, a display backplane, a display, and an electronic device, so that when the input transistor is a depletion TFT transistor, the NAND gate output can be losslessly transmitted, and the NAND gate output rail-to-rail is realized. .

In order to achieve the above object, the present disclosure provides a NAND gate circuit including at least two input transistors, each of which is connected to an input signal, a first pole and a NAND gate output of the first input transistor. Connecting, the second pole of the last input transistor is connected to the first level; except for the last input transistor, the second pole of each input transistor is connected to the first pole of the next input transistor; The circuit further includes at least two pull-up modules and at least two input control transistors. Each of the input control transistors has a gate connected to the input signal, and a first pole is respectively connected to a control end of the corresponding pull-up module. The second pole is connected to the first level;

a first pole of the first input transistor is connected to the second level output terminal through the pull-up module; and the input control transistor is configured to control when the input signal connected to the gate thereof is at a second level The potential of the control terminal of the pull-up module connected to the first pole of the input transistor is a first level;

The at least two pull-up modules are configured to disconnect the connection between the second level output end and the NAND gate output when all of the input signals are at a second level, and As all said When the input signals are not all at the second level, the connection between the second level output terminal and the NAND gate output terminal is turned on.

In one example, the at least two input transistors and the at least two input control transistors are both depletion mode NMOS transistors, wherein the first extreme source, the second extreme drain, and the second The level is high and the first level is low.

In one example, the at least two input transistors and the at least two input control transistors are both depletion mode PMOS transistors, wherein the first extreme drain, the second extreme source, the second level Is low, the first level is high.

In one example, the pull-up module includes a first pull-up transistor, a second pull-up transistor, and a storage capacitor, where

The gate of the second pull-up transistor is a control end of the pull-up module;

The first pull-up transistor is connected to the second level output terminal, the first pole is connected to the » pole of the first pull-up transistor, and the second pole is connected to the gate of the second pull-up transistor Pole connection

The second pull-up transistor has a first pole connected to the second level output terminal, and a second pole connected to the NAND gate output terminal;

The storage capacitor is connected between a gate of the second pull-up transistor and a second pole of the second pull-up transistor.

In implementation, when the input transistor and the input control transistor are depletion mode NMOS transistors, both the first pull-up transistor and the second pull-up transistor are depletion mode NMOS transistors.

In implementation, when the input transistor and the input control transistor are depletion mode PMOS transistors, both the first pull-up transistor and the second pull-up transistor are depletion mode PMOS transistors.

The present disclosure also provides a display backplane comprising the NAND gate circuit described above.

The present disclosure also provides a display comprising the display backplane described above.

The present disclosure also provides an electronic device including the NAND gate circuit described above.

Compared with the prior art, the NAND gate circuit, the display backplane, the display and the electronic device of the present disclosure can make the input transistor be a depletion TFT transistor by using an input control transistor and a pull-up module, The non-gate output can also be transmitted without loss, realize the NAND gate output rail-to-rail, and reduce leakage current, improving the stability and speed of the NAND gate circuit. 1 is a circuit diagram of a conventional NAND gate circuit composed of a CMOS circuit;

2 is a circuit diagram of a NAND gate of a conventional ffi N-type transistor;

3 is a circuit diagram of a NAND gate circuit according to an embodiment of the present disclosure;

4 is a circuit diagram of a NAND gate circuit according to another embodiment of the present disclosure.

BRIEF DESCRIPTION OF THE DRAWINGS The technical solutions in the embodiments of the present disclosure will be described in the following detailed description of the embodiments of the present disclosure. All other embodiments obtained by a person of ordinary skill in the art based on the embodiments of the present disclosure without making creative labor are within the scope of the present invention.

The source and drain of the TFT transistor employed in all embodiments of the present disclosure are symmetrical, so that the source and drain are indistinguishable. In the embodiment of the present disclosure, in order to distinguish the two poles of the TFT transistor except the drain, one of the poles is referred to as a source and the other pole is referred to as a drain. In addition, according to the characteristics of the field effect transistor, the transistor can be divided into an NMOS transistor (n-type metal-oxide-semiconductor field effect transistor) and a PMOS transistor (p-type metal-oxide-semiconductor field effect transistor). In the AMOLED pixel circuit provided by the embodiment of the present disclosure, all of the transistors are described by taking an NMOS transistor as an example. It is conceivable that the implementation of the PMOS transistor can be easily imagined by those skilled in the art without creative work. Therefore, it is also within the scope of the embodiments of the present disclosure.

The NAND gate circuit of the embodiment of the present disclosure includes at least two input transistors, a gate of each of the input transistors is connected to an input signal, and a first pole of the first input transistor is connected to a NAND gate output, and finally a second pole of an input transistor is coupled to the first level; except for the last input transistor, the second pole of each input transistor is coupled to the first pole of the next input transistor;

The NAND circuit further includes at least two pull-up modules and at least two input control transistors. Each of the input control transistors has a gate connected to the input signal, and the first pole and the corresponding pull-up module respectively. The control terminal is connected, and the second pole is connected to the first level;

a first pole of the first input transistor is connected to the second level output terminal through the pull-up module; and the input control transistor is configured to control when the input signal connected to the gate thereof is at a second level The potential of the control terminal of the pull-up module connected to the first pole of the input transistor is a first level; The at least two pull-up modules are configured to disconnect the connection between the second level output end and the NAND gate output when all of the input signals are at a second level, and When all of the input signals are not at the second level, the connection between the second level output and the NAND output is turned on.

The NAND gate circuit of the embodiment of the present disclosure can make the NAND gate output ffi non-destructively transmit and realize the NAND gate output when the input transistor is a depletion type TTT transistor by using an input control transistor and a pull-up module. Rail-to-rail, and reduce leakage current, improve the stability and speed of NAND gates.

According to a specific embodiment, the at least two input transistors and the at least two input control transistors are both depletion mode NMOS transistors, in which case the first source is the source, the second source is the drain, and the second level is the high level. Flat, the first level is low.

According to a specific embodiment, the at least two input transistors and the at least two input control transistors are both depletion mode PMOS transistors, wherein the first extreme drain, the second extreme source, and the second level are low Flat, the first level is high.

In the following specific NAND gate circuit provided by the embodiments of the present disclosure, all transistors are described by taking an NMOS transistor as an example. The first pole of the NMOS transistor may be a source, and the second pole of the NMOS transistor may be a drain. The second level can be a high level and the first level can be a low level. It is conceivable that the implementation using a PMOS transistor is easily conceivable by those skilled in the art without creative efforts and is therefore within the scope of the embodiments of the present disclosure.

As shown in FIG. 3, in a specific embodiment, the NAND circuit includes:

a first input transistor Ti, a gate connected to the first input signal IN1, a source and a NAND gate output

OUT connection;

a second input transistor T2, the gate is connected to the second input signal IN2, the source is connected to the drain of the first input transistor T1, and the drain is connected to the low level VSS;

The first input control transistor T3 has a gate connected to the first input signal IN1 and a drain connected to a low level VSS;

And a second input control transistor Τ4, the gate is connected to the second input signal ΙΝ2, and the drain is connected to a low level VSS;

The NAND gate circuit further includes a first pull-up module 31 and a second pull-up module 32;

a source of the first input control transistor T3 and a control terminal D1 of the first pull-up module 31 connection;

The source of the second input control transistor T4 is connected to the control terminal D2 of the second pull-up module 32;

The source of the first input transistor T1 is connected to the high-level output terminal of the output high level VDD through the first pull-up module 31;

The source of the first input transistor T1 is also connected to the high-level output terminal of the output high level VDD through the second pull-up module 32;

The first pull-up module 31 and the second pull-up module 32 are configured to turn off the high-level output when the first input signal IN1 and the second input signal IN2 are both high. a connection between the terminal and the NAND gate output terminal OUT, cutting off a charging current from the high-level output terminal to the NAND gate output terminal OUT, so that an output signal of the NAND gate output terminal OUT can be Reaching the low level output of the low level output

The first pull-up module 31 and the second pull-up module 32 are further configured to turn on the high when the first input signal IN1 and the second input signal IN2 are not both high. A connection between the level output terminal and the NAND gate output terminal OUT transmits a lossless high level VDD to the NAND gate output terminal OUT.

In the NAND gate circuit described in this embodiment of the present disclosure, T1 and T2, Τ3, and Τ4 are both depletion mode NMOS transistors. When both IN1 and ΙΝ2 are high level, Τ3 control makes the potential of D1 low. Ping, Τ4 control causes the potential of D2 to be low, thereby disconnecting the high-level output from OUT;

When IN1 is high and IN2 is low, T3 controls the potential of D1 to be low, and T4 is turned off, so that the second pull-up module 32 controls to make VDD transmit to OUT without loss;

When IN2 is high and IN1 is low, T4 control causes D2 to be low and T3 is turned off, so that the first pull-up module 31 controls VDD to be transmitted to OUT without loss.

Specifically, the pull-up module includes a first pull-up transistor, a second pull-up transistor, and a storage capacitor, and a gate of the second pull-up transistor is a control end of the pull-up module;

The first pull-up transistor has a gate connected to the second level output terminal, a first pole connected to a pole of the first pull-up transistor, and a second pole connected to a gate of the second pull-up transistor Pole connection The second pull-up transistor, the first pole is connected to the second level output terminal, and the second pole is connected to the NAND gate output terminal;

As shown in FIG. 4, the NAND gate circuit described in the embodiment of the present disclosure includes:

The first input transistor T1, the gate is connected to the first input signal ΙΝΊ, the source and the NAND gate output

OUT connection;

a second input transistor T2, the gate is connected to the second input signal ΙΝ2, the source is connected to the drain of the first input transistor T1, and the drain is connected to the low level VSS;

a first input control transistor Τ3, a gate connected to the first input signal IN1, and a drain connected to a low level VSS;

a second input control transistor Τ4, a gate connected to the second input signal ΙΝ2, and a drain connected to a low level VSS;

The first pull-up module 41 has its control terminal D1 connected to the source of the first input control transistor Τ3.

And the second pull-up module 42 has a control terminal D2 connected to the source of the second input control transistor Τ4;

The first pull-up module 41 includes:

The first pull-up transistor Τ5, the gate and the source are connected to a high level VDD;

a second pull-up transistor Τ6, the drain is connected to the drain of the first pull-up transistor Τ5 of the first pull-up module 41, the source is connected to the high level VDD, and the drain is connected to the NAND gate output terminal OUT And a first storage capacitor C1 connected between the gate of the second pull-up transistor T6 of the first pull-up module 41 and the drain of the second pull-up transistor T6;

The end point connected to the gate of the second pull-up transistor T6 is the control terminal D1 of the first pull-up module 41; The second pull-up module 42 includes:

The third pull-up transistor T7, the gate and the source are connected to a high level VDD;

a fourth pull-up transistor T8 having a gate connected to a drain of the third pull-up transistor Τ7, a source connected to a high level VDD, and a drain connected to the NAND gate output terminal OUT;

And a second storage capacitor C2 connected between the gate of the fourth pull-up transistor T8 and the drain of the fourth pull-up transistor T8;

The end point connected to the gate of the fourth pull-up transistor T8 is the control terminal D2 of the second pull-up module 42;

XI Π Τ 2, Τ 3, Τ 4, Τ 5, Ί, 6, Τ 7 and Π Τ 8 are depletion type NMOS tubes.

When the NAND gate circuit described in this embodiment of the present disclosure operates:

When IN1 and IN2 are at the same time, T1 and T2 are turned on at the same time, the output signal is pulled low; T3 and T4 are also turned on, and the gate voltages of T6 and T8 are pulled low to make T6 and Τ8 is turned off, and the charging current from the high-level output terminal of the output high level VDD to the NAND gate output terminal OUT is cut off. At this point, the output signal can reach VSS;

When IN1 is high and IN2 is low, T1 is turned on, T2 is turned off, and the pull-down path of NAND gate output terminal OUT is cut off by T2, while T3 is turned on and T4 is turned off; diode-connected T7 is turned on, and VDD is turned on. T7 charges C2, so that the gate potential of T8 rises, turns T8 on, and transmits high level to OUT. As the OUT voltage rises, VDD continuously charges C2 through the turned-on T7, so that the gate of T8 The pole potential continues to rise and can reach a positive voltage exceeding (VDD+VTH8). VTH8 is the threshold voltage of T8, making T8 fully conductive, so that VDD can be transmitted from the drain of T8 to the source of T8 without loss (ie OUT) );

When INI is low and IN2 is high, Ti is off and T2 is on. The pull-down path of the NAND gate output is truncated by T1. At the same time, T4 is turned on and T3 is turned off. The diode-connected T5 is turned on, and VDD is turned on. C1 is charged, so that the gate potential of T6 is raised, T6 is turned on, and the high level is transmitted to OUT. As the voltage of OUT rises, C1 causes the potential of T6 to continuously rise, which can be exceeded (VDD+VTH6). The positive voltage, VTH6 is the threshold voltage of T6, making T6 fully conductive, and VDD can be losslessly transmitted from the drain of T6 to the source of T6 (ie, OUT).

In Figure 4, compared to the drive transistor, T5 and T6 can be W/L (transistors with small width and length, which will make T6 gate low when OUT output low level, and leakage of T6 off state) Less than the conduction quiescent current of T3 in Figure 2. In addition, since the size of the Τ5 is small, the sum of the on-state quiescent currents of Τ5 and Τ6 is much smaller than the on-state quiescent current of Τ3 in Fig. 2, thereby reducing the leakage current. In Fig. 4, Τ7 and Τ8 are the same as Τ5 and Τ6, and will not be repeated here.

The NAND gate circuit of the embodiment of the present disclosure adopts a capacitor bootstrap structure, which is composed of 8 TFT transistors and 2 capacitors, can make the output rail-to-rail, realize full voltage swing, and make the output lossless transmission, and Reduce leakage current and improve the stability and speed of NAND gate circuits.

The present disclosure also provides an electronic device including the above NAND gate circuit.

The above is a preferred embodiment of the present invention, and it should be noted that those skilled in the art can also make several improvements and retouchings without departing from the principles of the present invention. It should be considered as the scope of protection of the present invention.

Claims

1. A NAND gate circuit, including at least two input transistors, the gate of each input transistor is connected to an input signal, the first electrode of the first input transistor is connected to the output terminal of the NAND gate, and the last input transistor The second pole of is connected to the first level; except for the last input transistor, the second pole of each input transistor is connected to the first pole of the next input transistor;

Wherein, the NAND gate circuit also includes at least two pull-up modules and at least two input control transistors; each of the input control transistors has a first pole connected to one of the input signals, and a first pole is connected to the corresponding upper pole respectively. The control end of the pull module is connected, and the second pole is connected to the first level;

The first pole of the first input transistor is connected to the second level output terminal through the pull-up module; the input control transistor is used to control the input signal connected to the second level when the input signal connected to its gate is the second level. The potential of the control terminal of the pull-up module connected to the first pole of the input transistor is the first level;

The at least two pull-up modules are used to disconnect the second level output terminal from the NAND gate output terminal when all the input signals are at the second level, and) ¾ When all the input signals are not at the second level, the connection between the second level output terminal and the NAND gate output terminal is turned on.

2. The NAND gate circuit of claim 1, wherein the at least two input transistors and the at least two input control transistors are depletion mode NMOS transistors.

3. The NAND gate circuit according to claim 2, wherein the first pole is a source, the second pole is a drain, the second level is a high level, and the first level is low level.

4. The NAND circuit of claim 1, wherein the at least two input transistors and the at least two input control transistors are depletion mode PMOS transistors.

5. The NAND gate circuit according to claim 4, wherein the first pole is a drain, the second pole is a source, the second level is a low level, and the first level is high level.

6. The NAND gate circuit of claim 1, wherein the pull-up module includes a first pull-up transistor, a second pull-up transistor and a storage capacitor, wherein,

The gate of the second pull-up transistor is the control end of the pull-up module;

The gate of the first pull-up transistor is connected to the second level output terminal, the first electrode is connected to the electrode of the first pull-up transistor, and the second electrode is connected to the gate of the second pull-up transistor. pole connection; The second pull-up transistor has a first pole connected to the second level output terminal and a second pole connected to the NAND gate output terminal;

The storage capacitor is connected between the gate electrode of the second pull-up transistor and the second electrode of the second pull-up transistor.

7. The NAND circuit of claim 6, wherein when the input transistor and the input control transistor are depletion NMOS transistors, both the first pull-up transistor and the second pull-up transistor are depletion mode. type NMOS transistor.

8. The NAND gate circuit according to claim 7, wherein the first pole is a source, the second pole is a drain, the second level is a high level, and the first level is low level.

9. The NAND circuit of claim 6, wherein when the input transistor and the input control transistor are depletion PMOS transistors, both the first pull-up transistor and the second pull-up transistor are depletion mode. type PMOS transistor.

10. The NAND gate circuit according to claim 9, wherein the first pole is a drain, the second pole is a source, the second level is a low level, and the first level is high level.

11. A display backplane, characterized by comprising a NAND gate circuit as claimed in any one of claims 1 to 10.

12. A display, characterized by comprising the display backplane as claimed in claim 13.

13. An electronic device, including the NAND gate circuit as claimed in claims 1-10.