WO2015068448A1 - 窒化物半導体 - Google Patents
窒化物半導体 Download PDFInfo
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- WO2015068448A1 WO2015068448A1 PCT/JP2014/072883 JP2014072883W WO2015068448A1 WO 2015068448 A1 WO2015068448 A1 WO 2015068448A1 JP 2014072883 W JP2014072883 W JP 2014072883W WO 2015068448 A1 WO2015068448 A1 WO 2015068448A1
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Definitions
- the present invention relates to a nitride semiconductor. Specifically, the present invention relates to a structure of a channel layer for improving the lifetime of a nitride semiconductor device.
- a structure using a heterojunction composed of AlGaN and GaN is generally used.
- a buffer layer made of a nitride semiconductor formed on a substrate such as sapphire or Si, a channel layer generally made of GaN formed on the buffer layer, and on the GaN channel layer
- a barrier layer made of AlGaN formed on the substrate a source electrode and a drain electrode that form ohmic contact with a two-dimensional electron gas region formed at the interface between the AlGaN barrier layer and the GaN channel layer, the source electrode and the drain electrode And a gate electrode formed between the two.
- a “semiconductor electronic device” disclosed in Japanese Patent Laid-Open No. 2005-85852 (Patent Document 1).
- a buffer layer a GaN electron transit layer (500 nm), an AlGaN electron supply layer (20 nm), and a GaN contact layer are sequentially stacked on a GaN intervening layer formed on a silicon substrate.
- the buffer layer is formed by alternately laminating single or plural first layers made of GaN and single or plural second layers made of AlGaN.
- Patent Document 1 has the following problems.
- FIG. 6 an AlGaN layer having a small lattice constant that does not cause stress relaxation is formed on a GaN layer (a GaN electron transit layer in Patent Document 1) having a substantially bulk lattice constant in which stress is relaxed. (AlGaN electron supply layer in Document 1) is formed.
- the piezoelectric polarization Ppe is generated by the difference in the spontaneous polarization Psp between the GaN layer and the AlGaN layer and the AlGaN layer on the GaN layer being distorted by the stress + ⁇ in the plane.
- 2-dimensional electron gas (2DEG) is formed at the interface.
- 2DHG two-dimensional hole gas
- an object of the present invention is to provide a nitride semiconductor capable of suppressing the generation of two-dimensional hole gas when using a superlattice buffer layer in which AlGaN layers having different compositions are alternately laminated.
- the nitride semiconductor of the present invention is A substrate, An initial growth layer formed on the substrate; A buffer layer formed on the initial growth layer; A superlattice buffer layer formed on the buffer layer; A channel layer composed of a plurality of layers formed on the superlattice buffer layer; A barrier layer formed on the channel layer,
- the superlattice buffer layer includes a high Al-containing layer having a thickness a having a composition of Al x Ga 1-x N (0.5 ⁇ x ⁇ 1.0), and Al y Ga 1-y N (0 ⁇ y A low Al content layer having a thickness b having a composition of ⁇ 0.3) is alternately laminated.
- the channel layer is joined to the superlattice buffer layer, and is formed by laminating at least an Al z Ga 1-z N layer and a GaN layer sequentially from the superlattice buffer layer side.
- the Al composition of the Al z Ga 1-z N layer is characterized by being the same as the average Al composition of the superlattice buffer layer.
- the barrier layer includes an Al w Ga 1-w N layer,
- the Al composition w in the Al w Ga 1-w N layer is larger than the Al composition z in the Al z Ga 1-z N layer of the channel layer.
- the range of thickness a of the high Al-containing layer in the superlattice buffer layer is 1 nm ⁇ a ⁇ 5 nm, and the range of thickness b of the low Al-containing layer is 22 nm ⁇ b ⁇ 30 nm.
- the channel layer joined to the AlGaN superlattice buffer layer is divided into an Al z Ga 1-z N layer and a GaN layer in this order from the AlGaN superlattice buffer layer side.
- the Al composition of the Al z Ga 1-z N layer are the same as the average Al composition of the AlGaN superlattice buffer layer. Therefore, the Al z Ga 1-z N layer can be regarded as having substantially the same lattice constant as that of the AlGaN superlattice buffer layer, which is equivalent to one AlGaN layer whose stress is relaxed. Therefore, it is possible to suppress the formation of a two-dimensional hole gas due to distortion caused by the stress of ⁇ at the interface between the AlGaN superlattice buffer layer and the Al z Ga 1-z N layer.
- the Al z Ga 1-z N layer formed on the superlattice buffer layer compensates for the two-dimensional hole gas formed between the superlattice buffer layer and the GaN layer, and leaks. It is possible to reduce the current.
- FIG. 2 is a cross-sectional view of a nitride semiconductor epitaxial wafer different from FIG. 1. It is a figure which shows the CV measurement result of HEMT using the nitride semiconductor epitaxial wafer shown in FIG. It is a figure which shows the mechanism of 2D electron gas production
- FIG. 1 is a cross-sectional view of a nitride semiconductor epitaxial wafer as the nitride semiconductor of the present embodiment.
- an AlN initial growth layer 2 made of AlN and having a thickness of 100 nm, and an Al 0.2 Ga 0.8 N buffer layer 3 having a thickness of 20 nm are sequentially formed on an Si substrate 1.
- a superlattice buffer layer 4 having a repetition period of 100 periods in which an AlN layer having a thickness of 4 nm and an Al 0.1 Ga 0.9 N layer having a thickness of 23 nm are alternately stacked is formed.
- a channel layer 5 composed of a plurality of layers is formed on the superlattice buffer layer 4.
- the channel layer 5 is formed by laminating an Al z Ga 1-z N layer 6 and a GaN channel region 7 which is the GaN layer in this order.
- the Al composition z in the Al z Ga 1-z N layer 6 of the channel layer 5 is such that the superlattice buffer layer 4 has a composition of Al x Ga 1-x N (0.5 ⁇ x ⁇ 1.0).
- a high Al-containing layer having a thickness of “a (nm)” and a low Al-containing layer having a thickness of “b (nm)” having a composition of Al y Ga 1-y N (0 ⁇ y ⁇ 0.3) Are given by the following formula (1).
- z (a * x + b * y) / (a + b) (1)
- the Al 0.23 Ga 0.77 N layer 6 is grown with a thickness of 1 ⁇ m.
- a GaN channel region 7 is grown with a thickness of 20 nm on the Al 0.23 Ga 0.77 N layer 6 to form a channel layer 5.
- the thickness “a” of the Al x Ga 1-x N layer (0.5 ⁇ x ⁇ 1.0) which is the high Al content layer in the superlattice buffer layer 4 is 1 nm ⁇ a ⁇ 5 nm.
- the thickness “b” of the Al y Ga 1-y N layer (0 ⁇ y ⁇ 0.3), which is the low Al content layer, is preferably 22 nm ⁇ b ⁇ 30 nm. The reason is as follows.
- the superlattice buffer layer 4 is formed by repeatedly laminating the Al x Ga 1-x N layer, which is the high Al-containing layer, and the Al y Ga 1-y N layer, which is the low Al-containing layer.
- the difference between the thickness “a” of the high Al-containing layer and the thickness “b” of the low Al-containing layer needs to be at least 17 nm or more. It is. Furthermore, it is necessary to make the thickness “a” of the high Al-containing layer that is easily warped thinner than the thickness “b” of the low Al-containing layer that is not easily warped.
- the superlattice buffer layer 4 approaches the same structure as the case where the low Al-containing layer is a single layer film, and the warp is effectively prevented. It cannot be suppressed.
- the thickness “b” of the low Al-containing layer exceeds 30 nm, the superlattice buffer layer 4 approaches a configuration equivalent to the single-layer film of the low Al-containing layer, and the warpage is effectively suppressed. Can not. Therefore, it is effective to set the thickness “a” of the high Al-containing layer and the thickness “b” of the low Al-containing layer from the above ranges.
- the Al composition “w” of the Al w Ga 1-w N barrier layer 8 is desirably larger than the Al composition “z” of the Al z Ga 1-z N layer 6 in the channel layer 5. The reason is as follows.
- Al It is necessary to generate a larger strain at the interface between the w Ga 1-w N barrier layer 8 and the GaN channel region 7 than at the interface between the GaN channel region 7 and the Al z Ga 1-z N layer 6.
- a The Al composition “w” of the l w Ga 1-w N barrier layer 8 needs to be larger than the Al composition “z” of the Al z Ga 1-z N layer 6 in the channel layer 5.
- an AlN intermediate layer (not shown) made of AlN may be grown between the GaN channel region 7 and the AlGaN barrier layer 8 in order to improve mobility.
- a GaN cap layer (not shown) made of GaN may be grown on the AlGaN barrier layer 8.
- an Al x Ga 1-x N (0.5 ⁇ x ⁇ 1.0) high Al-containing layer having a thickness of a and an Al y Ga 1-y N (0 ⁇ y ⁇ 0.0. 3) a low Al-containing layer is, on the AlGaN superlattice buffer layer 4 which is formed by alternately stacking, Al z Ga 1-z N layer 6 and the GaN channel region Al composition is given by the formula (1) 7 is formed in this order.
- an AlGaN layer 6 having the same Al composition as the average Al composition of the superlattice is formed on the AlGaN superlattice buffer layer 4.
- a nitride semiconductor epitaxial wafer can be obtained.
- the present invention is not limited to this combination.
- FIG. 2 shows the CV measurement (capacitance measurement) result of the HEMT formed using the obtained nitride semiconductor epitaxial wafer.
- FIG. 2A shows the case of this embodiment using a combination of a GaN channel region 7 and an AlGaN layer 6 as the channel layer 5.
- FIG. 2B shows a comparative example in which only the GaN layer is used as the channel layer.
- the horizontal axis “au” represents a relative distance in the substrate direction with respect to the surface of the wafer.
- a bias voltage is applied by the LCR meter 12 between the gate electrode G of the HEMT 10 and the stage 11 as shown in FIG.
- FIG. 2 (b) when only GaN is used as the channel layer, a carrier concentration peak 13 is observed between the GaN layer and the superlattice layer, and the presence of a two-dimensional hole gas. It suggests.
- FIG. 2A in which an AlGaN layer 6 having the same Al composition as the average Al composition of the superlattice is formed on the superlattice buffer layer 4, the carrier of the two-dimensional hole gas is absorbed. No peak is seen, indicating that the generation of two-dimensional hole gas is suppressed.
- AlGaN having the same Al composition as the average Al composition of the superlattice between the AlGaN superlattice buffer layer 4 and the GaN channel region 7.
- Layer 6 is formed.
- the AlGaN superlattice buffer layer 4 in which AlGaN layers having different Al compositions are alternately grown can be considered equivalent to one AlGaN layer whose stress is relaxed.
- the AlGaN layer 6 formed on the one AlGaN layer whose stress is relaxed has the same Al composition as the average Al composition of the superlattice buffer layer 4 equivalent to one AlGaN layer whose stress is relaxed. Therefore, it can be considered that the lattice constant is substantially equal to that of the superlattice buffer layer 4. Therefore, it is possible to suppress the formation of the two-dimensional hole gas due to the distortion caused by the stress ⁇ at the interface between the superlattice buffer layer 4 and the AlGaN layer 6.
- the AlGaN layer 6 formed on the superlattice buffer layer 4 compensates for the two-dimensional hole gas formed between the superlattice buffer layer 4 and the GaN layer, thereby reducing the leakage current. It can be made possible.
- FIG. 4 is a cross-sectional view of a nitride semiconductor epitaxial wafer as the nitride semiconductor of the present embodiment.
- an AlN initial growth layer 22 made of AlN and having a thickness of 100 nm and an Al 0.2 Ga 0.8 N buffer layer 23 having a thickness of 20 nm are sequentially formed on an Si substrate 21.
- a superlattice buffer layer 24 having a repetition cycle of 100 cycles in which an AlN layer having a thickness of 3 nm and an Al 0.1 Ga 0.9 N layer having a thickness of 25 nm are alternately stacked is formed.
- a channel layer 25 composed of a plurality of layers is formed on the superlattice buffer layer 24.
- the channel layer 25 is formed by laminating an Al z Ga 1-z N layer 26, an Al composition gradient AlGaN layer 27, and a GaN channel region 28 as the GaN layer in this order.
- the Al composition z in the Al z Ga 1-z N layer 26 of the channel layer 25 is such that the superlattice buffer layer 24 has a composition of Al x Ga 1-x N (0.5 ⁇ x ⁇ 1.0).
- the Al 0.2 Ga 0.8 N layer 26 is grown with a thickness of 1 ⁇ m.
- an Al composition graded AlGaN layer 27 having a thickness of 100 nm is grown on the Al 0.2 Ga 0.8 N layer 26 with the Al composition graded sequentially from 0.2 to 0 from the Si substrate 21 side. Further, the GaN channel region 28 is grown with a thickness of 20 nm, and the channel layer 25 is formed.
- the thickness “a” of Al x Ga 1-x N (0.5 ⁇ x ⁇ 1.0), which is the high Al-containing layer in the superlattice buffer layer 24, is 1 nm. ⁇ a ⁇ 5 nm, and the thickness “b” of Al y Ga 1-y N (0 ⁇ y ⁇ 0.3), which is the low Al-containing layer, is 22 nm ⁇ b ⁇ 30 nm. Therefore, the difference between the thickness “a” of the high Al-containing layer and the thickness “b” of the low Al-containing layer is set to at least 17 nm or more to effectively suppress the warp of the resulting nitride semiconductor epitaxial wafer. Can do.
- Al 0.4 Ga 0.6 N of the AlGaN barrier layer 29 continues in thickness 15nm is grown.
- an AlN intermediate layer (not shown) made of AlN may be grown between the GaN channel region 28 and the AlGaN barrier layer 29 in order to improve mobility.
- a GaN cap layer (not shown) made of GaN may be grown on the AlGaN barrier layer 29.
- the AlGaN layer 26 the Al composition gradient AlGaN layer 27 and the GaN channel whose Al composition is given by the above formula (1)
- the channel layer 25 is formed by growing the regions 28 in this order.
- the AlGaN layer 26 having the same Al composition as the average Al composition of the superlattice is formed on the AlGaN superlattice buffer layer 24.
- a nitride semiconductor epitaxial wafer can be obtained.
- the present invention is not limited to this combination.
- FIG. 5 shows the CV measurement result in the HEMT formed using the obtained nitride semiconductor epitaxial wafer.
- FIG. 5A shows the case of this embodiment using a combination of the GaN channel region 28, the Al composition gradient AlGaN layer 27, and the AlGaN layer 26 as the channel layer 25.
- FIG. 5B shows a comparative example in which only the GaN layer is used as the channel layer.
- the CV measurement method is the same as that in the first embodiment (FIG. 3).
- an Al z Ga 1-z N layer having the same Al composition z as the average Al composition of the superlattice is formed on the AlGaN superlattice buffer layer 24. 26 is formed. Therefore, as in the case of the first embodiment described above, two-dimensional holes formed between the superlattice buffer layer 24 and the GaN layer by the AlGaN layer 26 formed on the superlattice buffer layer 24. Gas compensation can be performed to reduce the leakage current.
- an Al composition gradient AlGaN layer 27 is formed between the AlGaN layer 26 and the GaN channel region 28 as the channel layer 25.
- GaN layer (GaN channel region 28) having a lattice constant of 2 is required. In that case, the GaN channel region 28 is laminated on the AlGaN layer 26, and a structure in which a two-dimensional hole gas is formed as shown in FIG.
- the distortion generated in the GaN channel region 28 is generated.
- a larger strain can be generated at the interface between the Al w Ga 1-w N barrier layer 29 and the GaN channel region 28 than at the interface between the GaN channel region 28 and the Al composition gradient AlGaN layer 27. Electron gas can be generated.
- the Al composition “w” of the Al w Ga 1-w N barrier layer 29 is the Al composition of the Al z Ga 1-z N layer 26 in the channel layer 25. In order to generate a two-dimensional electron gas, it is desirable to make it larger than z ”.
- nitride semiconductor chip as another example of the nitride semiconductor can be obtained by dicing the nitride semiconductor epitaxial wafer in each of the above embodiments.
- the nitride semiconductor of the present invention is Substrates 1, 21; Initial growth layers 2 and 22 formed on the substrates 1 and 21; Buffer layers 3 and 23 formed on the initial growth layers 2 and 22; Superlattice buffer layers 4, 24 formed on the buffer layers 3, 23; Channel layers 5, 25 comprising a plurality of layers formed on the superlattice buffer layers 4, 24; Barrier layers 8 and 29 formed on the channel layers 5 and 25, and
- the superlattice buffer layers 4 and 24 include a high Al-containing layer having a thickness a and a composition of Al x Ga 1-x N (0.5 ⁇ x ⁇ 1.0), and Al y Ga 1-y N ( And a low Al-containing layer having a thickness b having a composition of 0 ⁇ y ⁇ 0.3) is alternately laminated.
- the channel layers 5 and 25 are joined to the superlattice buffer layers 4 and 24, and at least the Al z Ga 1-z N layers 6 and 26 and the GaN layer 7 in this order from the superlattice buffer layers 4 and 24 side. , 28 are laminated and formed,
- the Al composition of the Al z Ga 1-z layers 6 and 26 is characterized by being the same as the average Al composition of the superlattice buffer layers 4 and 24.
- the AlGaN superlattice buffer layers 4 and 24 are equivalent to the AlGaN layer whose stress is relaxed. Therefore, when the channel layers 5 and 25 that are joined to the AlGaN superlattice buffer layers 4 and 24 are formed of only the GaN layer, the GaN channel layer formed on the AlGaN layer in which the stress is relaxed is more than the AlGaN layer. However, since the lattice constant is large, it is distorted on the tensile side due to the stress - ⁇ , and two-dimensional hole gas (2DHG) is formed at the interface.
- 2DHG two-dimensional hole gas
- the channel layers 5 and 25 joined to the superlattice buffer layers 4 and 24 are arranged in order from the superlattice buffer layers 4 and 24 side by Al z Ga 1-z layers 6 and 26 and GaN layers 7 and 28, and the Al composition of the Al z Ga 1-z layers 6 and 26 is the same as the average Al composition of the AlGaN superlattice buffer layers 4 and 24. Therefore, the Al z Ga 1-z layers 6 and 26 can be regarded as having substantially the same lattice constant as the AlGaN superlattice buffer layers 4 and 24, which are equivalent to one AlGaN layer whose stress is relaxed. Therefore, it is possible to suppress the formation of two-dimensional hole gas due to distortion caused by stress - ⁇ at the interface between the AlGaN superlattice buffer layers 4 and 24 and the Al z GaN 1-z layers 6 and 26. it can.
- the Al z Ga 1-z layers 6 and 26 formed on the superlattice buffer layers 4 and 24 are formed between the superlattice buffer layers 4 and 24 and the GaN layers 7 and 28. It is possible to compensate for the dimensional hole gas and to reduce the leakage current.
- the barrier layer 8 includes an Al w Ga 1-w N layer 8,
- the Al composition w in the Al w Ga 1-w N layer 8 is larger than the Al composition z in the Al z Ga 1-z layer 6 of the channel layer 5.
- the Al composition w in the Al w Ga 1-w N layer 8 is set to a value larger than the Al composition z in the Al z Ga 1-z layer 6 of the channel layer 5. Yes. Therefore, the interface between the Al w Ga 1-w N layer 8 of the barrier layer 8 and the GaN layer 7 of the channel layer 5 is closer than the interface between the GaN layer 7 and the Al z Ga 1-z layer 6. A large strain can be generated, and a two-dimensional electron gas can be formed at the interface.
- the range of the thickness a of the high Al-containing layer in the superlattice buffer layers 4 and 24 is 1 nm ⁇ a ⁇ 5 nm, and the range of the thickness b of the low Al-containing layer is 22 nm ⁇ b ⁇ 30 nm.
- the difference between the thickness “a” of the high Al-containing layer and the thickness “b” of the low Al-containing layer in the AlGaN superlattice buffer layers 4, 24 is at least 17 nm or more.
- the thickness “a” of the high Al-containing layer which is easily warped is made thinner than the thickness “b” of the low Al-containing layer which is difficult to warp, thereby effectively suppressing the warp of the resulting nitride semiconductor. be able to.
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- Junction Field-Effect Transistors (AREA)
- Recrystallisation Techniques (AREA)
Abstract
Description
基板と、
上記基板上に形成された初期成長層と、
上記初期成長層上に形成されたバッファ層と、
上記バッファ層上に形成され超格子バッファ層と、
上記超格子バッファ層上に形成された複数の層からなるチャネル層と、
上記チャネル層上に形成された障壁層と
を備え、
上記超格子バッファ層は、AlxGa1-xN(0.5≦x≦1.0)の組成からなる厚さaの高Al含有層と、AlyGa1-yN(0≦y≦0.3)の組成からなる厚さbの低Al含有層とが交互に積層されて形成されており、
上記チャネル層は、上記超格子バッファ層と接合すると共に、上記超格子バッファ層の側から順に、少なくともAlzGa1-zN層とGaN層とが積層されて形成されており、
上記AlzGa1-zN層のAl組成は、上記超格子バッファ層の平均Al組成と同じである
ことを特徴としている。
上記チャネル層の上記AlzGa1-zN層におけるAl組成zは、以下の式
z=(a×x+b×y)/(a+b)
で与えられる。
上記障壁層はAlwGa1-wN層を含んでおり、
上記AlwGa1-wN層におけるAl組成wは、上記チャネル層の上記AlzGa1-zN層におけるAl組成zよりも大きい値である。
上記超格子バッファ層における上記高Al含有層の厚さaの範囲は1nm≦a≦5nmであり、上記低Al含有層の厚さbの範囲は22nm≦b≦30nmである。
図1は、本実施の形態の上記窒化物半導体としての窒化物半導体エピタキシャルウエハにおける断面図である。図1において、Si基板1上に、AlNからなる厚さ100nmのAlN初期成長層2、厚さ20nmのAl0.2Ga0.8Nバッファ層3が順次形成されている。引き続き、4nm厚さのAlN層と23nm厚さのAl0.1Ga0.9N層とを交互に繰り返して積層する繰り返し周期が100周期である超格子バッファ層4が形成されている。
z=(a×x+b×y)/(a+b) …(1)
z=(4×1+23×0.1)/(4+23)=0.23
となり、Al0.23Ga0.77N層6が厚さ1μmで成長されることになる。
図4は、本実施の形態の上記窒化物半導体としての窒化物半導体エピタキシャルウエハにおける断面図である。図4において、Si基板21上に、AlNからなる厚さ100nmのAlN初期成長層22、厚さ20nmのAl0.2Ga0.8Nバッファ層23が順次形成されている。続いて、3nm厚さのAlN層と25nm厚さのAl0.1Ga0.9N層とを交互に繰り返して積層する繰り返し周期が100周期である超格子バッファ層24が形成されている。
z=(3×1+25×0.1)/(3+25)=0.20
となり、Al0.2Ga0.8N層26が厚さ1μmで成長されることになる。
基板1,21と、
上記基板1,21上に形成された初期成長層2,22と、
上記初期成長層2,22上に形成されたバッファ層3,23と、
上記バッファ層3,23上に形成され超格子バッファ層4,24と、
上記超格子バッファ層4,24上に形成された複数の層からなるチャネル層5,25と、
上記チャネル層5,25上に形成された障壁層8,29と
を備え、
上記超格子バッファ層4,24は、AlxGa1-xN(0.5≦x≦1.0)の組成からなる厚さaの高Al含有層と、AlyGa1-yN(0≦y≦0.3)の組成からなる厚さbの低Al含有層とが交互に積層されて形成されており、
上記チャネル層5,25は、上記超格子バッファ層4,24と接合すると共に、上記超格子バッファ層4,24の側から順に、少なくともAlzGa1-zN層6,26とGaN層7,28とが積層されて形成されており、
上記AlzGa1-z層6,26のAl組成は、上記超格子バッファ層4,24の平均Al組成と同じである
ことを特徴としている。
上記チャネル層5,25の上記AlzGa1-z層6,26におけるAl組成zは、以下の式
z=(a×x+b×y)/(a+b)
で与えられる。
上記障壁層8はAlwGa1-wN層8を含んでおり、
上記AlwGa1-wN層8におけるAl組成wは、上記チャネル層5の上記AlzGa1-z層6におけるAl組成zよりも大きい値である。
上記超格子バッファ層4,24における上記高Al含有層の厚さaの範囲は1nm≦a≦5nmであり、上記低Al含有層の厚さbの範囲は22nm≦b≦30nmである。
2,22…AlN初期成長層、
3,23…AlGaNバッファ層、
4,24…超格子バッファ層、
5,25…チャネル層、
6,26…AlzGa1-zN層、
7,28…GaNチャネル領域、
8,29…AlGaN障壁層、
10…HEMT、
11…ステージ、
12…LCRメータ、
13,30…キャリア濃度ピーク、
27…Al組成傾斜AlGaN層。
Claims (4)
- 基板(1,21)と、
上記基板(1,21)上に形成された初期成長層(2,22)と、
上記初期成長層(2,22)上に形成されたバッファ層(3,23)と、
上記バッファ層(3,23)上に形成され超格子バッファ層(4,24)と、
上記超格子バッファ層(4,24)上に形成された複数の層からなるチャネル層(5,25)と、
上記チャネル層(5,25)上に形成された障壁層(8,29)と
を備え、
上記超格子バッファ層(4,24)は、AlxGa1-xN(0.5≦x≦1.0)の組成からなる厚さaの高Al含有層と、AlyGa1-yN(0≦y≦0.3)の組成からなる厚さbの低Al含有層とが交互に積層されて形成されており、
上記チャネル層(5,25)は、上記超格子バッファ層(4,24)と接合すると共に、上記超格子バッファ層(4,24)の側から順に、少なくともAlzGa1-zN層(6,26)とGaN層(7,28)とが積層されて形成されており、
上記AlzGa1-zN層(6,26)のAl組成は、上記超格子バッファ層(4,24)の平均Al組成と同じである
ことを特徴とする窒化物半導体。 - 請求項1に記載の窒化物半導体において、
上記チャネル層(5,25)の上記AlzGa1-zN層(6,26)におけるAl組成zは、以下の式
z=(a×x+b×y)/(a+b)
で与えられる
ことを特徴とする窒化物半導体。 - 請求項1または請求項2に記載の窒化物半導体において、
上記障壁層(8)はAlwGa1-wN層を含んでおり、
上記AlwGa1-wN層(8)におけるAl組成wは、上記チャネル層(5)の上記AlzGa1-zN層(6)におけるAl組成zよりも大きい値である
ことを特徴とする窒化物半導体。 - 請求項1から請求項3までの何れか一つに記載の窒化物半導体において、
上記超格子バッファ層(4,24)における上記高Al含有層の厚さaの範囲は1nm≦a≦5nmであり、上記低Al含有層の厚さbの範囲は22nm≦b≦30nmである
ことを特徴とする窒化物半導体。
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN106711212A (zh) * | 2016-12-31 | 2017-05-24 | 华南理工大学 | 基于Si衬底AlGaN/GaN异质结基的增强型HEMT器件及其制造方法 |
| US11581269B2 (en) | 2019-10-17 | 2023-02-14 | Samsung Electronics Co., Ltd. | Semiconductor thin film structures and electronic devices including the same |
Families Citing this family (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20170207303A1 (en) * | 2015-04-03 | 2017-07-20 | Hermes-Epitek Corp. | Semiconductor multilayer structure |
| US10586701B2 (en) * | 2016-02-26 | 2020-03-10 | Sanken Electric Co., Ltd. | Semiconductor base having a composition graded buffer layer stack |
| US9768258B1 (en) * | 2016-03-17 | 2017-09-19 | Infineon Technologies Austria Ag | Substrate structure, semiconductor component and method |
| WO2018120363A1 (zh) * | 2016-12-31 | 2018-07-05 | 华南理工大学 | 基于Si衬底的GaN基增强型HEMT器件及其制造方法 |
| JP2021144993A (ja) * | 2020-03-10 | 2021-09-24 | 富士通株式会社 | 半導体装置 |
| CN111599854A (zh) * | 2020-06-04 | 2020-08-28 | 芜湖启迪半导体有限公司 | 一种3C-SiC外延结构 |
| CN115020481B (zh) * | 2022-06-08 | 2025-10-17 | 世创微(福建)电子有限公司 | 一种氮化物外延层及其制备方法与功率射频器件 |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2011023642A (ja) * | 2009-07-17 | 2011-02-03 | Sharp Corp | エピタキシャルウェハ |
| WO2011055774A1 (ja) * | 2009-11-06 | 2011-05-12 | 日本碍子株式会社 | 半導体素子用エピタキシャル基板、半導体素子、および半導体素子用エピタキシャル基板の製造方法 |
| WO2011102044A1 (ja) * | 2010-02-16 | 2011-08-25 | 日本碍子株式会社 | エピタキシャル基板およびエピタキシャル基板の製造方法 |
| WO2011155496A1 (ja) * | 2010-06-08 | 2011-12-15 | 日本碍子株式会社 | エピタキシャル基板およびエピタキシャル基板の製造方法 |
Family Cites Families (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3960957B2 (ja) | 2003-09-05 | 2007-08-15 | 古河電気工業株式会社 | 半導体電子デバイス |
| JP5580009B2 (ja) * | 2009-08-28 | 2014-08-27 | 日本碍子株式会社 | 半導体素子用エピタキシャル基板、半導体素子、および、半導体素子用エピタキシャル基板の作製方法 |
| EP2555232A4 (en) * | 2010-03-24 | 2014-12-10 | Ngk Insulators Ltd | EPITACTICAL SUBSTRATE FOR A SEMICONDUCTOR ELEMENT AND SEMICONDUCTOR ELEMENT |
| JP2011258782A (ja) * | 2010-06-10 | 2011-12-22 | Covalent Materials Corp | 窒化物半導体基板 |
| EP2600394B1 (en) * | 2010-07-29 | 2017-12-27 | NGK Insulators, Ltd. | Epitaxial substrate for semiconductor element and production method thereof |
| EP2610898B1 (en) * | 2010-08-25 | 2020-11-25 | NGK Insulators, Ltd. | Method for fabricating epitaxial substrate for semiconductor device, and method for fabricating semiconductor device |
| JP2012109344A (ja) * | 2010-11-16 | 2012-06-07 | Rohm Co Ltd | 窒化物半導体素子および窒化物半導体パッケージ |
| CN103828030B (zh) * | 2012-08-10 | 2017-11-10 | 日本碍子株式会社 | 半导体元件、hemt元件、以及半导体元件的制造方法 |
| JP2014072431A (ja) * | 2012-09-28 | 2014-04-21 | Fujitsu Ltd | 半導体装置 |
-
2014
- 2014-09-01 WO PCT/JP2014/072883 patent/WO2015068448A1/ja not_active Ceased
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2011023642A (ja) * | 2009-07-17 | 2011-02-03 | Sharp Corp | エピタキシャルウェハ |
| WO2011055774A1 (ja) * | 2009-11-06 | 2011-05-12 | 日本碍子株式会社 | 半導体素子用エピタキシャル基板、半導体素子、および半導体素子用エピタキシャル基板の製造方法 |
| WO2011102044A1 (ja) * | 2010-02-16 | 2011-08-25 | 日本碍子株式会社 | エピタキシャル基板およびエピタキシャル基板の製造方法 |
| WO2011155496A1 (ja) * | 2010-06-08 | 2011-12-15 | 日本碍子株式会社 | エピタキシャル基板およびエピタキシャル基板の製造方法 |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106711212A (zh) * | 2016-12-31 | 2017-05-24 | 华南理工大学 | 基于Si衬底AlGaN/GaN异质结基的增强型HEMT器件及其制造方法 |
| US11581269B2 (en) | 2019-10-17 | 2023-02-14 | Samsung Electronics Co., Ltd. | Semiconductor thin film structures and electronic devices including the same |
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