WO2015051663A1 - 阵列基板及其驱动方法、显示装置 - Google Patents

阵列基板及其驱动方法、显示装置 Download PDF

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Publication number
WO2015051663A1
WO2015051663A1 PCT/CN2014/083352 CN2014083352W WO2015051663A1 WO 2015051663 A1 WO2015051663 A1 WO 2015051663A1 CN 2014083352 W CN2014083352 W CN 2014083352W WO 2015051663 A1 WO2015051663 A1 WO 2015051663A1
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Prior art keywords
electrode
common electrode
common
array substrate
strip
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Ceased
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PCT/CN2014/083352
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English (en)
French (fr)
Inventor
曲莹莹
张洪林
王丹
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BOE Technology Group Co Ltd
Beijing BOE Display Technology Co Ltd
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BOE Technology Group Co Ltd
Beijing BOE Display Technology Co Ltd
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Priority to US14/429,105 priority Critical patent/US9436044B2/en
Publication of WO2015051663A1 publication Critical patent/WO2015051663A1/zh
Anticipated expiration legal-status Critical
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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3696—Generation of voltages supplied to electrode drivers
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/133345—Insulating layers
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134318—Electrodes characterised by their geometrical arrangement having a patterned common electrode
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134381—Hybrid switching mode, i.e. for applying an electric field with components parallel and orthogonal to the substrates
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/12—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode
    • G02F2201/121—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode common or background
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/12—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode
    • G02F2201/124—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode interdigital
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections

Definitions

  • Embodiments of the present invention relate to an array substrate, a driving method thereof, and a display device. Background technique
  • liquid crystal display technology people have higher requirements for the resolution of liquid crystal display products.
  • ADS Advanced Super Dimension Switch
  • the transmittance is only about 78% of the TN mode (Twisted Nematic). Therefore, Improving the transmission rate of the ADS mode is particularly important.
  • Fig. 1 is a view showing the structure of an array substrate of an ADS mode liquid crystal display panel.
  • the substrate 1 includes: a pixel electrode 5, a common electrode 6, and a passivation layer 7.
  • the common electrode 6 and the pixel electrode 5 are designed in a slit shape on the substrate 1.
  • FIG. 2 under the action of an electric field formed between the slit-shaped common electrode 6 and the pixel electrode 5, the liquid crystal molecules are rotated by the electric field formed by the pixel electrode and the common electrode to make the display panel transmittance.
  • the liquid crystal molecular distribution diagram shows the situation shown in FIG. 2, and the display function is realized. Summary of the invention
  • One aspect of the present invention provides an array substrate including gate lines and data lines, and a plurality of pixel units defined by the gate lines and the data lines, each of the pixel units including a common electrode and a pixel electrode.
  • the common electrode and the pixel electrode are located in different film layers and insulated by an insulating layer, the common electrode includes a first common electrode and a second common electrode, and the first common electrode is connected to the first common electrode line, The second common electrode is connected to the second common electrode line, the first common electrode and the second common electrode are both slit-shaped electrodes and respectively include a plurality of first strip electrodes and a plurality of second strip electrodes, and The first strip electrode and the second strip electrode are alternately disposed to form an electric field with the pixel electrode, respectively.
  • the pixel electrode is a slit electrode and includes a plurality of third strip electrodes, a third strip electrode of the pixel electrode and a first strip electrode of the first common electrode and the a second strip electrode of the second common electrode is alternately disposed, and a third strip shape of the pixel electrode is spaced apart between the first strip electrode of the adjacent first common electrode and the second strip electrode of the second common electrode Electricity Extreme.
  • the first common electrode and the second common electrode are located in the same film layer, and the first common electrode and the second common electrode are both located on the base substrate of the pixel electrode away from the array substrate.
  • One side, or both the first common electrode and the second common electrode are located on a side of the substrate electrode adjacent to the array substrate of the array substrate.
  • the first common electrode and the second common electrode are located in different film layers, and the first common electrode and the second common electrode are both located on a base substrate of the pixel electrode away from the array substrate.
  • One side, or the first common electrode and the second common electrode are both located on a side of the substrate electrode adjacent to the array substrate, or the first common electrode is located away from the array substrate of the pixel electrode
  • One side of the base substrate and the second common electrode are located on a side of the substrate electrode adjacent to the array substrate.
  • a distance between projections of the first strip electrode of the adjacent first common electrode and the second strip electrode of the second common electrode on the substrate is greater than the pixel electrode The width of the third strip electrode.
  • the distance between the first strip electrode of the first common electrode and the third strip electrode of the pixel electrode in a direction parallel to the array substrate is 0 to 0.6 ⁇ m
  • the second common electrode a distance between the second strip electrode and the third strip electrode of the pixel electrode in a direction parallel to the array substrate is 0 to 0.6 ⁇ m
  • the first strip electrode, the second strip electrode, and the first The width of the three strip electrodes is 2 ⁇ 2.6 ⁇ m.
  • the pixel electrode is a plate electrode
  • the first common electrode and the second common electrode are both located in the same film layer or different film layers on the side of the substrate electrode away from the substrate substrate of the array substrate.
  • a further aspect of the present invention provides a method for driving an array substrate, wherein the array substrate is any one of the array substrates described above; the driving method includes: applying a first common voltage to the first common electrode through the first common electrode line And applying a second common voltage to the second common electrode through the second common electrode line, the second common voltage being different from the first common voltage.
  • the driving method further includes: providing a pixel voltage signal to the pixel electrode through the data line, the pixel voltage signal being between the first common voltage and the second common voltage.
  • FIG. 1 is a schematic structural view of an array substrate in a liquid crystal display device
  • FIG. 2 is a schematic diagram of simulation of light transmittance of a liquid crystal display device
  • FIG. 3 is a schematic plan view showing an example of an array substrate according to an embodiment of the present invention
  • FIG. 4 is a schematic cross-sectional view showing an example of an array substrate according to Embodiment 1 of the present invention; Transmittance simulation diagram;
  • FIG. 6 is a schematic cross-sectional view showing an example of an array substrate according to an embodiment of the present invention
  • FIG. 7 is a schematic cross-sectional view showing an example of an array substrate according to Embodiment 2 of the present invention; Transmittance simulation diagram;
  • FIG. 9 is a schematic cross-sectional view showing another example of an array substrate according to a second embodiment of the present invention.
  • FIG. 10 is a schematic diagram showing a simulation of light transmittance according to a second embodiment of the present invention.
  • FIG. 11 is a schematic cross-sectional view showing an example of an array substrate according to a second embodiment of the present invention
  • FIG. 12 is a schematic cross-sectional view showing an example of an array substrate according to Embodiment 3 of the present invention
  • FIG. 14 is a cross-sectional view showing an example of a liquid crystal display device according to Embodiment 4 of the present invention.
  • FIG. 15 is a flow chart showing a driving method of an array substrate according to Embodiment 5 of the present invention. detailed description
  • the relative positional relationship is It may also change accordingly.
  • the inventors have noticed that among the array substrates shown in FIGS. 1 and 2, since the voltages of the common electrodes of the array substrate are the same, the transmittance of the liquid crystal panel is not high.
  • the present embodiment provides an array substrate.
  • the array substrate of this embodiment is shown in FIG. 3 and FIG. 4, FIG. 3 is a schematic diagram of a pixel unit on the array substrate, and FIG. 4 is a cross-sectional view of the array substrate shown in FIG.
  • the array substrate includes gate lines 12 and data lines 11 formed on the base substrate 1, and a plurality of pixel units defined by the gate lines 12 and the data lines 11, each of the pixel units including the common electrodes 2, 3 And the pixel electrode 5, the pixel electrode 5 and the common electrode 2, 3 are formed in different film layers of the array substrate, and are insulated by the insulating layer.
  • the common electrodes 2, 3 include: a first common electrode 2 and a second common electrode 3 for respectively connecting different signal lines, and the first common electrode 2 and the second common electrode 3 are slit-shaped electrodes.
  • the first common electrode 2 includes a plurality of first strip electrodes
  • the second common electrode 3 includes a plurality of second strip electrodes
  • the first strip electrodes and the second strip electrodes are alternately arranged for respectively corresponding to the pixels
  • the electrode 5 forms a multi-dimensional electric field.
  • the pixel electrode 5 is connected to the drain electrode 13 of the thin film transistor through the via 15, the source 14 of the thin film transistor is connected to the data line 11, and the gate of the thin film transistor is connected to the gate line 12.
  • the surface of the pixel electrode 5 may also be covered with a passivation layer 7.
  • the pixel electrode 5 is a slit electrode.
  • the pixel electrode 5 includes a plurality of third strip electrodes, and the third strip electrodes of the pixel electrodes 5, the first strip electrodes of the first common electrode 2, and the second strip electrodes of the second common electrode 3 are alternately disposed.
  • a third strip electrode of the pixel electrode 5 is spaced apart between the first strip electrode of the adjacent first common electrode 2 and the second strip electrode of the second common electrode 3.
  • the first common electrode 2 and the second common electrode 3 are located on the same film layer, and the first common electrode 2 and the second common electrode 3 are both located on the side of the substrate electrode of the pixel electrode 5 away from the array substrate, or the first common electrode 2 and The second common electrodes 3 are both located on the side of the substrate electrode 5 adjacent to the array substrate.
  • the first common electrode 2 and the second common electrode 3 are located in the same layer, and are located at different layers from the pixel electrode 5, and the first common electrode 2 and the second common electrode 3 are both located near the array of the pixel electrodes 5.
  • the pixel electrode 5 is located above the first common electrode 2 and the second common electrode 3 in FIG.
  • the first common electrode 2, the second common electrode 3, and the pixel electrode 5 are all slit-shaped electrodes, and the third strip electrode of the pixel electrode 5, the first strip electrode of the first common electrode 2, and the second common electrode 3
  • the second strip electrodes are alternately arranged, adjacent to the first common electrode 2
  • a third strip electrode of the pixel electrode 5 is spaced between the first strip electrode and the second strip electrode of the second common electrode 3.
  • the projection of the first strip electrode of the adjacent first common electrode 2 and the second strip electrode of the second common electrode 3 on the base substrate 1 is larger than the width of the third strip electrode of the pixel electrode 5.
  • a transverse electric field is formed between the first common electrode 2 and the second common electrode 3, the pixel electrode 5 forms a multi-dimensional electric field with the first common electrode 2, and the pixel electrode 5 and the second common electrode 3 form a multi-dimensional electric field.
  • the interval g between the first common electrode 2, the second common electrode 3, and the pixel electrode 5 is the same.
  • the widths of the three are the same, for example, 0 ⁇ g ⁇ 0 ⁇ m, and the electrode width is 2.6 ⁇ m.
  • the first common electrode 2 and the second common electrode 3 are respectively connected to different signal lines to load different voltages.
  • the polarities of the first common electrode 2 and the second common electrode 3 are different, that is, the voltage polarity of the first common electrode 2 is positive, and the voltage polarity of the second common electrode 3 is Sex is negative (and vice versa).
  • the voltage of the pixel electrode 5 may be between the voltages of the first common electrode 2 and the second common electrode 3. For example: a voltage (.
  • V c ml and V ⁇ m2) a first common electrode 2 and the second common electrode 3 is equal to the absolute value of the voltage polarity of the first common electrode 2 is positive, the second common electrode voltage polarity 3 Negative, the voltage V pixel of the pixel electrode 5 is between V ⁇ ml and V com2 , and _ CO m2 '
  • i _ Vpixdl I Vpi xel _
  • FIG. 5 is a schematic diagram showing the light transmittance simulation of the array substrate of FIG. 4.
  • the first common electrode and the second common electrode respectively form a multi-dimensional electric field with the pixel electrode, so that the liquid crystal molecules above the pixel electrode are sufficiently horizontally rotated to improve the transmittance.
  • FIG. 6 Another array substrate structure of the embodiment of the present invention is as shown in FIG. 6.
  • the first common electrode 2 and the second common electrode 3 are located in the same layer, and are located at different layers from the pixel electrode 5, and the first common electrode 2 and the second The common electrodes 3 are located on the side of the substrate electrode of the pixel electrode 5 remote from the array substrate.
  • the pixel electrode 5 in Fig. 6 is located below the first common electrode 2 and the second common electrode 3.
  • a transverse electric field is formed between the first common electrode 2 and the second common electrode 3
  • the pixel electrode 5 forms a multi-dimensional electric field with the first common electrode 2, and the pixel electrode 5 and the second common electrode 3 are formed.
  • the multi-dimensional electric field, the effect achieved by the array substrate of FIG. 6 is substantially the same as that achieved by the array substrate shown in FIG. 4, and details are not described herein again.
  • the array substrate provided in this embodiment is ADS (Advanced) of planar electric field wide viewing angle technology.
  • ADS Advanced
  • Super Dimension Switch, advanced super-dimensional field conversion technology) mode which forms a multi-dimensional electric field by the electric field generated by the slit-shaped electrode edge in the same plane and the electric field generated between the slit-shaped electrode layer and the plate-shaped electrode layer, so that the liquid crystal cell is narrow All the aligned liquid crystal molecules directly between the slit electrodes and the electrodes can be rotated, thereby improving the liquid crystal working efficiency and increasing the light transmission efficiency.
  • FIG. 7 is a schematic structural diagram of an example of an array substrate provided by the embodiment.
  • the pixel electrode 5, the first common electrode 2, and the second common electrode 3 are located in different layers, and all three are slit electrodes.
  • the first common electrode 2 is located on the side of the substrate electrode 1 away from the array substrate of the pixel electrode 5 and the second common electrode 3 is located on the side of the substrate electrode 1 of the pixel electrode 5 which is adjacent to the array substrate.
  • the first common electrode 2 is located above the substrate 1, and the layer of the pixel electrode 5 is located between the layers where the first common electrode 2 and the second common electrode 3 are located, the pixel electrode 5 and the first common electrode 2 and the second
  • the common electrodes 3 are spaced apart by insulating layers 8 and 8', respectively.
  • a passivation layer 7 is also formed on the second common electrode 3.
  • the array substrate shown in FIG. 7 works on the principle that the first common electrode 2 and the second common electrode 3 respectively form a multi-dimensional electric field with the pixel electrode 5, and a multi-dimensional electric field is formed between the first common electrode 2 and the second common electrode 3.
  • the combined electric field of the three multi-dimensional electric fields causes the liquid crystal molecules to rotate in the same direction in the horizontal direction, the horizontal rotation angle of the liquid crystal molecules is larger.
  • the effect achieved is shown in Fig. 8.
  • the liquid crystal molecules above the pixel electrode are rotated horizontally to increase the transmittance.
  • FIG. 9 is a schematic structural diagram of still another example of an array substrate according to an embodiment of the present invention.
  • the pixel electrode 5, the first common electrode 2, and the second common electrode 3 are located in different layers, all of which are slit-shaped electrodes, and the first common electrode 2 and the second common electrode 3 are located near the array substrate of the pixel electrode 5.
  • the second common electrode 3 is located on the base substrate 1, and the layer of the first common electrode 2 is located between the layer where the pixel electrode 5 and the second common electrode 3 are located, and the first common electrode 2 and the second common electrode 3 are
  • the pixel electrodes 5 are spaced apart by insulating layers 8 and 8', respectively, and a passivation layer 7 is formed on the pixel electrodes 5.
  • the first common electrode 2 and the second common electrode 3 respectively form a multi-dimensional electric field with the pixel electrode 5, and a multi-dimensional electric field is formed between the first common electrode 2 and the second common electrode 3, when When the combined electric fields of the three multi-dimensional electric fields cause the liquid crystal molecules to rotate in the same direction in the horizontal direction, the horizontal rotation angle of the liquid crystal molecules is larger.
  • the effect achieved is shown in Fig. 10.
  • the liquid crystal molecules above the pixel electrode are rotated horizontally to increase the transmittance.
  • FIG. 11 is a schematic structural diagram of another example of an array substrate provided by the embodiment.
  • the pixel electrode 5, the first common electrode 2, and the second common electrode 3 are located in different layers, all of which are equivalent to slit electrodes, and the first common electrode 2 and the second common electrode 3 are located at a distance from the pixel electrode 5.
  • the pixel electrode 5 is located on the base substrate 1, and the layer of the first common electrode 2 is located between the layer where the pixel electrode 5 and the second common electrode 3 are located, the first common electrode 2 and the pixel electrode 5 and the second common electrode. 3 are respectively separated by insulating layers 8 and 8', and a passivation layer 7 is further formed on the second common electrode 3.
  • FIG. 11 is a schematic structural diagram of another example of an array substrate provided by the embodiment.
  • the pixel electrode 5, the first common electrode 2, and the second common electrode 3 are located in different layers, all of which are equivalent to slit electrodes, and the first common electrode 2 and the second common electrode 3
  • the first common electrode 2 and the second common electrode 3 respectively form a multi-dimensional electric field with the pixel electrode 5, and a multi-dimensional electric field is also formed between the first common electrode 2 and the second common electrode 3.
  • the effect achieved by the array substrate is substantially the same as that achieved by the array substrate shown in FIG. 9, and details are not described herein again.
  • the projection between the first strip electrode of the adjacent first common electrode 2 and the second strip electrode of the second common electrode 3 on the base substrate 1 is larger than the pixel electrode 5
  • the first strip electrode of the first common electrode 2 and the third strip electrode of the pixel electrode 5 have a distance of 0 to 0.6 ⁇ m in a direction parallel to the array substrate.
  • the second strip electrode of the second common electrode 5 and the third strip electrode of the pixel electrode 5 have a distance of 0 to 0.6 ⁇ m in a direction parallel to the array substrate.
  • the first strip electrode of the first common electrode 2 and the third strip electrode of the pixel electrode 5 are in a direction parallel to the array substrate and the second strip electrode of the second common electrode 3 and the third strip of the pixel electrode 5
  • the electrodes are equidistant in a direction parallel to the array substrate.
  • the widths of the first strip electrode, the second strip electrode and the third strip electrode are respectively 2 ⁇ 2.6 ⁇ .
  • FIG. 12 is a schematic structural diagram of an example of an array substrate according to an embodiment of the present invention.
  • the array substrate includes a pixel electrode 5 (which is a plate electrode) formed on the substrate 1 .
  • the common electrodes 2, 3 (which are slit-shaped electrodes), wherein the common electrode comprises: a first common electrode 2 and a second common electrode 3 for respectively connecting different signal lines, the first common electrode 2 being connected to the first common
  • the second common electrode 3 is connected to the second common electrode line.
  • the first common electrode 2 and the second common electrode 3 are slit electrodes, and are alternately disposed.
  • the common electrode and the pixel electrode 5 are separated by an insulating layer 9 . And for forming a multi-dimensional electric field with the pixel electrode 5, respectively.
  • the surfaces of the first common electrode 2 and the second common electrode 3 also cover the passivation layer 7.
  • the pixel electrode 5 is a plate electrode formed on the base substrate 1, and the first common electrode 2 and the second common electrode 3 are both located above the pixel electrode 5.
  • the first common electrode 2 and the second common electrode 3 are distributed in the same layer and are uniform It is formed above the insulating layer 9.
  • a multi-dimensional electric field is formed between the pixel electrode 5 and the first common electrode 2
  • a multi-dimensional electric field is formed between the pixel electrode 5 and the second common electrode 3
  • a transverse electric field is also formed between the first common electrode 2 and the second common electrode 3.
  • FIG. 13 a schematic structural diagram of an example of an array substrate according to an embodiment of the present invention is provided.
  • the first common electrode 2 and the second common electrode 3 are distributed in different layers with respect to the array substrate in FIG. 12 .
  • the first common electrode 2 and the second common electrode 3 are slit electrodes, and the pixel electrode 5 is a plate electrode.
  • the pixel electrode 5 is spaced apart from the first common electrode 2 by an insulating layer 10, and the first common electrode 2 and the second common electrode 3 are separated by an insulating layer 10'.
  • a passivation layer 7 is also overlaid on the second common electrode 3.
  • a multi-dimensional electric field is formed between the pixel electrode 5 and the first common electrode 2
  • a multi-dimensional electric field is formed between the pixel electrode 5 and the second common electrode 3
  • the first common electrode 2 and the second common electrode are formed.
  • a multi-dimensional electric field is also formed between the three, thereby enhancing the multi-dimensional electric field, the superposition of a plurality of multi-dimensional electric fields in the same layer and different layers, so that the liquid crystal molecules above the pixel electrode 5 are sufficiently horizontally rotated to improve the transmittance.
  • the array substrate in FIG. 12 and FIG. 13 is similar in operation to the array substrate of FIG. 4 in the first embodiment, and similar effects can be achieved, and are not described herein again.
  • a schematic structural diagram of an example of a liquid crystal display device according to an embodiment of the present invention includes: a liquid crystal layer 15 , a color filter substrate 16 , and any of the above embodiments.
  • the array substrate A schematic diagram of the light transmittance simulation of the liquid crystal display device is shown in Fig. 5, Fig. 8, or Fig. 10.
  • the display device may be: a product or a component having a display function such as a liquid crystal panel, an electronic paper, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like.
  • the embodiment of the invention further provides a driving method of the array substrate. As shown in FIG. 15, the method includes:
  • Step S401 applying a first common voltage to the first common electrode through the first common electrode line;
  • Step S402 applying a second common voltage to the second common electrode through the second common electrode line, the second common voltage and the first A common voltage is different.
  • the polarities of the first common electrode and the second common electrode are different, that is, the voltage polarity of the first common electrode is positive, and the voltage polarity of the second common electrode is negative (or vice versa).
  • the voltage of the pixel electrode may be between the first common electrode and the second common electrode voltage.
  • the voltages of the first common electrode and the second common electrode (V ⁇ ml and V ⁇ m2 ) are equal in absolute value, the voltage polarity of the first common electrode is positive, and the voltage polarity of the second common electrode is negative, the pixel electrode
  • I Vpixel -
  • the first common electrode and the second common electrode respectively form a multi-dimensional electric field with the pixel electrode, so that the liquid crystal molecules above the pixel electrode rotate horizontally sufficiently, Increased transmission rate.
  • the present invention provides an array substrate, a driving method thereof, and a display device.
  • Two common electrodes that is, a first common electrode and a second common electrode, a first common electrode edge, a second common electrode edge, and a first electrode are disposed on the array substrate.
  • An electric field is generated between the common electrode and the second common electrode, and a multi-dimensional electric field is generated between the first common electrode and the pixel electrode and the second common electrode and the pixel electrode, and the multiple electric fields are superimposed together, so that the liquid crystal molecules in the region directly between the electrodes and the electrodes are easier. Driven, thereby increasing the efficiency of the liquid crystal and increasing the transmittance.

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Abstract

一种阵列基板及其驱动方法、显示装置。阵列基板包括栅线(12)和数据线(11)、像素单元，每个像素单元包括公共电极(2、3)和像素电极(5)，公共电极(2、3)包括第一公共电极(2)和第二公共电极(3)，第一公共电极(2)包括多个第一条形电极，第二公共电极(3)包括多个第二条形电极，第一条形电极和第二条形电极交替设置，用于分别与所述像素电极(5)形成电场。通过设置分别与像素电极形成多维电场的第一公共电极和第二公共电极，提高显示装置的光透过率。

Description

阵列基板及其驱动方法、 显示装置 技术领域
本发明的实施例涉及一种阵列基板及其驱动方法和显示装置。 背景技术
随着液晶显示技术的不断发展， 人们对液晶显示产品的分辨率的要求越 来越高。 对于传统的液晶显示技术如 ADS ( ADvanced Super Dimension Switch,高级超维场转换技术）技术，其透过率仅为 TN模式（ Twisted Nematic, 扭曲向列型）透过率的 78%左右， 因此， 提高 ADS模式的透过率显得尤为 重要。
图 1示出一种 ADS模式液晶显示面板的阵列基板的结构示意图。基板 1 包括： 像素电极 5、公共电极 6和钝化层 7。在基板 1上将公共电极 6和像素 电极 5设计成狭缝状。 如图 2所示， 在狭缝状的公共电极 6与像素电极 5之 间形成的电场的作用下， 液晶分子在像素电极和公共电极形成的电场的作用 下进行旋转， 使显示面板透过率以及液晶分子分布图呈现图 2所示的情形， 实现显示功能。 发明内容
本发明一个方面提供了一种阵列基板， 包括栅线和数据线， 以及由所 述栅线和所述数据线限定的多个像素单元， 每个像素单元包括公共电极和像 素电极。所述公共电极和所述像素电极位于不同膜层并且通过绝缘层相绝缘， 所述公共电极包括第一公共电极和第二公共电极， 所述第一公共电极连接第 一公共电极线， 所述第二公共电极连接第二公共电极线， 所述第一公共电极 和所述第二公共电极均为狭缝状电极且分别包括多个第一条形电极和多个第 二条形电极， 且所述第一条形电极和所述第二条形电极交替设置， 用于分别 与所述像素电极形成电场。
在一个示例中， 所述像素电极为狭缝状电极且包括多个第三条形电极， 所述像素电极的第三条形电极与所述第一公共电极的第一条形电极和所述第 二公共电极的第二条形电极交替设置， 相邻的第一公共电极的第一条形电极 和第二公共电极的第二条形电极之间间隔设置所述像素电极的第三条形电 极。
在一个示例中， 所述第一公共电极和所述第二公共电极位于同一膜层， 所述第一公共电极和所述第二公共电极均位于所述像素电极的远离阵列基板 的衬底基板一侧， 或者所述第一公共电极和所述第二公共电极均位于所述像 素电极的靠近阵列基板的衬底基板一侧。
在一个示例中， 所述第一公共电极和所述第二公共电极位于不同膜层， 所述第一公共电极和所述第二公共电极均位于所述像素电极的远离阵列基板 的衬底基板一侧， 或者所述第一公共电极和所述第二公共电极均位于所述像 素电极的靠近阵列基板的衬底基板一侧， 或者所述第一公共电极位于所述像 素电极的远离阵列基板的衬底基板一侧且所述第二公共电极位于所述像素电 极的靠近阵列基板的衬底基板一侧。
在一个示例中， 相邻的所述第一公共电极的第一条形电极和所述第二公 共电极的第二条形电极的在所述基板上的投影的之间距大于所述像素电极的 第三条形电极的宽度。
在一个示例中， 所述第一公共电极的第一条形电极和所述像素电极的第 三条形电极在平行于阵列基板方向上的距离为 0 ~ 0.6μπι，所述第二公共电极 的第二条形电极和所述像素电极的第三条形电极在平行于阵列基板方向上的 距离为 0 ~ 0.6μπι， 所述第一条形电极、 所述第二条形电极和所述第三条形电 极的宽度分别为 2 ~ 2.6μπι。
在一个示例中， 所述像素电极为板状电极， 所述第一公共电极和第二公 共电极均位于所述像素电极远离阵列基板的衬底基板一侧的同一膜层或不同 膜层。
本发明另一方面还提供了一种显示装置， 包括上述任一阵列基板。 本发明又一方面还提供了一种阵列基板的驱动方法， 所述阵列基板为上 述任一的阵列基板； 所述驱动方法包括： 通过第一公共电极线向第一公共电 极施加第一公共电压； 以及通过第二公共电极线向第二公共电极施加第二公 共电压， 所述第二公共电压与所述第一公共电压不同。
在一个示例中， 所述驱动方法还包括： 通过数据线向像素电极提供像素 电压信号， 所述像素电压信号介于所述第一公共电压和所述第二公共电压之 间。 附图说明
图 1是一种液晶显示装置中阵列基板的结构示意图；
图 2是液晶显示装置的光透过率模拟示意图；
图 3是本发明实施例一提供的一种阵列基板示例的结构平面示意图； 图 4是本发明实施例一提供的一种阵列基板示例的截面示意图； 图 5是本发明实施例一提供的光透过率模拟示意图；
图 6是本发明实施例一提供的另一种阵列基板示例的截面示意图； 图 7是本发明实施例二提供的一种阵列基板示例的截面示意图； 图 8是本发明实施例二提供的光透过率模拟示意图；
图 9是本发明实施例二提供的另一种阵列基板示例的截面示意图； 图 10是本发明实施例二提供的光透过率模拟示意图；
图 11是本发明实施例二提供的又一种阵列基板示例的截面示意图； 图 12是本发明实施例三提供的一种阵列基板示例的截面示意图； 图 13是本发明实施例三提供的另一种阵列基板示例的截面示意图； 图 14是本发明实施例四提供的一种液晶显示装置示例的截面示意图； 图 15是本发明实施例五提供的一种阵列基板示例的驱动方法流程图。 具体实施方式
为使本发明的实施例的目的、 技术方案和优点更加清楚， 下面将结合本 发明实施例的附图对本发明的实施例的技术方案进行清楚、 完整的描述。 显 然， 所描述的实施例仅是本发明的一部分示例性实施例， 而不是全部的实施 例。 基于所描述的本发明的示例性实施例， 本领域普通技术人员在无需创造 性劳动的前提下所获得的所有其它实施例都属于本发明的保护范围。
除非另作定义， 此处使用的技术术语或者科学术语应当为本发明所属领 域内具有一般技能的人士所理解的通常意义。 本发明专利申请说明书以及权 利要求书中使用的"第一"、 "第二 "以及类似的词语并不表示任何顺序、 数量 或者重要性， 而只是用来区分不同的组成部分。 同样， "一个，，、 "一"或者"该，， 等类似词语也不表示数量限制， 而是表示存在至少一个。 "包括，，或者"包含" 等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的 元件或者物件及其等同， 而不排除其他元件或者物件。 "上"、 "下"、 等仅用 于表示相对位置关系， 当被描述对象的绝对位置改变后， 则该相对位置关系 也可能相应地改变。 发明人注意到， 在图 1和图 2所示的阵列基板之中， 由 于阵列基板公共电极的电压相同， 所以液晶面板透过率不高。
实施例 1
本实施例提供了一种阵列基板，本实施例的阵列基板如图 3和图 4所示， 图 3为阵列基板上一个像素单元的示意图， 图 4为图 3所示阵列基板的截面 图。 该阵列基板包括形成在衬底基板 1上的栅线 12和数据线 11， 以及由所 述栅线 12和所述数据线 11限定的多个像素单元， 每个像素单元包括公共电 极 2、 3和像素电极 5， 像素电极 5和公共电极 2、 3形成在阵列基板的不同 膜层， 且通过绝缘层相绝缘。
公共电极 2、 3包括： 用于分别连接不同的信号线的第一公共电极 2和第 二公共电极 3， 且第一公共电极 2和第二公共电极 3均为狭缝状电极。 第一 公共电极 2包括多个第一条形电极，第二公共电极 3包括多个第二条形电极， 且第一条形电极和所述第二条形电极交替设置， 用于分别与像素电极 5形成 多维电场。 像素电极 5通过过孔 15与薄膜晶体管的漏极 13连接， 薄膜晶体 管的源极 14与数据线 11相连， 薄膜晶体管的栅极连接栅线 12。 像素电极 5 的表面还可以覆盖有钝化层 7。
本实施例中， 像素电极 5为狭缝状电极。 像素电极 5包括多个第三条形 电极， 且像素电极 5的第三条形电极、 第一公共电极 2的第一条形电极和第 二公共电极 3的第二条形电极交替设置， 相邻的第一公共电极 2的第一条形 电极和第二公共电极 3的第二条形电极之间间隔设置像素电极 5的第三条形 电极。
第一公共电极 2和第二公共电极 3位于同一膜层， 第一公共电极 2和第 二公共电极 3均位于像素电极 5的远离阵列基板的衬底基板一侧， 或者第一 公共电极 2和第二公共电极 3均位于像素电极 5的靠近阵列基板的衬底基板 一侧。
如图 4所示， 第一公共电极 2和第二公共电极 3位于同一层， 且与像素 电极 5位于不同层， 且第一公共电极 2和第二公共电极 3均位于像素电极 5 的靠近阵列基板的衬底基板一侧， 在图 4中像素电极 5位于第一公共电极 2 和第二公共电极 3的上方。 第一公共电极 2、 第二公共电极 3和像素电极 5 均为狭缝状电极， 且像素电极 5的第三条形电极、 第一公共电极 2的第一条 形电极和第二公共电极 3的第二条形电极交替设置， 相邻的第一公共电极 2 的第一条形电极和第二公共电极 3的第二条形电极之间间隔设置像素电极 5 的第三条形电极。 相邻的第一公共电极 2的第一条形电极和第二公共电极 3 的第二条形电极在衬底基板 1上的投影的之间距大于像素电极 5的第三条形 电极的宽度。这样在第一公共电极 2和第二公共电极 3之间会形成横向电场， 像素电极 5与第一公共电极 2形成多维电场， 像素电极 5与第二公共电极 3 形成多维电场。 当一个横向电场和两个多维电场的合电场使得液晶分子在水 平方向朝同一方向旋转时， 液晶分子水平旋转角度会更大。 为了使第一公共 电极 2和第二公共电极 3分别与像素电极 5形成的电场均匀分布， 例如， 第 一公共电极 2、 第二公共电极 3和像素电极 5三者之间的间隔 g均相同， 三 者的宽度均相同， 例如， 0 < g < 0^m, 电极宽度均为 2.6μπι。
工作时， 第一公共电极 2和第二公共电极 3分别连接不同的信号线， 以 加载不同的电压。 为了使得液晶分子充分水平旋转， 本实施例中， 第一公共 电极 2和第二公共电极 3的极性不同， 即第一公共电极 2的电压极性为正， 第二公共电极 3的电压极性为负（反之亦可）。像素电极 5的电压可以介于第 一公共电极 2和第二公共电极 3电压之间。 例如： 第一公共电极 2和第二公 共电极 3的电压（ Vc。ml 和 V∞m2 )绝对值相等， 第一公共电极 2的电压极性 为正，第二公共电极 3的电压极性为负，像素电极 5的电压 Vpixel介于 V∞ml 和 V com2之间， 且
Figure imgf000006_0001
_ COm2 ' |V讓 i _ Vpixdl = I Vpixel _ |ν∞πι2||。 其中， 0.2V<Vcoml<0.3V, - 0.2V< Vcom2< - 0.3V。
图 5所示， 为图 4的阵列基板的光透过率模拟示意图。 第一公共电极和 第二公共电极分别与像素电极形成多维电场， 从而使得像素电极上方的液晶 分子充分水平旋转， 提高了透过率。
本发明实施例的另一种阵列基板结构如图 6所示， 第一公共电极 2和第 二公共电极 3位于同一层， 且与像素电极 5位于不同层， 且第一公共电极 2 和第二公共电极 3均位于像素电极 5的远离阵列基板的衬底基板一侧。 相对 于图 5中的结构， 图 6中像素电极 5位于第一公共电极 2和第二公共电极 3 的下方。 该图 6所示的阵列基板， 第一公共电极 2和第二公共电极 3之间会 形成横向电场， 像素电极 5与第一公共电极 2形成多维电场， 像素电极 5与 第二公共电极 3形成多维电场， 该图 6的阵列基板所达到的效果与图 4所示 的阵列基板所达到的效果基本相同， 此处不再赘述。
本实施例提供的阵列基板为平面电场宽视角技术的 ADS ( Advanced Super Dimension Switch, 高级超维场转换技术）模式， 通过同一平面内狭缝 状电极边缘所产生的电场以及狭缝状电极层与板状电极层间产生的电场形成 多维电场， 使液晶盒内狭缝状电极间、 电极正上方所有取向液晶分子都能够 产生旋转， 从而提高了液晶工作效率并增大了透光效率。
实施例 2
图 7所示为本实施例提供的一种阵列基板示例的结构示意图。 像素电极 5、第一公共电极 2和第二公共电极 3三者位于不同层，三者均为狭缝状电极。 第一公共电极 2位于像素电极 5的远离阵列基板的衬底基板 1一侧且第二公 共电极 3位于像素电极 5的靠近阵列基板的衬底基板 1的一侧。 在图 7中， 第一公共电极 2位于基板 1之上， 像素电极 5所在层位于第一公共电极 2和 第二公共电极 3所在层之间， 像素电极 5和第一公共电极 2及第二公共电极 3分别间隔有绝缘层 8和 8'。 第二公共电极 3上还形成有钝化层 7。 该图 7 所示的阵列基板的工作原理为， 第一公共电极 2和第二公共电极 3分别与像 素电极 5形成多维电场， 且第一公共电极 2和第二公共电极 3之间形成多维 电场，当三个多维电场的合电场使得液晶分子在水平方向朝同一方向旋转时， 液晶分子水平旋转角度会更大。 达到的效果如图 8所示， 像素电极上方的液 晶分子充分水平旋转， 提高了透过率。
如图 9所示为本发明实施例提供的又一种阵列基板示例的结构示意图。 像素电极 5、 第一公共电极 2和第二公共电极 3三者位于不同层， 三者均为 狭缝状电极， 第一公共电极 2和第二公共电极 3均位于像素电极 5的靠近阵 列基板的衬底基板 1一侧。 图 9中， 第二公共电极 3位于衬底基板 1上， 第 一公共电极 2所在层位于像素电极 5和第二公共电极 3所在层之间， 第一公 共电极 2与第二公共电极 3和像素电极 5分别间隔有绝缘层 8和 8'，像素电 极 5上还形成有钝化层 7。 在该图 9所示的阵列基板中， 第一公共电极 2和 第二公共电极 3分别与像素电极 5形成多维电场， 第一公共电极 2和第二公 共电极 3之间还形成多维电场， 当三个多维电场的合电场使得液晶分子在水 平方向朝同一方向旋转时， 液晶分子水平旋转角度会更大。 达到的效果如图 10所示， 像素电极上方的液晶分子充分水平旋转， 提高了透过率。
如图 11所示为本实施例提供的另一种阵列基板示例的结构示意图。像素 电极 5、 第一公共电极 2和第二公共电极 3三者位于不同层， 三者均相当于 狭缝状电极， 第一公共电极 2和第二公共电极 3均位于像素电极 5的远离阵 列基板的衬底基板 1一侧。 图 11中，像素电极 5位于衬底基板 1上， 第一公 共电极 2所在层位于像素电极 5和第二公共电极 3所在层之间， 第一公共电 极 2和像素电极 5及第二公共电极 3分别间隔有绝缘层 8和 8'，第二公共电 极 3上还形成有钝化层 7。 该图 11所示的阵列基板， 第一公共电极 2和第二 公共电极 3分别与像素电极 5形成多维电场， 第一公共电极 2和第二公共电 极 3之间还形成多维电场。 该阵列基板达到的效果与图 9所示的阵列基板达 到的效果基本相同， 此处不再赘述。
另外， 当第一公共电极 2、 第二公共电极 3和像素电极 5三者位于不同 层时， 在图 7、 图 9和图 10中， 第一公共电极 2和第二公共电极 3的位置互 换后达到的效果基本相同， 此处不再赘述。
在上述示例中， 上述相邻的第一公共电极 2的第一条形电极和第二公共 电极 3的第二条形电极的在衬底基板 1上的投影的之间距大于像素电极 5的 第三条形电极的宽度。 第一公共电极 2的第一条形电极和像素电极 5的第三 条形电极在平行于阵列基板方向上的距离为 0 ~ 0.6μπι。第二公共电极 5的第 二条形电极和像素电极 5的第三条形电极在平行于阵列基板方向上的距离为 0 ~ 0.6μπι。 第一公共电极 2的第一条形电极和像素电极 5的第三条形电极在 平行于阵列基板方向上的距离与第二公共电极 3的第二条形电极和像素电极 5的第三条形电极在平行于阵列基板方向上的距离相等。所述第一条形电极、 第二条形电极和第三条形电极的宽度分别为 2 ~ 2.6μπι。
实施例 3
本实施例提供了一种阵列基板，如图 12所示为本发明实施例提供的阵列 基板示例的结构示意图， 该阵列基板包括形成在衬底基板 1上的像素电极 5 (为板状电极）和公共电极 2、 3 (为狭缝状电极）， 其中， 公共电极包括： 用于分别连接不同的信号线的第一公共电极 2和第二公共电极 3， 第一公共 电极 2连接第一公共电极线， 第二公共电极 3连接第二公共电极线， 第一公 共电极 2和第二公共电极 3均为狭缝状电极， 且交替设置， 公共电极和像素 电极 5之间间隔有绝缘层 9， 用于分别与所述像素电极 5形成多维电场。 第 一公共电极 2和第二公共电极 3的表面还覆盖钝化层 7。
像素电极 5为板状电极， 形成在衬底基板 1上， 第一公共电极 2和第二 公共电极 3均位于像素电极 5的上方。
如图 12所示，第一公共电极 2和第二公共电极 3分布在同一层，且均形 成在绝缘层 9上方。 像素电极 5与第一公共电极 2之间形成多维电场， 像素 电极 5与第二公共电极 3之间形成多维电场， 且第一公共电极 2与第二公共 电极 3之间也会形成横向电场， 从而增强了多维电场， 同层、 不同层的多个 多维电场的叠加， 从而使得像素电极 5上方的液晶分子充分水平旋转， 提高 了透过率。
如图 13 所示， 为本发明实施例提供的有一种阵列基板示例的结构示意 图，相对于图 12中的阵列基板，第一公共电极 2和第二公共电极 3分布在不 同层， 且均位于像素电极 5上方， 且第一公共电极 2和第二公共电极 3均为 狭缝状电极， 像素电极 5为板状电极。 像素电极 5与第一公共电极 2间隔有 绝缘层 10， 第一公共电极 2和第二公共电极 3间隔有绝缘层 10'。 第二公共 电极 3之上还覆盖有钝化层 7。 该图 13所示的阵列基板， 像素电极 5与第一 公共电极 2之间形成多维电场， 像素电极 5与第二公共电极 3之间形成多维 电场， 且第一公共电极 2与第二公共电极 3之间也会形成多维电场， 从而增 强了多维电场， 同层、 不同层的多个多维电场的叠加， 从而使得像素电极 5 上方的液晶分子充分水平旋转， 提高了透过率。
图 12和图 13中的阵列基板在工作时与实施例一中的图 4的阵列基板在 工作时原理类似， 且能达到相似的效果， 此处不再赘述。
实施例 4
本实施例还提供了一种显示装置， 如图 14 所示为本发明实施例提供的 一种液晶显示装置示例的结构示意图， 包括： 液晶层 15、 彩膜基板 16及上 述实施例中任一所述的阵列基板。 该液晶显示装置的光透过率模拟示意图如 图 5、 图 8或图 10所示。 所述显示装置可以为： 液晶面板、 电子纸、 手机、 平板电脑、 电视机、 显示器、 笔记本电脑、 数码相框、 导航仪等任何具有显 示功能的产品或部件。
实施例 5
本发明实施例还提供了一种阵列基板的驱动方法， 如图 15 所示， 该方 法包括：
步骤 S401、 通过第一公共电极线向第一公共电极施加第一公共电压； 步骤 S402、通过第二公共电极线向第二公共电极施加第二公共电压， 所 述第二公共电压与所述第一公共电压不同。
通过数据线向像素电极提供像素电压信号， 所述像素电压信号介于所述 第一公共电压和所述第二公共电压之间。
在本发明实施例中， 第一公共电极和第二公共电极的极性不同， 即第一 公共电极的电压极性为正， 第二公共电极的电压极性为负（反之亦可）。像素 电极的电压可以介于第一公共电极和第二公共电极电压之间。 例如： 第一公 共电极和第二公共电极的电压（V∞ml 和 V∞m2 )绝对值相等， 第一公共电极 的电压极性为正， 第二公共电极的电压极性为负，像素电极的电压 vpixel介于 coml 和 V com2之间， 且 Vcoml =-Vcom2， |V醒 i _ Vpixel| = I Vpixel - |Vcom2| | »
0.2V<Vcomi<0.3V, -0.2V< Vcom2<-0.3Vo 第一公共电极和第二公共电极分别与 像素电极形成多维电场， 从而使得像素电极上方的液晶分子充分水平旋转， 提高了透过率。
本发明通过提供一种阵列基板及其驱动方法、 显示装置， 阵列基板上设 置两个公共电极， 即第一公共电极和第二公共电极， 第一公共电极边缘、 第 二公共电极边缘以及第一公共电极和第二公共电极之间产生电场， 第一公共 电极和像素电极之间以及第二公共电极和像素电极产生多维电场， 多重电场 共同叠加， 使电极间、 电极正上方区域液晶分子更容易被驱动， 从而提高了 液晶工作效率并增大了透过率。
以上实施方式仅用于说明本发明， 而并非对本发明的限制， 有关技术领 域的普通技术人员， 在不脱离本发明的精神和范围的情况下， 还可以做出各 种变化和变型，这些变化和变型以及等同的技术方案也应属于本发明的范畴， 本发明的专利保护范围应由权利要求限定。
本申请要求于 2013年 10月 09日提交的名称为"阵列基板及其驱动方法、 显示装置" 的中国专利申请 No. 201310467672.9的优先权， 其全文以引用方 式合并于本文。

Claims

权利要求书
1、 一种阵列基板， 包括栅线和数据线， 以及由所述栅线和所述数据线 限定的多个像素单元， 每个像素单元包括公共电极和像素电极，
其中， 所述公共电极和所述像素电极位于不同膜层并通过绝缘层相绝 缘， 所述公共电极包括第一公共电极和第二公共电极， 所述第一公共电极连 接第一公共电极线， 所述第二公共电极连接第二公共电极线， 所述第一公共 电极和所述第二公共电极均为狭缝状电极且分别包括多个第一条形电极和多 个第二条形电极， 且所述第一条形电极和所述第二条形电极交替设置， 用于 分别与所述像素电极形成电场。
2、 根据权利要求 1 所述的阵列基板， 其中， 所述像素电极为狭缝状电 极且包括多个第三条形电极， 且所述像素电极的第三条形电极与所述第一公 共电极的第一条形电极和所述第二公共电极的第二条形电极交替设置， 相邻 的所述第一公共电极的第一条形电极和所述第二公共电极的第二条形电极之 间间隔设置所述像素电极的第三条形电极。
3、 根据权利要求 1或 2所述的阵列基板， 其中， 所述第一公共电极和 所述第二公共电极位于同一膜层， 所述第一公共电极和所述第二公共电极均 位于所述像素电极的远离阵列基板的村底基板一侧， 或者所述第一公共电极 和所述第二公共电极均位于所述像素电极的靠近阵列基板的衬底基板一侧。
4、 根据权利要求 1或 2所述的阵列基板， 其中所述第一公共电极和所 述第二公共电极位于不同膜层， 所述第一公共电极和所述第二公共电极均位 于所述像素电极的远离阵列基板的衬底基板一侧， 或者所述第一公共电极和 所述第二公共电极均位于所述像素电极的靠近阵列基板的衬底基板一侧， 或 者所述第一公共电极位于所述像素电极的远离阵列基板的村底基板一侧且所 述第二公共电极位于所述像素电极的靠近阵列基板的衬底基板一侧。
5、根据权利要求 2-4中任一项所述的阵列基板， 其中相邻的所述第一公 共电极的第一条形电极和所述第二公共电极的第二条形电极的在基板上的投 影的之间距大于所述像素电极的第三条形电极的宽度。
6、根据权利要求 2-5任一项所述的阵列基板， 其中所述第一公共电极的 第一条形电极和所述像素电极的第三条形电极在平行于阵列基板方向上的距 离为 0 ~ 0.6μπι，所述第二公共电极的第二条形电极和所述像素电极的第三条 形电极在平行于阵列基板方向上的距离为 0 ~ 0.6μπι， 所述第一条形电极、 第 二条形电极和第三条形电极的宽度为 2 ~ 2.6μπι。
7、 根据权利要求 1 所述的阵列基板， 其中所述像素电极为板状电极， 所述第一公共电极和第二公共电极均位于像素电极远离阵列基板的衬底基板 一侧的同一膜层或不同膜层。
8、 一种显示装置， 包括如权利要求 1-7任一项所述的阵列基板。
9、一种阵列基板的驱动方法， 用于如权利要求 1-7任一项所述的阵列基 板， 所述驱动方法包括：
通过第一公共电极线向第一公共电极施加第一公共电压； 以及
通过第二公共电极线向第二公共电极施加第二公共电压， 所述第二公共 电压与所述第一公共电压不同。
10、 根据权利要求 9所述的驱动方法， 还包括：
通过数据线向像素电极提供像素电压信号， 所述像素电压信号介于所述 第一公共电压和所述第二公共电压之间。
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